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* MFC 304140:andrew2016-09-072-3/+150
* MFC 302849, 302851, 302896 GICv3 improvements:andrew2016-09-074-110/+101
* MFC 302847, 302848, 302852, 302853:andrew2016-08-318-588/+1
* MFC 302789:andrew2016-08-312-1/+17
* MFC r303923:ed2016-08-151-0/+2
* MFC r302448:ed2016-07-121-0/+1
* Remove the old pre-INTRNG arm64 interrupt framework. GENERIC was switchedandrew2016-07-066-3554/+0
* ARM64: fix DMAP calculationwma2016-06-301-2/+2
* Fix a race when the hardware has raised an exception with an unknown orandrew2016-06-221-4/+3
* Update comments for the MD functions managing contexts for newkib2016-06-162-12/+11
* Switch arm64 to use intrng by default. The old interrupt handling code canandrew2016-06-072-15/+1
* INTRNG - change the way how an interrupt mapping data are providedskra2016-06-052-1/+5
* Add the GICv3 ITS intrng driver. As the interface to the interruptandrew2016-06-035-10/+1706
* Return real error value instead of hard-coded ENXIO (fix after r300149)zbb2016-06-011-1/+3
* dpcpu_init should have also passed in the calculated cpuid, not theandrew2016-05-311-1/+1
* Allow the kernel to boot on a CPU where the devicetree has numbered it withandrew2016-05-311-12/+47
* Enable setting BF_COHERENT on DMA tags. This allows the kernel to startandrew2016-05-311-2/+0
* Mark the ThunderX and generic PCI drivers as cache-coherent when we knowandrew2016-05-313-0/+29
* Extract the correct bits from the GICD_TYPER register. The interrupt countandrew2016-05-201-1/+1
* Add more useful GICv3 register definitions. While here fixandrew2016-05-201-1/+25
* Filter out BUS_DMASYNC_POSTWRITE sync operations, there is nothing for usandrew2016-05-201-0/+3
* Enable NEW_PCIB on arm64.andrew2016-05-201-0/+1
* Handle PCI_RES_BUS on the generic and ThunderX PCIe drivers. This has beenandrew2016-05-201-0/+14
* Define PCI_RES_BUS for NEW_PCIBandrew2016-05-191-0/+3
* Return the struct intr_pic pointer from intr_pic_register. This will beandrew2016-05-181-2/+2
* Add support for MSI/MSIX deallocation on GICv3-ITSzbb2016-05-182-8/+87
* The GIC (v2 at least) has a bit in the TYPER register to indicate whether the...bz2016-05-172-4/+10
* Add an arm64 kernel config to help testing intrng. It is expected thisandrew2016-05-171-0/+15
* Clean up the GICv3 intrng code:andrew2016-05-171-4/+10
* Add intrng support to the GICv3 driver. It lacks ITS support so won't handleandrew2016-05-163-4/+626
* Move the call to intr_pic_init_secondary to the same place as in theandrew2016-05-161-5/+3
* Add support for intrng to arm64. As the GICv3 drivers will need to beandrew2016-05-164-1/+298
* Teach the ThunderX PCI PEM driver about intrng. This will be used laterandrew2016-05-161-0/+55
* Add a pcib interface for use by interrupt controllers that need toandrew2016-05-165-61/+97
* Add support to the arm64 busdma to handle the cache. For now this isandrew2016-05-132-23/+203
* Rename the internal BUC_DMA_* flags to BF_* so they won't conflict withandrew2016-05-121-20/+20
* Restrict the memory barriers in bus_dmamap_sync to just the operationsandrew2016-05-121-46/+47
* Call busdma_swi from swi_vm as is done from other architectures.andrew2016-05-112-1/+4
* On arm64 always create a bus_dmamap_t object. This will be use to hold theandrew2016-05-111-44/+72
* Add data barriers to the arm64 bus_dmamap_sync function. We need theseandrew2016-05-111-1/+14
* Fix I/O coherence issues on ThunderX when SMP is disabledzbb2016-05-111-4/+0
* Push the logic to talk with the MSI/MSI-X interrupt controller to the FDTandrew2016-05-102-11/+76
* Native PCI-express HotPlug support.jhb2016-05-051-0/+1
* Fix GICv3 build after r299090zbb2016-05-054-7/+6
* Disable ACPI on arm64 ad it has only had minimal testing and is causingandrew2016-04-261-1/+1
* Move arm's devmap to some generic place, so it can be usedbr2016-04-263-93/+4
* Use the yield instruction in the arm64 cpu_spinwait. This instruction isandrew2016-04-251-1/+1
* sys: use our roundup2/rounddown2() macros when param.h is available.pfg2016-04-211-1/+1
* Group the ThunderX PCIe PEM newbus methods to help find them.andrew2016-04-201-3/+6
* Pull out the MSI/MSI-X handling calls to simplify future intrngandrew2016-04-201-5/+48
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