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* MFC r289477:ian2016-01-241-1/+5
| | | | | | | | | | Fix a strange macro re-definition compile error. If the VM_MAXUSER_ADDRESS value is defined as a config option the definition is emitted into opt_global.h which is force-included into everything. In addition, the symbol is emitted by the genassym mechanism, but that by its nature reduces the value to a 0xnnnnnnnn number. When compiling a .S file you end up with two different definitions of the macro (they evaluate to the same number, but the text is different, upsetting the compiler).
* MFC of r288447. Only the Marvell driver has been updated as there is noandrew2015-10-121-6/+6
| | | | | | | | | | | | | | | | | | | support for Raspbetty Pi 2 in stable/10. An IPI must be cleared before it is handled otherwise next IPI could be missed. In other words, if a new request for an IPI is sent while the previous request is being handled but the IPI is not cleared yet, the clearing of the previous IPI request also clears the new one and the handling is missed. There are only three MP interrupt controllers in ARM now. Two of them are fixed by this change, the third one is correct, probably only just by accident. The fix is minimalistic as new interrupt framework is awaited. It was debugged on RPi2 where missing IPI handling together with SCHED_ULE led to situation in which tdq_ipipending was not cleared and so IPI_PREEMPT was stopped to be sent. Various odditys were found related to slow system response time like various events timed out, and slow console response.
* MFC r280451:mav2015-08-222-878/+0
| | | | | | | Remove from legacy ata(4) driver support for hardware, supported by newer and more functional drivers ahci(4), siis(4) and mvs(4). This removes about 3400 lines of code, unused since FreeBSD 9.0 release.
* MFC r262409, r267129, r267130, r280709:ian2015-05-232-13/+22
| | | | | | | | | | | Move the declaration for mpentry() into a header file Fix broken SMP startup on Armada XP after r265694 Avoid using hard-coded SoC's register address in mptramp code for Armada XP Use pmap_mapdev()/unmapdev() to temporarily map on-chip sram while copying the startup trampoline code.
* MFC r274249, r274484, r275583:ian2015-05-231-1/+1
| | | | | | | | Avoid panic in ofwbus caused by not released resource list entry Fix typo in ARM GIC device_printf() Fix buffer overflow in Marvell PCI/PCIe driver
* MFC r277454, r277460, r277465, r277466, r277467, r277469, r277470, r277471,ian2015-02-132-163/+1
| | | | | | | | | | | | | | | | | | | | | r277472, r277473, r277474, r277475, r277476, r277477, r277478, r277479, r277480, r277512, r277516: Add inline implementations of arm bus_space_read/write_N(). Revise the arm bus_space implementation to avoid dereferencing the tag on every operation to retrieve the bs_cookie value almost nothing actually uses. Use the explicit member initializer style to init the bus_space struct. Use arm/bus_space-v6.c for all armv6 systems Consolidate many identical implementations of bus_space to a single common tag and implementation shared by armv4 and armv6. Micro-optimize the new arm inline bus_space implementation by grouping all the data the inline functions access together at the start of the bus_space struct so that they all fit in a single cache line.
* MFC r276047: Add -march=armv7a to the kernel compile for all v7a ARM systems.ian2015-02-111-0/+1
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* MFC r270945:ian2014-10-261-1/+1
| | | | | Rename OF_xref_phandle() to OF_node_from_xref() and add a new function that provides the inverse translation, OF_xref_from_node().
* MFC 265852: Map device memory using PTE_DEVICE rather than PTE_NOCACHE.ian2014-05-184-11/+11
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* MFC 265694, 265705, 265784:ian2014-05-182-0/+58
| | | | | | | | | | | Move the mptramp code which is specific to the Marvell ArmadaXP SoC out of the common locore.S file and into the mv/armadaxp directory. Consolidate all the AP core startup stuff under a single #ifdef SMP block Call idcache_inv_all from the AP core entry code before turning on the MMU. Also, enable instruction and branch caches, which should be safe now that they're properly initialized/invalidated first.
* MFC 262952, 262958, 262966, 262979, 262980, 262986, 262987, 262995, 262997,ian2014-05-171-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 263030, 263033, 263034, 263056, 263057, Remove all the redundant external declarations of exception vectors and runtime setting of the pointers that's scattered around various places. Remove all traces of support for ARM chips prior to the arm9 series. Make the default exception handler vectors point to where I thought they were already pointing: the default handlers (not a panic that says there is no default handler). Eliminate irq_dispatch.S. Move the data items it contained into arm/intr.c and the functionality it provided into arm/exception.S. Move the exception vector table (so-called "page0" data) into exception.S and eliminate vectors.S. Change the way the asm GET_CURTHREAD_PTR() macro is defined so that code using it doesn't have to have an "AST_LOCALS" macro somewhere in the file. Arrange for arm fork_trampoline() to return to userland via the standard swi_exit code in exception.S instead of having its own inline expansion of the DO_AST and PULLFRAME macros. Now that the PUSHFRAME and PULLFRAME macros are used only in the swi entry/exit code, they don't need to be macros. Except that didn't work and the whole change was reverted. Remove some unnecessary indirection and jump right to the handler functions. Use panic rather than printf to "handle" an arm26 address exception (should never happen on arm32). Remove the unreferenced DATA() macro. Remove #include <machine/asmacros.h> from files that don't need it.
* MFC 257774, 256760, 262916, 262905, 262918, 262919, 262920, 262921, 262924,ian2014-05-173-3/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 262925, 262929, 262932, 262935, 262940, 262941, 262942, 262948, 262949, 262950 Strip arm/conf/DEFAULTS down to just items that are mandatory for running the architecture. Move all the files named foo/common.c to foo/foo_common.c Initial cut for DTS on the hl201 board. Add commented out dts for sam9260ek as well as early printf support. Make clock optional on uart nodes, then back it out ("I don't know what I was thinking, but it is lame.") Set the baud rate if it isn't 0 Make at91_soc_id() public. Properly round at91 resource on unmapping. Move AT91 AIC related stuff to own file. Fix another bug in multicast filtering. i.MX uses 6 bits from MSB in LE CRC32 for the hash value, not the lowest 6 bits in BE CRC32. Follow r262916 with one more config file that references a renamed common.c Remove bogus AT91 define that causes compile errors. Most of the defines for SAM9X are going away soonish anyway (once FDT works), but until then... Remove all dregs of a per-thread undefined-exception-mode stack. Rework the VFP code that handles demand-based save and restore of state. Always call vfp_discard() on thread death. When a thread begins life it doesn't own the VFP hardware state on any cpu. Make undefined exception entry MP-safe.
* MFC r262534, r262548, r262549, r262552, r262568, r262581, r262583, r262584,ian2014-05-161-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | r262585, r262587, r262696, r262712 Replace many pasted identical definitions of cpu_initclocks() with a common implementation in arm/machdep.c. aicasm: Don't complain about missing prototypes to ease bootstrap issues. Vybrid: Add driver for Inter-Integrated Circuit (I2C). imx6: Initialize the Low Power Mode bits to keep the ARM cores running during WFI. All our current ARM multi-core systems have all cores in one package with a shared L2 cache, reflect that in the common cpu_topo() routine. mpcore timer: Supply a DELAY() implementation via weak linkage, so that SoC-specific code can supply a better implementation. imx6: Add some rudimentary voltage control. Add an armv7 implementation of cpu_sleep(). Add __used attribute so that the DELAY implementation doesn't get optimized away as unreferenced, causing linker errors when trying to resolve the weak reference to the missing function.
* MFC r262409, r262411, r262413, r262420, r262426, r262427, r262440, r262456,ian2014-05-161-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | r262482, r262483, r262531, Move the declaration for mpentry() into a header file instead of pasting it into a bunch of different .c files. If the L2 cache type is PIPT, pass a physical address for a flush. Actually set the proper bit to indicate TTB shared memory. Add a new cache maintenance function, idcache_inv_all, to the table, and implementations for each of the chips we support. Invalidate caches immediately upon entry to init_secondary(). Also set the Bufferable bit in the PDE entries of the secondary processor startup pagetables. Add the bits needed to run SMP on imx6. Invalidate the SCU cache tag ram on all 4 cores, not just 1-3. Minor tweaks to the imx GPT timer Vybrid enhancements... - Pin configuration is a complete iomux register now and includes drive strength, pull mode, mux mode, speed, etc. - Add i2c devices to the tree - Add IPG clock - Add support for Quartz Module. - Pin configuration is a complete iomux register now and includes drive strength, pull mode, mux mode, speed, etc. - Add i2c devices to the tree - Add IPG clock
* MFC r261423, r261424, r261516, r261513, r261562, r261563, r261564, r261565,ian2014-05-152-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | r261596, r261606 Add the imx sdhci controller. Move Open Firmware device root on PowerPC, ARM, and MIPS systems to a sub-node of nexus (ofwbus) rather than direct attach under nexus. This fixes FDT on x86 and will make coexistence with ACPI on ARM systems easier. SPARC is unchanged. Add the missing ')' at end of sentence. Reword it to use a more common idiom. Pass the kernel physical address to initarm through the boot param struct. Make functions only used in vfp.c static, and remove vfp_enable. Fix __syscall on armeb EABI. As it returns a 64-bit value it needs to place 32-bit data in r1, not r0. 64-bit data is already packed correctly. Use abp_physaddr for the physical address over KERNPHYSADDR. This helps us remove the need to load the kernel at a fixed address. Remove references to PHYSADDR where it's used only in debugging output. Dynamically generate the page table. This will allow us to detect the physical address we are loaded at to change the mapping.
* MFC r261410ian2014-05-158-0/+24
| | | | | Follow r261352 by updating all drivers which are children of simplebus to check the status property in their probe routines.
* MFC r261351, r261352, r261355, r261396, r261397, r261398, r261403, r261404,ian2014-05-151-5/+7
| | | | | | | | | | | | | | | | | | | | | | | | | r261405 Open Firmware interrupt specifiers can consist of arbitrary-length byte strings and include arbitrary information (IRQ line/domain/sense). When the ofw_bus_map_intr() API was introduced, it assumed that, as on most systems, these were either 1 cell, containing an interrupt line, or 2, containing a line number plus a sense code. It turns out a non-negligible number of ARM systems use 3 (or even 4!) cells for interrupts, so make this more general. Provide a simpler and more standards-compliant simplebus implementation to get the Routerboard 800 up and running with the vendor device tree. This does not implement some BERI-specific features (which hopefully won't be necessary soon), so move the old code to mips/beri, with a higher attach priority when built, until MIPS interrupt domain support is rearranged. Allow nesting of simplebuses. Add a set of helpers (ofw_bus_get_status() and ofw_bus_status_okay()) to process "status" properties of OF nodes. Fix one remnant endian flaw in nexus.
* MFC r261252, r261279, r261304, r261305, r261322, r261336, r261337, r261338,ian2014-05-155-5/+0
| | | | | | | | | | | | | | | | | r261353 Fix the name of the dts file for the HL201... When mapping an address, the bsh needs the same offset we do for other things. Add explicit depends on bus_if.h and device_if.h to avoid a chicken and egg problem in some compilation environments. Switch to using PAs rather than VAs for the addresses we map for devices. This is a nop, except for what's reported by atmelbus for the resources. Comment cleanups. Move things around for diff reduction against FDT work.
* MFC r257738, r259202, r258410, r260288, r260292, r260294, r260320, r260323,ian2014-05-143-6/+183
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | r260326, r260327, r260331, r260333, r260340, r260371, r260372, r260373, r260374, r260375 Add common bus_space tag definition shared for most supported ARMv6/v7 SoCs. Correct license statements to reflect the fact that these files were all derived from sys/arm/mv/bus_space.c. In pmap_unmapdev(), remember the size, and use that as an argument to kva_free(), or we'd end up always passing it a size of 0 In pmap_mapdev(), first check whether a static mapping exists, Convert TI static device mapping to use the new arm_devmap_add_entry(), Use the common armv6 fdt_bus_tag defintion for tegra instead of a local copy. Eliminate use of fdt_immr_addr(), it's not needed for tegra Convert lpc from using fdt_immr style to arm_devmap_add_entry() to make static device mappings. Retire machine/fdt.h as a header used by MI code, as its function is now obsolete. This involves the following pieces: - Remove it entirely on PowerPC, where it is not used by MD code either - Remove all references to machine/fdt.h in non-architecture-specific code (aside from uart_cpu_fdt.c, shared by ARM and MIPS, and so is somewhat non-arch-specific). - Fix code relying on header pollution from machine/fdt.h includes - Legacy fdtbus.c (still used on x86 FDT systems) now passes resource requests to its parent (nexus). This allows x86 FDT devices to allocate both memory and IO requests and removes the last notionally MI use of fdtbus_bs_tag. - On those architectures that retain a machine/fdt.h, unused bits like FDT_MAP_IRQ and FDT_INTR_MAX have been removed. Add #include <machine/fdt.h> to a few files that used to get it via pollution Enable the mv cesa security/crypto device by providing the required property in the dts source, and adding the right devices to the kernel config. Remove dev/fdt/fdt_pci.c, which was code specific to Marvell ARM SoCs, related to setting up static device mappings. Since it was only used by arm/mv/mv_pci.c, it's now just static functions within that file, plus one public function that gets called only from arm/mv/mv_machdep.c. Switch RPi to using arm_devmap_add_entry() to set up static device mapping. Allow 'no static device mappings' to potentially work. Don't try to find a static mapping before calling pmap_mapdev(), that logic is now part of pmap_mapdev() and doesn't need to be duplicated here. Switch a10 to using arm_devmap_add_entry() to set up static device mapping.
* MFC r257170, r257171, r257172, r257240, r257278, r257279, r257280, r257281,ian2014-05-144-6/+90
| | | | | | | | | | | | | | | | | | | | | | | | | r257282, r257332 Wait for DesignWare UART transfers completion before accessing line control Enable UART busy detection handling for Armada XP - based board Enable SATA interface on Armada XP Run mvs SATA driver on Armada XP instead of old mv_sata Retire arm_remap_nocache() and the data and constants associated with it. Remove hard-coded mappings related to Armada XP support Fix-up DTB for Armada XP registers' base according to the actual settings Change Armada XP kernel load address to the u-boot's end address Remove not working and deprecated PJ4Bv6 support Switch off explicit broadcasting of the TLB flush operations for PJ4B CPU Add missing ARMv6 CPU functions to ARM Makefile
* MFC r258800, r258802, r258805, r258806, r258807, r258851, r258857,ian2014-05-141-28/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | r259199, r259484, r259513, r259514, r259516 The kernel stack guard pages are only below the stack pointer, not above. Remove unnecessary double-setting of the thread's onfault state in copyinstr(). Open Firmware mandates that certain cross-references, in particular those in /chosen, be ihandles. The ePAPR spec makes those cross-reference phandles, since FDT has no concept of ihandles. Have the OF FDT CI module interpret queries about ihandles as cross-reference phandles. Real OF systems have an ihandle under /chosen/stdout, not a phandle. Use the right type. Rearchitect platform memory map parsing to make it less Open Firmware-centric. Remove fdtbus_bs_tag definition, which is now obsolete. The remainder of this file is also slated for future demolition. Return the correct IEEE 1275 code for "nextprop". Use the common Open Firmware PCI interrupt routing code instead of the duplicate version in dev/fdt. Configure interrupt sense based on device tree information. Simplify the ofw_bus_lookup_imap() API slightly: make it allocate maskbuf internally instead of requiring the caller to allocate it.
* MFC r257702, r257745, r257746, r257747, r257751, r257791, r257793,ian2014-05-142-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | r257794, r257795, r257992 Teach nexus(4) about Open Firmware (e.g. FDT) on ARM and MIPS, retiring fdtbus in most cases. Make OF_nextprop() work correctly for FDT by using the libfdt fdt_next_property_offset() API. Do not panic if pmap_mincore() is called. An addendum: it is possible, though of questionable utility, for a node to have no properties at all. Add definition for the Atheros 8021 gigabit PHY. Consolidate Apple firmware hacks and improve them by switching on the presence of mac-io devices in the tree, which uniquely identifies Apple hardware. Allow OF_decode_addr() to also be able to map resources on big-endian devices. Make tsec work with the device tree present on the RB800. Be more flexible about which compatible strings to accept. This brings up the PCI Express bus on the RB800 using the firmware device tree. Rename the "bare" platform "mpc85xx", which is what it actually is, and add actual platform probing based on PVR.
* MFC r256932, r256938, r256966, r256953, r256967, r256969, r257015:ian2014-05-131-4/+1
| | | | | | | | | Add a new function (OF_getencprop()) that undoes the transformation applied by encode-int. Specifically, it takes a set of 32-bit cell values and changes them to host byte order. Most non-string instances of OF_getprop() should be using this function, which is a no-op on big-endian platforms. Use the new function all over the place.
* MFC r258779,r258780,r258787,r258822:eadler2014-02-041-1/+1
| | | | | | | | | | | | | Fix undefined behavior: (1 << 31) is not defined as 1 is an int and this shifts into the sign bit. Instead use (1U << 31) which gets the expected result. Similar to the (1 << 31) case it is not defined to do (2 << 30). This fix is not ideal as it assumes a 32 bit int, but does fix the issue for most cases. A similar change was made in OpenBSD.
* MFC r257669, r257672, r257673, r257676, r257678:ian2013-12-141-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | Call initarm_lastaddr() later in the init sequence, after establishing static device mappings, rather than as the first of the initializations that a platform can hook into. This allows a platform to allocate KVA from the top of the address space downwards for things like static device mapping, and return the final "last usable address" result after that and other early init work is done. Because some platforms were doing work in initarm_lastaddr() that needs to be done early, add a new initarm_early_init() routine and move the early init code to that routine on those platforms. Make PTE_DEVICE a synonym for PTE_NOCACHE on armv4, to make it easier to share the same code on both architectures. Add new helper routines for arm static device mapping. The new code allocates kva space from the top down for the device mappings and builds entries in an internal table which is automatically used later by arm_devmap_bootstrap(). The platform code just calls the new arm_devmap_add_entry() function as many times as it needs to (up to 32 entries allowed; most platforms use 2 or 3 at most). Remove imx local devmap code and use the essentially identical common code that got moved from imx_machdep.c to arm/devmap.c.
* MFC r257648, r257649, r257660:ian2013-12-133-7/+10
| | | | | | | | | | | | | | | | | Begin reducing code duplication in arm pmap.c and pmap-v6.c by factoring out common code related to mapping device memory into a new devmap.c file. Remove the growing duplication of code that used pmap_devmap_find_pa() and then did some math with the returned results to generate a virtual address, and likewise in reverse to get a physical address. Now there are a pair of functions, arm_devmap_vtop() and arm_devmap_ptov(), to do that. The bus_space_map() implementations are rewritten in terms of these. Move remaining code and data related to static device mapping into the new devmap.[ch] files. Emphasize the MD nature of these things by using the prefix arm_devmap_ on the function and type names (already a few of these things found their way into MI code, hopefully it will be harder to do by accident in the future).
* MFC r257201, r257202ian2013-12-131-1/+1
| | | | Retire arm_remap_nocache() and the data and constants associated with it.
* MFC r257199, r257200, r257217:ian2013-12-134-5/+0
| | | | | | | | | | | | | | | Remove all #include <machine/pmap.h> from arm code. It's already included by vm/pmap.h, which is a prerequisite for arm/machine/pmap.h so there's no reason to ever include it directly. Remove #include <machine/frame.h> from all the arm code that doesn't really need it. That would be almost everywhere it was included. Add it in a couple files that really do need it and were previously getting it by accident via another header. Remove the last dregs of trapframe_t. It turns out only arm was using this type, so remove it to make arm code more consistant with other platforms.
* Replace kernel virtual address space allocation with vmem. This providesjeff2013-08-071-2/+2
| | | | | | | | | | | | | transparent layering and better fragmentation. - Normalize functions that allocate memory to use kmem_* - Those that allocate address space are named kva_* - Those that operate on maps are named kmap_* - Implement recursive allocation handling for kmem_arena in vmem. Reviewed by: alc Tested by: pho Sponsored by: EMC / Isilon Storage Division
* Fix the passing of time on Armada XP.gber2013-06-042-1/+12
| | | | | | | In order to become independent of Coherency Fabric frequency, configure Timer and Watchdog to operate in 25MHz mode. Submitted by: Zbigniew Bodek <zbb@semihalf.com>
* decode_win_sdram_fixup() function should be declared, defined and usedgber2013-05-071-0/+4
| | | | | | only by Armada XP Obtained from: Semihalf
* Disable decoding windows with no FDT entry.gber2013-05-063-0/+61
| | | | | | | | | | - On ARMADAXP B0 (GP development board) we are not able to use PCI due to whole 32-bit address space used by 4GB of RAM memory. - Change is required to destroy unnecessary window to free address space for PCI and other devices - Fix offset value for SDRAM decoding windows Obtained from: Semihalf
* Properly initialize Armada XP MP subsystem.gber2013-05-063-85/+117
| | | | | | | | | | - correct setting of Auxiliary Control Register for MP mode - correct setting of Auxiliarty Debug registers - cleanup management of memory contains bootup code - early initialization of Coherency Fabric (MP and not-MP mode) - enable Snoop Filtering Obtained from: Semihalf
* Initialize L2 cache for Armada XP.gber2013-05-063-0/+109
| | | | Obtained from: Semihalf
* Move initialization of CESA decoding windows from common sectiongber2013-05-063-158/+48
| | | | | | | | | | | | to driver specific files. - window initialization is done during device attach - CESA TDMA decoding windows values are set based on DTS, not copied from CPU registers - remove unnecessary virtual mapping - update dts file Obtained from: Semihalf
* MFcalloutng:mav2013-02-281-20/+11
| | | | | | | Switch eventtimers(9) from using struct bintime to sbintime_t. Even before this not a single driver really supported full dynamic range of struct bintime even in theory, not speaking about practical inexpediency. This change legitimates the status quo and cleans up the code.
* Add a default do-nothing implementation of fdt_pci_devmap() using a weak alias,ian2013-01-274-53/+19
| | | | | | | | | | | so that we don't need an empty implementation of it for every Marvell platform that has no PCI. This allows the removal of the SheevaPlug-specific stub and config files, and eliminates the need to add similar stubs for future models. Marvell platforms that do expose PCI are compiled with 'device pci' which causes the real (non-weak) implementation in dev/fdt/fdt_pci.c to be used. Approved by: cognet (mentor)
* Allow building LINT by defining both SAMPLE_AT_RESET on the one handmarcel2012-11-271-3/+4
| | | | | and SAMPLE_AT_RESET_{LO|HI} on the other. It doesn't matter which values they take, as long as they are defined.
* Merge the FDT versions of initarm.andrew2012-11-031-490/+6
| | | | | | | | | The copies of initarm used on platforms with FDT support were almost identical. The differences were pulled out into separate functions that were called by initarm. This change merges the, now identical, copies of initarm and a few of it's support functions. This is a step towards a common kernel on ARMv6.
* Fix build for SMP.cognet2012-11-011-1/+1
| | | | Submitted by: Giovanni Trematerra <gianni at freebsd DOT org>
* Merge r242125 into the other ARMv6 copies of initarm.andrew2012-10-311-0/+5
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* Pull out the SoC specific parts of initarm into separate functionsandrew2012-09-231-21/+42
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* Reduce the diff between the FDT implementations of initarm.andrew2012-09-221-6/+6
| | | | This only touches whitespace and comments.
* Create a common set_stackptrs in sys/arm/machdep.c.andrew2012-09-221-19/+0
| | | | | | | On single core devices set_stackptrs is only ever called with cpu = 0 in initarm and will be identical to the existing function. On SMP this needs to be implemented for sys/arm/mp_machdep.c, but the implementations are identical for each SoC.
* Implement MSI support.gber2012-09-141-2/+101
| | | | | | | | | | MSI are implemented via Inbound Shared Doorbell 1 interrupts. Interrupts are triggered by writing to Software Triggered Interrupt registeri (PCIe card using physical address of this register in BAR0 space). There are 32 interrupts available. It can be increased by using Doorbell 2 and Doorbell 3 registers to 96 interrupts. Obtained from: Marvell, Semihalf
* Add support for MSI in interrupt controlller.gber2012-09-142-18/+113
| | | | | | | | MSI are implemented via software interrupt. PCIe cards will write into software interrupt register which will cause inbound shared interrupt which will be interpreted as a MSI. Obtained from: Marvell, Semihalf
* Remove unused structure fieldsgber2012-09-141-2/+0
| | | | Obtained from: Semihalf
* Enable PCI for Armada XPgber2012-09-141-8/+0
| | | | Obtained from: Semihalf
* pci: Implement new memory and io space allocator for PCI.gber2012-09-142-110/+235
| | | | | | | Cleanup code and move initializing bridge into separate function. Add checking of PCI mode (RC or endpoint). Obtained from: Semihalf
* Add support for Armada XP A0.gber2012-09-146-11/+202
| | | | | | | | | | - Add functions to calculate clocks instead using hardcoded values - Update reset and timers functions - Update number of interrupts - Change name of platform from db88f78100 to db78460 - Correct DRAM size and PCI IRQ routing in dts file. Obtained from: Semihalf
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