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* Implement barriers for AMRv6 and ARMv7gonzo2013-01-071-3/+19
| | | | | Submitted by: Daisuke Aoyama <aoyama at peach.ne.jp> Reviewed by: ian, cognet
* Only work around errata when we are on a part where the erratum applies.andrew2013-01-061-0/+1
| | | | Reviewed by: gonzo
* Add hw.board.serial and hw.board.revision for exporting board-specific infogonzo2013-01-051-0/+4
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* Document the known values of the RTL release field in the cache is registerandrew2013-01-011-0/+8
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* PL310 driver update:gonzo2012-12-311-1/+122
| | | | | | | | | | | | | | | | | - Add pl310.disable tunable to disable L2 cache altogether. In order to make sure that it's 100% disabled we use cache event counters for cache line eviction and read allocate events and panic if any of these counters increased. This is purely for debugging purpose - Direct access DEBUG_CTRL and CTRL might be unavailable in unsecure mode, so use platform-specific functions for these registers - Replace #if 1 with proper erratum numbers - Add erratum 753970 workaround - Remove wait function for atomic operations - Protect cache operations with spin mutex in order to prevent race condition - Disable instruction cache prefetch and make sure data cache prefetch is enabled in OMAP4-specific intialization
* Replace generic ARM11 option with more specificgonzo2012-12-204-5/+48
| | | | | | | support for ARM1136 and ARM1176 Submitted by: Daisuke Aoyama <aoyama at peach.ne.jp> Obtained from: NetBSD
* Fix misleading commentgonzo2012-12-201-1/+1
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* Properly implement pmap_[get|set]_memattrcognet2012-12-192-3/+5
| | | | Submitted by: Ian Lepore <freebsd@damnhippie.dyndns.org>
* Don't define intr_disable and intr_restore as macros. The macrosmarcel2012-11-271-8/+24
| | | | | | | | | | | | interfere with structure fields of the same name in drivers, like the intr_disable function pointer in struct cphy_ops in cxgb(4). Instead define intr_disable and intr_restore as inline functions. With intr_disable() an inline function, the I32_bit and F32_bit macros now need to be visible in MI code and given the rather poor names, this is not at all good. Define ARM_CPSR_F32 and ARM_CPSR_I32 and use that instead of F32_bit and I32_bit (resp) for now.
* Merge the FDT versions of initarm.andrew2012-11-031-0/+4
| | | | | | | | | The copies of initarm used on platforms with FDT support were almost identical. The differences were pulled out into separate functions that were called by initarm. This change merges the, now identical, copies of initarm and a few of it's support functions. This is a step towards a common kernel on ARMv6.
* Fix the clobber list on the atomic operators that do comparisons. Withoutandrew2012-10-011-15/+17
| | | | | | this some compilers will place a cmp instruction before the atomic operation and expect to be able to use the result afterwards. By adding "cc" to the list of used registers we tell the compiler to not do this.
* Eliminate an unused declaration.alc2012-09-291-2/+0
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* Implementing pmap_kextract(va) as pmap_extract(kernel_pmap, va) isalc2012-09-271-2/+2
| | | | | | | | | | | | | | problematic because some callers to pmap_kextract() expect its implementation to be lock-less. In particular, uma_dbg_alloc() implicitly requires this. Otherwise, lock-order reversals occur between pmap locks and UMA zone locks. So, this change introduces a lock-less implementation of pmap_kextract(). Disable recursion on the pvh global lock in the new armv6 pmap. While recursion on this locks occurs in the old arm pmap, it thankfully doesn't occur in the armv6 pmap. Tested by: jmg
* Pull out the SoC specific parts of initarm into separate functionsandrew2012-09-231-0/+5
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* Create a common set_stackptrs in sys/arm/machdep.c.andrew2012-09-221-0/+11
| | | | | | | On single core devices set_stackptrs is only ever called with cpu = 0 in initarm and will be identical to the existing function. On SMP this needs to be implemented for sys/arm/mp_machdep.c, but the implementations are identical for each SoC.
* Add support for MSI in interrupt controlller.gber2012-09-141-1/+6
| | | | | | | | MSI are implemented via software interrupt. PCIe cards will write into software interrupt register which will cause inbound shared interrupt which will be interpreted as a MSI. Obtained from: Marvell, Semihalf
* Add support for Armada XP A0.gber2012-09-141-0/+2
| | | | | | | | | | - Add functions to calculate clocks instead using hardcoded values - Update reset and timers functions - Update number of interrupts - Change name of platform from db88f78100 to db78460 - Correct DRAM size and PCI IRQ routing in dts file. Obtained from: Semihalf
* Support identification of new PJ4B cores.gber2012-09-141-2/+3
| | | | Obtained from: Semihalf
* Eliminate an unused macro.alc2012-09-071-7/+0
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* Add support for ARM11 cpufuncgonzo2012-08-261-0/+7
| | | | Obtained from: NetBSD (partially)
* Piggyback MIPS changes and add ARM syscons support for devices withgonzo2012-08-251-0/+71
| | | | | | framebuffer While here - sort #if defined() order alphabetically
* ARM11 might have more then 32 interrupts, e.g. BCM2835: 72 interruptsgonzo2012-08-251-0/+2
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* Merging projects/armv6, part 1gonzo2012-08-1519-161/+1196
| | | | | | | | | Cummulative patch of changes that are not vendor-specific: - ARMv6 and ARMv7 architecture support - ARM SMP support - VFP/Neon support - ARM Generic Interrupt Controller driver - Simplification of startup code for all platforms
* Revert committal of local change accidentally swept up in r238329.imp2012-07-101-3/+1
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* Remove some unused variables/externs that have been copied too many times...imp2012-07-101-1/+3
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* Create a generic way to support multiple boards within animp2012-07-071-0/+62
| | | | | | arm platform. Add all the atmel boards to the ATMEL kernel for testing purposes. Until boot loader arg parsing of baord type is done, this won't actually be able to do the runtime selection.
* Make the wchar_t type machine dependent.andrew2012-06-242-6/+10
| | | | | | | | | | | | | | This is required for ARM EABI. Section 7.1.1 of the Procedure Call for the ARM Architecture (AAPCS) defines wchar_t as either an unsigned int or an unsigned short with the former preferred. Because of this requirement we need to move the definition of __wchar_t to a machine dependent header. It also cleans up the macros defining the limits of wchar_t by defining __WCHAR_MIN and __WCHAR_MAX in the same machine dependent header then using them to define WCHAR_MIN and WCHAR_MAX respectively. Discussed with: bde
* Implement mechanism to export some kernel timekeeping data tokib2012-06-221-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | usermode, using shared page. The structures and functions have vdso prefix, to indicate the intended location of the code in some future. The versioned per-algorithm data is exported in the format of struct vdso_timehands, which mostly repeats the content of in-kernel struct timehands. Usermode reading of the structure can be lockless. Compatibility export for 32bit processes on 64bit host is also provided. Kernel also provides usermode with indication about currently used timecounter, so that libc can fall back to syscall if configured timecounter is unknown to usermode code. The shared data updates are initiated both from the tc_windup(), where a fast task is queued to do the update, and from sysctl handlers which change timecounter. A manual override switch kern.timecounter.fast_gettime allows to turn off the mechanism. Only x86 architectures export the real algorithm data, and there, only for tsc timecounter. HPET counters page could be exported as well, but I prefer to not further glue the kernel and libc ABI there until proper vdso-based solution is developed. Minimal stubs neccessary for non-x86 architectures to still compile are provided. Discussed with: bde Reviewed by: jhb Tested by: flo MFC after: 1 month
* Reserve AT_TIMEKEEP auxv entry for providing usermode the pointer tokib2012-06-221-0/+1
| | | | | | timekeeping information. MFC after: 1 week
* The page flag PGA_WRITEABLE is set and cleared exclusively by the pmapalc2012-06-161-0/+1
| | | | | | | | | | | | | | | | layer, but it is read directly by the MI VM layer. This change introduces pmap_page_is_write_mapped() in order to completely encapsulate all direct access to PGA_WRITEABLE in the pmap layer. Aesthetics aside, I am making this change because amd64 will likely begin using an alternative method to track write mappings, and having pmap_page_is_write_mapped() in place allows me to make such a change without further modification to the MI VM layer. As an added bonus, tidy up some nearby comments concerning page flags. Reviewed by: kib MFC after: 6 weeks
* Defines for parsing linux ATAGs lists.imp2012-06-141-0/+129
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* More Linux boot support. Create arm_dump_avail_init() to initializeimp2012-06-141-0/+5
| | | | | | this array either from Linux boot data, when enabled, or in the typical way that most ports do it. arm_pyhs_avail_init is coming soon since it must be a separate function.
* Add support for parsing Linux ATAGs such as you'd see from uboot orimp2012-06-141-0/+2
| | | | | | | redboot. Support is very preiminary and likely needs some work. Also, do some minor code shuffling of the FreeBSD /boot/loader metadata parsing code. This code is preliminary and should be used with caution.
* Create default_parse_boot_param which, if FreeBSD /boot/loader supportimp2012-06-141-3/+3
| | | | | | | | | is enabled, sets values based on the metadata passed in. Otherwise fake_preload_metadata is called. Change the default parse_boot_param to default_parse_boot_param. Enable this functionality only on the mv platform, which is where most of the code is from. Reviewed by: cognet, Ian Lapore
* Modify all the arm platform files to call parse_boot_param passing inimp2012-06-141-1/+4
| | | | | | | | | | | | | the boot parameters from initarm first thing. parse_boot_param parses the boot arguments and converts them to the /boot/loader metadata the rest of the kernel uses. parse_boot_param is a weak alias to fake_preload_metadata, which all the platforms use now, but may become more extensive in the future. Since it is a weak symbol, specific boards may define their own parse_boot_param to interface to custom boot loaders. Reviewed by: cognet@, Ian Lapore
* Add ARM callchain support for hwpmc.fabient2012-06-131-3/+11
| | | | | Sponsored by: NETASQ MFC after: 3 days
* trim trailing whitespaceimp2012-06-1321-36/+33
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* Pull out the common code to initialise proc0 & thread0 from initarm to aandrew2012-06-101-0/+1
| | | | | | common function. Reviewed by: imp
* Minor rearrangement of the locore <-> initarm interface. Pass in aimp2012-06-031-6/+14
| | | | | | structure with the first 4 registers to allow a wider range of boot loaders to work. Future commits will make use of this to centralize support for the different loaders.
* Flush D and I caches after setting a breakpoint.gber2012-05-301-0/+3
| | | | | Reviewed by: imp Obtained from: Semihalf
* MFp4 bz_ipv6_fast:bz2012-05-241-0/+2
| | | | | | | | | | | | | | | | | | | | in_cksum.h required ip.h to be included for struct ip. To be able to use some general checksum functions like in_addword() in a non-IPv4 context, limit the (also exported to user space) IPv4 specific functions to the times, when the ip.h header is present and IPVERSION is defined (to 4). We should consider more general checksum (updating) functions to also allow easier incremental checksum updates in the L3/4 stack and firewalls, as well as ponder further requirements by certain NIC drivers needing slightly different pseudo values in offloading cases. Thinking in terms of a better "library". Sponsored by: The FreeBSD Foundation Sponsored by: iXsystems Reviewed by: gnn (as part of the whole) MFC After: 3 days
* Soft PMC support for ARM.fabient2012-05-231-0/+6
| | | | | | Callgraph is not captured, only current location. Sample system wide profiling: "pmcstat -Sclock.hard -T"
* Add architecture dependent code to support NAND Framework on Marvell SoCs.gber2012-05-181-0/+1
| | | | | Obtained from: Semihalf Supported by: FreeBSD Foundation, Juniper Networks
* Fix the MACHINE_ARCH for big endian arm to be armeb.imp2012-05-061-0/+4
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* Add a convenience macro for the returns_twice attribute, and apply it todim2012-04-291-1/+1
| | | | | | | the prototypes of the appropriate functions (getcontext, savectx, setjmp, sigsetjmp and vfork). MFC after: 2 weeks
* Replace the C implementation of __aeabi_read_tp with an assembly version.andrew2012-04-162-0/+7
| | | | | | This ensures we follow the ABI by preserving registers r1-r3. Reviewed by: jmallett, imp
* - Revert part of r234005, which I did not intend to commit.stas2012-04-071-1/+1
| | | | Sorry! :(
* - Add kernel config file for QEMU-emulated gumstix board.stas2012-04-071-1/+1
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* Add software PMC support.fabient2012-03-281-1/+1
| | | | | | | | | | | | | New kernel events can be added at various location for sampling or counting. This will for example allow easy system profiling whatever the processor is with known tools like pmcstat(8). Simultaneous usage of software PMC and hardware PMC is possible, for example looking at the lock acquire failure, page fault while sampling on instructions. Sponsored by: NETASQ MFC after: 1 month
* Add C11 macros describing subnormal numbers to float.h.das2012-01-231-0/+16
| | | | Reviewed by: bde
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