summaryrefslogtreecommitdiffstats
path: root/sys/arm/include
Commit message (Collapse)AuthorAgeFilesLines
* Add dl_unwind_find_exidx() for ARM EABI, required for C++ exceptionian2014-07-191-0/+3
| | | | | | | | | | | | | | | | handling. For statically linked apps this uses the __exidx_start/end symbols set up by the linker. For dynamically linked apps it finds the shared object that contains the given address and returns the location and size of the exidx section in that shared object. The dl_unwind_find_exidx() name is used by other BSD projects and Android, and is mentioned in clang 3.5 comments as "the BSD interface" for finding exidx data. GCC (in libgcc_s) expects the exact same API and functionality to be provided by a function named __gnu_Unwind_Find_exidx(), so we provide that with an alias ("strong reference"). Reviewed by: kib@ MFC after: 1 week
* Different versions of the ARM processor use different registers.tuexen2014-06-171-0/+9
| | | | | | Fix the code used on a Raspberry Pi. Reviewed by: markm@
* Delete obsolete and unused PJ4B CPU functionszbb2014-05-251-9/+0
| | | | | Since PJ4Bv7 uses armv7_ CPU functions only pj4b_config function is necessary. Remove obsolete routines.
* Eliminate one of the causes of spurious interrupts on armv6. The arm weakian2014-05-241-0/+2
| | | | | | | | | | | | | | memory ordering model allows writes to different devices to complete out of order, leading to a situation where the write that clears an interrupt source at a device can complete after a write that unmasks and EOIs the interrupt at the interrupt controller, leading to a spurious re-interrupt. This adds a generic barrier function specific to the needs of interrupt controllers, and calls that function from the GIC and TI AINTC controllers. There may still be other soc-specific controllers that need to make the call. Reviewed by: cognet, Svatopluk Kraus <onwahe@gmail.com> MFC after: 3 days
* Remove NetBSD implementation details not relevant to FreeBSD.imp2014-05-231-8/+0
|
* Add FDT_PLATFORM_DEF2 for when there are multiple platforms needing to useandrew2014-05-171-15/+18
| | | | the same platform methods.
* Fix a comment s/initarm_/platform_/andrew2014-05-171-1/+1
|
* Add the start of the ARM platform code. This is based on the PowerPCandrew2014-05-173-34/+142
| | | | | | | | | | platform code, it is expected these will be merged in the future when the ARM code is more complete. Until more boards can be tested only use this with the Raspberry Pi and rrename the functions on the other SoCs. Reviewed by: ian@
* Give suitably-endowed ARMs a register similar to the x86 TSC register.markm2014-05-141-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Here, "suitably endowed" means that the System Control Coprocessor (#15) has Performance Monitoring Registers, including a CCNT (Cycle Count) register. The CCNT register is used in a way similar to the TSC register in x86 processors by the get_cyclecount(9) function. The entropy-harvesting thread is a heavy user of this function, and will benefit from not having to call binuptime(9) instead. One problem with the CCNT register is that it is 32-bit only, so the upper 32-bits of the returned number are always 0. The entropy harvester does not care, but in case any one else does, follow-up work may include an interrup trap to increment an upper-32-bit counter on CCNT overflow. Another problem is that the CCNT register is not readable in user-mode code; in can be made readable by userland, but then it is also writable, and so is a good chunk of the PMU system. For that reason, the CCNT is not enabled for user-mode access in this commit. Like the x86, there is one CCNT per core, so they don't all run in perfect sync. Reviewed by: ian@ (an earlier version) Tested by: ian@ (same earlier version) Committed from: WANDBOARD-QUAD
* Add cpu_l2cache_drain_writebuf(), use it to implement generic_bs_barrier().ian2014-05-111-0/+2
| | | | | | | | | | | | | | | | | | | | On modern ARM SoCs the L2 cache controller sits between the CPU and the AXI bus, and most on-chip memory-mapped devices are on the AXI bus. We map the device registers using the 'Device' memory attribute, which means the memory is not cached, but writes to it are buffered. Ensuring that a write has made it all the way to a device may require that the L2 controller take some action. There is currently only one implementation of the new function, for the PL310 cache controller. It invokes a function that the controller manual calls "cache sync" but it actually has nothing to do with cache at all, it triggers a drain of all pending store buffer writes and it blocks until they complete. The sheeva and xscale L2 controllers (which predate the concept of Device memory) don't seem to have a corresponding function. It appears that the standard armv5 drain_writebuf function includes draining all the way through the L2 controller.
* Make the hardware memory and instruction barrier functions work on armv4ian2014-05-111-3/+3
| | | | and armv5 as well.
* Add a public routine to set the L2 cache ram latencies. This can beian2014-05-061-0/+13
| | | | called by platform init routines to fine-tune cache performance.
* Add defines for the bits in the PL310 debug control register.ian2014-05-061-0/+2
| | | | This should have been part of r265444.
* Make this declaration into a proper function prototype.ian2014-04-291-1/+1
|
* Move duplicated code to print l2 cache config into the common code.ian2014-04-271-0/+2
|
* There is no difference between IPI_STOP and IPI_STOP_HARD on ARM, soian2014-04-271-1/+1
| | | | map them both to the same interrupt number like other arches do.
* Remove cpu_idcache_wbinv_all() from kdb_cpu_trap(), it's no longer needed.ian2014-04-271-2/+0
| | | | | | | This was added ca. 2004 for the purpose of ensuring the caches were in the right state after the debugger set a breakpoint. kdb_cpu_sync_icache() was added in 2007 to handle that situation, and now the wbinv_all is actually harmful because the operation isn't broadcast to other cores.
* Provide a proper armv7 implementation of icache_sync_all rather thanian2014-04-271-0/+1
| | | | | | | | | | using armv7_idcache_wbinv_all, because wbinv_all doesn't broadcast the operation to other cores. In elf_cpu_load_file() use icache_sync_all() and explain why it's needed (and why other sync operations aren't). As part of doing this, all callers of cpu_icache_sync_all() were inspected to ensure they weren't relying on the old side effect of doing a wbinv_all along with the icache work.
* Call cpu_icache_sync_range() rather than sync_all since we know the rangeian2014-04-261-1/+1
| | | | and flushing the entire icache is needlessly expensive.
* Tell VM we now have ARM platforms with physically discontiguous memory.ian2014-04-061-2/+2
|
* We don't support any ARM systems with an ISA bus and don't need a freelistian2014-04-041-7/+2
| | | | of memory to support ISA addressing limitations.
* Rename __wchar_t so it no longer conflicts with __wchar_t from clang 3.4tijl2014-04-011-2/+2
| | | | | | -fms-extensions. MFC after: 2 weeks
* Add Cortex-A15 cpu id revisions.br2014-04-011-1/+4
|
* VFP fixes/cleanups for ARM11:andrew2014-03-291-0/+3
| | | | | | | | | | | * Save the required VFP registers on context switch. If the exception bit is set we need to save and restore the FPINST register, and if the fp2v bit is also set we need to save and restore FPINST2. * Move saving and restoring the floating point control registers to C. * Clear the fpexc exception and fp2v flags on a floating-point exception. * Signal a SIGFPE if the fpexc exception flag is set on an undefined instruction. This is how the ARM core signals to software there is a floating-point exception.
* Add more flags for the fpexc register from the ARM1176JZF-S Manualandrew2014-03-291-0/+5
|
* Move an else case that was missed in r263676andrew2014-03-241-25/+25
|
* Reorder the pmap macros so "ARM_MMU_V6 + ARM_MMU_V7" is first. As they areandrew2014-03-231-41/+42
| | | | identical this allows us to build for both v6 and v7 together.
* Simplify how we build MACHINE_ARCH. There are 3 options that may be setandrew2014-03-221-9/+15
| | | | however only arm, armeb, armv6, and soon armv6hf will be used.
* Remove #include <machine/asmacros.h> from files that don't need it.ian2014-03-111-1/+1
|
* Remove the unreferenced DATA() macro. That leaves only GET_CURTHREAD_PTR()ian2014-03-111-26/+8
| | | | | | | which was added by cognet in 2012, so remove the no-longer-applicable license stuff that referred to all the old contents, and put in a standard 2-clause BSD license (to cover the 6 lines of useful code left in here).
* Arrange for arm fork_trampoline() to return to userland via the standardian2014-03-101-208/+0
| | | | | | | swi_exit code in exception.S instead of having its own inline expansion of the DO_AST and PULLFRAME macros. That means that now all references to the PUSH/PULLFRAME and DO_AST macros are localized to exception.S, so move the macros themselves into there and remove them from asmacros.h
* Change the way the asm GET_CURTHREAD_PTR() macro is defined so that codeian2014-03-101-7/+4
| | | | using it doesn't have to have an "AST_LOCALS" macro somewhere in the file.
* Remove all traces of support for ARM chips prior to the arm9 series. Weian2014-03-096-209/+13
| | | | | | | never actually ran on these chips (other than using SA1 support in an emulator to do the early porting to FreeBSD long long ago). The clutter and complexity of some of this code keeps getting in the way of other maintenance, so it's time to go.
* Always call vfp_discard() on thread death, not just when the VFP isian2014-03-091-1/+1
| | | | | | | | | enabled. In vfp_discard(), if the state in the VFP hardware belongs to the thread which is dying, NULL out pcpu fpcurthread to indicate the state currently in the hardware belongs to nobody. Submitted by: Juergen Weiss Pointy hat to: me
* Remove all dregs of a per-thread undefined-exception-mode stack. This isian2014-03-092-5/+2
| | | | | | | | | | | | | | | | | | a leftover from the days when a low-level debugger had hooks in the undefined exception vector and needed stack space to function. These days it effectively isn't used because we switch immediately to the svc32 mode stack on exception entry. For that, the single undef mode stack per core that gets set up at init time works fine. The stack wasn't necessary but it was harmful, because the space for it was carved out of the normal per-thread svc32 stack, in effect cutting that 8K stack in half. If svc32 mode used more than 4k of stack space it wandered down into the undef mode stack, and then an undef exception would overwrite a couple words on the stack while switching to svc32 mode, corrupting the scv32 stack. Having another stack abut the bottom of the svc32 stack also effectively mooted the guard page below the stack. This work is based on analysis and patches submitted by Juergen Weiss.
* Rework the VFP code that handles demand-based save and restore of state.ian2014-03-092-2/+5
| | | | | | | | | | | | | | | | | | | The old code was full of complexity that would only matter if the kernel itself used the VFP hardware. Now that's reduced to either killing the userland process or panicking the kernel on an illegal VFP instruction. This removes most of the complexity from the assembler code, reducing it to just calling the save code if the outgoing thread used the VFP. The routine that stores the VFP state now takes a flag that indicates whether the hardware should be disabled after saving state. Right now it always is, but this makes the code ready to be used by get/set_mcontext() (doing so will be addressed in a future commit). Remove the arm-specific pc_vfpcthread from struct pcpu and use the MI field pc_fpcurthread instead. Reviewed by: cognet
* Add an armv7 implementation of cpu_sleep(). The arm11/armv6 implementationian2014-02-281-0/+1
| | | | | | we've been using was actually just spinning due to ARM having redefined the old 'wait for interrupt' operation via the system coprocessor as a nop and replacing it with a WFI instruction.
* Replace many pasted identical definitions of cpu_initclocks() with a commonian2014-02-261-0/+1
| | | | | | | | implementation in arm/machdep.c. Most arm platforms either don't need to do anything, or just need to call the standard eventtimer init routines. A generic implementation that does that is now provided via weak linkage. Any platform that needs to do something different can provide a its own implementation to override the generic one.
* Add a new cache maintenance function, idcache_inv_all, to the table, andian2014-02-241-0/+11
| | | | | | | implementations for each of the chips we support. Most chips up through armv6 can use the armv4 implementation which has a single coprocessor opcode for this operation. The rather more complex armv7 implementation comes from netbsd.
* Move the declaration for mpentry() into a header file instead of pastingian2014-02-231-0/+1
| | | | | | | it into a bunch of different .c files. Remove declarations for the unused mptramp() function from everywhere except AramadaXP (and I think it's really not used there either, because the code that references it appears to be insanely does-nothing in nature).
* Give the fdt helper routines static linkage since no global definitionian2014-02-171-2/+2
| | | | | of them is provided anywhere. (gcc was nice enough to warn about this, clang didn't for some reason.)
* Always clear L1 PTE descriptor when removing superpage on ARMzbb2014-02-151-0/+1
| | | | | | | Invalidate L1 PTE regardles of existance of the corresponding l2_bucket. This is relevant when superpage is entered via pmap_enter_object() and will fix crash on entering page in place of not properly removed superpage.
* Use the right symbols for determining arm architecture. Include theian2014-02-121-0/+2
| | | | necessary header file which has the new FAULT_WNR symbol defined in it.
* Pass the pagetable used from locore.S to initarm to allow it to map dataandrew2014-02-091-0/+6
| | | | in as required.
* Use vm_paddr_t, not vm_offset_t, when dealing with physical addresses.ian2014-02-091-3/+3
| | | | Pointed out by: alc
* It turns out a global variable is the only straightforward way toian2014-02-091-0/+5
| | | | | | | | | | | communicate the kernel's physical load address from where it's known in initarm() into cpu_mp_start() which is called from non-arm code and takes no parameters. This adds the global variable and ensures that all the various copies of initarm() set it. It uses the variable in cpu_mp_start(), eliminating the last uses of KERNPHYSADDR outside of locore.S (where we can now calculate it instead of relying on the constant).
* Consolidate code related to setting up physical memory configuration intoian2014-02-082-3/+86
| | | | | | | | | | | | | | a new physmem.c file. The new code provides helper routines that can be used by legacy SoCs and newer FDT-based systems. There are routines to add one or more regions of physically contiguous ram, and exclude one or more physically contiguous regions of ram. Ram can be excluded from crash dumps, from being given over to the vm system for allocation management, or both. After all the included and excluded regions have been added, arm_physmem_init_kernel_globals() processes the regions into the global dump_avail and phys_avail arrays and realmem and physmem variables that communicate memory configuration to the rest of the kernel. Convert all existing SoCs to use the new helper code.
* Remove the ARM_USE_SMALL_ALLOC option and code related to it.ian2014-02-083-66/+6
| | | | | | | | | | This was an optimization used only by a few xscale platforms. Part of the optimization was to create a direct map for all physical pages, and that resulted in making multiple mappings of pages in a way that bypassed the logic in pmap.c to handle VIVT cache aliasing. It also just generally made the code more complex and hard to maintain for all SoCs. Reviewed by: cognet
* Use abp_physaddr for the physical address over KERNPHYSADDR. This helps usandrew2014-02-061-1/+1
| | | | remove the need to load the kernel at a fixed address.
* Pass the kernel physical address to initarm through the boot param struct.andrew2014-02-061-0/+1
|
OpenPOWER on IntegriCloud