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* Remove the unused major/minor numbers from iodev and memdev.ed2008-06-251-1/+0
* Support for the XScale PXA255 SoC as found on the Gumstix Basix and Connexbenno2008-06-061-0/+3
* On the AT91, we need to write on the EOI register after we handle ancognet2008-04-201-0/+1
* Take the first baby step towards unifying and cleaning up arminit():imp2008-04-031-5/+5
* When building a kernel module, define MAXCPU the same as SMP sojb2008-03-271-2/+2
* Remove unused pv_list_count from the vm_page, and pm_count from the structcognet2008-03-061-2/+0
* Remove errant % in license comment.rwatson2008-02-261-1/+1
* Improve ARM_TP_ADDRESS and RAS area.raj2008-02-053-60/+47
* Bring in the nice work from Mark Tinguely on arm pmap.cognet2008-01-311-15/+2
* Add configuration knobs for the superpage reservation system. Initially,alc2007-12-271-0/+7
* Add stubs to unbreak LINT.jkoshy2007-12-071-0/+4
* Break out stack(9) from ddb(4):rwatson2007-12-021-0/+42
* Close a race.cognet2007-12-022-19/+49
* In atomic_fetchadd_32(), do not blindly increase the value of %3.cognet2007-11-271-2/+3
* __CPU_XSCALE_PXA2XX -> CPU_XSCALE_PXA2X0kevlo2007-11-011-1/+1
* Merge support from p4 (from NetBSD) for arm9e and arm10, arm11 cores. Notimp2007-10-182-10/+88
* Merge definitions for ARM9E, ARM10 and ARM11 processors from p4 (whichimp2007-10-181-2/+14
* Define _ARM_ARCH_5E too, so that we know if pld/strd/ldrd are available.cognet2007-10-131-1/+6
* Change the management of cached pages (PQ_CACHE) in two fundamentalalc2007-09-251-2/+3
* Twist the RAS logic a bit to avoid branching.cognet2007-09-221-12/+9
* In __bswap16_var(), make sure the 16 upper bits are cleared; whilecognet2007-09-091-2/+4
* XScale core 3 definitions.cognet2007-07-271-0/+5
* Fix the cache mode description.cognet2007-07-271-5/+5
* Properly handle supersections.cognet2007-07-271-4/+20
* Add a new set of functions to handle L2 cache. Make them no-op for everycognet2007-07-271-9/+20
* The iop34x has 128 interrupts.cognet2007-06-161-1/+3
* Introduce pmap_kenter_supersection(), which maps 16MB super-sections intocognet2007-06-112-0/+69
* Add kdb_cpu_sync_icache(), intended to synchronize instructionmarcel2007-06-091-0/+5
* - PCPU_ADD is no longer spelled with LAZY_ in the middle.jeff2007-06-061-1/+1
* Rework the PCPU_* (MD) interface:attilio2007-06-041-1/+2
* Add the machine-specific definitions for configuring the new physicalalc2007-06-041-0/+15
* Eliminate some unused definitions that came from NetBSD.alc2007-05-281-19/+0
* Use __mcount() instead of _mcount() to reduce diffs with NetBSD.cognet2007-05-192-4/+4
* Switch the kernel's pmap domain from 15 to 0.cognet2007-05-191-2/+2
* Define every architecture as either VM_PHYSSEG_DENSE oralc2007-05-051-0/+5
* Remove __Pkevlo2007-03-213-18/+18
* Push down the implementation of PCPU_LAZY_INC() into the machine-dependentalc2007-03-111-0/+6
* o break newbus api: add a new argument of type driver_filter_t topiso2007-02-231-2/+2
* - Add bounce pages for arm, largely based on the i386 implementation.cognet2007-01-173-1/+6
* MFp4: Add missing atomic functionsticso2007-01-051-34/+64
* Introduce CPU_XSCALE_CORE3, as XScale Core 3 is significally different thancognet2006-11-301-0/+3
* correct bus space unmap prototypesam2006-11-191-29/+141
* Fix a comment.ru2006-11-131-1/+1
* Eliminate unused global variables.alc2006-11-111-3/+0
* Identify the xscale 81342.cognet2006-11-074-6/+30
* Add atomic_cmpset_acq_32.cognet2006-11-071-0/+1
* PR:jb2006-10-041-34/+0
* First part of a little cleanup in the calendar/timezone/RTC handling.phk2006-10-021-3/+0
* Use __builtin_va_start instead of __builtin_stdarg_start. GCC4 obsoleteskan2006-09-211-1/+1
* Remove dead code, already defined in sys/cdef.hcognet2006-08-301-9/+0
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