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* MFC r270882, r270930:ian2014-09-091-1/+1
| | | | | | | | | | | | | In ARM asm code, ensure that every ENTRY(foo) has a matching END(foo). The EABI unwind info requires a .fnend for every .fnstart, and newer binutils will complain about seeing two .fnstart in a row. This change allows newer tools to compile our code. Do not generate unwind info in asm functions if _STANDALONE is defined. The .fnend op causes the assembler to emit RELOC references to unwind support functions that don't exist in libstand. Approved by: re(gjb)
* MFC r270862, r270878: MMU fixes for kernel startup.ian2014-09-091-2/+2
| | | | | | | | | | Fix the handling of MMU type in the AP entry code. The ARM_MMU_V6/V7 symbols are always #defined to 0 or 1, so use #if SYM not #if defined(SYM). Also, it helps if you include the header file that defines the symbols. The Marvell PJ4B cpu family is armv7, not armv6. Approved by: re(gjb)
* MFC r269594, r269596, r269597, r269598, r269605, r269606:ian2014-08-171-0/+3
| | | | | | | | | | | | | | | | | | | | | Set ofwbus and simplebus to attach during BUS_PASS_BUS. Define names that drivers can use to adjust their position relative to other drivers within a BUS_PASS Adjust ofwbus and simplebus to attach at BUS_PASS_ORDER_MIDDLE, so that a platform can attach some other bus first if necessary. Set the pl310 L2 cache driver to attach during the middle of BUS_PASS_CPU. Attach arm generic interrupt and timer drivers in the middle of BUS_PASS_INTERRUPT and BUS_PASS_TIMER, respectively. Add an arm option, ARM_DEVICE_MULTIPASS, used to opt-in to multi-pass device attachment on arm platforms. If this is defined, nexus attaches early in BUS_PASS_BUS, and other busses and devices attach later, in the pass number they are set up for. Without it defined, nexus attaches in BUS_PASS_DEFAULT and thus so does everything else, which is status quo.
* MFC r269403, r269405, r269410, r269414:ian2014-08-111-0/+321
| | | | | | Add 64-bit atomic ops for armv6, and also for armv4 only in kernel code. Use the new ops in the cddl code (and avoid defining functions with the same names locally).
* MFC r269390: Fix unwind info in hand-written asm (avoid nested functions).ian2014-08-111-1/+18
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* MFC r268993, r268893, r268994, plus partial r264070, r264082ian2014-08-101-0/+3
| | | | | | | | Fix C++ exception handling for ARM EABI. Just the part of r264070 that creates the FBSD_1.4 namespace in libc is hand-applied, and then r264082 which creates the Versions.def entry is MFC'd.
* MFC 266621: Eliminte spurious interrupts caused by ARM weak memory ordering.ian2014-05-271-0/+2
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* MFC 257231:ian2014-05-181-1/+5
| | | | | Make sure the PCB is aligned on 8 bytes, we may use ldrd/strd to access it, which may have strong alignment requirements.
* MFC 257189:ian2014-05-181-1/+1
| | | | | Fix an itt instruction. We need to execute both the mov and b instructions when building for Thumb.
* MFC 265861, 265870:ian2014-05-182-3/+5
| | | | | | | Make the hardware memory and instruction barrier functions work on armv4 and armv5 as well. Add cpu_l2cache_drain_writebuf(), use it to implement generic_bs_barrier().
* MFC 265440, 265441, 265444, 265445, 265446, 265447:ian2014-05-181-0/+15
| | | | | | | | | | | | | | | | | | Move the pl310.enabled tunable to hw.pl310.enabled. Clean up a few minor style(9) nits. Use DEVMETHOD_END. Break out the code that figures out the L2 cache geometry to its own routine, so that it can be called from multiple places in upcoming changes. Call platform_pl310_init() before enabling the controller, and handle the case where the controller is already enabled. Add defines for the bits in the PL310 debug control register. Add a public routine to set the L2 cache ram latencies. This can be called by platform init routines to fine-tune cache performance. Enable PL310 power-saving modes and tune the cache ram latencies for imx6.
* MFC 265111: Make a declaration into a proper function prototype.ian2014-05-171-1/+1
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* MFC 265035: Move duplicated code to print l2 config into the common code.ian2014-05-171-0/+2
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* MFC 265023, 265024, 265036:ian2014-05-171-1/+1
| | | | | | | | | | There is no difference between IPI_STOP and IPI_STOP_HARD on ARM, so map them both to the same interrupt number like other arches do. Flush and invalidate caches on each CPU as part of handling IPI_STOP. Don't use multiprocessing-extensions instruction on processors that don't support SMP.
* MFC 264990, 264994, 265020, 265025:ian2014-05-172-3/+2
| | | | | | | | | | | | | | | | Call cpu_icache_sync_range() rather than sync_all since we know the range and flushing the entire icache is needlessly expensive. Provide a proper armv7 implementation of icache_sync_all rather than using armv7_idcache_wbinv_all, because wbinv_all doesn't broadcast the operation to other cores. In elf_cpu_load_file() use icache_sync_all() and explain why it's needed (and why other sync operations aren't). Remove cpu_idcache_wbinv_all() from kdb_cpu_trap(), it's no longer needed. Explain why wbinv_all is SMP-safe when dumping, and add a missing l2 cache flush. (Either it was missing here, or it isn't needed in the minidump case. Adding it here seems like the safer path to consistancy.)
* MFC 264203, 264204, 264206, 264218:ian2014-05-171-2/+2
| | | | | | | | Tell VM we now have ARM platforms with physically discontiguous memory. Define the full 1024M of ram on the imx51 and imx53 boards. Use a more professional uart device description.
* MFC 264128, 264129, 264130, 264135,ian2014-05-171-7/+2
| | | | | | | | | | | | | | | | | | | Fix TTB set operation for armv7. Perform sychronization (by "isb" barrier) after TTB is set. Fix TLB maintenance issues for armv6 and armv7. - Add cpu_cpwait to comply with the convention. - Add missing TLB invalidations, especially in pmap_kenter & pmap_kremove with distinguishing between D and ID pages. - Modify pmap init/bootstrap invalidations to ID, just to be safe. - Fix TLB-inv and PTE_SYNC ordering. Allocate per-cpu resources for doing pmap_zero_page() and pmap_copy_page(). This is performance enhancement rather than bugfix. We don't support any ARM systems with an ISA bus and don't need a freelist of memory to support ISA addressing limitations.
* MFC 263910, 263913, 263914, 263933, 263934, 263935, 263936, 263981, 263982,ian2014-05-173-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add more flags for the fpexc register from the ARM1176JZF-S Manual Initialise fpscr to a sane value when we create the pcb. This sets NaNs to be the default NaN and for denormalised numbers to be flushed to zero. VFP fixes/cleanups for ARM11: * Save the required VFP registers on context switch. If the exception bit is set we need to save and restore the FPINST register, and if the fp2v bit is also set we need to save and restore FPINST2. * Move saving and restoring the floating point control registers to C. * Clear the fpexc exception and fp2v flags on a floating-point exception. * Signal a SIGFPE if the fpexc exception flag is set on an undefined instruction. This is how the ARM core signals to software there is a floating-point exception. Add Cortex-A15 cpu id revisions. Exynos/Arndale... - Merge SoC-common parts - Enable iicbus device - Directly call kmem_alloc_contig to allocate framebuffer memory and pass VM_MEMATTR_UNCACHEABLE (no-cache, no-buffer). This fixes screen refreshing problem when data is updated too slowly. - Add support for keyboard used in Samsung Chromebook (ARM machine) Support covers device drivers for: - Interrupt Combiner - gpio/pad, External Interrupts Controller (pad) - I2C Interface - Chrome Embedded Controller - Chrome Keyboard - Use new gpio dev class in EHCI driver - Expand device tree information - Release i2c bus on detach.
* MFC 263631, 263637, 263664, 263676, 263679, 263698, 263711,ian2014-05-172-50/+57
| | | | | | | | | | | | | | | | | | Implement __flt_rounds for ARMv6 hard-float. The fpscr register stores the current rounding mode used by the VFP unit. Simplify how we build MACHINE_ARCH. There are 3 options that may be set however only arm, armeb, armv6, and soon armv6hf will be used. Add the llvm/clang patch for r263619. Reorder the pmap macros so "ARM_MMU_V6 + ARM_MMU_V7" is first. As they are identical this allows us to build for both v6 and v7 together. Add code for enabling second CPU core for A20 SoC. Enable SMP on Cubieboard2. Switch to freebsd.org emal address in copyright.
* MFC 262952, 262958, 262966, 262979, 262980, 262986, 262987, 262995, 262997,ian2014-05-178-450/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 263030, 263033, 263034, 263056, 263057, Remove all the redundant external declarations of exception vectors and runtime setting of the pointers that's scattered around various places. Remove all traces of support for ARM chips prior to the arm9 series. Make the default exception handler vectors point to where I thought they were already pointing: the default handlers (not a panic that says there is no default handler). Eliminate irq_dispatch.S. Move the data items it contained into arm/intr.c and the functionality it provided into arm/exception.S. Move the exception vector table (so-called "page0" data) into exception.S and eliminate vectors.S. Change the way the asm GET_CURTHREAD_PTR() macro is defined so that code using it doesn't have to have an "AST_LOCALS" macro somewhere in the file. Arrange for arm fork_trampoline() to return to userland via the standard swi_exit code in exception.S instead of having its own inline expansion of the DO_AST and PULLFRAME macros. Now that the PUSHFRAME and PULLFRAME macros are used only in the swi entry/exit code, they don't need to be macros. Except that didn't work and the whole change was reverted. Remove some unnecessary indirection and jump right to the handler functions. Use panic rather than printf to "handle" an arm26 address exception (should never happen on arm32). Remove the unreferenced DATA() macro. Remove #include <machine/asmacros.h> from files that don't need it.
* MFC 257774, 256760, 262916, 262905, 262918, 262919, 262920, 262921, 262924,ian2014-05-174-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 262925, 262929, 262932, 262935, 262940, 262941, 262942, 262948, 262949, 262950 Strip arm/conf/DEFAULTS down to just items that are mandatory for running the architecture. Move all the files named foo/common.c to foo/foo_common.c Initial cut for DTS on the hl201 board. Add commented out dts for sam9260ek as well as early printf support. Make clock optional on uart nodes, then back it out ("I don't know what I was thinking, but it is lame.") Set the baud rate if it isn't 0 Make at91_soc_id() public. Properly round at91 resource on unmapping. Move AT91 AIC related stuff to own file. Fix another bug in multicast filtering. i.MX uses 6 bits from MSB in LE CRC32 for the hash value, not the lowest 6 bits in BE CRC32. Follow r262916 with one more config file that references a renamed common.c Remove bogus AT91 define that causes compile errors. Most of the defines for SAM9X are going away soonish anyway (once FDT works), but until then... Remove all dregs of a per-thread undefined-exception-mode stack. Rework the VFP code that handles demand-based save and restore of state. Always call vfp_discard() on thread death. When a thread begins life it doesn't own the VFP hardware state on any cpu. Make undefined exception entry MP-safe.
* MFC r262534, r262548, r262549, r262552, r262568, r262581, r262583, r262584,ian2014-05-162-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | r262585, r262587, r262696, r262712 Replace many pasted identical definitions of cpu_initclocks() with a common implementation in arm/machdep.c. aicasm: Don't complain about missing prototypes to ease bootstrap issues. Vybrid: Add driver for Inter-Integrated Circuit (I2C). imx6: Initialize the Low Power Mode bits to keep the ARM cores running during WFI. All our current ARM multi-core systems have all cores in one package with a shared L2 cache, reflect that in the common cpu_topo() routine. mpcore timer: Supply a DELAY() implementation via weak linkage, so that SoC-specific code can supply a better implementation. imx6: Add some rudimentary voltage control. Add an armv7 implementation of cpu_sleep(). Add __used attribute so that the DELAY implementation doesn't get optimized away as unreferenced, causing linker errors when trying to resolve the weak reference to the missing function.
* MFC r257854 (discussed with alc@)ian2014-05-161-6/+11
| | | | | | | | | | | | | As of r257209, all architectures have defined VM_KMEM_SIZE_SCALE. In other words, every architecture is now auto-sizing the kmem arena. This revision changes kmeminit() so that the definition of VM_KMEM_SIZE_SCALE becomes mandatory and the definition of VM_KMEM_SIZE becomes optional. Replace or eliminate all existing definitions of VM_KMEM_SIZE. With auto-sizing enabled, VM_KMEM_SIZE effectively became an alternate spelling for VM_KMEM_SIZE_MIN on most architectures. Use VM_KMEM_SIZE_MIN for clarity.
* MFC r262409, r262411, r262413, r262420, r262426, r262427, r262440, r262456,ian2014-05-162-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | r262482, r262483, r262531, Move the declaration for mpentry() into a header file instead of pasting it into a bunch of different .c files. If the L2 cache type is PIPT, pass a physical address for a flush. Actually set the proper bit to indicate TTB shared memory. Add a new cache maintenance function, idcache_inv_all, to the table, and implementations for each of the chips we support. Invalidate caches immediately upon entry to init_secondary(). Also set the Bufferable bit in the PDE entries of the secondary processor startup pagetables. Add the bits needed to run SMP on imx6. Invalidate the SCU cache tag ram on all 4 cores, not just 1-3. Minor tweaks to the imx GPT timer Vybrid enhancements... - Pin configuration is a complete iomux register now and includes drive strength, pull mode, mux mode, speed, etc. - Add i2c devices to the tree - Add IPG clock - Add support for Quartz Module. - Pin configuration is a complete iomux register now and includes drive strength, pull mode, mux mode, speed, etc. - Add i2c devices to the tree - Add IPG clock
* MFC r261982, r261987, r262123, r262244, r262278, r262280, r262353, r262354,ian2014-05-151-2/+2
| | | | | | | | | | | | | | | | | | | | | | r262355, r262419, Add Vybrid driver for Synchronous Audio Interface (SAI). Decrease SAI buffer size. Handle eDMA interrupt on running channel only. Give the physmem fdt helper routines static linkage since no global definition of them is provided anywhere. Add imx6 early printf support, wrapped in #if 0 because it's rarely needed. Add basic cpu frequency control and temperature monitoring to imx6_anatop. Add the FREEBSD_BOOT_LOADER option so that a loaded DTB passed in from ubldr will actually get used. Create a generic IMX6 kernel config, then fix it to have an ident line. Don't force imx6 bootverbose on anymore, it can be set from ubldr now.
* MFC r261917, r261918, r261919, r261920, r261921, r261922ian2014-05-151-0/+1
| | | | | | | | | | | | | | | | | | | Always clear L1 PTE descriptor when removing superpage on ARM Invalidate L1 PTE regardles of existance of the corresponding l2_bucket. Ensure proper TLB invalidation on superpage promotion and demotion on ARM Base pages within newly created superpage need to be invalidated so that new mapping is "visible" immediately after creation. Fix superpage promotion on ARM with respect to RO/RW and wired attributes Avoid redundant superpage promotion attempts on ARM Remove spurious assertion from pmap_extract_locked() on ARM Handle pmap_enter() on already promoted mappings for ARMv6/v7
* MFC r261803, r261808, r261814, r261815, r261816, r261817, r261818, r261826,ian2014-05-151-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | r261848, r261855 On armv6 and later, use the WriteNotRead bit of the fault status register to decide what protections are required by the faulting access. Use the right symbols for determining arm architecture. Include the necessary header file which has the new FAULT_WNR symbol defined in it. Allow the kernel to be loaded at any 1MiB address. This requirement is because we use the 1MiB section maps as they only need a single pagetable. Add function for configuring Vybrid PLL4 (Audio) clock frequency output. imx6 changes ... - Fix the definition of the SDHCI_STATE_DAT and SDHCI_STATE_CMD fields, and add SDHCI_RETUNE_REQUEST. None of these are actually used in the code yet. - Write translation code for the SDHCI_PRESENT_STATE register. Freescale moved some bits around in their version of the register, adjust things so that the sdhci code sees the standard layout. - Add standard non-removable and cd-gpios properties to the usdhc devices. That generates references to gpio devices, so uncomment them even though there isn't a gpio driver to do anything with them yet. - Add handling of standard "non-removable" property, and also some workaround code so that if card detect is wired to a gpio pin, for now we just treat it the same as non-removable (because there isn't a gpio driver yet). - Enable both sdcard slots, but not the sdio-based wifi that we don't yet have a driver for. - Remove a couple obsolete function declarations.
* MFC r261643, r261646, r261648, r261649, r261651, r261656, r261657, r261663,ian2014-05-153-3/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | r261676, r261677, r261698, r261778 Consolidate code related to setting up physical memory configuration into a new physmem.c file. Replace compile-time constant KERNPHYSADDR with abp_physaddr Calculate the kernel's load address from the PC in the elf / gzip trampoline instead of relying on KERNPHYSADDR as a compile-time constant. It turns out a global variable is the only straightforward way to communicate the kernel's physical load address from where it's known in initarm() into cpu_mp_start() which is called from non-arm code and takes no parameters. Remove the now unused MMU_INIT macro. Use vm_paddr_t, not vm_offset_t, when dealing with physical addresses. No need to set physmem in each initarm() instance anymore, it's handled in common code now. Pass the pagetable used from locore.S to initarm to allow it to map data in as required. Fix the physmem exclude-region clipping logic for the edge-trim case. Add some extra debugging output when DEBUG is defined. Update legacy platforms to use new arm_physmem helper routines.
* MFC r257549, r261642ian2014-05-153-62/+8
| | | | | | | | | Don't create a distinct free page pool for segregating allocations that are accessed through the direct map unless the kernel configuration actually includes a direct map. Only a few configurations do, and for the rest the unnecessary free page pool is a small pessimization. Remove the ARM_USE_SMALL_ALLOC option and code related to it.
* MFC r261423, r261424, r261516, r261513, r261562, r261563, r261564, r261565,ian2014-05-152-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | r261596, r261606 Add the imx sdhci controller. Move Open Firmware device root on PowerPC, ARM, and MIPS systems to a sub-node of nexus (ofwbus) rather than direct attach under nexus. This fixes FDT on x86 and will make coexistence with ACPI on ARM systems easier. SPARC is unchanged. Add the missing ')' at end of sentence. Reword it to use a more common idiom. Pass the kernel physical address to initarm through the boot param struct. Make functions only used in vfp.c static, and remove vfp_enable. Fix __syscall on armeb EABI. As it returns a 64-bit value it needs to place 32-bit data in r1, not r0. 64-bit data is already packed correctly. Use abp_physaddr for the physical address over KERNPHYSADDR. This helps us remove the need to load the kernel at a fixed address. Remove references to PHYSADDR where it's used only in debugging output. Dynamically generate the page table. This will allow us to detect the physical address we are loaded at to change the mapping.
* MFC r261414, r261415, r261417, r261418, r261419ian2014-05-152-11/+27
| | | | | | | | | | | | | Don't call device_set_ivars() for the mmchs Change the way pcpu and curthread are stored per-core Invalidate cachelines for bounce pages on PREREAD too, there may still be stale entries from a previous transfer. Only use the CPU ID register if SMP is defined. Some non-MPCore armv6 cpu, such as the one found in the RPi, don't have it, and just hang when we try to access it.
* MFC r261137, r261393ian2014-05-152-13/+18
| | | | | | Correct the alignment of sp through functions that use UNWINDSVCFRAME. Update all arm code that manipulates the PSR registers to use modern syntax.
* MFC r260440, r260441, r260447, r260490, r260493ian2014-05-141-0/+3
| | | | | | | | Add option USB_HOST_ALIGN to configs that contain 'device usb'. Update dts files of Cubieboard1,2 to use 1GB memory. Add a function to print the contents of the static device mapping table,
* MFC r257738, r259202, r258410, r260288, r260292, r260294, r260320, r260323,ian2014-05-144-10/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | r260326, r260327, r260331, r260333, r260340, r260371, r260372, r260373, r260374, r260375 Add common bus_space tag definition shared for most supported ARMv6/v7 SoCs. Correct license statements to reflect the fact that these files were all derived from sys/arm/mv/bus_space.c. In pmap_unmapdev(), remember the size, and use that as an argument to kva_free(), or we'd end up always passing it a size of 0 In pmap_mapdev(), first check whether a static mapping exists, Convert TI static device mapping to use the new arm_devmap_add_entry(), Use the common armv6 fdt_bus_tag defintion for tegra instead of a local copy. Eliminate use of fdt_immr_addr(), it's not needed for tegra Convert lpc from using fdt_immr style to arm_devmap_add_entry() to make static device mappings. Retire machine/fdt.h as a header used by MI code, as its function is now obsolete. This involves the following pieces: - Remove it entirely on PowerPC, where it is not used by MD code either - Remove all references to machine/fdt.h in non-architecture-specific code (aside from uart_cpu_fdt.c, shared by ARM and MIPS, and so is somewhat non-arch-specific). - Fix code relying on header pollution from machine/fdt.h includes - Legacy fdtbus.c (still used on x86 FDT systems) now passes resource requests to its parent (nexus). This allows x86 FDT devices to allocate both memory and IO requests and removes the last notionally MI use of fdtbus_bs_tag. - On those architectures that retain a machine/fdt.h, unused bits like FDT_MAP_IRQ and FDT_INTR_MAX have been removed. Add #include <machine/fdt.h> to a few files that used to get it via pollution Enable the mv cesa security/crypto device by providing the required property in the dts source, and adding the right devices to the kernel config. Remove dev/fdt/fdt_pci.c, which was code specific to Marvell ARM SoCs, related to setting up static device mappings. Since it was only used by arm/mv/mv_pci.c, it's now just static functions within that file, plus one public function that gets called only from arm/mv/mv_machdep.c. Switch RPi to using arm_devmap_add_entry() to set up static device mapping. Allow 'no static device mappings' to potentially work. Don't try to find a static mapping before calling pmap_mapdev(), that logic is now part of pmap_mapdev() and doesn't need to be duplicated here. Switch a10 to using arm_devmap_add_entry() to set up static device mapping.
* MFC r260161, r260163, r260165, r260166, r260189ian2014-05-141-0/+3
| | | | | | | | | | Add polarity and level support to ARM GIC Do not attach to PCI bridges in AHCI driver Use only mapped BIOs on ARM Fix race condition in DELAY for SP804 timer.
* MFC r258359, r258742, r258845, r259936, r259640ian2014-05-145-4/+9
| | | | | | | | | | | Apply access flags for managed and unmanaged pages properly on ARMv6/v7 Set the PGA_WRITEABLE flag when the protections indicate write access, not just when the current access is a write. Enable missing Access Flag for secondary cores on ARMv6/v7 Add identification and necessary type checks for Krait CPU cores.
* MFC r256707, r256708, r257291, r258358ian2014-05-141-4/+12
| | | | | | | | | | | | | | | | | Switch to use WBWA mappings for page tables on armv6, this is needed for SMP. Fix PTE_SYNC() for PIPT L2 caches, using the virtual address wasn't so useful. Use PTE_SYNC() for >= armv6 Spell cpu_l2cache_wb_range correctly. Fix condition that determines PMAP_NEEDS_PTE_SYNC value for ARM Use values of the correct defines to determine statement's result. ARM_ARCH_ symbols are always defined, hence only values are relevant. Avoid clearing EXEC permission bit when setting the page RW on ARMv6/v7 When emulating modified bit the executable attribute was cleared by mistake when calling pmap_set_prot().
* MFC r257170, r257171, r257172, r257240, r257278, r257279, r257280, r257281,ian2014-05-142-14/+1
| | | | | | | | | | | | | | | | | | | | | | | | | r257282, r257332 Wait for DesignWare UART transfers completion before accessing line control Enable UART busy detection handling for Armada XP - based board Enable SATA interface on Armada XP Run mvs SATA driver on Armada XP instead of old mv_sata Retire arm_remap_nocache() and the data and constants associated with it. Remove hard-coded mappings related to Armada XP support Fix-up DTB for Armada XP registers' base according to the actual settings Change Armada XP kernel load address to the u-boot's end address Remove not working and deprecated PJ4Bv6 support Switch off explicit broadcasting of the TLB flush operations for PJ4B CPU Add missing ARMv6 CPU functions to ARM Makefile
* MFC r263998:tijl2014-04-151-2/+2
| | | | | Rename __wchar_t so it no longer conflicts with __wchar_t from clang 3.4 -fms-extensions.
* MFC r258779,r258780,r258787,r258822:eadler2014-02-041-1/+1
| | | | | | | | | | | | | Fix undefined behavior: (1 << 31) is not defined as 1 is an int and this shifts into the sign bit. Instead use (1U << 31) which gets the expected result. Similar to the (1 << 31) case it is not defined to do (2 << 30). This fix is not ideal as it assumes a 32 bit int, but does fix the issue for most cases. A similar change was made in OpenBSD.
* MFC r257669, r257672, r257673, r257676, r257678:ian2013-12-143-7/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | Call initarm_lastaddr() later in the init sequence, after establishing static device mappings, rather than as the first of the initializations that a platform can hook into. This allows a platform to allocate KVA from the top of the address space downwards for things like static device mapping, and return the final "last usable address" result after that and other early init work is done. Because some platforms were doing work in initarm_lastaddr() that needs to be done early, add a new initarm_early_init() routine and move the early init code to that routine on those platforms. Make PTE_DEVICE a synonym for PTE_NOCACHE on armv4, to make it easier to share the same code on both architectures. Add new helper routines for arm static device mapping. The new code allocates kva space from the top down for the device mappings and builds entries in an internal table which is automatically used later by arm_devmap_bootstrap(). The platform code just calls the new arm_devmap_add_entry() function as many times as it needs to (up to 32 entries allowed; most platforms use 2 or 3 at most). Remove imx local devmap code and use the essentially identical common code that got moved from imx_machdep.c to arm/devmap.c.
* MFC r257648, r257649, r257660:ian2013-12-134-23/+78
| | | | | | | | | | | | | | | | | Begin reducing code duplication in arm pmap.c and pmap-v6.c by factoring out common code related to mapping device memory into a new devmap.c file. Remove the growing duplication of code that used pmap_devmap_find_pa() and then did some math with the returned results to generate a virtual address, and likewise in reverse to get a physical address. Now there are a pair of functions, arm_devmap_vtop() and arm_devmap_ptov(), to do that. The bus_space_map() implementations are rewritten in terms of these. Move remaining code and data related to static device mapping into the new devmap.[ch] files. Emphasize the MD nature of these things by using the prefix arm_devmap_ on the function and type names (already a few of these things found their way into MI code, hopefully it will be harder to do by accident in the future).
* MFC r257201, r257202ian2013-12-131-5/+0
| | | | Retire arm_remap_nocache() and the data and constants associated with it.
* MFC r257199, r257200, r257217:ian2013-12-136-6/+6
| | | | | | | | | | | | | | | Remove all #include <machine/pmap.h> from arm code. It's already included by vm/pmap.h, which is a prerequisite for arm/machine/pmap.h so there's no reason to ever include it directly. Remove #include <machine/frame.h> from all the arm code that doesn't really need it. That would be almost everywhere it was included. Add it in a couple files that really do need it and were previously getting it by accident via another header. Remove the last dregs of trapframe_t. It turns out only arm was using this type, so remove it to make arm code more consistant with other platforms.
* On ARM EABI double precision floating point values are stored in theandrew2013-09-071-1/+1
| | | | | | endian the CPU is in, i.e. little-endian on most ARM cores. This allows ARMv4 and ARMv5 boards to boot with the ARM EABI.
* Fix of r255318: move sf_buf_alloc()/sf_buf_free() out of #ifdefglebius2013-09-071-3/+4
| | | | ARM_USE_SMALL_ALLOC.
* Fix build with gcc. Move sf_buf_alloc()/sf_buf_free() declarationsglebius2013-09-061-0/+2
| | | | to MD headers.
* Introduce superpages support for ARMv6/v7.raj2013-08-263-9/+43
| | | | | | | | | | | | | | | | | | | | | Promoting base pages to superpages can increase TLB coverage and allow for efficient use of page table entries. This development provides FreeBSD/ARM with superpages management mechanism roughly equivalent to what we have for i386 and amd64 architectures. 1. Add mechanism for automatic promotion of 4KB page mappings to 1MB section mappings (and demotion when not needed, respectively). 2. Managed and non-kernel mappings are now superpages-aware. 3. The functionality can be enabled by setting "vm.pmap.sp_enabled" tunable to a non-zero value (either in loader.conf or by modifying "sp_enabled" variable in pmap-v6.c file). By default, automatic promotion is currently disabled. Submitted by: Zbigniew Bodek <zbb@semihalf.com> Reviewed by: alc Sponsored by: The FreeBSD Foundation, Semihalf
* Provide settings for superpage reservation system on ARM.raj2013-08-261-2/+9
| | | | | | | | | | This allows for enabling and configuring superpages reservation mechanism in order to allocate and populate 256 4KB base pages (for the purpose of promotion to a 1MB superpage). Submitted by: Zbigniew Bodek <zbb@semihalf.com> Reviewed by: alc Sponsored by: The FreeBSD Foundation, Semihalf
* Do not use pv_kva on ARMv6/v7 and save some space on each vm_page. It's onlyraj2013-08-191-0/+2
| | | | | | | | relevant for older ARM variants (with virtual cache). Submitted by: Zbigniew Bodek <zbb@semihalf.com> Reviewed by: gber Sponsored by: The FreeBSD Foundation, Semihalf
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