| Commit message (Collapse) | Author | Age | Files | Lines |
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Allow to override default kernel virtual address assignment on ARM.
Do not save/restore the TLS pointer on context switch for armv6.
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Clean data cache before instruction cache in armv7_icache_sync_range().
Add minimum cache line sizes to struct cpuinfo, use them in the new cache
maintenance routines. Also add a routine to invalidate the branch cache.
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Add logic for handling new-style ARM cpu ID info.
Correct a comment which was exactly backwards from reality.
There is no reason to do i+dcache writeback and invalidate when changing
the translation table (this may be left over from armv5 days). It's
especially bad to do so using a cache operation that isn't coherent on
SMP systems.
Add casting to make atomic ops work for pointers. (Apparently nobody has
ever done atomic ops on pointers before now on arm).
Revert incorrect casting.
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r277472, r277473, r277474, r277475, r277476, r277477, r277478, r277479,
r277480, r277512, r277516:
Add inline implementations of arm bus_space_read/write_N().
Revise the arm bus_space implementation to avoid dereferencing the tag on
every operation to retrieve the bs_cookie value almost nothing actually uses.
Use the explicit member initializer style to init the bus_space struct.
Use arm/bus_space-v6.c for all armv6 systems
Consolidate many identical implementations of bus_space to a single
common tag and implementation shared by armv4 and armv6.
Micro-optimize the new arm inline bus_space implementation by grouping all
the data the inline functions access together at the start of the bus_space
struct so that they all fit in a single cache line.
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Add accessors for the ARM CP15 performance monitor registers.
Move the inclusion of cpu-v6.h inside the #ifdef _KERNEL block.
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Give suitably-endowed ARMs a register similar to the x86 TSC register.
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Split syscall handling out to a separate file.
Include sys/kernel.h to pick up the definition of hz in syscall.c
Add a new trap-v6.c which has support for all armv7 exceptions.
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Put in a workaround for bug 196407 (arm modules cause crashes & panics).
(Don't allow movw/movt insn in modules.)
Fix alignment directives in arm asm code after clang 3.5 import.
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Define a WFI macro that expands to the right form of wait-for-interrupt
depending on the architecture.
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Include acle-compat.h directly rather than getting it via sysreg.h.
Add new code to read and parse cpu identification data using the new CPUID
mechanism defined for armv7.
Add new TLB and cache maintainence functions for armv6 and armv7.
Eliminate an unused macro whose name clashes now with a function in the
new cpu-v6.h
Add cache maintenance functions which will be used by startup code to
initially set up the MMU.
Fix a "decl is not a prototype" error noticed by gcc (but not clang).
Update comments (r4 is not used anywhere), use non-profiling entry macros.
Add arm option ARM_NEW_PMAP, to allow us to begin adding the new pmap
code alongside the existing implementation
Add armv6 implementations of cache operations to avoid duplication
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Add machine/sysreg.h to simplify accessing the system control coprocessor
registers and use it in the ARMv7 CPU functions.
Add macros for asm barrier instructions with arch-specific implementations.
Define only the CP15 register operations that are valid for the architecture.
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For data and instruction prefetch aborts, call the same handler in the C
code, passing a 0/1 flag that indicates which type of abort it was. This
sets the stage for unifying the handling of page faults in a single routine.
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Change the style of the DO_AST macro to match the others
Remove _PROF_PROLOGUE from the EENTRY() macros.
Stylish changes... put tabs where they need to be in macros, move lines
around so that related things are more grouped together, rewrite comments.
Fix the GLOBAL macro so it works (upper vs lowercase X), use it in _EENTRY.
Create 'L' variants of all the ENTRY macros for file-static/local symbols.
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Rename pmap_kenter_temp to pmap_kenter_temporary to be consistent with the
other architectures with this function.
Eliminate unnecessary references to pte.h internals by using the standard
pmap_kenter_temporary() to map pages while dumping.
Cleanup up ARM *frame structures.
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Add more register values to armreg.h and remove CPU_CONTROL_32BP_ENABLE
from asm.h as they were already defined in armreg.h.
Unify interrupts bit definition and usage. While here remove PSR_C_bit.
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Define the old-school arm arch constants we still use internally based on
the somewhat newer constants predefined by the compiler. This will allow
userland apps to use various machine/foo.h headers without CPUTYPE defined.
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Pull in the NetBSD global offset table handling code. Clang 3.5 creates
relocations the linker complains about.
Obtained from: NetBSD
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MFC 275256:
Switch to the ARM unified assembly language as the clang integrated as only
supports it. Binutils supports it when the ".syntax unified" directive
is set.
Sponsored by: ABT Systems Ltd
MFC 275264:
Update _ENTRY to use _EENTRY to reduce the common code.
MFC 275321:
Remove extra labels, ENTRY_NP already provides them.
Sponsored by: ABT Systems Ltd
MFC 275322:
Correctly a few incorrect uses of ENTRY/EENTRY and END/EEND
Sponsored by: ABT Systems Ltd
MFC 275416:
Fix the name of the coprocessor to include the "p" prefix, the clang
integrated assembler expects this.
Sponsored by: ABT Systems Ltd
MFC 275418:
Switch to unified syntax so these can be built with clang 3.5.
Sponsored by: ABT Systems Ltd
MFC 275519:
Add missing END macros to some of the xscale functions.
Sponsored by: ABT Systems Ltd
MFC 275520:
Use the unified syntax in a few more assembly files
Sponsored by: ABT Systems Ltd
MFC 275521:
Set the alignment to 4-bytes after a string as clang 3.5 can switch to
thumb mode if this is incorrect.
Sponsored by: ABT Systems Ltd
MFC 275522:
Place the literal pool after a RET otherwise clang 3.5 tries to put it too
far away from a ldr psuedo instruction. With this clang will place the
literal value here where it's close enough to be loaded.
Sponsored by: ABT Systems Ltd
MFC 275523:
Switch to an armv6k cpu, without this clang 3.5 complains "bx lr" is
unsupported as it needs a newer cpu.
Sponsored by: ABT Systems Ltd
MFC 275524:
Switch to a .cpu directive. These will work when clang 3.5 is imported
where the .arch directive is a nop.
Sponsored by: ABT Systems Ltd
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MFC r273783:
Add fueword(9) and casueword(9) functions.
MFC note: ia64 is handled like arm, with NO_FUEWORD define.
MFC r273784:
Replace some calls to fuword() by fueword() with proper error checking.
MFC r273785:
Convert kern_umtx.c to use fueword() and casueword().
MFC note: the sys__umtx_lock and sys__umtx_unlock syscalls are not
converted, they are removed from HEAD, and not used. The do_sem2*()
family is not yet merged to stable/10, corresponding chunk will be
merged after do_sem2* are committed.
MFC r273788 (by jkim):
Actually install casuword(9) to fix build.
MFC r273911:
Add type qualifier volatile to the base (userspace) address argument
of fuword(9) and suword(9).
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From https://sourceware.org/ml/newlib/2014/msg00113.html
By Richard Earnshaw at ARM
>
>GCC has for a number of years provides a set of pre-defined macros for
>use with determining the ISA and features of the target during
>pre-processing. However, the design was always somewhat cumbersome in
>that each new architecture revision created a new define and then
>removed the previous one. This meant that it was necessary to keep
>updating the support code simply to recognise a new architecture being
>added.
>
>The ACLE specification (ARM C Language Extentions)
>(http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.set.swdev/index.html)
>provides a much more suitable interface and GCC has supported this
>since gcc-4.8.
>
>This patch makes use of the ACLE pre-defines to map to the internal
>feature definitions. To support older versions of GCC a compatibility
>header is provided that maps the traditional pre-defines onto the new
>ACLE ones.
Stop using __FreeBSD_ARCH_armv6__ and switch to __ARM_ARCH >= 6 in the
couple of places in tree. clang already implements ACLE. Add a define
that says we implement version 1.1, even though the implementation
isn't quite complete.
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Add compat strings for all the flavors of GIC this driver should support.
Also allow the driver to attach to ofwbus as well as simplebus, some FDT
data puts the root interrupt controller on the root bus.
Add a common routine for parsing FDT data describing an ARM GIC interrupt.
Use gic_decode_fdt() rather than a local routine to parse fdt interrupt
properties. Move fdt_pic_table and fdt_fixup_table into imx6_machdep.c,
which means imx6 doesn't need imx_common.c anymore.
The private peripheral interrupts start at offset 16, not 0. Also, use
names rather than inline mystery constants for these offsets.
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Rename new to newval in inline asm code, to avoid clashes with C++ new.
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In ARM asm code, ensure that every ENTRY(foo) has a matching END(foo).
The EABI unwind info requires a .fnend for every .fnstart, and newer
binutils will complain about seeing two .fnstart in a row. This change
allows newer tools to compile our code.
Do not generate unwind info in asm functions if _STANDALONE is defined.
The .fnend op causes the assembler to emit RELOC references to unwind
support functions that don't exist in libstand.
Approved by: re(gjb)
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Fix the handling of MMU type in the AP entry code. The ARM_MMU_V6/V7
symbols are always #defined to 0 or 1, so use #if SYM not #if defined(SYM).
Also, it helps if you include the header file that defines the symbols.
The Marvell PJ4B cpu family is armv7, not armv6.
Approved by: re(gjb)
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Set ofwbus and simplebus to attach during BUS_PASS_BUS.
Define names that drivers can use to adjust their position relative to
other drivers within a BUS_PASS
Adjust ofwbus and simplebus to attach at BUS_PASS_ORDER_MIDDLE, so that
a platform can attach some other bus first if necessary.
Set the pl310 L2 cache driver to attach during the middle of BUS_PASS_CPU.
Attach arm generic interrupt and timer drivers in the middle of
BUS_PASS_INTERRUPT and BUS_PASS_TIMER, respectively.
Add an arm option, ARM_DEVICE_MULTIPASS, used to opt-in to multi-pass
device attachment on arm platforms. If this is defined, nexus attaches
early in BUS_PASS_BUS, and other busses and devices attach later, in the
pass number they are set up for. Without it defined, nexus attaches in
BUS_PASS_DEFAULT and thus so does everything else, which is status quo.
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Add 64-bit atomic ops for armv6, and also for armv4 only in kernel code.
Use the new ops in the cddl code (and avoid defining functions with the
same names locally).
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Fix C++ exception handling for ARM EABI.
Just the part of r264070 that creates the FBSD_1.4 namespace in libc
is hand-applied, and then r264082 which creates the Versions.def entry
is MFC'd.
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Make sure the PCB is aligned on 8 bytes, we may use ldrd/strd to access it,
which may have strong alignment requirements.
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Fix an itt instruction. We need to execute both the mov and b instructions
when building for Thumb.
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Make the hardware memory and instruction barrier functions work on armv4
and armv5 as well.
Add cpu_l2cache_drain_writebuf(), use it to implement generic_bs_barrier().
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Move the pl310.enabled tunable to hw.pl310.enabled. Clean up a few minor
style(9) nits. Use DEVMETHOD_END.
Break out the code that figures out the L2 cache geometry to its own
routine, so that it can be called from multiple places in upcoming changes.
Call platform_pl310_init() before enabling the controller, and handle the
case where the controller is already enabled.
Add defines for the bits in the PL310 debug control register.
Add a public routine to set the L2 cache ram latencies. This can be
called by platform init routines to fine-tune cache performance.
Enable PL310 power-saving modes and tune the cache ram latencies for imx6.
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There is no difference between IPI_STOP and IPI_STOP_HARD on ARM, so
map them both to the same interrupt number like other arches do.
Flush and invalidate caches on each CPU as part of handling IPI_STOP.
Don't use multiprocessing-extensions instruction on processors that don't
support SMP.
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Call cpu_icache_sync_range() rather than sync_all since we know the range
and flushing the entire icache is needlessly expensive.
Provide a proper armv7 implementation of icache_sync_all rather than
using armv7_idcache_wbinv_all, because wbinv_all doesn't broadcast the
operation to other cores. In elf_cpu_load_file() use icache_sync_all()
and explain why it's needed (and why other sync operations aren't).
Remove cpu_idcache_wbinv_all() from kdb_cpu_trap(), it's no longer needed.
Explain why wbinv_all is SMP-safe when dumping, and add a missing l2 cache
flush. (Either it was missing here, or it isn't needed in the minidump
case. Adding it here seems like the safer path to consistancy.)
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Tell VM we now have ARM platforms with physically discontiguous memory.
Define the full 1024M of ram on the imx51 and imx53 boards.
Use a more professional uart device description.
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Fix TTB set operation for armv7. Perform sychronization (by "isb" barrier)
after TTB is set.
Fix TLB maintenance issues for armv6 and armv7.
- Add cpu_cpwait to comply with the convention.
- Add missing TLB invalidations, especially in pmap_kenter & pmap_kremove
with distinguishing between D and ID pages.
- Modify pmap init/bootstrap invalidations to ID, just to be safe.
- Fix TLB-inv and PTE_SYNC ordering.
Allocate per-cpu resources for doing pmap_zero_page() and pmap_copy_page().
This is performance enhancement rather than bugfix.
We don't support any ARM systems with an ISA bus and don't need a freelist
of memory to support ISA addressing limitations.
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Add more flags for the fpexc register from the ARM1176JZF-S Manual
Initialise fpscr to a sane value when we create the pcb. This sets NaNs to
be the default NaN and for denormalised numbers to be flushed to zero.
VFP fixes/cleanups for ARM11:
* Save the required VFP registers on context switch. If the exception bit
is set we need to save and restore the FPINST register, and if the fp2v
bit is also set we need to save and restore FPINST2.
* Move saving and restoring the floating point control registers to C.
* Clear the fpexc exception and fp2v flags on a floating-point exception.
* Signal a SIGFPE if the fpexc exception flag is set on an undefined
instruction. This is how the ARM core signals to software there is a
floating-point exception.
Add Cortex-A15 cpu id revisions.
Exynos/Arndale...
- Merge SoC-common parts
- Enable iicbus device
- Directly call kmem_alloc_contig to allocate framebuffer memory
and pass VM_MEMATTR_UNCACHEABLE (no-cache, no-buffer).
This fixes screen refreshing problem when data is updated too slowly.
- Add support for keyboard used in Samsung Chromebook (ARM machine)
Support covers device drivers for:
- Interrupt Combiner
- gpio/pad, External Interrupts Controller (pad)
- I2C Interface
- Chrome Embedded Controller
- Chrome Keyboard
- Use new gpio dev class in EHCI driver
- Expand device tree information
- Release i2c bus on detach.
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Implement __flt_rounds for ARMv6 hard-float. The fpscr register stores the
current rounding mode used by the VFP unit.
Simplify how we build MACHINE_ARCH. There are 3 options that may be set
however only arm, armeb, armv6, and soon armv6hf will be used.
Add the llvm/clang patch for r263619.
Reorder the pmap macros so "ARM_MMU_V6 + ARM_MMU_V7" is first. As they are
identical this allows us to build for both v6 and v7 together.
Add code for enabling second CPU core for A20 SoC.
Enable SMP on Cubieboard2.
Switch to freebsd.org emal address in copyright.
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263030, 263033, 263034, 263056, 263057,
Remove all the redundant external declarations of exception vectors and
runtime setting of the pointers that's scattered around various places.
Remove all traces of support for ARM chips prior to the arm9 series.
Make the default exception handler vectors point to where I thought they
were already pointing: the default handlers (not a panic that says there
is no default handler).
Eliminate irq_dispatch.S. Move the data items it contained into
arm/intr.c and the functionality it provided into arm/exception.S.
Move the exception vector table (so-called "page0" data) into exception.S
and eliminate vectors.S.
Change the way the asm GET_CURTHREAD_PTR() macro is defined so that code
using it doesn't have to have an "AST_LOCALS" macro somewhere in the file.
Arrange for arm fork_trampoline() to return to userland via the standard
swi_exit code in exception.S instead of having its own inline expansion
of the DO_AST and PULLFRAME macros.
Now that the PUSHFRAME and PULLFRAME macros are used only in the swi
entry/exit code, they don't need to be macros. Except that didn't work
and the whole change was reverted.
Remove some unnecessary indirection and jump right to the handler functions.
Use panic rather than printf to "handle" an arm26 address exception
(should never happen on arm32).
Remove the unreferenced DATA() macro.
Remove #include <machine/asmacros.h> from files that don't need it.
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262925, 262929, 262932, 262935, 262940, 262941, 262942, 262948, 262949,
262950
Strip arm/conf/DEFAULTS down to just items that are mandatory for running
the architecture.
Move all the files named foo/common.c to foo/foo_common.c
Initial cut for DTS on the hl201 board.
Add commented out dts for sam9260ek as well as early printf support.
Make clock optional on uart nodes, then back it out ("I don't know what I
was thinking, but it is lame.")
Set the baud rate if it isn't 0
Make at91_soc_id() public.
Properly round at91 resource on unmapping.
Move AT91 AIC related stuff to own file.
Fix another bug in multicast filtering. i.MX uses 6 bits from MSB in
LE CRC32 for the hash value, not the lowest 6 bits in BE CRC32.
Follow r262916 with one more config file that references a renamed common.c
Remove bogus AT91 define that causes compile errors. Most of the defines
for SAM9X are going away soonish anyway (once FDT works), but until
then...
Remove all dregs of a per-thread undefined-exception-mode stack.
Rework the VFP code that handles demand-based save and restore of state.
Always call vfp_discard() on thread death.
When a thread begins life it doesn't own the VFP hardware state on any cpu.
Make undefined exception entry MP-safe.
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r262585, r262587, r262696, r262712
Replace many pasted identical definitions of cpu_initclocks() with a common
implementation in arm/machdep.c.
aicasm: Don't complain about missing prototypes to ease bootstrap issues.
Vybrid: Add driver for Inter-Integrated Circuit (I2C).
imx6: Initialize the Low Power Mode bits to keep the ARM cores running
during WFI.
All our current ARM multi-core systems have all cores in one package with
a shared L2 cache, reflect that in the common cpu_topo() routine.
mpcore timer: Supply a DELAY() implementation via weak linkage, so that
SoC-specific code can supply a better implementation.
imx6: Add some rudimentary voltage control.
Add an armv7 implementation of cpu_sleep().
Add __used attribute so that the DELAY implementation doesn't get
optimized away as unreferenced, causing linker errors when trying to
resolve the weak reference to the missing function.
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As of r257209, all architectures have defined
VM_KMEM_SIZE_SCALE. In other words, every architecture is now
auto-sizing the kmem arena. This revision changes kmeminit() so
that the definition of VM_KMEM_SIZE_SCALE becomes mandatory and
the definition of VM_KMEM_SIZE becomes optional.
Replace or eliminate all existing definitions of VM_KMEM_SIZE.
With auto-sizing enabled, VM_KMEM_SIZE effectively became an
alternate spelling for VM_KMEM_SIZE_MIN on most architectures.
Use VM_KMEM_SIZE_MIN for clarity.
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r262482, r262483, r262531,
Move the declaration for mpentry() into a header file instead of pasting
it into a bunch of different .c files.
If the L2 cache type is PIPT, pass a physical address for a flush.
Actually set the proper bit to indicate TTB shared memory.
Add a new cache maintenance function, idcache_inv_all, to the table, and
implementations for each of the chips we support.
Invalidate caches immediately upon entry to init_secondary(). Also set
the Bufferable bit in the PDE entries of the secondary processor startup
pagetables.
Add the bits needed to run SMP on imx6.
Invalidate the SCU cache tag ram on all 4 cores, not just 1-3.
Minor tweaks to the imx GPT timer
Vybrid enhancements...
- Pin configuration is a complete iomux register now and includes
drive strength, pull mode, mux mode, speed, etc.
- Add i2c devices to the tree
- Add IPG clock
- Add support for Quartz Module.
- Pin configuration is a complete iomux register now and includes
drive strength, pull mode, mux mode, speed, etc.
- Add i2c devices to the tree
- Add IPG clock
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r262355, r262419,
Add Vybrid driver for Synchronous Audio Interface (SAI).
Decrease SAI buffer size. Handle eDMA interrupt on running channel only.
Give the physmem fdt helper routines static linkage since no global
definition of them is provided anywhere.
Add imx6 early printf support, wrapped in #if 0 because it's rarely needed.
Add basic cpu frequency control and temperature monitoring to imx6_anatop.
Add the FREEBSD_BOOT_LOADER option so that a loaded DTB passed in from
ubldr will actually get used.
Create a generic IMX6 kernel config, then fix it to have an ident line.
Don't force imx6 bootverbose on anymore, it can be set from ubldr now.
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