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* Remove dead code, already defined in sys/cdef.hcognet2006-08-301-9/+0
| | | | Spotted out by: bde
* Eliminate unused definitions. (They came from NetBSD.)alc2006-08-251-9/+0
| | | | Discussed with: cognet, grehan, marcel
* Finally bring it support for the i80219 XScale processor.cognet2006-08-243-10/+17
| | | | Submitted by: Max M. Boyarov <m.boyarov bsd by>
* Use ELFDATA2MSB if we're building big endian.cognet2006-08-241-0/+4
| | | | Noticed by: Oleksandr Tymoshenko <gonzo freebsd org>
* Rewrite ARM_USE_SMALL_ALLOC so that instead of the current behavior, it mapscognet2006-08-083-2/+35
| | | | | | | | whole the physical memory, cached, using 1MB section mappings. This reduces the address space available for user processes a bit, but given the amount of memory a typical arm machine has, it is not (yet) a big issue. It then provides a uma_small_alloc() that works as it does for architectures which have a direct mapping.
* Define BYTE_MSF if we're compiling a big endian kernel, so that DDB cancognet2006-07-271-0/+3
| | | | correctly disassemble instructions on big endian.
* Add remote GDB bits for arm.cognet2006-07-141-0/+52
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* Add partial pmap locking.alc2006-06-061-1/+13
| | | | | | Eliminate the unused allpmaps list. Tested by: cognet@
* Don't #error if no CPU is defined but we're not compiling the kernel.cognet2006-06-021-2/+2
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* Don't enable the FIQ in enable_interrupts() if F32_bit is not specified.cognet2006-06-011-1/+1
| | | | | | This has been committed by mistake. Reported by: ssouhlal
* Ooops arm10 is armv5, not armv4.cognet2006-05-311-3/+3
| | | | Submitted by: kevlo
* Include machine/cpuconf.h in pmap.h in order to get ARM_NMMUS defined,cognet2006-05-311-1/+1
| | | | to appease -Wundef.
* Add definitions for atomic_subtract_rel_32, atomic_add_rel_32 andcognet2006-05-151-0/+3
| | | | atomic_load_acq_32, needed for hwpmc.
* Switch to a 64bit time_t, while it's not a big problem to do so.cognet2006-05-151-1/+1
| | | | Suggested by: imp
* Resurrect Skyeye support :cognet2006-05-131-0/+5
| | | | | | | | | | | | | Add a new option, SKYEYE_WORKAROUNDS, which as the name suggests adds workarounds for things skyeye doesn't simulate. Specifically : - Use USART0 instead of DBGU as the console, make it not use DMA, and manually provoke an interrupt when we're done in the transmit function. - Skyeye maintains an internal counter for clock, but apparently there's no way to access it, so hack the timecounter code to return a value which is increased at every clock interrupts. This is gross, but I didn't find a better way to implement timecounters without hacking Skyeye to get the counter value. - Force the write-back of PTEs once we're done writing them, even if they are supposed to be write-through. I don't know why I have to do that.
* Clean out sysctl machdep.* related defines.phk2006-05-111-8/+0
| | | | The cmos clock related stuff should really be in MI code.
* Disable/enable fiqs as well as irqs.cognet2006-04-132-4/+4
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* MFp4: Don't write-back the PTEs if they are mapped write-through, this wascognet2006-04-091-5/+0
| | | | apparently only needed because skyeye has bugs in its cache emulation.
* MFp4: Forget the asm inlined version of in_cksum_hdr(). It doesn't work ifcognet2006-03-091-74/+1
| | | | the pointer is unaligned, and it just doesn't worth it.
* Try to honor BUS_DMA_COHERENT : if the flag is set, normally allocate memorycognet2006-03-011-0/+7
| | | | | | with malloc() or contigmalloc() as usual, but try to re-map the allocated memory into a VA outside the KVA, non-cached, thus making the calls to bus_dmamap_sync() for these buffers useless.
* Use memory clobbers, to be on the safe side.cognet2006-02-061-6/+11
| | | | Suggested by: jhb
* Backout rev 1.12. It would have been a good thing, if gcc was smart enoughcognet2006-02-051-24/+18
| | | | not to generate bad code.
* By popular demand, move __HAVE_ACPI and __PCI_REROUTE_INTERRUPT intoimp2006-01-092-2/+2
| | | | | | | | param.h. Per request, I've placed these just after the _NO_NAMESPACE_POLLUTION ifndef. I've not renamed anything yet, but may since we don't need the __. Submitted by: bde, jhb, scottl, many others.
* Define __HAVE_ACPI and/or __PCI_REROUTE_INTERRUPT, as appropriate forimp2006-01-011-0/+2
| | | | | each platform. These will be used in the pci code in preference to the complicated #ifdefs we have there now.
* Tweak how the MD code calls the fooclock() methods some. Instead ofjhb2005-12-222-25/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | passing a pointer to an opaque clockframe structure and requiring the MD code to supply CLKF_FOO() macros to extract needed values out of the opaque structure, just pass the needed values directly. In practice this means passing the pair (usermode, pc) to hardclock() and profclock() and passing the boolean (usermode) to hardclock_cpu() and hardclock_process(). Other details: - Axe clockframe and CLKF_FOO() macros on all architectures. Basically, all the archs were taking a trapframe and converting it into a clockframe one way or another. Now they can just extract the PC and usermode values directly out of the trapframe and pass it to fooclock(). - Renamed hardclock_process() to hardclock_cpu() as the latter is more accurate. - On Alpha, we now run profclock() at hz (profhz == hz) rather than at the slower stathz. - On Alpha, for the TurboLaser machines that don't have an 8254 timecounter, call hardclock() directly. This removes an extra conditional check from every clock interrupt on Alpha on the BSP. There is probably room for even further pruning here by changing Alpha to use the simplified timecounter we use on x86 with the lapic timer since we don't get interrupts from the 8254 on Alpha anyway. - On x86, clkintr() shouldn't ever be called now unless using_lapic_timer is false, so add a KASSERT() to that affect and remove a condition to slightly optimize the non-lapic case. - Change prototypeof arm_handler_execute() so that it's first arg is a trapframe pointer rather than a void pointer for clarity. - Use KCOUNT macro in profclock() to lookup the kernel profiling bucket. Tested on: alpha, amd64, arm, i386, ia64, sparc64 Reviewed by: bde (mostly)
* A #define is not enough, we need to cast from u_long * to uint32_t *.cognet2005-12-091-1/+8
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* Define atomic_whatever_longcognet2005-12-091-0/+4
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* Drop _MACHINE_ARCH and _MACHINE defines (not to be confused withru2005-12-061-6/+0
| | | | | | | MACHINE_ARCH and MACHINE). Their purpose was to be able to test in cpp(1), but cpp(1) only understands integer type expressions. Using such unsupported expressions introduced a number of subtle bugs, which were discovered by compiling with -Wundef.
* Use a magic number to know we were started from the elf wrapper.cognet2005-11-241-0/+5
| | | | Add a dummy _start function to make the non-elf version of the wrapper work.
* Force pmap to write-back the pte cacheline after each pte modification,cognet2005-11-211-0/+5
| | | | | even if the pte is supposed to be cached in write through mode (might be a skyeye bug, I'll have to check).
* Add an alternate ID for the arm920t (the real solution is to havecognet2005-11-211-0/+1
| | | | per-cpu class masks, but oh well).
* There's no need to include <machine/asmacros.h> here.cognet2005-11-081-1/+0
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* MFi386 rev 1.536 (sort of)cognet2005-11-061-0/+2
| | | | | | | | Move what can be moved (UMA zones creation, pv_entry_* initialization) from pmap_init2() to pmap_init(). Create a new function, pmap_postinit(), called from cpu_startup(), to do the L1 tables allocation. pmap_init2() is now empty for arm as well.
* Whitespace.jhb2005-10-141-1/+1
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* Change the userland atomic operations on arm to use memory operands forjhb2005-10-141-16/+22
| | | | | | | | | the modified memory rather than using register operands that held a pointer to the memory. The biggest effect is that we now correctly tell the compiler that these functions change the memory that these functions modify. Reviewed by: cognet
* dump_avail has nothing to do with ARM_USE_SMALL_ALLOC, so move itscognet2005-10-041-1/+1
| | | | declaration out of the #ifdef.
* Provide a dump_avail[] variable, which contains the page ranges to becognet2005-10-031-0/+2
| | | | | | | dumped. For iq31244_machdep.c, attempt to recognize hints provided by the elf trampoline.
* Add a new API to let platform-specific ports provide functions for bigcognet2005-10-031-0/+10
| | | | copy/zeroing.
* asm versions of in_cksum_hdr() and in_pseudo().cognet2005-10-031-2/+80
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* Add a new atomic_fetchadd() primitive that atomically adds a value to ajhb2005-09-271-0/+38
| | | | | | | | | variable and returns the previous value of the variable. Tested on: i386, alpha, sparc64, arm (cognet) Reviewed by: arch@ Submitted by: cognet (arm) MFC after: 1 week
* Move MINSIGSTKSZ from <machine/signal.h> to <machine/_limits.h> and renamestefanf2005-08-202-4/+3
| | | | | | | | | | it to __MINSIGSTKSZ. Define MINSIGSTKSZ in <sys/signal.h>. This is done in order to use MINSIGSTKSZ for the macro PTHREAD_STACK_MIN in <pthread.h> (soon <limits.h>) without having to include the whole <sys/signal.h> header. Discussed with: bde
* msdosfs_conv.c references cmos_wall_clock and adjkerntz. Since theseimp2005-07-271-0/+3
| | | | | are 0 for arm, define them as such to make msdosfs_conv.c compile again on arm.
* Add extra constraints to tell the compiler that the memory be modifiedjhb2005-07-271-2/+4
| | | | | | | | | | | | in the arm __swp() and sparc64 casa() and casax() functions is actually being used as an input and output and not just the value of the register that points to the memory location. This was the underlying source of the mbuf refcount problems on sparc64 a while back. For arm this should be a nop because __swp() has a constraint to clobber all memory which can probably be removed now. Reviewed by: alc, cognet MFC after: 1 week
* Use a + constraint modifier for a register arg in __bswap16_var().jhb2005-07-271-3/+2
| | | | Reviewed by: cognet
* Convert the atomic_ptr() operations over to operating on uintptr_tjhb2005-07-151-8/+4
| | | | | | | | | | variables rather than void * variables. This makes it easier and simpler to get asm constraints and volatile keywords correct. MFC after: 3 days Tested on: i386, alpha, sparc64 Compiled on: ia64, powerpc, amd64 Kernel toolchain busted on: arm
* Fix a typo.jhb2005-06-231-1/+1
| | | | Approved by: re (scottl)
* MFP4:jkoshy2005-06-091-0/+14
| | | | | | | | | | | | | | | | - Implement sampling modes and logging support in hwpmc(4). - Separate MI and MD parts of hwpmc(4) and allow sharing of PMC implementations across different architectures. Add support for P4 (EMT64) style PMCs to the amd64 code. - New pmcstat(8) options: -E (exit time counts) -W (counts every context switch), -R (print log file). - pmc(3) API changes, improve our ability to keep ABI compatibility in the future. Add more 'alias' names for commonly used events. - bug fixes & documentation.
* - MFp4: modify slightly the arm intr API, there's arm CPUs with more than 32cognet2005-06-091-4/+4
| | | | | interrupts. - Implement teardown methods where appropriate.
* Add a new arm-specific option, ARM_USE_SMALL_ALLOC. If defined, it providescognet2005-06-072-0/+16
| | | | | an implementation of uma_small_alloc() which tries to preallocate memory 1MB per 1MB, and maps it into a section mapping.
* Bring in bits I forgot while importing write back support for arm9.cognet2005-06-031-11/+13
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