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* Use a magic number to know we were started from the elf wrapper.cognet2005-11-241-0/+5
* Force pmap to write-back the pte cacheline after each pte modification,cognet2005-11-211-0/+5
* Add an alternate ID for the arm920t (the real solution is to havecognet2005-11-211-0/+1
* There's no need to include <machine/asmacros.h> here.cognet2005-11-081-1/+0
* MFi386 rev 1.536 (sort of)cognet2005-11-061-0/+2
* Whitespace.jhb2005-10-141-1/+1
* Change the userland atomic operations on arm to use memory operands forjhb2005-10-141-16/+22
* dump_avail has nothing to do with ARM_USE_SMALL_ALLOC, so move itscognet2005-10-041-1/+1
* Provide a dump_avail[] variable, which contains the page ranges to becognet2005-10-031-0/+2
* Add a new API to let platform-specific ports provide functions for bigcognet2005-10-031-0/+10
* asm versions of in_cksum_hdr() and in_pseudo().cognet2005-10-031-2/+80
* Add a new atomic_fetchadd() primitive that atomically adds a value to ajhb2005-09-271-0/+38
* Move MINSIGSTKSZ from <machine/signal.h> to <machine/_limits.h> and renamestefanf2005-08-202-4/+3
* msdosfs_conv.c references cmos_wall_clock and adjkerntz. Since theseimp2005-07-271-0/+3
* Add extra constraints to tell the compiler that the memory be modifiedjhb2005-07-271-2/+4
* Use a + constraint modifier for a register arg in __bswap16_var().jhb2005-07-271-3/+2
* Convert the atomic_ptr() operations over to operating on uintptr_tjhb2005-07-151-8/+4
* Fix a typo.jhb2005-06-231-1/+1
* MFP4:jkoshy2005-06-091-0/+14
* - MFp4: modify slightly the arm intr API, there's arm CPUs with more than 32cognet2005-06-091-4/+4
* Add a new arm-specific option, ARM_USE_SMALL_ALLOC. If defined, it providescognet2005-06-072-0/+16
* Bring in bits I forgot while importing write back support for arm9.cognet2005-06-031-11/+13
* Remove bus_{mem,p}io.h and related code for a micro-optimization on i386nyan2005-05-292-66/+0
* s/_KLD_MODULE/KLD_MODULE/cognet2005-05-261-1/+1
* Remove bits specific to CPUs we won't support (< armv4).cognet2005-05-251-36/+4
* Use asm versions of in_cksum() and friends.cognet2005-05-241-1/+11
* Asm version of bswap16().cognet2005-05-241-5/+6
* Make sure we clean the RAS start address once we're done.cognet2005-05-241-0/+12
* Add empty header (except of the multiple-inclusion protection) tomarcel2005-04-201-0/+10
* Break out the definition of bus_space_{tag,handle}_t and a few other typesimp2005-04-182-11/+47
* Import a basic implementation of the restartable atomic sequences to providecognet2005-04-072-38/+148
* - Try harder to report dirty page.cognet2005-04-071-0/+2
* Divorce critical sections from spinlocks. Critical sections as denoted byjhb2005-04-042-55/+2
* Bring in a version of float.h more correct for softfloat.cognet2005-03-201-12/+17
* Refactor the bus_dma header files so that the interface is described inscottl2005-03-142-152/+108
* netchild's mega-patch to isolate compiler dependencies into a centraljoerg2005-03-023-11/+18
* Instead of using sysarch() to store-retrieve the tp, add a magic address,cognet2005-02-263-0/+5
* Add the field in the md part of the struct thread required by ARM_[GET|SET]_TP.cognet2005-02-261-0/+1
* Implement two new sysarch for arm, ARM_GET_TP and ARM_SET_TP, to work aroundcognet2005-02-251-0/+3
* Use a common multi-inclusion protection, and add such aru2005-02-191-4/+4
* Define NIRQ to 64 for CPU_ARM9, because Cirrus Logic EP93XX cores providescognet2005-02-131-0/+4
* Sort functions.njl2005-02-011-4/+4
* Start to support the big endian case as well.cognet2005-01-181-0/+13
* Add the prototype for bus_dmamap_load_mbuf_sg().cognet2005-01-151-0/+3
* Add support for ptrace() and gdb breakpoints.cognet2005-01-102-0/+8
* Start all license statements with /*-imp2005-01-0540-43/+39
* Make sure gcc doesn't generate something such as swp r3, r4, [r3] for __swp,cognet2004-12-181-1/+1
* Remove an unused field from the struct pv_entry.cognet2004-12-051-4/+3
* Implement breakpoints and single stepping on arm.cognet2004-11-212-6/+13
* Implement enough to be able to enter and leave DDB.cognet2004-11-202-3/+20
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