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* Support kernel crash mini dumps on ARM architecture.raj2008-11-061-0/+1
| | | | Obtained from: Juniper Networks, Semihalf
* Remove unused pv_list_count from the vm_page, and pm_count from the structcognet2008-03-061-2/+0
| | | | | | pmap. Submitted by: Mark Tinguely
* Bring in the nice work from Mark Tinguely on arm pmap.cognet2008-01-311-15/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The only downside is that it renames pmap_vac_me_harder() to pmap_fix_cache(). From Mark's email on -arm : pmap_get_vac_flags(), pmap_vac_me_harder(), pmap_vac_me_kpmap(), and pmap_vac_me_user() has been rewritten as pmap_fix_cache() to be more efficient in the kernel map case. I also removed the reference to the md.kro_mappings, md.krw_mappings, md.uro_mappings, and md.urw_mappings counts. In pmap_clearbit(), we can also skip over tests and writeback/invalidations in the PVF_MOD and PVF_REF cases if those bits are not set in the pv_flag. PVF_WRITE will turn caching back on and remove the PV_MOD bit. In pmap_nuke_pv(), the vm_page_flag_clear(pg, PG_WRITEABLE) has been moved to the pmap_fix_cache(). We can be more agressive in attempting to turn caching back on by calling pmap_fix_cache() at times that may be appropriate to turn cache on (a kernel mapping has been removed, a write has been removed or a read has been removed and we know the mapping does not have multiple write mappings to a page). In pmap_remove_pages() the cpu_idcache_wbinv_all() is moved to happen before the page tables are NULLed because the caches are virtually indexed and virtually tagged. In pmap_remove_all(), the pmap_remove_write(m) is added before the page tables are NULLed because the caches are virtually indexed and virtually tagged. This also removes the need for the caches fixing routine (whichever is being used pmap_vac_me_harder() or pmap_fix_cache()) to be called on any of these mappings. In pmap_remove(), I simplified the cache cleaning process and removed extra TLB removals. Basically if more than PMAP_REMOVE_CLEAN_LIST_SIZE are removed, then just flush the entire cache.
* Properly handle supersections.cognet2007-07-271-4/+20
| | | | | | Make sure we cache entries in the L2 cache. Approved by: re (blanket)
* Introduce pmap_kenter_supersection(), which maps 16MB super-sections intocognet2007-06-111-0/+1
| | | | | the kernel pmap. Document a bit more the behavior of the xscale core 3.
* Switch the kernel's pmap domain from 15 to 0.cognet2007-05-191-2/+2
| | | | | This should be a no-op, and this is needed for xscale core 3 supersections support, as they are always part of the domain 0
* - Add bounce pages for arm, largely based on the i386 implementation.cognet2007-01-171-1/+1
| | | | | | | - Add a default parent dma tag, similar to what has been done for sparc64. - Before invalidating the dcache in POSTREAD, save the bits which are in the same cachelines than our buffers, but not part of it, and restore them after the invalidation.
* Fix a comment.ru2006-11-131-1/+1
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* Eliminate unused global variables.alc2006-11-111-3/+0
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* Identify the xscale 81342.cognet2006-11-071-1/+1
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* Rewrite ARM_USE_SMALL_ALLOC so that instead of the current behavior, it mapscognet2006-08-081-1/+2
| | | | | | | | whole the physical memory, cached, using 1MB section mappings. This reduces the address space available for user processes a bit, but given the amount of memory a typical arm machine has, it is not (yet) a big issue. It then provides a uma_small_alloc() that works as it does for architectures which have a direct mapping.
* Add partial pmap locking.alc2006-06-061-1/+13
| | | | | | Eliminate the unused allpmaps list. Tested by: cognet@
* Include machine/cpuconf.h in pmap.h in order to get ARM_NMMUS defined,cognet2006-05-311-1/+1
| | | | to appease -Wundef.
* Resurrect Skyeye support :cognet2006-05-131-0/+5
| | | | | | | | | | | | | Add a new option, SKYEYE_WORKAROUNDS, which as the name suggests adds workarounds for things skyeye doesn't simulate. Specifically : - Use USART0 instead of DBGU as the console, make it not use DMA, and manually provoke an interrupt when we're done in the transmit function. - Skyeye maintains an internal counter for clock, but apparently there's no way to access it, so hack the timecounter code to return a value which is increased at every clock interrupts. This is gross, but I didn't find a better way to implement timecounters without hacking Skyeye to get the counter value. - Force the write-back of PTEs once we're done writing them, even if they are supposed to be write-through. I don't know why I have to do that.
* MFp4: Don't write-back the PTEs if they are mapped write-through, this wascognet2006-04-091-5/+0
| | | | apparently only needed because skyeye has bugs in its cache emulation.
* Try to honor BUS_DMA_COHERENT : if the flag is set, normally allocate memorycognet2006-03-011-0/+7
| | | | | | with malloc() or contigmalloc() as usual, but try to re-map the allocated memory into a VA outside the KVA, non-cached, thus making the calls to bus_dmamap_sync() for these buffers useless.
* Force pmap to write-back the pte cacheline after each pte modification,cognet2005-11-211-0/+5
| | | | | even if the pte is supposed to be cached in write through mode (might be a skyeye bug, I'll have to check).
* MFi386 rev 1.536 (sort of)cognet2005-11-061-0/+2
| | | | | | | | Move what can be moved (UMA zones creation, pv_entry_* initialization) from pmap_init2() to pmap_init(). Create a new function, pmap_postinit(), called from cpu_startup(), to do the L1 tables allocation. pmap_init2() is now empty for arm as well.
* dump_avail has nothing to do with ARM_USE_SMALL_ALLOC, so move itscognet2005-10-041-1/+1
| | | | declaration out of the #ifdef.
* Provide a dump_avail[] variable, which contains the page ranges to becognet2005-10-031-0/+2
| | | | | | | dumped. For iq31244_machdep.c, attempt to recognize hints provided by the elf trampoline.
* Add a new arm-specific option, ARM_USE_SMALL_ALLOC. If defined, it providescognet2005-06-071-0/+12
| | | | | an implementation of uma_small_alloc() which tries to preallocate memory 1MB per 1MB, and maps it into a section mapping.
* - Try harder to report dirty page.cognet2005-04-071-0/+2
| | | | - Garbage-collect pmap_update(), it became quite useless.
* Instead of using sysarch() to store-retrieve the tp, add a magic address,cognet2005-02-261-0/+1
| | | | | | | | | | | ARM_TP_ADDRESS, where the tp will be stored. On CPUs that support it, a cache line will be allocated and locked for this address, so that it will never go to RAM. On CPUs that does not, a page is allocated for it (it will be a bit slower, and is wrong for SMP, but should be fine for UP). The tp is still stored in the mdthread struct, and at each context switch, ARM_TP_ADDRESS gets updated. Suggested by: davidxu
* Start all license statements with /*-imp2005-01-051-1/+1
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* Remove an unused field from the struct pv_entry.cognet2004-12-051-4/+3
| | | | While I'm there, fix style.
* Import md bits for mem(4) on arm.cognet2004-11-071-45/+6
| | | | While I'm there, cleanup a bit pmap.h.
* Implement pmap_growkernel() and pmap_extract_and_hold().cognet2004-09-231-66/+26
| | | | | | | | | Remove the cache state logic : right now, it provides more problems than it helps. Add helper functions for mapping devices while bootstrapping. Reorganize the code a bit, and remove dead code. Obtained from: NetBSD (partially)
* Define pmap_page_is_mapped().cognet2004-07-211-0/+1
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* Forward declare "struct pcb", so that one does not need to includecognet2004-07-121-0/+2
| | | | <machine/pcb.h> before including <machine/pmap.h>.
* Import FreeBSD/arm kernel bits.cognet2004-05-141-0/+586
It only supports sa1110 (on simics) right now, but xscale support should come soon. Some of the initial work has been provided by : Stephane Potvin <sepotvin at videotron.ca> Most of this comes from NetBSD.
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