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* Merging projects/armv6, part 1gonzo2012-08-151-10/+76
| | | | | | | | | Cummulative patch of changes that are not vendor-specific: - ARMv6 and ARMv7 architecture support - ARM SMP support - VFP/Neon support - ARM Generic Interrupt Controller driver - Simplification of startup code for all platforms
* trim trailing whitespaceimp2012-06-131-1/+1
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* Fix 2 bugs :cognet2011-10-161-16/+14
| | | | | | | | | | | | | | - A race condition could happen if two threads were using RAS at the same time as the code didn't reset RAS_END, the RAS code could believe we were not in a RAS, when we were in fact. - Using signed value logic to compare addresses wasn't such a good idea. Many thanks to Ian to investigate on these issues. Pointy hat to: cognet PR: arm/161498 Submitted by: Ian Lepore <freebsd At damnhippie DOT dyndns dot org MFC after: 1 week
* Improve ARM_TP_ADDRESS and RAS area.raj2008-02-051-4/+4
| | | | | | | | | | | | | | De-hardcode usage of ARM_TP_ADDRESS and RAS local storage, and move this special purpose page to a more convenient place i.e. after the vectors high page, more towards the end of address space. Previous location (0xe000_0000) caused grief if KVA was to go beyond the default limit. Note that ARM world rebuilding is required after this change since the location of ARM_TP_ADDRESS is shared between kernel and userland. Submitted by: Grzegorz Bernacki (gjb AT semihalf dot com) Reviewed by: imp Approved by: cognet (mentor)
* Close a race.cognet2007-12-021-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The RAS implementation would set the end address, then the start address. These were used by the kernel to restart a RAS sequence if it was interrupted. When the thread switching code ran, it would check these values and adjust the PC and clear them if it did. However, there's a small flaw in this scheme. Thread T1, sets the end address and gets preempted. Thread T2 runs and also does a RAS operation. This resets end to zero. Thread T1 now runs again and sets start and then begins the RAS sequence, but is preempted before the RAS sequence executes its last instruction. The kernel code that would ordinarily restart the RAS sequence doesn't because the PC isn't between start and 0, so the PC isn't set to the start of the sequence. So when T1 is resumed again, it is at the wrong location for RAS to produce the correct results. This causes the wrong results for the atomic sequence. The window for the first race is 3 instructions. The window for the second race is 5-10 instructions depending on the atomic operation. This makes this failure fairly rare and hard to reproduce. Mutexs are implemented in libthr using atomic operations. When the above race would occur, a lock could get stuck locked, causing many downstream problems, as you might expect. Also, make sure to reset the start and end address when doing a syscall, or a malicious process could set them before doing a syscall. Reviewed by: imp, ups (thanks guys) Pointy hat to: cognet MFC After: 3 days
* Twist the RAS logic a bit to avoid branching.cognet2007-09-221-12/+9
| | | | | MFC After: 1 week Approved by: re (blanket)
* Disable/enable fiqs as well as irqs.cognet2006-04-131-3/+3
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* Import a basic implementation of the restartable atomic sequences to providecognet2005-04-071-1/+15
| | | | | atomic operations to userland (this is OK for UP only, but SMP is still so far away).
* Start all license statements with /*-imp2005-01-051-1/+1
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* Rename macroes, as we don't need to mess with alignment faults.cognet2004-09-231-41/+14
| | | | Call ast() if TDF_NEEDRESCHED is set too, not just TDF_ASTPENDING.
* Import FreeBSD/arm kernel bits.cognet2004-05-141-0/+204
It only supports sa1110 (on simics) right now, but xscale support should come soon. Some of the initial work has been provided by : Stephane Potvin <sepotvin at videotron.ca> Most of this comes from NetBSD.
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