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* MFC r292419, r294237:ian2016-01-241-2/+10
| | | | | | Fix the clock divisor calc for imx6 sdcard bus speed. Quick exit after setting the clock control register.
* MFC r291149, r291367:ian2016-01-245-16/+46
| | | | | | | | | | | | | | Update the imx5/imx6 cpu_reset() implementation based on a new understanding of the SRS (software reset) bit in the watchdog control register. Despite what the manual seems to imply, this bit DOES trigger an immediate reset, as opposed to simply flagging the type of reset as software-triggered. Rename sysctl node hw.imx6 to hw.imx. Move its definition to imx_machdep.c so that code shared between imx5 and imx6 can work with OIDs under that node. Add last_reset_status (integer) and last_reset_reason (string) OIDs that provide info about the last chip reset (power-on, software reset, watchdog timeout).
* MFC r281828, r289083, r289084, r289091, r289093, r289095, r289097, r289098,ian2015-10-202-172/+123
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | r289104, r289105, r289118: various i2c fixes... Fix numerous issues in iic(4) and iicbus(4): --Allow multiple open iic fds by storing addressing state in cdevpriv --Fix, as much as possible, the baked-in race conditions in the iic ioctl interface by requesting bus ownership on I2CSTART, releasing it on I2CSTOP/I2CRSTCARD, and requiring bus ownership by the current cdevpriv to use the I/O ioctls --Reduce internal iic buffer size and remove 1K read/write limit by iteratively calling iicbus_read/iicbus_write --Eliminate dynamic allocation in I2CWRITE/I2CREAD --Move handling of I2CRDWR to separate function and improve error handling --Add new I2CSADDR ioctl to store address in current cdevpriv so that I2CSTART is not needed for read(2)/write(2) to work --Redesign iicbus_request_bus() and iicbus_release_bus(): --iicbus_request_bus() no longer falls through if the bus is already owned by the requesting device. Multiple threads on the same device may want exclusive access. Also, iicbus_release_bus() was never device-recursive anyway. --Previously, if IICBUS_CALLBACK failed in iicbus_release_bus(), but the following iicbus_poll() call succeeded, IICBUS_CALLBACK would not be issued again --Do not hold iicbus mtx during IICBUS_CALLBACK call. There are several drivers that may sleep in IICBUS_CALLBACK, if IIC_WAIT is passed. --Do not loop in iicbus_request_bus if IICBUS_CALLBACK returns EWOULDBLOCK; instead pass that to the caller so that it can retry if so desired. Bugfix: Exit the transfer loop if any read or write operation fails. Also, perform a stop operation on the bus if there was an error, otherwise the bus will remain hung forever. Consistantly use 'if (error != 0)' style in the function. Mostly rewrite the imx i2c driver. This started out as an attempt to fix one specific problem: the driver didn't check for ACK/NAK after writing a slave address byte to the bus, and some slaves signal that they are busy (such as when completing an internal write to flash memory) by sending a NAK in response to being addressed. Use IIC_EBUSBSY and IIC_BUSERR status values consistantly across all drivers. Make it clearer what each one means in the comments that define them. Add iic2errno(), a helper function to translate IIC_Exxxxx status values to errno values that are at least vaguely equivelent. Also add a new status value, IIC_ERESOURCE, to indicate a failure to acquire memory or other required resources to complete a transaction. Return only IIC_Exxxx status values from iicbus-layer functions. Most of these functions are thin wrappers around calling the hardware-layer driver, but some of them do sanity checks and return an error. Add a short name, IIC_INTRWAIT, for the common case (IIC_INTR | IIC_WAIT). Replace a local sx lock that allowed only one client at a time to access an eeprom device with iicbus_request/release_bus(), which achieves the same effect and also keeps other i2c slave drivers from clashing on the bus.
* MFC r286942, r286943, r286944: imx watchdog fixes...ian2015-08-232-33/+38
| | | | | | | | | | | | | | | | Add compatible strings for all the hardware this driver works with. Also, move the READ/WRITE bus space access macros from the header into the source file, and rename them to RD2/WR2 to make it clear they're 16-bit accessors. (READ/WRITE just don't seem like good names to be in a public header file.) Make the imx watchdog actually work, by setting WDOG_CR_WDE (enable bit). Also, follow the rules from watchdog(9) about what values to return in various situations (especially, don't touch *error when asked to set a non-zero timeout that isn't achievable on the hardware). Enable the watchdog driver on imx6, now that it works.
* MFC r282516:ian2015-05-244-21/+63
| | | | | Add the code necessary to run the imx6 chip at its lowest clock/power operating point (396MHz/950mV).
* MFC r268838, r277644:ian2015-05-2411-1/+1896
| | | | | | | | | Add support for Toradex Apalis i.MX6 development board. Add support for imx6 audio transmitting, include drivers for: o Digital Audio Multiplexer (AUDMUX) o Smart Direct Memory Access Controller (SDMA) o Synchronous Serial Interface (SSI)
* MFC r279723, r279724:ian2015-05-231-1/+8
| | | | | | | | | Define new linker set, UART_FDT_CLASS_AND_DEVICE, for registering full (class and device) FDT UART. Define second one, UART_FDT_CLASS, for UART class only. Move the uart_class definitions and fdt compat data into the individual uart implementations, and export them using the new linker-set mechanism.
* MFC r274670, r274671, r276168:loos2015-02-142-19/+0
| | | | | | | | | | | | | | Moves all the duplicate code to a single function. Verify for invalid modes and unwanted flags before pass the new flags to driver. Make gpio_default_map_gpios() static. No functional changes. Improves the GPIO API description a little bit. gpio_pin_max must return the maximum supported pin number and not the total number of pins on the system.
* MFC r273799:loos2015-02-142-4/+4
| | | | | | | | Make the GPIO children attach to the first unit available and not only to unit 0. This fix a bug where a GPIO controller could fail to attach its children (gpioc and gpiobus) if another GPIO driver attach first.
* MFC r277555, r277568:ian2015-02-132-4/+29
| | | | | | Enable all sd device clocks on imx6. Add imx5/6 pinmux driver support for encoded input register configs.
* MFC r277454, r277460, r277465, r277466, r277467, r277469, r277470, r277471,ian2015-02-134-4/+4
| | | | | | | | | | | | | | | | | | | | | r277472, r277473, r277474, r277475, r277476, r277477, r277478, r277479, r277480, r277512, r277516: Add inline implementations of arm bus_space_read/write_N(). Revise the arm bus_space implementation to avoid dereferencing the tag on every operation to retrieve the bs_cookie value almost nothing actually uses. Use the explicit member initializer style to init the bus_space struct. Use arm/bus_space-v6.c for all armv6 systems Consolidate many identical implementations of bus_space to a single common tag and implementation shared by armv4 and armv6. Micro-optimize the new arm inline bus_space implementation by grouping all the data the inline functions access together at the start of the bus_space struct so that they all fit in a single cache line.
* MFC r257740, r257739: Switch to using common armv6 bus_space tag.ian2015-02-134-133/+3
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* MFC r276047: Add -march=armv7a to the kernel compile for all v7a ARM systems.ian2015-02-114-0/+4
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* MFC r266969 and r276717:hselasky2015-02-051-0/+1
| | | | | | Add 64-bit DMA support in the XHCI controller driver. - Fix some comments and whitespaces while at it. - Add support for PAE.
* MFC r274641, r274644, r274822, r276049:ian2014-12-271-12/+42
| | | | | | | | | | | Allow i2c bus speed to be configured via hints, FDT data, and sysctl. Implement bus speed setting for OMAP4, AM335x, and imx5/6. Fix the i2c bus speed divisors for TI OMAP4 and AM335x to give the advertised 100, 400, and 1000 KHz speeds. PR: 195009
* MFC r274412, r274413, r274414: Bugfixes for imx5/6 pinctrl driver.ian2014-12-271-3/+21
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* MFC r273561:ian2014-10-261-1/+35
| | | | | Install a temporary workaround to avoid problems in fdt data with linux's workaround for an imx6 chip erratum by using gpio1_6 as an interrupt.
* MFC r273353, r273514:ian2014-10-261-1/+26
| | | | | | | Attach the imx6 CCM driver during BUS_PASS_CPU. Unconditionally enable the clocks for all imx6 devices that we have drivers for, or that are required to run the chip (such as busses).
* MFC r273352: Ask for the fastest available clock for the GTP timecounter.ian2014-10-261-1/+1
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* MFC r273283:ian2014-10-261-7/+38
| | | | | | | Attach this driver during BUS_PASS_BUS and move the cpu init code to a bus_new_pass() handler so it doesn't happen until BUS_PASS_CPU. This allows the anatop driver to outbid the generic simplebus driver (which the FDT data describes as compatible).
* MFC r271595, r271601, r271607, r271630:ian2014-10-262-1/+13
| | | | | | | | | | | | | | | Add compat strings for all the flavors of GIC this driver should support. Also allow the driver to attach to ofwbus as well as simplebus, some FDT data puts the root interrupt controller on the root bus. Add a common routine for parsing FDT data describing an ARM GIC interrupt. Use gic_decode_fdt() rather than a local routine to parse fdt interrupt properties. Move fdt_pic_table and fdt_fixup_table into imx6_machdep.c, which means imx6 doesn't need imx_common.c anymore. The private peripheral interrupts start at offset 16, not 0. Also, use names rather than inline mystery constants for these offsets.
* MFC r271550, r271591:ian2014-10-2611-2036/+291
| | | | | Replace the imx5 and imx6 iomux drivers with a single common driver that uses the new fdt_pinctrl interface.
* MFC r271097, r271100, r271101, r271102, r271124:ian2014-10-268-84/+1045
| | | | | | | | - Add a basic iomux driver for imx6. - Implement the same public interface in imx51 and imx6 iomux - The iomux driver is no longer optional, remove it from kernel configs. - Implement the imx_iomux_get/set_gpr() interface for imx6. - Stop setting the iomux device status to disabled, now that we have a driver.
* MFC r268973, r268977: Rename i.MX I2C driver file, enable it on imx6.ian2014-10-265-6/+12
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* MFC r268834, r268835:ian2014-10-264-7/+12
| | | | | | | | o Enable GPIO device driver for i.MX6. It was originally written for i.MX5 and compatible with newer chip. o Extend device tree information o style(9) fixes o Rename gpio driver file.
* MFC r271055, r271084, r271094:ian2014-10-265-0/+92
| | | | | | | | | | | | | Add a function to get the frequency of the AHB bus. Another stopgap function until we have full clock support for imx6. The imx5x and imx6 chips have an onboard IOMUX device which also contains a few "general purpose registers" whose values control chip behavior in ways that have nothing to do with IO pin mux control. Define a simple API that other soc-specific code can use to read and write the registers, and provide the imx51 implementation of them. Fix a typo.
* MFC r270955,r270956: make the imx6 octop and anatop drivers early attachers.ian2014-10-262-6/+21
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* MFC r270945:ian2014-10-261-1/+1
| | | | | Rename OF_xref_phandle() to OF_node_from_xref() and add a new function that provides the inverse translation, OF_xref_from_node().
* MFC r270065:ian2014-09-091-4/+2
| | | | | | | Move the imx6 sysctl temperature info to hw.imx6 where all the other soc-wide info lives. It was under dev.imx6_anatop.0. Approved by: re(gjb)
* MFC: r270885, r270948marius2014-09-031-0/+1
| | | | | | | | | | | | - Nuke unused sdhci_softc. - Static'ize sdhci_debug local to sdhci.c. - Const'ify PCI device description strings. - Nuke redundant resource ID members from sdhci_pci_softc. - Nuke unused hw.sdhci_pci.debug tunable. - Add support for using MSI instead of INTx, controllable via the tunable hw.sdhci.enable_msi (defaulting to on) and tested with a RICOH R5CE823 SD controller. - Use NULL instead of 0 for pointers.
* vt(4): Colors are indexed against a console palette, not a VGA palettedumbbell2014-08-211-5/+5
| | | | | | | | | | | | | | | | | | | | | | | Rename vt_generate_vga_palette() to vt_generate_cons_palette() and change it to build a palette where the color index is the same than in terminal escape codes, not the VGA index. That's what TCHAR_CREATE() uses and passes to vt(4). The main differences between both orders are: o Blue and red are swapped (1 <-> 4) o Yellow and cyan are swapped (3 <-> 6) The problem remained unnoticed, because the RGB bit indexes passed to vt_generate_vga_palette() were reversed. This inversion was cancelled by the colors inversions in the generated palette. For instance, red (0xff0000) and blue (0x0000ff) have bytes in opposite order, but were swapped in the palette. But after changing the value of blue (see last paragraph), the modified color was in fact the red one. While here, tune the palette to better match console colors and improve the readability (especially the dark blue). This is an MFC of r269783 and r269791.
* MFC r269607, r269698:ian2014-08-172-5/+15
| | | | | | | Cache the imx6 SoC type in a static var so that it only has to be figured out by sniffing hardware registers once. Add a missing clock register definition.
* MFC r268401, r268495:ian2014-07-252-2/+2
| | | | | | Pending interrupt status is cleared by writing to the ISR, not the data reg. Use named constant rather than '0' to access the reset controller register.
* MFC 265440, 265441, 265444, 265445, 265446, 265447:ian2014-05-181-0/+13
| | | | | | | | | | | | | | | | | | Move the pl310.enabled tunable to hw.pl310.enabled. Clean up a few minor style(9) nits. Use DEVMETHOD_END. Break out the code that figures out the L2 cache geometry to its own routine, so that it can be called from multiple places in upcoming changes. Call platform_pl310_init() before enabling the controller, and handle the case where the controller is already enabled. Add defines for the bits in the PL310 debug control register. Add a public routine to set the L2 cache ram latencies. This can be called by platform init routines to fine-tune cache performance. Enable PL310 power-saving modes and tune the cache ram latencies for imx6.
* MFC 265035: Move duplicated code to print l2 config into the common code.ian2014-05-171-36/+0
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* MFC 264977:ian2014-05-178-46/+117
| | | | | | Stop calling imx51_ccm_foo() clock functions from imx6 code. Instead define a few imx_ccm_foo() functions that are implemented by the imx51 or imx6 ccm code.
* MFC 264251: Updates to i.MX53:ian2014-05-174-67/+107
| | | | | * Define support for the SDHCI driver, although it doesn't work yet * Fix the memory mappings for IPU
* MFC 264180, 264181, 264182:ian2014-05-171-0/+2
| | | | | | | | Follow files.imx51 and add vt support for imx53. Add fsl,imx53 compatible string. Need to include machine/fdt.h in vt_early_fb.c
* MFC 264052, 264057, 264065, 264094, 264103, 264120ian2014-05-172-59/+182
| | | | | | | | | | | | | | | | | Actually save the mpcore clock frequency retrieved from fdt data. imx6.. - Don't call sdhci_init_slot() until after handling the FDT properties related to detecting card presence. - Flag several sysctl variables as tunables. - Rework the cpu frequency management code for imx6 to add "operating points" and min/max frequency controls. generic timer... - Setup both secure and non-secure timer IRQs. We don't know our ARM security state, so one of them will operate. - Don't set frequency, since it's unpossible in non-secure state. Only rely on DTS clock-frequency value or get clock from timer.
* MFC 264054, 264056ian2014-05-173-0/+7
| | | | | | | | Switch imx6 to using the mpcore per-cpu event timers, but continue to use the GPT timer, which is fixed-frequency, as a timecounter. Change NO_EVENTTIMERS from an arm-specific to an MI option, so that it can be used in MI code.
* MFC 262952, 262958, 262966, 262979, 262980, 262986, 262987, 262995, 262997,ian2014-05-174-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 263030, 263033, 263034, 263056, 263057, Remove all the redundant external declarations of exception vectors and runtime setting of the pointers that's scattered around various places. Remove all traces of support for ARM chips prior to the arm9 series. Make the default exception handler vectors point to where I thought they were already pointing: the default handlers (not a panic that says there is no default handler). Eliminate irq_dispatch.S. Move the data items it contained into arm/intr.c and the functionality it provided into arm/exception.S. Move the exception vector table (so-called "page0" data) into exception.S and eliminate vectors.S. Change the way the asm GET_CURTHREAD_PTR() macro is defined so that code using it doesn't have to have an "AST_LOCALS" macro somewhere in the file. Arrange for arm fork_trampoline() to return to userland via the standard swi_exit code in exception.S instead of having its own inline expansion of the DO_AST and PULLFRAME macros. Now that the PUSHFRAME and PULLFRAME macros are used only in the swi entry/exit code, they don't need to be macros. Except that didn't work and the whole change was reverted. Remove some unnecessary indirection and jump right to the handler functions. Use panic rather than printf to "handle" an arm26 address exception (should never happen on arm32). Remove the unreferenced DATA() macro. Remove #include <machine/asmacros.h> from files that don't need it.
* MFC 257774, 256760, 262916, 262905, 262918, 262919, 262920, 262921, 262924,ian2014-05-174-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 262925, 262929, 262932, 262935, 262940, 262941, 262942, 262948, 262949, 262950 Strip arm/conf/DEFAULTS down to just items that are mandatory for running the architecture. Move all the files named foo/common.c to foo/foo_common.c Initial cut for DTS on the hl201 board. Add commented out dts for sam9260ek as well as early printf support. Make clock optional on uart nodes, then back it out ("I don't know what I was thinking, but it is lame.") Set the baud rate if it isn't 0 Make at91_soc_id() public. Properly round at91 resource on unmapping. Move AT91 AIC related stuff to own file. Fix another bug in multicast filtering. i.MX uses 6 bits from MSB in LE CRC32 for the hash value, not the lowest 6 bits in BE CRC32. Follow r262916 with one more config file that references a renamed common.c Remove bogus AT91 define that causes compile errors. Most of the defines for SAM9X are going away soonish anyway (once FDT works), but until then... Remove all dregs of a per-thread undefined-exception-mode stack. Rework the VFP code that handles demand-based save and restore of state. Always call vfp_discard() on thread death. When a thread begins life it doesn't own the VFP hardware state on any cpu. Make undefined exception entry MP-safe.
* MFC 262695, 262708, 262709, 262710, 262711, 262728, 262870, 262877, 262880,ian2014-05-166-48/+430
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 262885, 262891, 262903, imx6: Add a tunable to set the number of active cores, enable SMP by default. ffec: Fix multicast filtering. Allwinner a10/a20... - Add gpio and clock bits for A10/A20's EMAC ethernet controller driver - EMAC gpio configuration - EMAC clock activation - Add Static Random Access Memory controller driver for A10/A20. A10/A20's SRAM is used by devices, such as CPU, EMAC, for extra fast memory or as cache. - Add EMAC 10/100 Ethernet controller driver for A10/A20. It is available mostly in A10 devices like Hackberry, Marsboard, Mele A1000, A2000, A100 HTPC, cubieboard1 and A20 device like cubieboard2. TX performance can be improved using both channels 0 and 1. RX performance is poor and needs improvement with the assistance of external DMA controller in case there - Add EMAC and SRAM controller entries to FDT. - Add EMAC device to kernel config files and enable EMAC, SRAM drivers. OMAP: When calculating the MPU freq, make sure not to overflow. Vybrid: - Add driver for Port control and interrupts (PORT). - Export panel info to DTS - Reset all the layers before setup first one - Enable display nandfs: Slight code reordering to make error branch last. Add option TMPFS to arm/conf/DEFAULTS, remove it from the few configs that have it individually. Concensus on freebsd-arm@ is that it should be included in all ARM kernels. Fix the arm sys_sigreturn(): its argument is a struct ucontext, not a struct sigframe containing the struct ucontext.
* MFC r262534, r262548, r262549, r262552, r262568, r262581, r262583, r262584,ian2014-05-166-20/+584
| | | | | | | | | | | | | | | | | | | | | | | | | | | | r262585, r262587, r262696, r262712 Replace many pasted identical definitions of cpu_initclocks() with a common implementation in arm/machdep.c. aicasm: Don't complain about missing prototypes to ease bootstrap issues. Vybrid: Add driver for Inter-Integrated Circuit (I2C). imx6: Initialize the Low Power Mode bits to keep the ARM cores running during WFI. All our current ARM multi-core systems have all cores in one package with a shared L2 cache, reflect that in the common cpu_topo() routine. mpcore timer: Supply a DELAY() implementation via weak linkage, so that SoC-specific code can supply a better implementation. imx6: Add some rudimentary voltage control. Add an armv7 implementation of cpu_sleep(). Add __used attribute so that the DELAY implementation doesn't get optimized away as unreferenced, causing linker errors when trying to resolve the weak reference to the missing function.
* MFC r262409, r262411, r262413, r262420, r262426, r262427, r262440, r262456,ian2014-05-166-40/+229
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | r262482, r262483, r262531, Move the declaration for mpentry() into a header file instead of pasting it into a bunch of different .c files. If the L2 cache type is PIPT, pass a physical address for a flush. Actually set the proper bit to indicate TTB shared memory. Add a new cache maintenance function, idcache_inv_all, to the table, and implementations for each of the chips we support. Invalidate caches immediately upon entry to init_secondary(). Also set the Bufferable bit in the PDE entries of the secondary processor startup pagetables. Add the bits needed to run SMP on imx6. Invalidate the SCU cache tag ram on all 4 cores, not just 1-3. Minor tweaks to the imx GPT timer Vybrid enhancements... - Pin configuration is a complete iomux register now and includes drive strength, pull mode, mux mode, speed, etc. - Add i2c devices to the tree - Add IPG clock - Add support for Quartz Module. - Pin configuration is a complete iomux register now and includes drive strength, pull mode, mux mode, speed, etc. - Add i2c devices to the tree - Add IPG clock
* MFC r261982, r261987, r262123, r262244, r262278, r262280, r262353, r262354,ian2014-05-156-29/+1268
| | | | | | | | | | | | | | | | | | | | | | r262355, r262419, Add Vybrid driver for Synchronous Audio Interface (SAI). Decrease SAI buffer size. Handle eDMA interrupt on running channel only. Give the physmem fdt helper routines static linkage since no global definition of them is provided anywhere. Add imx6 early printf support, wrapped in #if 0 because it's rarely needed. Add basic cpu frequency control and temperature monitoring to imx6_anatop. Add the FREEBSD_BOOT_LOADER option so that a loaded DTB passed in from ubldr will actually get used. Create a generic IMX6 kernel config, then fix it to have an ident line. Don't force imx6 bootverbose on anymore, it can be set from ubldr now.
* MFC r261938, r261939, r261940, r261944, r261945, r261946, r261947, r261956, ↵ian2014-05-155-26/+425
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | r261957, r261983, r261094, r261955, r261958, Add a driver to provide access to imx6 on-chip one-time-programmble data. Make it possible to access the ocotp registers before the ocotp device is attached, by establishing a temporary mapping of the registers when necessary. It turns out Freescale cleverly made the ocotp device compatible across several different families of SoCs, so move it to the freescale directory and prefix everything with fsl rather than imx6. Convert the imx6 sdhci "R1B fix" from a busy-loop in the interrupt handler to a callout. Increase the wait time for acquiring the SD bus from 10 to 250ms. If no compatible cards were found after probing the SD bus, say so. Add timeout logic to sdhci, separate from the timeouts done by the hardware. After a timeout, reset the controller using SDHCI_RESET_CMD|SDHCI_RESET_DATA rather than SDHCI_RESET_ALL; the latter turns off clocks and power, removing any possibility of recovering from the error. Add a helper routine to depth-search the device tree for a node with a matching 'compatible' property.
* MFC r261803, r261808, r261814, r261815, r261816, r261817, r261818, r261826,ian2014-05-154-14/+100
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | r261848, r261855 On armv6 and later, use the WriteNotRead bit of the fault status register to decide what protections are required by the faulting access. Use the right symbols for determining arm architecture. Include the necessary header file which has the new FAULT_WNR symbol defined in it. Allow the kernel to be loaded at any 1MiB address. This requirement is because we use the 1MiB section maps as they only need a single pagetable. Add function for configuring Vybrid PLL4 (Audio) clock frequency output. imx6 changes ... - Fix the definition of the SDHCI_STATE_DAT and SDHCI_STATE_CMD fields, and add SDHCI_RETUNE_REQUEST. None of these are actually used in the code yet. - Write translation code for the SDHCI_PRESENT_STATE register. Freescale moved some bits around in their version of the register, adjust things so that the sdhci code sees the standard layout. - Add standard non-removable and cd-gpios properties to the usdhc devices. That generates references to gpio devices, so uncomment them even though there isn't a gpio driver to do anything with them yet. - Add handling of standard "non-removable" property, and also some workaround code so that if card detect is wired to a gpio pin, for now we just treat it the same as non-removable (because there isn't a gpio driver yet). - Enable both sdcard slots, but not the sdio-based wifi that we don't yet have a driver for. - Remove a couple obsolete function declarations.
* MFC r261616, r261639ian2014-05-155-0/+729
| | | | | | | | Remove FreeBSD 6 support from atmel usb controllers. Add Vybrid drivers for: - Enhanced Direct Memory Access Controller (eDMA) - Direct Memory Access Multiplexer (DMAMUX)
* MFC r259270loos2014-05-153-3/+0
| | | | | After r266105 ofw_iicbuc.c will be built by default for any kernel which includes options 'iicbus' and 'fdt'. Remove the (now) unnecessary entries.
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