summaryrefslogtreecommitdiffstats
path: root/sys/amd64
Commit message (Collapse)AuthorAgeFilesLines
* OK, this might be a bit silly, but add another popcnt() candidate.peter2003-11-061-0/+6
|
* When remapping an ISA interrupt from one intpin to another, disable thejhb2003-11-052-9/+21
| | | | | | | | | pin that is used by the default identity mapping if it still maps to the old vector. The ACPI case might need some tweaking for the SCI interrupt case since ACPI likes to address the intpin using both the IRQ remapped to it as well as the previous existing PCI IRQ mapped to it. Reported by: kan
* Two style nits.jhb2003-11-051-0/+2
|
* - Adjust some of the bitfields in the ioapic_intsrc struct to be unsignedjhb2003-11-051-18/+18
| | | | | | | | | | rather than signed. This fixes some cosmetics such as verbose printf's for IRQs greater than 127. - The calculation for next_ioapic_base was also adjusted so that it will only complain once for each hole in the IRQs provided by ACPI for IO APICs. Reported by: Michal Mertl <mime@traveller.cz>
* Add a workaround for MP Tables that list the same PCI IRQ twice withjhb2003-11-051-3/+16
| | | | | | the same APIC / pin destination in both cases. Reported by: Pawel Jakub Dawidek <nick@garage.freebsd.pl>
* Tweak the version string output for ioapic devices.jhb2003-11-041-2/+3
|
* Fix to support pc98.nyan2003-11-041-0/+6
|
* Split pc98 support into pc98/pc98/nmi.c.nyan2003-11-041-22/+1
|
* Make this compile with PAE.peter2003-11-041-5/+6
|
* New i386 SMP code:jhb2003-11-032-1993/+359
| | | | | | | | | | | | | | | | | | | | | | - The MP code no longer knows anything specific about an MP Table. Instead, the local APIC code adds CPUs via the cpu_add() function when a local APIC is enumerated by an APIC enumerator. - Don't divide the argument to mp_bootaddress() by 1024 just so that we can turn around and mulitply it by 1024 again. - We no longer panic if SMP is enabled but we are booted on a UP machine. - init_secondary(), the asm code between init_secondary() and ap_init() in mpboot.s and ap_init() have all been merged together in C into init_secondary(). - We now use the cpuid feature bits to determine if we should enable PSE, PGE, or VME on each AP. - Due to the change in the implementation of critical sections, acquire the SMP TLB mutex around a slightly larger chunk of code for TLB shootdowns. - Remove some of the debug code from the original SMP implementation that is no longer used or no longer applies to the new APIC code. - Use a temporary hack to disable the ACPI module until the SMP code has been further reorganized to allow ACPI to work as a module again. - Add a DDB command to dump the interesting contents of the IDT.
* Don't probe PnP BIOS devices for PICs for now to avoid problems with thosejhb2003-11-031-9/+3
| | | | | | devices claiming resources that they don't actually use. The PIC drivers only register valid interrupt sources, so we don't need to rely on these drivers to claim invalid IRQs to prevent their use by other drivers.
* Add the ACPI MADT table APIC enumerator. This code uses the ACPI Multiplejhb2003-11-031-0/+650
| | | | | | | | | | APIC Descriptor Table to enumerate both I/O APICs and local APICs. ACPI does not embed PCI interrupt routing information in the MADT like the MP Table does. Instead, ACPI stores the PCI interrupt routing information in the _PRT object under each PCI bus device. The MADT table simply provides hints about which interrupt vectors map to which I/O APICs. Thus when using ACPI, the existing ACPI PCI bridge drivers are sufficient to route PCI interrupts.
* Add the MP Table APIC enumerator. This code uses the BIOS MP Table tojhb2003-11-033-5346/+862
| | | | | enumerate I/O APICs as well as local APICs. It also provides Host-PCI and PCI-PCI bridge drivers to use the MP Table to route PCI interrupts.
* New APIC support code:jhb2003-11-035-350/+1725
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - The apic interrupt entry points have been rewritten so that each entry point can serve 32 different vectors. When the entry is executed, it uses one of the 32-bit ISR registers to determine which vector in its assigned range was triggered. Thus, the apic code can support 159 different interrupt vectors with only 5 entry points. - We now always to disable the local APIC to work around an errata in certain PPros and then re-enable it again if we decide to use the APICs to route interrupts. - We no longer map IO APICs or local APICs using special page table entries. Instead, we just use pmap_mapdev(). We also no longer export the virtual address of the local APIC as a global symbol to the rest of the system, but only in local_apic.c. To aid this, the APIC ID of each CPU is exported as a per-CPU variable. - Interrupt sources are provided for each intpin on each IO APIC. Currently, each source is given a unique interrupt vector meaning that PCI interrupts are not shared on most machines with an I/O APIC. That mapping for interrupt sources to interrupt vectors is up to the APIC enumerator driver however. - We no longer probe to see if we need to use mixed mode to route IRQ 0, instead we always use mixed mode to route IRQ 0 for now. This can be disabled via the 'NO_MIXED_MODE' kernel option. - The npx(4) driver now always probes to see if a built-in FPU is present since this test can now be performed with the new APIC code. However, an SMP kernel will panic if there is more than one CPU and a built-in FPU is not found. - PCI interrupts are now properly routed when using APICs to route interrupts, so remove the hack to psuedo-route interrupts when the intpin register was read. - The apic.h header was moved to apicreg.h and a new apicvar.h header that declares the APIs used by the new APIC code was added.
* Add the new atpic(4) driver for the 8259A master and slave PICs. Byjhb2003-11-032-178/+492
| | | | | | | | | | | | default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
* New device interrupt code. This defines an interrupt source abstractionjhb2003-11-032-0/+387
| | | | | | | | | | | | | | | | | | that provides methods via a PIC driver to do things like mask a source, unmask a source, enable it when the first interrupt handler is added, etc. The interrupt code provides a table of interrupt sources indexed by IRQ numbers, or vectors. These vectors are what new-bus uses for its IRQ resources and for bus_setup_intr()/bus_teardown_intr(). The interrupt code then maps that vector a given interrupt source object. When an interrupt comes in, the low-level interrupt code looks up the interrupt source for the source that triggered the interrupt and hands it off to this code to execute the appropriate handlers. By having an interrupt source abstraction, this allows us to have different types of interrupt source providers within the shared IRQ address space. For example, IRQ 0 may map to pin 0 of the master 8259A PIC, IRQs 1 through 60 may map to pins on various I/O APICs, and IRQs 120 through 128 may map to MSI interrupts for various PCI devices.
* Move the NMI handling code out to its own file.jhb2003-11-031-586/+2
|
* Include "opt_pmap.h" so that the DISABLE_P* options are honored.jhb2003-10-301-0/+2
|
* Always export r_gdt and r_idt and give them extern declarations injhb2003-10-303-9/+0
| | | | machine/segments.h.
* MFi386: thread specific fpu state optimizationspeter2003-10-301-1/+3
|
* MFi386: rev 1.451 (jhb): call pmap_kremove() rather than duplicate itpeter2003-10-301-5/+2
|
* MFi386: trap.c rev 1.259: fetch thread mailbox address in page fault trappeter2003-10-301-0/+2
|
* Oops. Remove some rather noisy debug printfs that slipped in therepeter2003-10-281-9/+0
| | | | somehow.
* A few whitespace and comment tweaks.jhb2003-10-243-18/+9
|
* Add __va_copy and make it always visible, in spite of the __ISO_C_VISIBLEpeter2003-10-241-1/+4
| | | | | | | | | setting. Make va_copy be an alias if __ISO_C_VISIBLE >= 1999. Why? more than a few ports have an autoconf that looks for __va_copy because it is available on glibc. It is critical that we use it if at all possible on amd64. It generally isn't a problem for i386 and its ilk because autoconf driven code tends to fall back to an assignment.
* Use a more robust API altogether for the amd64_get_fsbase() etc functions.peter2003-10-231-4/+4
|
* Renumber the sysarch vectors for amd64 specific syscalls so that I canpeter2003-10-231-6/+5
| | | | | | | implement i386 compat numbers where it makes sense. This would save a syscall translation layer. Yes, this breaks the abi slightly again, but fortunately its just a recompile rather than tweaking the source. I will be fixing the libc stubs while I'm here.
* Change all SYSCTLS which are readonly and have a related TUNABLEsilby2003-10-212-2/+2
| | | | | from CTLFLAG_RD to CTLFLAG_RDTUN so that sysctl(8) can provide more useful error messages.
* Add the cpu_idle_hook() function pointer so that other idlers can benjl2003-10-181-9/+17
| | | | | hooked at runtime. Make C1 sleep (e.g., HLT) be the default. This prepares the way for further ACPI sleep states.
* Don't forget to load %es with the kernel data segment selector inbde2003-10-161-0/+3
| | | | | | | | | | | Xcpustop(). %es is used in at least the call to savectx() when savectx() calls bcopy(), so not loading it was fatal if a stop IPI interrupts user mode. This reduces bugs starting and stopping CPUs for debuggers. CPUs are stopped mainly in kdb_trap() and cpu_reset(). At reset time there is a good chance that all the CPUs are in the kernel, so the bug was probably harmless then.
* Pull the tier-2 card one last time and break the get/setcontext andpeter2003-10-155-5/+17
| | | | | | | | | | | | | | | | | | | | | | sigreturn() ABI and the signal context on the stack. Make the trapframe (and its shadows in the ucontext and sigframe etc) 8 bytes larger in order to preserve 16 byte stack alignment for the following C code calls. I could have done some padding after the trapframe was saved, but some of the C code still expects an argument of 'struct trapframe'. Anyway, this gives me a spare field that can be used to store things like 'partial trapframe' status or something else in the future. The runtime impact is fairly small, *except* for threaded apps and things that decode contexts and the signal stack (eg: cvsup binary). Signal delivery isn't too badly affected because the kernel generates the sigframe that sigreturn uses after the handler has been called. The size of mcontext_t and struct sigframe hasn't changed. Only the last few fields (sc_eip etc) got moved a little and I eliminated a spare field. mc_len/sc_len did change location though so the sanity checks there will still trap it.
* MFia64alc2003-10-142-47/+82
| | | | Move uma_small_alloc() and uma_small_free() to uma_machdep.c.
* Implement preliminary support for the PT_SYSCALL command to ptrace(2).robert2003-10-091-0/+5
|
* Move pmap_resident_count() from the MD pmap.h to the MI pmap.h.bms2003-10-061-1/+0
| | | | | | | | Add a definition of pmap_wired_count(). Add a definition of vmspace_wired_count(). Reviewed by: truckman Discussed with: peter
* Don't bother setting a page table page's valid field. It is unused andalc2003-10-051-2/+0
| | | | not setting it is consistent with other uses of VM_ALLOC_NOOBJ pages.
* Migrate pmap_prefault() into the machine-independent virtual memory layer.alc2003-10-031-100/+21
| | | | | | | A small helper function pmap_is_prefaultable() is added. This function encapsulate the few lines of pmap_prefault() that actually vary from machine to machine. Note: pmap_is_prefaultable() and pmap_mincore() have much in common. Going forward, it's worth considering their merger.
* Reimplement pagezero() using "movnti".alc2003-10-021-39/+11
|
* Commit Bosko's patch to clean up the PSE/PG_G initialization to andpeter2003-10-015-36/+34
| | | | | | | | | | | | | | | | | | | | | avoid problems with some Pentium 4 cpus and some older PPro/Pentium2 cpus. There are several problems, some documented in Intel errata. This patch: 1) moves the kernel to the second page in the PSE case. There is an errata that says that you Must Not point a 4MB page at physical address zero on older cpus. We avoided bugs here due to sheer luck. 2) sets up PSE page tables right from the start in locore, rather than trying to switch from 4K to 4M (or 2M) pages part way through the boot sequence at the same time that we're messing with PG_G. For some reason, the pmap work over the last 18 months seems to tickle the problems, and the PAE infrastructure changes disturb the cpu bugs even more. A couple of people have reported a problem with APM bios calls during boot. I'll work with people to get this resolved. Obtained from: bmilekic
* Use __register_t instead of register_t, otherwise <sys/types.h> is apeter2003-10-011-24/+24
| | | | prerequisite for <ucontext.h> on amd64. Oops.
* MFi386: Do not depend on LEAPYEAR() macro boolean values being 0 or 1.peter2003-09-301-2/+3
| | | | MFi386: Add quality field for timer0
* MFi386: BURN_BRIDGES around timer0 functionspeter2003-09-302-3/+17
|
* - Remove the definition for TD_SWITCHIN as it is not used.jeff2003-09-301-1/+0
| | | | Approved by: peter
* Eliminate the pte object.alc2003-09-272-27/+49
|
* MFi386alc2003-09-261-4/+4
| | | | Allocate the page table directory page as "no object" pages.
* MFi386alc2003-09-251-14/+7
| | | | | | Reimplement pmap_release() such that it uses the page table rather than the pte object to locate the page table directory pages. (Temporarily, retain an assertion on the emptiness of the pte object.)
* Re-raise the default datasize and stacksize now that the 32 bit execpeter2003-09-251-2/+2
| | | | support can clip it to sensible values.
* Add sysentvec->sv_fixlimits() hook so that we can catch cases on 64 bitpeter2003-09-252-13/+2
| | | | | | | | | | | | | | | | | | | | | systems where the data/stack/etc limits are too big for a 32 bit process. Move the 5 or so identical instances of ELF_RTLD_ADDR() into imgact_elf.c. Supply an ia32_fixlimits function. Export the clip/default values to sysctl under the compat.ia32 heirarchy. Have mmap(0, ...) respect the current p->p_limits[RLIMIT_DATA].rlim_max value rather than the sysctl tweakable variable. This allows mmap to place mappings at sensible locations when limits have been reduced. Have the imgact_elf.c ld-elf.so.1 placement algorithm use the same method as mmap(0, ...) now does. Note that we cannot remove all references to the sysctl tweakable maxdsiz etc variables because /etc/login.conf specifies a datasize of 'unlimited'. And that causes exec etc to fail since it can no longer find space to mmap things.
* Implement the bus_space_map() function to allocate resources and initializenyan2003-09-231-4/+12
| | | | a bus_handle, but currently it does only initializing a bus_handle.
* Oops. back out last commit. The data and stack limits are used by thepeter2003-09-231-2/+2
| | | | | | | | 32 bit binary stuff. 32 bit binaries do not like it much when the kernel tries hard to put things above the 8GB mark. I have a work-in-progress to fix this properly, but I didn't want to burn anybody with this yet.
* Fix patch transcription typo. s/IDT_BPT/IDT_BP/peter2003-09-231-1/+1
|
OpenPOWER on IntegriCloud