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* Remove redundant, bogus, and even harmful uses of setting TS bit in CR0.jkim2011-01-142-2/+1
* Fix up a few more sysctl(9) mis-typing found in various LINT builds.mdf2011-01-131-9/+9
* If an interrupt on an I/O APIC is moved to a different CPU after it hasjhb2011-01-131-6/+4
* sysctl(9) cleanup checkpoint: amd64 GENERIC builds cleanly.mdf2011-01-121-1/+1
* Move repeated MAXSLP definition from machine/vmparam.h to sys/vmmeter.h.kib2011-01-091-11/+0
* Copy powerpc/include/_inttypes.h to x86 and replace i386/amd64/pc98tijl2011-01-081-210/+3
* Create shared (readonly) page. Each ABI may specify the use of page bykib2011-01-084-6/+10
* On mixed 32/64 bit architectures (mips, powerpc) use __LP64__ rather thantijl2011-01-081-2/+2
* Fix types of some values in machine/_limits.h.tijl2011-01-081-12/+7
* Add AT_STACKPROT elf aux vector. Will be used to inform rtld about thekib2011-01-071-1/+2
* Increase size of pcb_flags to four bytes.jkim2010-12-223-16/+16
* Improve PCB flags handling and make it more robust. Add two new functionsjkim2010-12-2212-100/+152
* Merge amd64 and i386 bus.h and move the resulting header to x86. Replacetijl2010-12-201-1081/+3
* Inform a compiler which asm statements in the x86 implementation ofkib2010-12-181-9/+10
* Stop lying about supporting cpu_est_clockrate() when TSC is invariant. Thisjkim2010-12-142-3/+18
* Add options NO_ADAPTIVE_SX to the XENHVM kernel configuration, matchingrwatson2010-12-131-0/+1
* In fpudna()/npxdna(), mark FPU context initialized and optionallykib2010-12-121-1/+3
* Derive the XENHVM kernel from GENERIC, adding only the options requiredrwatson2010-12-101-138/+9
* Replace i386/i386/busdma_machdep.c and amd64/amd64/busdma_machdep.ccperciva2010-12-091-1222/+0
* Do not subtract 0.5% from estimated frequency if DELAY(9) is driven by TSC.jkim2010-12-081-7/+1
* On amd64, we have (since r1.72, in December 2005) MAX_BPAGES=8192,cperciva2010-12-081-0/+4
* MFi386 r1.94: If XEN, make pmap_kextract = pmap_kextract_ma. This is acperciva2010-12-081-0/+5
* MFi386 r1.81, r1.82, r1.84: Reorganize code to reduce cache pressure andcperciva2010-12-081-72/+80
* Merge sys/amd64/amd64/tsc.c and sys/i386/i386/tsc.c and move to sys/x86/x86.jkim2010-12-082-253/+1
* Remove stale comments about P-state invariant TSC and fix style(9) nits.jkim2010-12-072-8/+4
* Do not register a event handler for CPU freqency changes when it is foundjkim2010-12-071-4/+16
* Now the P-state invariant TSC is probed early enough, do not register eventjkim2010-12-071-10/+8
* Probe P-state invariant TSC from rightful place.jkim2010-12-072-22/+23
* Update some comments related to use of amd64 full context switch.kib2010-12-073-5/+5
* Retire write-only PCB_FULLCTX pcb flag on amd64.kib2010-12-077-10/+2
* Do not leak %rdx value in the previous image to the new image afterkib2010-12-061-0/+1
* Revert r216161. It is not necessary because we zero-fill BSS anyway.jkim2010-12-031-1/+1
* Explicitly initialize TSC frequency. To calibrate TSC frequency, we usejkim2010-12-031-1/+1
* Do not change CPU ticker frequency if TSC is P-state invariant. Note thisjkim2010-12-031-0/+3
* Revert r216134. This checkin broke platforms where bus_space are macros:brucec2010-12-031-18/+12
* Disallow passing in a count of zero bytes to the bus_space(9) functions.brucec2010-12-021-12/+18
* Calling fill_fpregs() for curthread is legitimate, and ELF coredumpkib2010-11-281-1/+2
* Make the size of the direct map easily configurable. Changing NDMPML4Ealc2010-11-263-11/+29
* Remove npxgetregs(), npxsetregs(), fpugetregs() and fpusetregs()kib2010-11-265-64/+41
* Merge amd64/i386 _align.h by aligning on the size of register_t (copiedtijl2010-11-261-50/+3
* Remove kernel support for BB profiling, now that kernbb(8) is gone, too.uqs2010-11-261-19/+0
* Apply the same fix as in r215823 to sys/amd64/amd64/fpu.c: usedim2010-11-251-1/+1
* Change ambiguous (or invalid, depending on how strict you want to be :)dim2010-11-241-1/+1
* Remove a stale tunable introduced in r215703.jkim2010-11-231-2/+1
* Reinitialize PAT MSR via pmap_init_pat() while resuming. This function doesjkim2010-11-234-9/+2
* specialreg.h: add definitions for some useful bits found in CPUID.6 EAX and ECXavg2010-11-231-0/+9
* - Disable caches and flush caches/TLBs when we update PAT as we do for MTRR.jkim2010-11-221-74/+62
* specialreg.h: add definitions for MPERF/APERF pair of MSRsavg2010-11-191-0/+2
* specialreg.h: add AMD-specific "Hardware Configuration Register" MSRavg2010-11-191-0/+1
* specialreg.h: add definition for AMD Core Performance Boost bitavg2010-11-191-0/+1
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