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* Since version 4.3, gcc changed its behaviour concerning the i386/amd64kib2008-03-133-5/+5
| | | | | | | | | | | | | | | | | | ABI and the direction flag, that is it now assumes that the direction flag is cleared at the entry of a function and it doesn't clear once more if needed. This new behaviour conforms to the i386/amd64 ABI. Modify the signal handler frame setup code to clear the DF {e,r}flags bit on the amd64/i386 for the signal handlers. jhb@ noted that it might break old apps if they assumed DF == 1 would be preserved in the signal handlers, but that such apps should be rare and that older versions of gcc would not generate such apps. Submitted by: Aurelien Jarno <aurelien aurel32 net> PR: 121422 Reviewed by: jhb MFC after: 2 weeks
* The variable MTRR registers actually have variable-sized PhysBase andjhb2008-03-122-8/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | PhysMask fields based on the number of physical address bits supported by the current CPU. The old code assumed 36 bits on i386 and 40 bits on amd64. In truth, all Intel CPUs up until recently used 36 bits (a newer Intel CPU uses 38 bits) and all the Opteron CPUs used 40 bits. In at least one case (the new Intel CPU) having the size of the mask field wrong resulted in writing questionable values into the MTRR registers on the application processors (BSP as well if you modify the MTRRs via memcontrol or running X, etc.). The result of the questionable physmask was that all of memory was apparently treated as uncached rather than write-back resulting in a very significant performance hit. Fix this by constructing a run-time mask for the PhysBase and PhysMask fields based on the number of physical address bits supported by the CPU. All 64-bit capable CPUs provide a count of PA bits supported via the 0x80000008 extended CPUID feature, so use that if it is available. If that feature is not available, then assume 36 PA bits. While I'm here, expand the (now-unused) macros for the PhysBase and PhysMask fields to the current largest possible value (52 PA bits). MFC after: 1 week PR: i386/120516 Reported by: Nokia
* Minimize diffs with i686_mem.c:jhb2008-03-122-6/+9
| | | | | - A few whitespace changes I missed in the style(9) changes. - Move M_MEMDESC to mem.c.
* Remove kernel support for M:N threading.jeff2008-03-125-25/+2
| | | | | | | | While the KSE project was quite successful in bringing threading to FreeBSD, the M:N approach taken by the kse library was never developed to its full potential. Backwards compatibility will be provided via libmap.conf for dynamically linked binaries and static binaries will be broken.
* Style(9) these files. No changes in the compiled code. (Verified byjhb2008-03-111-405/+443
| | | | diff'ing objdump -d output).
* Add constants for the various fields in MTRR registers.jhb2008-03-112-11/+27
| | | | | MFC after: 1 week Verified by: md5(1)
* Probe CPUs after the PCI hierarchy on i386, amd64, and ia64. This allowsjhb2008-03-101-12/+23
| | | | | | | | | | | | | | | | | the cpufreq drivers to reliably use properties of PCI devices for quirks, etc. - For the legacy drivers, add CPU devices via an identify routine in the CPU driver itself rather than in the legacy driver's attach routine. - Add CPU devices after Host-PCI bridges in the acpi bus driver. - Change the ichss(4) driver to use pci_find_bsf() to locate the ICH and check its device ID rather than having a bogus PCI attachment that only checked for the ID in probe and always failed. As a side effect, you can now kldload ichss after boot. - Fix the ichss(4) driver to use the correct device_t for the ICH (and not for ichss0) when doing PCI config space operations to enable SpeedStep. MFC after: 2 weeks Reviewed by: njl, Andriy Gapon avg of icyb.net.ua
* - Rather than repeating the same preemption code everywhere call the schedulerjeff2008-03-101-9/+2
| | | | specific sched_preempt() routine.
* Import uslcom(4) from OpenBSD - this is a driver for Silicon Laboratoriesrink2008-03-051-0/+1
| | | | | | | | CP2101/CP2102 based USB serial adapters. Reviewed by: imp, emaste Obtained from: OpenBSD MFC after: 2 weeks
* Add support for automatic promotion of 4KB page mappings to 2MB pagealc2008-03-042-105/+1081
| | | | | | | | | mappings. Automatic promotion can be enabled by setting the tunable "vm.pmap.pg_ps_enabled" to a non-zero value. By default, automatic promotion is disabled. (Expect this to change.) Reviewed by: ups Tested by: kris, Peter Holm
* - Remove the old smp cpu topology specification with a new, more flexiblejeff2008-03-023-43/+41
| | | | | | | | | | | | | | | | | tree structure that encodes the level of cache sharing and other properties. - Provide several convenience functions for creating one and two level cpu trees as well as a default flat topology. The system now always has some topology. - On i386 and amd64 create a seperate level in the hierarchy for HTT and multi-core cpus. This will allow the scheduler to intelligently load balance non-uniform cores. Presently we don't detect what level of the cache hierarchy is shared at each level in the topology. - Add a mechanism for testing common topologies that have more information than the MD code is able to provide via the kern.smp.topology tunable. This should be considered a debugging tool only and not a stable api. Sponsored by: Nokia
* Eliminate whitespace diffs to the i386 version.ru2008-02-191-2/+1
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* Teach the dump and minidump code to respect the maxioszie attribute ofscottl2008-02-152-4/+12
| | | | the disk; the hard-coded assumption of 64K doesn't work in all cases.
* If busdma is being used to realign dynamic buffers and the alignment is set toscottl2008-02-121-2/+2
| | | | | | | | PAGE_SIZE or less, the bounce page counting logic was flawed and wouldn't reserve any pages. Adjust to be correct. Review of other architectures is forthcoming. Submitted by: Joseph Golio
* Fix Linux mmap with MAP_GROWSDOWN flag.jkim2008-02-111-13/+14
| | | | | | | Reported by: Andriy Gapon (avg at icyb dot net dot ua) Tested by: Andriy Gapon (avg at icyb dot net dot ua) Pointyhat: me MFC after: 3 days
* Remove the rr232x driver. It has been superceded by the hptrr driver.scottl2008-02-032-6/+0
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* Add a few more CPUID feature bits while here. We don't support thesedas2008-02-022-2/+4
| | | | features yet.
* SSE4 CPUID bitsdas2008-02-022-3/+6
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* For no good reason I had assumed that ACPI table headers would be pagejhb2008-01-311-5/+7
| | | | | | | | | | | | | | | | | | | | aligned (or at least not cross a page boundary). However, it turns out that on at least one machine one table header does cross a page boundary. This caused problems with the MADT early probe as it uses the crash dump map to load ACPI tables by loading the RSDT/XSDT into pages 1 ... N and loading the header of each ACPI table header into page 0 looking for the MADT. However, if a table header crossed a page boundary, then page 1 would get trashed resulting in a panic. Fix this by reserving the first 2 pages for ACPI table headers (headers are less than a page in size, so 2 pages will be sufficient) and use pages 2 .. N for the RSDT and XSDT. Note: amd64 should probably be simplified to just use pmap_mapbios() for all these tables which will use the direct map and not need the crash dump hack. MFC after: 5 days Tested on: i386 Reported by: Pete French petefrench of ticketswitch.com
* Move GET_STACK_USAGE from MI header to i386/amd64 MD ones.mav2008-01-311-0/+13
| | | | | Somebody who can, please feel free to implement it for other archs or copy this one if it suits.
* Add a wrapper function that bound checks writes to the dump device.ru2008-01-282-11/+11
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* Use cpu_spinwait() (i.e., "pause") when spinning on rdtsc during DELAY().jhb2008-01-171-0/+1
| | | | MFC after: 1 week
* Retire PMAP_DIAGNOSTIC. Any useful diagnostics that were conditionallyalc2008-01-171-27/+10
| | | | | | | | | | | | | compiled under PMAP_DIAGNOSTIC are now KASSERT()s. (Note: The kernel option DIAGNOSTIC still disables inlining of certain pmap functions.) Eliminate dead code from pmap_enter(). This code implemented an assertion. On i386, an equivalent check is already implemented. However, on amd64, a small change is required to implement an equivalent check. Eliminate \n from a nearby panic string. Use KASSERT() to reimplement pmap_copy()'s two assertions.
* Translate from the i386. All FP constants and operations are evaluatedbde2008-01-172-2/+2
| | | | | | | | | | in the range and precision of their type(s) on amd64, but FLT_EVAL_METHOD said that they were evalated in the "interesting" (buggy) i387 methods. float_t was broken compatibly with FLT_EVAL_METHOD. These definitions seem to be broken on powerpc and possibly on arm. float_t is float on powerpc with gcc [-notraditional] according to glibc, and FLT_EVAL_METHOD is marked with XXX on arm.
* Make pmap_is_prefaultable() more TLB friendly. Specifically, make it usealc2008-01-141-1/+1
| | | | | | | | | the kernel's direct map instead of the pmap's recursive mapping to access the lowest level in the page table. The direct map is preferable for two reasons: (1) The TLB is more likely to hold the required direct mapping because pmap_enter() has already used the direct map to access a nearby PTE and (2) loading a direct mapping into the TLB involves walking only 2 or 3 levels of the page table instead of 4.
* Fix fpset*() to not trap if there is a currently unmasked exception.bde2008-01-111-12/+42
| | | | | | | | | | | | | | | | | | | Unmasked exceptions (which can be fixed up using fpset*() before they trap) are very rare, especially on amd64 since SSE exceptions trap synchronously, but I want to merge the faster amd64 implementations of fpset*() back to i386 without introducing the bug on i386. The i386 implementation has always avoided the trap automatically by changing things using load/store of the FP environment, but this is very slow. Most changes only affect the control word, so they can usually be done much more efficiently, and amd64 has always done this, but loading the control word can trap. This version use the fast method only in the usual case where it will not trap. This only costs a couple of integer instructions (including one branch which I haven't optimized carefully yet) in the usual case, but bloats the inlines a lot. The inlines were already a bit too large to handle both the FPU and SSE.
* Fix some style bugs:bde2008-01-111-24/+25
| | | | | | | | | | | - fix a previous style fix: shifts should be in the correct direction even if they are null. - restore a comment about namespace pollution from floatingpoint.h 1.12 and update it. - remove unused namespace pollution FP_*REG. - improve some comments. - sort macro definitions for entry points. - don't use underscores for macro args.
* Simplify the ifdefs:bde2008-01-091-21/+14
| | | | | | | | | | | | | | | | | - fix this to compile with C++ by casting ints to enums in a few places and by using the correct parameter type for _fpsetprec(). Remove __cplusplus ifdefs which disabled the buggy code. - remove __CC_SUPPORTS___INLINE ifdefs. `__inline' vs `inline', and either of these #defined away, are supposed to be handled by very old ifdefs in <sys/cdefs.h>. Thus the __CC_SUPPORTS___INLINE macro is not needed here (or anywhere else that it used). It is less needed here than in most places, since this file is userland-only and userland is far from supporting INTEL_COMPILER. The __CC_SUPPORTS___INLINE__ macro which was used here is even less needed. It is to support spelling `inline' as `__inline__' instead of the usual spelling `__inline'. Fix some style bugs that I missed in the previous commit (remove unused asms and sort more variables).
* Fix some style bugs (mainly, use explicit shifts when accessing bit-fieldsbde2008-01-091-31/+31
| | | | | even if the shift count happens to be 0, sort declarations, and spell __inline normally).
* Improve some comments.bde2008-01-091-14/+13
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* Convert a PMAP_DIAGNOSTIC to a KASSERT.alc2008-01-081-9/+2
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* Add COMPAT_FREEBSD7 and enable it in configs that have COMPAT_FREEBSD6.jhb2008-01-071-0/+1
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* Shrink the size of struct vm_page on amd64 and i386 by eliminatingalc2008-01-062-8/+0
| | | | | | pv_list_count from struct md_page. Ever since Peter rewrote the pv entry allocator for amd64 and i386 pv_list_count has been correctly maintained but otherwise unused.
* Add an access type parameter to pmap_enter(). It will be used to implementalc2008-01-031-2/+2
| | | | | | | superpage promotion. Correct a style error in kmem_malloc(): pmap_enter()'s last parameter is a Boolean.
* Provide a legitimate pindex to vm_page_alloc() in pmap_growkernel()alc2008-01-021-6/+3
| | | | | | | | instead of writing apologetic comments. As it turns out, I need every kernel page table page to have a legitimate pindex to support superpage promotion on kernel memory. Correct a nearby style error: Pointers should be compared to NULL.
* Add asmc(4).rpaulo2007-12-281-1/+2
| | | | Requested by: njl (mentor)
* Add configuration knobs for the superpage reservation system. Initially,alc2007-12-271-0/+14
| | | | the reservation will only be enabled on amd64.
* Add a new 'why' argument to kdb_enter(), and a set of constants to userwatson2007-12-252-2/+3
| | | | | | | | | for that argument. This will allow DDB to detect the broad category of reason why the debugger has been entered, which it can use for the purposes of deciding which DDB script to run. Assign approximate why values to all current consumers of the kdb_enter() interface.
* Add the 'hptrr' driver for supporting the following Highpoint RocketRAIDscottl2007-12-152-2/+7
| | | | | | | | | | | | | | | | | | | cards: o RocketRAID 172x series o RocketRAID 174x series o RocketRAID 2210 o RocketRAID 222x series o RocketRAID 2240 o RocketRAID 230x series o RocketRAID 231x series o RocketRAID 232x series o RocketRAID 2340 o RocketRAID 2522 Many thanks to Highpoint for their continued support of FreeBSD. Submitted by: Highpoint
* Disallow the legacy USB circuit to generate an SMI# via an ICHrpaulo2007-12-121-0/+25
| | | | | | | | | | | register (MacBooks only). This allows MacBooks to boot in SMP mode without any trick and solves the timer problems with HZ=1000. MFC after: 1 week Reviewed by: njl (mentor), jhb Approved by: njl (mentor), jhb
* Eliminate compilation warnings due to the use of non-static inlinesalc2007-12-091-3/+3
| | | | | | | through the introduction and use of the __gnu89_inline attribute. Submitted by: bde (i386) MFC after: 3 days
* Use 1GB virtual pages to implement the direct map on architectures thatalc2007-12-081-13/+24
| | | | | | | | support this feature. Wrap a nearby line that is too long. MFC after: 6 weeks
* Recognize architectural support for 1GB virtual pages.alc2007-12-082-1/+2
| | | | MFC after: 6 weeks
* Kernel and hwpmc(4) support for callchain capture.jkoshy2007-12-073-3/+99
| | | | Sponsored by: FreeBSD Foundation and Google Inc.
* Fix the ABI change of the signal delivered on the access to the pagekib2007-12-041-2/+29
| | | | | | | | | | | | | | | | | | | | | with insufficient protection mode. For the i386 and amd64, create the tunable, machdep.prot_fault_translation, with the following behaviour: 0 = autodetect the signal to be delivered on KERN_PROTECTION_FAILURE from vm_fault based on the ELF OSABI note: no note or __FreeBSD_version < 700004 - SIGBUS/BUS_PAGE_FAULT note, and __FreeBSD_version >= 700004 - SIGSEGV/SEGV_ACCERR 1 = always SIGBUS/BUS_PAGE_FAULT 2 = always SIGSEGV/SEGV_ACCERR This would do mostly automatic correction of ABI breakage, with the exception of the untaged binaries for 7-CURRENT/RELENG_7 before the note is fixed. For them, sysctl would allow to run the binary with manual settings. Discussed with: portmgr (kris) PR: kern/118304 MFC after: 3 days
* Style change: Use NULL rather than 0 where appropriate.alc2007-12-041-3/+3
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* Break out stack(9) from ddb(4):rwatson2007-12-024-38/+133
| | | | | | | | | | | | | | | | | | | | - Introduce per-architecture stack_machdep.c to hold stack_save(9). - Introduce per-architecture machine/stack.h to capture any common definitions required between db_trace.c and stack_machdep.c. - Add new kernel option "options STACK"; we will build in stack(9) if it is defined, or also if "options DDB" is defined to provide compatibility with existing users of stack(9). Add new stack_save_td(9) function, which allows the capture of a stacktrace of another thread rather than the current thread, which the existing stack_save(9) was limited to. It requires that the thread be neither swapped out nor running, which is the responsibility of the consumer to enforce. Update stack(9) man page. Build tested: amd64, arm, i386, ia64, powerpc, sparc64, sun4v Runtime tested: amd64 (rwatson), arm (cognet), i386 (rwatson)
* Remove XRPU driver, after asking all the users.phk2007-12-011-2/+0
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* Improve get_pv_entry()'s handling of low-memory conditions. After pagealc2007-11-301-12/+14
| | | | | | | | | | | | | allocation fails and pv entries are reclaimed, there may be an unused pv entry in a pv chunk that survived the reclamation. However, previously, after reclamation, get_pv_entry() did not look for an unused pv entry in a surviving pv chunk; it simply retried the page allocation. Now, it does look for an unused pv entry before retrying the page allocation. Note: This only applies to RELENG_7. Earlier branches use a different pv entry allocator. MFC after: 6 weeks
* Don't use plain "ret" instructions at targets of jump instructions,bde2007-11-291-2/+2
| | | | | | | | | | | | | | | | | | | | | since the branch caches on at least Athlon XP through Athlon 64 CPU's don't understand such instructions and guarantee a cache miss taking at least 10 cycles. Use the documented workaround "ret $0" instead ("nop; ret" also works, but "ret $0" is probably faster on old CPUs). Normal code (even asm code) doesn't branch to "ret", since there is usually some cleanup to do, but the __mcount, .mcount and .mexitcount entry points were optimized too well to have the minimum number of instructions (3 instructions each if profiling is not enabled) and they did this. I didn't see a significant number of cache misses for .mexitcount, but for the shared "ret" for __mcount and .mcount I observed cache misses costing 26 cycles each. For a send(2) syscall that makes about 70 function calls, the cost of these cache misses alone increased the syscall time from about 4000 cycles to about 7000 cycles. 4000 is for a profiling (GUPROF) kernel with profiling disabled; after this fix, configuring profiling only costs about 600 cycles in the 4000, which is consistent with almost perfect branch prediction in the mcounting calls.
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