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| * MSR_KGSBASE is no longer saved and restored from the guest MSR save area. Thisneel2014-09-201-7/+0
| * Restructure the MSR handling so it is entirely handled by processor-specificneel2014-09-209-371/+201
* | Simplify register state save and restore across a VMRUN:neel2014-09-274-145/+85
* | Allow more VMCB fields to be cached:neel2014-09-215-223/+245
* | Get rid of unused stat VMM_HLT_IGNORED.neel2014-09-212-2/+0
* | IFC r271888.neel2014-09-2012-404/+433
* | IFC @r271694neel2014-09-176-93/+337
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| * Optimize the common case of injecting an interrupt into a vcpu after a HLTneel2014-09-122-1/+63
| * The "SUB" instruction used in getcc() actually does 'x -= y' so use theneel2014-08-301-42/+66
| * Implement the 0x2B SUB instruction, and the OR variant of 0x81.grehan2014-08-271-13/+91
| * Add "hw.vmm.topology.threads_per_core" and "hw.vmm.topology.cores_per_package"neel2014-08-241-24/+77
| * Fix a bug in the emulation of CPUID leaf 0x4 where bhyve was claiming thatneel2014-08-231-2/+2
| * Return the spurious interrupt vector (IRQ7 or IRQ15) if the atpic cannotneel2014-08-231-2/+8
| * Reword comment to match the interrupt mode names from the MPtable spec.neel2014-08-141-7/+10
* | Rework vNMI injection.neel2014-09-171-7/+73
* | Minor cleanup.neel2014-09-162-15/+1
* | Use V_IRQ, V_INTR_VECTOR and V_TPR to offload APIC interrupt delivery to theneel2014-09-162-46/+155
* | Set the 'vmexit->inst_length' field properly depending on the type of theneel2014-09-141-127/+158
* | Bug fixes.neel2014-09-132-1/+6
* | style(9): insert an empty line if the function has no local variablesneel2014-09-131-0/+2
* | AMD processors that have the SVM decode assist capability will store theneel2014-09-135-20/+68
* | style(9): indent the switch, don't indent the case, indent case body one tab.neel2014-09-111-152/+132
* | Repurpose the V_IRQ interrupt injection to implement VMX-style interruptneel2014-09-111-71/+177
* | Allow intercepts and irq fields to be cached by the VMCB.neel2014-09-102-117/+133
* | Move the VMCB initialization into svm.c in preparation for changes to theneel2014-09-103-84/+79
* | Move the event injection function into svm.c and add KTR logging forneel2014-09-103-41/+66
* | Remove a bogus check that flagged an error if the guest %rip was zero.neel2014-09-101-5/+0
* | Make the KTR tracepoints uniform and ensure that every VM-exit is logged.neel2014-09-103-50/+61
* | Allow guest read access to MSR_EFER without hypervisor intervention.neel2014-09-101-19/+24
* | Remove gratuitous forward declarations.neel2014-09-091-16/+12
* | Do proper ASID management for guest vcpus.neel2014-09-064-84/+216
* | Merge svm_set_vmcb() and svm_init_vmcb() into a single function that is calledneel2014-09-053-71/+33
* | Remove unused header file.neel2014-09-041-49/+0
* | Consolidate the code to restore the host TSS after a #VMEXIT into a singleneel2014-09-041-29/+23
* | IFC @r269962neel2014-09-0217-571/+1878
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| * Use the max guest memory address when creating its iommu domain.neel2014-08-142-1/+21
| * Support PCI extended config space in bhyve.neel2014-08-081-0/+23
| * - Output a summary of optional VT-x features in dmesg similar to CPUjhb2014-07-303-30/+27
| * If a vcpu has issued a HLT instruction with interrupts disabled then it sleepsneel2014-07-262-2/+10
| * Don't return -1 from the push emulation handler. Negative return values areneel2014-07-261-4/+11
| * Fix a couple of issues in the PUSH emulation:neel2014-07-241-5/+15
| * Fix fault injection in bhyve.neel2014-07-241-57/+15
| * Emulate instructions emitted by OpenBSD/i386 version 5.5:neel2014-07-232-60/+415
| * Fix build without INVARIANTS defined by getting rid of unused variable 'exc'.neel2014-07-201-2/+1
| * Handle nested exceptions in bhyve.neel2014-07-193-66/+293
| * Add emulation for legacy x86 task switching mechanism.neel2014-07-163-5/+88
| * Add support for operand size and address size override prefixes in bhyve'sneel2014-07-153-116/+223
| * Use the correct offset when converting a logical address (segment:offset)neel2014-07-111-4/+5
| * Accurately identify the vcpu's operating mode as 64-bit, compatibility,neel2014-07-081-4/+12
| * Invalidate guest TLB mappings as a side-effect of its CR3 being updated.neel2014-07-081-27/+68
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