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* Handle writes to the SELF_IPI MSR by the guest when the vlapic is configuredneel2014-02-172-3/+33
* Use spinlocks to lock accesses to the vioapic.neel2014-02-171-3/+3
* Support level triggered interrupts with VT-x virtual interrupt delivery.neel2014-01-252-19/+26
* There is no need to initialize the IOMMU if no passthru devices have beenneel2014-01-213-4/+30
* Add an API to rendezvous all active vcpus in a virtual machine. The rendezvousneel2014-01-143-17/+147
* Don't expose 'vmm_ipinum' as a global.neel2014-01-092-4/+4
* Use the 'Virtual Interrupt Delivery' feature of Intel VT-x if supported byneel2014-01-072-38/+60
* Allow vlapic_set_intr_ready() to return a value that indicates whether or notneel2014-01-072-24/+47
* Fix a bug in the HPET emulation where a timer interrupt could be lost when theneel2014-01-031-67/+84
* Modify handling of writes to the vlapic LVT registers.neel2013-12-283-58/+131
* Modify handling of writes to the vlapic ICR_TIMER, DCR_TIMER, ICRLO and ESRneel2013-12-272-36/+42
* Modify handling of write to the vlapic SVR register.neel2013-12-273-15/+28
* Modify handling of writes to the vlapic ID, LDR and DFR registers.neel2013-12-262-51/+81
* vlapic code restructuring to make it easy to support hardware-assist for APICneel2013-12-253-141/+209
* Extend the support for local interrupts on the local APIC:jhb2013-12-232-15/+155
* Consolidate the virtual apic initialization in a single function: vlapic_reset()neel2013-12-221-15/+6
* Add an API to deliver message signalled interrupts to vcpus. This allowsneel2013-12-166-95/+242
* Fix typo when initializing the vlapic version register ('<<' instead of '<').neel2013-12-111-1/+1
* Fix x2apic support in bhyve.neel2013-12-102-14/+24
* Use callout(9) to drive the vlapic timer instead of clocking it on each VM exit.neel2013-12-072-114/+226
* If a vcpu disables its local apic and then executes a 'HLT' then spin down theneel2013-12-072-2/+47
* Add support for level triggered interrupt pins on the vioapic. Prior to thisneel2013-11-276-89/+205
* Add HPET device emulation to bhyve.neel2013-11-253-3/+818
* Add an ioctl to assert and deassert an ioapic pin atomically. This will be usedneel2013-11-232-4/+31
* Move the ioapic device model from userspace into vmm.ko. This is needed forneel2013-11-122-0/+415
* Remove the 'vdev' abstraction that was meant to sit on top of device modelsneel2013-11-044-415/+8
* Rename the VMM_CTRx() family of macros to VCPU_CTRx() to highlight that theseneel2013-10-311-2/+2
* Merge projects/bhyve_npt_pmap into head.neel2013-10-052-12/+48
* Fix a limitation in bhyve that would limit the number of virtual machines toneel2013-09-112-0/+7
* Mask off the vector from the MSI-x data word.grehan2013-09-071-1/+1
* Fix a gcc warning uncovered after r251745.pluknet2013-06-181-0/+3
* Replace cpusetffs_obj with CPU_FFS, missed in r251703.pluknet2013-06-141-1/+1
* Support array-type of stats in bhyve.neel2013-05-101-2/+6
* Don't panic when a valid divisor of 1 has been requested.grehan2013-04-051-0/+2
* Add counter to keep track of the number of timer interrupts generated byneel2013-03-311-0/+4
* Implement guest vcpu pinning using 'pthread_setaffinity_np(3)'.neel2013-02-111-27/+2
* Fix a broken assumption in the passthru implementation that the MSI-X tableneel2013-02-011-1/+10
* Increase the number of passthru devices supported by bhyve.neel2013-02-011-1/+1
* Modify the default behavior of bhyve such that it no longer forces the use ofneel2012-12-161-3/+1
* Fix a bug in the MSI-X resource allocation for PCI passthrough devices.neel2012-11-221-37/+26
* Calculate the number of host ticks until the next guest timer interrupt.neel2012-10-202-53/+62
* Provide per-vcpu locks instead of relying on a single big lock.neel2012-10-121-0/+2
* Deliver the MSI to the correct guest virtual cpu.neel2012-10-111-4/+1
* Allocate memory pages for the guest from the host's free page queue.neel2012-10-082-2/+57
* Change vm_malloc() to map pages in the guest physical address space in 4KBneel2012-10-041-1/+0
* Add an option "-a" to present the local apic in the XAPIC mode instead of theneel2012-09-262-9/+16
* Add support for trapping MMIO writes to local apic registers and emulating them.neel2012-09-251-5/+34
* Add an explicit exit code 'SPINUP_AP' to tell the controlling process that anneel2012-09-251-5/+54
* Restructure the x2apic access code in preparation for supporting memory mappedneel2012-09-212-3/+34
* MSI-x interrupt support for PCI pass-thru devices.grehan2012-04-283-5/+180
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