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* vlapic code restructuring to make it easy to support hardware-assist for APICneel2013-12-252-6/+44
| | | | | | | | | | | | | | | | | | | | emulation. The vlapic initialization and cleanup is done via processor specific vmm_ops. This will allow the VT-x/SVM modules to layer any hardware-assist for APIC emulation or virtual interrupt delivery on top of the vlapic device model. Add a parameter to 'vcpu_notify_event()' to distinguish between vlapic interrupts versus other events (e.g. NMI). This provides an opportunity to use hardware-assists like Posted Interrupts (VT-x) or doorbell MSR (SVM) to deliver an interrupt to a guest without causing a VM-exit. Get rid of lapic_pending_intr() and lapic_intr_accepted() and use the vlapic_xxx() counterparts directly. Associate an 'Apic Page' with each vcpu and reference it from the 'vlapic'. The 'Apic Page' is intended to be referenced from the Intel VMCS as the 'virtual APIC page' or from the AMD VMCB as the 'vAPIC backing page'.
* Add a resume hook for bhyve that runs a function on all CPUs duringjhb2013-12-231-0/+9
| | | | | | | resume. For Intel CPUs, invoke vmxon for CPUs that were in VMX mode at the time of suspend. Reviewed by: neel
* Re-arrange bits in the amd64/pmap 'pm_flags' field.neel2013-12-201-0/+3
| | | | | | | | | | The least significant 8 bits of 'pm_flags' are now used for the IPI vector to use for nested page table TLB shootdown. Previously we used IPI_AST to interrupt the host cpu which is functionally correct but could lead to misleading interrupt counts for AST handler. The AST handler was also doing a lot more than what is required for the nested page table TLB shootdown (EOI and IRET).
* Use vmcs_read() and vmcs_write() in preference to vmread() and vmwrite()neel2013-12-184-149/+62
| | | | | respectively. The vmcs_xxx() functions provide inline error checking of all accesses to the VMCS.
* Fix x2apic support in bhyve.neel2013-12-101-4/+17
| | | | | | | | | | | | When the guest is bringing up the APs in the x2APIC mode a write to the ICR register will now trigger a return to userspace with an exitcode of VM_EXITCODE_SPINUP_AP. This gets SMP guests working again with x2APIC. Change the vlapic timer lock to be a spinlock because the vlapic can be accessed from within a critical section (vm run loop) when guest is using x2apic mode. Reviewed by: grehan@
* Use callout(9) to drive the vlapic timer instead of clocking it on each VM exit.neel2013-12-071-1/+0
| | | | | | | | This decouples the guest's 'hz' from the host's 'hz' setting. For e.g. it is now possible to have a guest run at 'hz=1000' while the host is at 'hz=100'. Discussed with: grehan@ Tested by: Tycho Nightingale (tycho.nightingale@pluribusnetworks.com)
* If a vcpu disables its local apic and then executes a 'HLT' then spin down theneel2013-12-071-1/+4
| | | | | | | | | | | | vcpu and destroy its thread context. Also modify the 'HLT' processing to ignore pending interrupts in the IRR if interrupts have been disabled by the guest. The interrupt cannot be injected into the guest in any case so resuming it is futile. With this change "halt" from a Linux guest works correctly. Reviewed by: grehan@ Tested by: Tycho Nightingale (tycho.nightingale@pluribusnetworks.com)
* The 'protection' field in the VM exit collateral for the PAGING exit is notneel2013-12-031-16/+0
| | | | used - get rid of it.
* Fix undefined behavior: (1 << 31) is not defined as 1 is an int and thiseadler2013-11-303-4/+4
| | | | | | | | | | | | | shifts into the sign bit. Instead use (1U << 31) which gets the expected result. This fix is not ideal as it assumes a 32 bit int, but does fix the issue for most cases. A similar change was made in OpenBSD. Discussed with: -arch, rdivacky Reviewed by: cperciva
* Rename the VMM_CTRx() family of macros to VCPU_CTRx() to highlight that theseneel2013-10-311-15/+15
| | | | | | | tracepoints are vcpu-specific. Add support for tracepoints that are global to the virtual machine - these tracepoints are called VM_CTRx().
* Remove unnecessary includes of <machine/pmap.h>neel2013-10-294-6/+0
| | | | Requested by: alc@
* Add a new capability, VM_CAP_ENABLE_INVPCID, that can be enabled to exposeneel2013-10-163-1/+24
| | | | | | | | | | | | | | 'invpcid' instruction to the guest. Currently bhyve will try to enable this capability unconditionally if it is available. Consolidate code in bhyve to set the capabilities so it is no longer duplicated in BSP and AP bringup. Add a sysctl 'vm.pmap.invpcid_works' to display whether the 'invpcid' instruction is available. Reviewed by: grehan MFC after: 3 days
* Merge projects/bhyve_npt_pmap into head.neel2013-10-058-341/+282
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make the amd64/pmap code aware of nested page table mappings used by bhyve guests. This allows bhyve to associate each guest with its own vmspace and deal with nested page faults in the context of that vmspace. This also enables features like accessed/dirty bit tracking, swapping to disk and transparent superpage promotions of guest memory. Guest vmspace: Each bhyve guest has a unique vmspace to represent the physical memory allocated to the guest. Each memory segment allocated by the guest is mapped into the guest's address space via the 'vmspace->vm_map' and is backed by an object of type OBJT_DEFAULT. pmap types: The amd64/pmap now understands two types of pmaps: PT_X86 and PT_EPT. The PT_X86 pmap type is used by the vmspace associated with the host kernel as well as user processes executing on the host. The PT_EPT pmap is used by the vmspace associated with a bhyve guest. Page Table Entries: The EPT page table entries as mostly similar in functionality to regular page table entries although there are some differences in terms of what bits are used to express that functionality. For e.g. the dirty bit is represented by bit 9 in the nested PTE as opposed to bit 6 in the regular x86 PTE. Therefore the bitmask representing the dirty bit is now computed at runtime based on the type of the pmap. Thus PG_M that was previously a macro now becomes a local variable that is initialized at runtime using 'pmap_modified_bit(pmap)'. An additional wrinkle associated with EPT mappings is that older Intel processors don't have hardware support for tracking accessed/dirty bits in the PTE. This means that the amd64/pmap code needs to emulate these bits to provide proper accounting to the VM subsystem. This is achieved by using the following mapping for EPT entries that need emulation of A/D bits: Bit Position Interpreted By PG_V 52 software (accessed bit emulation handler) PG_RW 53 software (dirty bit emulation handler) PG_A 0 hardware (aka EPT_PG_RD) PG_M 1 hardware (aka EPT_PG_WR) The idea to use the mapping listed above for A/D bit emulation came from Alan Cox (alc@). The final difference with respect to x86 PTEs is that some EPT implementations do not support superpage mappings. This is recorded in the 'pm_flags' field of the pmap. TLB invalidation: The amd64/pmap code has a number of ways to do invalidation of mappings that may be cached in the TLB: single page, multiple pages in a range or the entire TLB. All of these funnel into a single EPT invalidation routine called 'pmap_invalidate_ept()'. This routine bumps up the EPT generation number and sends an IPI to the host cpus that are executing the guest's vcpus. On a subsequent entry into the guest it will detect that the EPT has changed and invalidate the mappings from the TLB. Guest memory access: Since the guest memory is no longer wired we need to hold the host physical page that backs the guest physical page before we can access it. The helper functions 'vm_gpa_hold()/vm_gpa_release()' are available for this purpose. PCI passthru: Guest's with PCI passthru devices will wire the entire guest physical address space. The MMIO BAR associated with the passthru device is backed by a vm_object of type OBJT_SG. An IOMMU domain is created only for guest's that have one or more PCI passthru devices attached to them. Limitations: There isn't a way to map a guest physical page without execute permissions. This is because the amd64/pmap code interprets the guest physical mappings as user mappings since they are numerically below VM_MAXUSER_ADDRESS. Since PG_U shares the same bit position as EPT_PG_EXECUTE all guest mappings become automatically executable. Thanks to Alan Cox and Konstantin Belousov for their rigorous code reviews as well as their support and encouragement. Thanks for John Baldwin for reviewing the use of OBJT_SG as the backing object for pci passthru mmio regions. Special thanks to Peter Holm for testing the patch on short notice. Approved by: re Discussed with: grehan Reviewed by: alc, kib Tested by: pho
* Allocate VPIDs by using the unit number allocator to keep do the bookkeeping.neel2013-09-071-39/+103
| | | | | Also deal with VPID exhaustion by allocating out of a reserved range as the last resort.
* Do not create superpage mappings in the iommu.neel2013-08-201-1/+18
| | | | | | This is a workaround to hide the fact that we do not have any code to demote a superpage mapping before we unmap a single page that is part of the superpage.
* Extract the location of the remapping hardware units from the ACPI DMAR table.neel2013-08-201-60/+54
| | | | Submitted by: Gopakumar T (gopakumar_thekkedath@yahoo.co.in)
* Follow-up commit to fix CR0 issues. Maintaingrehan2013-08-031-4/+38
| | | | | | | | architectural state on CR vmexits by guaranteeing that EFER, CR0 and the VMCS entry controls are all in sync when transitioning to IA-32e mode. Submitted by: Tycho Nightingale (tycho.nightingale <at> plurisbusnetworks.com)
* Correctly maintain the CR0/CR4 shadow registers.grehan2013-08-011-11/+54
| | | | | | | | | | | | | | | This was exposed with AP spinup of Linux, and booting OpenBSD, where the CR0 register is unconditionally written to prior to the longjump to enter protected mode. The CR-vmexit handling was not updating CPU state which resulted in a vmentry failure with invalid guest state. A follow-on submit will fix the CPU state issue, but this fix prevents the CR-vmexit prior to entering protected mode by properly initializing and maintaining CR* state. Reviewed by: neel Reported by: Gopakumar.T @ netapp
* Ignore guest PAT settings by default in EPT mappings.grehan2013-07-011-2/+10
| | | | | | | From experimentation, other hypervisors also do this. Diagnosed by: tycho nightingale at pluribusnetworks com Reviewed by: neel
* Add RIP-relative addressing to the instruction decoder.grehan2013-04-253-42/+37
| | | | | | | | | | | | Rework the guest register fetch code to allow the RIP to be extracted from the VMCS while the kernel decoder is functioning. Hit by the OpenBSD local-apic code. Submitted by: neel Reviewed by: grehan Obtained from: NetApp
* Create sysctl node 'hw.vmm.vmx' and populate it with oids that expose the VMXneel2013-04-131-0/+19
| | | | | | hardware capabilities. Obtained from: NetApp
* Make the code to check if VMX is enabled more readable by using macrosneel2013-04-111-1/+2
| | | | | | instead of magic numbers. Discussed with: Chris Torek
* Add some more stats to keep track of all the reasons that a vcpu is exiting.neel2013-03-301-1/+16
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* Allow vmm stats to be specific to the underlying hardware assist technology.neel2013-03-161-4/+3
| | | | | | | | | This can be done by using the new macros VMM_STAT_INTEL() and VMM_STAT_AMD(). Statistic counters that are common across the two are defined using VMM_STAT(). Suggested by: Anish Gupta Discussed with: grehan Obtained from: NetApp
* Always allow access to the sysenter cs/esp/eip MSRs since theygrehan2013-01-251-0/+7
| | | | | | | are automatically saved and restored in the VMCS. Reviewed by: neel Obtained from: NetApp
* Add support for the 0x81 AND instruction, now generatedgrehan2012-11-291-4/+5
| | | | | | | | | | | by clang in the local APIC code. 0x81 is a read-modify-write instruction - the EPT check that only allowed read or write and not both has been relaxed to allow read and write. Reviewed by: neel Obtained from: NetApp
* Cleanup the user-space paging exit handler now that the unified instructionneel2012-11-281-2/+0
| | | | | | emulation is in place. Obtained from: NetApp
* Change emulate_rdmsr() and emulate_wrmsr() to return 0 on sucess and errno onneel2012-11-281-6/+8
| | | | | | | failure. The conversion from the return value to HANDLED or UNHANDLED can be done locally in vmx_exit_process(). Obtained from: NetApp
* Revamp the x86 instruction emulation in bhyve.neel2012-11-282-25/+21
| | | | | | | | | | | | | | | | | | | On a nested page table fault the hypervisor will: - fetch the instruction using the guest %rip and %cr3 - decode the instruction in 'struct vie' - emulate the instruction in host kernel context for local apic accesses - any other type of mmio access is punted up to user-space (e.g. ioapic) The decoded instruction is passed as collateral to the user-space process that is handling the PAGING exit. The emulation code is fleshed out to include more addressing modes (e.g. SIB) and more types of operands (e.g. imm8). The source code is unified into a single file (vmm_instruction_emul.c) that is compiled into vmm.ko as well as /usr/sbin/bhyve. Reviewed by: grehan Obtained from: NetApp
* Get rid of redundant comparision which is guaranteed to be "true" for unsignedneel2012-11-221-1/+1
| | | | | | integers. Obtained from: NetApp
* Fix issue found with clang build. Avoid code insertion by the compilergrehan2012-11-061-29/+48
| | | | | | | | | | | | | between inline asm statements that would in turn modify the flags value set by the first asm, and used by the second. Solve by making the common error block a string that can be pulled into the first inline asm, and using symbolic labels for asm variables. bhyve can now build/run fine when compiled with clang. Reviewed by: neel Obtained from: NetApp
* Convert VMCS_ENTRY_INTR_INFO field into a vmcs identifier before passing itneel2012-10-291-1/+1
| | | | | | | | | | | | | to vmcs_getreg(). Without this conversion vmcs_getreg() will return EINVAL. In particular this prevented injection of the breakpoint exception into the guest via the "-B" option to /usr/sbin/bhyve which is hugely useful when debugging guest hangs. This was broken in r241921. Pointy hat: me Obtained from: NetApp
* Corral all the host state associated with the virtual machine into its own file.neel2012-10-292-24/+17
| | | | | | | This state is independent of the type of hardware assist used so there is really no need for it to be in Intel-specific code. Obtained from: NetApp
* Unconditionally enable fpu emulation by setting CR0.TS in the host after theneel2012-10-261-1/+9
| | | | | | | | | | guest does a vm exit. This allows us to trap any fpu access in the host context while the fpu still has "dirty" state belonging to the guest. Reported by: "s vas" on freebsd-virtualization@ Obtained from: NetApp
* If the guest vcpu wants to idle then use that opportunity to relinquish theneel2012-10-251-3/+18
| | | | | | | | | | | | host cpu to the scheduler until the guest is ready to run again. This implies that the host cpu utilization will now closely mirror the actual load imposed by the guest vcpu. Also, the vcpu mutex now needs to be of type MTX_SPIN since we need to acquire it inside a critical section. Obtained from: NetApp
* Maintain state regarding NMI delivery to guest vcpu in VT-x independent manner.neel2012-10-242-15/+2
| | | | | | Also add a stats counter to count the number of NMIs delivered per vcpu. Obtained from: NetApp
* Test for AST pending with interrupts disabled right before entering the guest.neel2012-10-234-28/+86
| | | | | | | If an IPI was delivered to this cpu before interrupts were disabled then return right away via vmx_setjmp() with a return value of VMX_RETURN_AST. Obtained from: NetApp
* Add the guest physical address and r/w/x bits togrehan2012-10-121-0/+2
| | | | | | | | the paging exit in preparation for a rework of bhyve MMIO handling. Reviewed by: neel Obtained from: NetApp
* Provide per-vcpu locks instead of relying on a single big lock.neel2012-10-121-2/+2
| | | | | | | This also gets rid of all the witness.watch warnings related to calling malloc(M_WAITOK) while holding a mutex. Reviewed by: grehan
* Allocate memory pages for the guest from the host's free page queue.neel2012-10-081-5/+45
| | | | | It is no longer necessary to hard-partition the memory between the host and guests at boot time.
* Get rid of assumptions in the hypervisor that the host physical memoryneel2012-10-033-20/+102
| | | | | | | associated with guest physical memory is contiguous. Rewrite vm_gpa2hpa() to get the GPA to HPA mapping by querying the nested page tables.
* Intel VT-x provides the length of the instruction at the time of the nestedneel2012-09-271-3/+13
| | | | | | | | | | page table fault. Use this when fetching the instruction bytes from the guest memory. Also modify the lapic_mmio() API so that a decoded instruction is fed into it instead of having it fetch the instruction bytes from the guest. This is useful for hardware assists like SVM that provide the faulting instruction as part of the vmexit.
* Add support for trapping MMIO writes to local apic registers and emulating them.neel2012-09-252-14/+70
| | | | | The default behavior is still to present the local apic to the guest in the x2apic mode.
* Add an explicit exit code 'SPINUP_AP' to tell the controlling process that anneel2012-09-251-0/+8
| | | | | | | | | | AP needs to be activated by spinning up an execution context for it. The local apic emulation is now completely done in the hypervisor and it will detect writes to the ICR_LO register that try to bring up the AP. In response to such writes it will return to userspace with an exit code of SPINUP_AP. Reviewed by: grehan
* Stash the 'vm_exit' information in each 'struct vcpu'.neel2012-09-241-1/+4
| | | | | There is no functional change at this time but this paves the way for vm exit handler functions to easily modify the exit reason going forward.
* Force certain bits in %cr4 to be hard-wired to '1' or '0' from a guest'sneel2012-08-041-16/+52
| | | | | | | perspective. If we don't do this some guest OSes (e.g. Linux) will reset the CR4_VMXE bit in %cr4 with disastrous consequences. Reported by: grehan
* Verify that VMX operation has been enabled by BIOS before executing theneel2012-07-251-1/+11
| | | | | | VMXON instruction. Reported by "s vas" on freebsd-virtualization@
* MSI-x interrupt support for PCI pass-thru devices.grehan2012-04-282-0/+5
| | | | | | | | | | Includes instruction emulation for memory r/w access. This opens the door for io-apic, local apic, hpet timer, and legacy device emulation. Submitted by: ryan dot berryhill at sandvine dot com Reviewed by: grehan Obtained from: Sandvine
* Add support for running as a nested hypervisor under VMWare Fusion, ongrehan2011-12-241-18/+54
| | | | | | | | | | | | | | | | | | | | | | | | systems with VT-x/EPT (e.g. Sandybridge Macbooks). This will most likely work on VMWare Workstation8/Player4 as well. See the VMWare app note at: http://communities.vmware.com/docs/DOC-8970 Fusion doesn't propagate the PAT MSR auto save-restore entry/exit control bits. Deal with this by noting that fact and setting up the PAT MSR to essentially be a no-op - it is init'd to power-on default, and a software shadow copy maintained. Since it is treated as a no-op, o/s settings are essentially ignored. This may not give correct results, but since the hypervisor is running nested, a number of bets are already off. On a quad-core/HT-enabled 'MacBook8,2', nested VMs with 1/2/4 vCPUs were fired up. The more nested vCPUs the worse the performance, unless the VMs were started up in multiplexed mode where things worked perfectly up to the limit of 8 vCPUs. Reviewed by: neel
* Some tweaks to the CPUID support:jhb2011-06-021-6/+5
| | | | | | | | | | | | - Don't always pass the cpuid request to the current CPU as some nodes we will emulate purely in software. - Pass in the APIC ID of the virtual CPU so we can return the proper APIC ID. - Always report a completely flat topology with no SMT or multicore. - Report the CPUID2_HV feature and implement support for the 0x40000000 CPUID level. - Use existing constants from <machine/specialreg.h> when possible and use cpu_feature2 when checking for VMX support.
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