summaryrefslogtreecommitdiffstats
path: root/sys/amd64/vmm/intel
Commit message (Expand)AuthorAgeFilesLines
* vmm(4): Small spelling fixes.pfg2016-05-031-1/+1
* Restructure memory allocation in bhyve to support "devmem".neel2015-06-181-1/+1
* Support guest writes to the TSC by enabling the "use TSC offsetting"tychon2015-06-093-4/+26
* Fix non-deterministic delays when accessing a vcpu that was in "running" orneel2015-05-281-3/+9
* Don't rely on the 'VM-exit instruction length' field in the VMCS to alwaysneel2015-05-221-0/+1
* Emulate machine check related MSRs to allow guest OSes like Windows to boot.neel2015-05-021-0/+7
* Don't require <sys/cpuset.h> to be always included before <machine/vmm.h>.neel2015-04-301-1/+0
* Advertise the MTRR feature via CPUID and emulate the minimal set of MTRR MSRs.neel2015-04-301-0/+15
* When fetching an instruction in non-64bit mode, consider the value of thetychon2015-03-241-0/+6
* Use lapic_ipi_alloc() to dynamically allocate IPI slots needed by bhyve whenneel2015-03-142-7/+5
* Always emulate MSR_PAT on Intel processors and don't rely on PAT save/restoreneel2015-02-244-22/+56
* Simplify instruction restart logic in bhyve.neel2015-01-181-0/+1
* 'struct vm_exception' was intended to be used only as the collateral for theneel2015-01-131-9/+9
* Clear blocking due to STI or MOV SS in the hypervisor when an instruction isneel2015-01-062-10/+29
* Allow ktr(4) tracing of all guest exceptions via the tunableneel2014-12-233-13/+71
* Emulate writes to the IA32_MISC_ENABLE MSR.neel2014-12-201-2/+24
* IFC @r273214neel2014-10-201-1/+1
* IFC @r272887neel2014-10-102-0/+108
|\
| * Support Intel-specific MSRs that are accessed when booting up a linux in bhyve:neel2014-10-091-0/+100
| * Inject #UD into the guest when it executes either 'MONITOR' or 'MWAIT'.neel2014-10-061-0/+8
* | IFC @r272481neel2014-10-051-55/+17
|\ \ | |/
| * Get rid of code that dealt with the hardware not being able to save/restoreneel2014-10-021-55/+17
* | IFC @r272185neel2014-09-271-7/+0
|\ \ | |/
| * MSR_KGSBASE is no longer saved and restored from the guest MSR save area. Thisneel2014-09-201-7/+0
| * Restructure the MSR handling so it is entirely handled by processor-specificneel2014-09-206-41/+201
* | IFC r271888.neel2014-09-206-41/+201
* | IFC @r271694neel2014-09-171-0/+46
|\ \ | |/
| * Optimize the common case of injecting an interrupt into a vcpu after a HLTneel2014-09-121-0/+46
* | AMD processors that have the SVM decode assist capability will store theneel2014-09-131-0/+1
* | IFC @r269962neel2014-09-026-196/+496
|\ \ | |/
| * Use the max guest memory address when creating its iommu domain.neel2014-08-141-0/+5
| * - Output a summary of optional VT-x features in dmesg similar to CPUjhb2014-07-303-30/+27
| * If a vcpu has issued a HLT instruction with interrupts disabled then it sleepsneel2014-07-261-1/+1
| * Fix build without INVARIANTS defined by getting rid of unused variable 'exc'.neel2014-07-201-2/+1
| * Handle nested exceptions in bhyve.neel2014-07-191-47/+75
| * Add emulation for legacy x86 task switching mechanism.neel2014-07-163-5/+88
| * Add support for operand size and address size override prefixes in bhyve'sneel2014-07-151-1/+16
| * Accurately identify the vcpu's operating mode as 64-bit, compatibility,neel2014-07-081-4/+12
| * Invalidate guest TLB mappings as a side-effect of its CR3 being updated.neel2014-07-081-27/+68
| * Bring an overly enthusiastic KASSERT inline with the Intel SDM.tychon2014-06-161-2/+18
| * Add helper functions to populate VM exit information for rendezvous andneel2014-06-101-32/+8
| * Turn on interrupt window exiting unconditionally when an ExtINT is beingneel2014-06-101-2/+6
| * Add reserved bit checking when doing %CR8 emulation and inject #GP if required.neel2014-06-091-6/+9
| * Support guest accesses to %cr8.tychon2014-06-061-50/+144
| * If VMX isn't enabled so long as the lock bit isn't set yet in MSRtychon2014-05-301-1/+10
| * - Rework the XSAVE/XRSTOR emulation to only expose XCR0 features to thejhb2014-05-271-2/+24
* | ins/outs support for SVM. Modelled on the Intel VT-x code.grehan2014-06-061-2/+0
|/
* Do the linear address calculation for the ins/outs emulation using a newneel2014-05-251-1/+0
* Consolidate all the information needed by the guest page table walker intoneel2014-05-241-10/+14
* When injecting a page fault into the guest also update the guest's %cr2 toneel2014-05-241-0/+2
OpenPOWER on IntegriCloud