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* Commit MD parts of a loosely functional AMD64 port. This is based onpeter2003-05-012-558/+18
* Initiate de-orbit burn for USE_PCI_BIOS_FOR_READ_WRITE. This has beenpeter2003-02-182-147/+28
* Outdent the string rather than use concatenation.phk2002-12-231-2/+2
* MFp4:imp2002-11-141-1/+1
* Recognize the Serverworks CIOB30 host to pci bridge.peter2002-11-131-0/+5
* MFp4:imp2002-11-021-10/+34
* Use 0xffffffff instead of -1 for id to compare against.imp2002-11-021-10/+11
* Revert last commit, there actually was a -1 waaaaay down in pcireg_cfgread().phk2002-10-201-0/+2
* "id" is never going to be -1 when it is unsigned.phk2002-10-201-2/+0
* Use the global pcib devclass instead of our own static copy.jhb2002-10-161-2/+0
* o go ahead and route the interupt, even if it is supposedly unique.imp2002-10-071-7/+12
* Add 2 Ids for new ServerWorks host to PCI bridge chipset.iwasaki2002-10-021-0/+8
* Don't call function in return() for a void function.phk2002-09-281-3/+5
* Now that we only probe host-PCI bridges once, we no longer have to check tojhb2002-09-231-10/+0
* Put verbose printf's in the PCI BIOS interrupt routing code underjhb2002-09-231-1/+4
* Change the nexus_pcib driver (eventually to be renamed to legacy_pcib) tojhb2002-09-231-7/+7
* Axe unused include.jhb2002-09-201-1/+0
* Make sure a $PIR table header has a valid length before accepting the tablejhb2002-09-091-1/+2
* #include "opt_bla.h" goes first says Bruce.phk2002-09-091-2/+2
* Fix style(9) bugs.phk2002-09-081-2/+2
* Add a subclass of the PCI-PCI bridge driver that uses the PCIBIOS tojhb2002-09-061-2/+69
* Add a function pci_probe_route_table() that returns true if our PCI BIOSjhb2002-09-061-0/+19
* Dump the $PIR table if booting verbose.jhb2002-09-061-0/+3
* - Add a pci_cfgintr_valid() function to see if a given IRQ is a validjhb2002-09-062-2/+35
* Add support for printing out the contents of a PCI BIOS $PIR interruptjhb2002-09-061-2/+54
* Prefer the physical bus number of the PCI bus as the unit of the pciXjhb2002-09-061-1/+1
* Test PCIbios.ventry against 0 to see if we found a PCIbios entry point,jhb2002-09-051-2/+2
* Change the support for AMDs ElanSC520 CPU from being a device driver tophk2002-09-041-0/+7
* Move a prototype to the least wrong place.phk2002-08-021-0/+1
* style(9)ize the whole fileimp2002-07-211-474/+492
* Add support for probing secondary buses on the ServerWorks Grand Championgallatin2002-07-191-0/+11
* Add initialization code for the AMD Elan sc520 which maps the MMCRphk2002-07-181-0/+2
* Add an entry for the AMD Elan SC520 hostbridge. I do not belive we canphk2002-07-181-0/+3
* Use a common function to map the bogus intlines.imp2002-06-011-11/+17
* Restore the irq=0 => irq=255 hack to pci_cfgintr_search(). Just havingbrooks2002-05-291-0/+8
* o Work around bugs in the powerof2 macro: It thinks that 0 is a power ofimp2002-04-241-12/+18
* Fix a PNPID in a commentimp2002-04-241-1/+1
* Major rework of the iicbus/smbus framework:nsouch2002-03-231-0/+13
* Don't call the bios if the interrupt appaers to be already routed. Someimp2002-03-161-3/+3
* The Libretto L series has no $PIR table, but does have a _PIR table.imp2002-01-201-13/+22
* Add identification string for AMD-761 host to PCI bridge.murray2001-12-101-0/+3
* MFS: I was confused. This code wasn't in -current after all.imp2001-11-261-5/+14
* It turns out that while Toshiba laptops don't want to route interruptsimp2001-08-281-17/+10
* MFS: IRQ ordering, PRVERB and more whining in pcibios_get_version on failure.imp2001-08-271-30/+60
* The general conesnsus on irc was that pci bios for config registersimp2001-08-211-2/+25
* Detect a certain type of PCIBIOS brain damage. For some reason,peter2001-08-212-0/+31
* Un-swap irq/link byte values so that printf works.msmith2001-05-111-1/+1
* Free the memory we get from devclass_get_devices and device_get_children.msmith2001-02-081-3/+8
* Fix a warning due to missing prototype.peter2001-01-191-1/+1
* Remove declaration of airq variable from outer block. There were twobmilekic2001-01-121-1/+1
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