summaryrefslogtreecommitdiffstats
path: root/sys/amd64/pci
Commit message (Expand)AuthorAgeFilesLines
* It turns out that while Toshiba laptops don't want to route interruptsimp2001-08-281-17/+10
* MFS: IRQ ordering, PRVERB and more whining in pcibios_get_version on failure.imp2001-08-271-30/+60
* The general conesnsus on irc was that pci bios for config registersimp2001-08-211-2/+25
* Detect a certain type of PCIBIOS brain damage. For some reason,peter2001-08-212-0/+31
* Un-swap irq/link byte values so that printf works.msmith2001-05-111-1/+1
* Free the memory we get from devclass_get_devices and device_get_children.msmith2001-02-081-3/+8
* Fix a warning due to missing prototype.peter2001-01-191-1/+1
* Remove declaration of airq variable from outer block. There were twobmilekic2001-01-121-1/+1
* Next phase in the PCI subsystem cleanup.msmith2000-12-082-4/+54
* Hack to work around a probe which will lock up at least some i450GX-basedmsmith2000-11-081-1/+5
* Improve the PCI interrupt routing code. Now the process is as follows:msmith2000-11-021-16/+162
* Return -10000 in pci_hostb_probe to allow agp driver (disabled otherwise)ache2000-10-201-1/+1
* Add i815 Host to Hubache2000-10-201-0/+3
* Call the BIOS to route the selected interrupt. Correctly calculate themsmith2000-10-191-4/+22
* Remove debug writes introduced in prior commitimp2000-10-161-5/+2
* Add the ability to use the $PIR table in the BIOS to route interruptsimp2000-10-162-3/+74
* Change the text for the ServerWorks north bridge chips. RCC is nowalc2000-10-141-4/+4
* When testing for PCI bus overlap with another enumerator, make sure wemsmith2000-10-111-1/+1
* Only attach "legacy" PCI busses if none have been attached via any othermsmith2000-10-091-3/+23
* Move the i386 PCI attachment code out of i386/isa back into i386/pci.msmith2000-10-022-1028/+255
* Get out the roto-rooter and clean up the abuse of nexus ivars by thepeter2000-09-282-38/+12
* Catch a few more bogosities in certain chipsets before they mess us up.peter2000-09-052-38/+178
* Take a shot at fixing multiple pci busses on i386.peter2000-08-312-20/+100
* * Completely rewrite the alpha busspace to hide the implementation fromdfr2000-08-282-96/+168
* Add PnP probe methods to some common AT hardware drivers. In each case,msmith2000-06-232-0/+108
* Add OPTi 82C700 chipset.kuriyama2000-05-242-0/+6
* Add 440MX chipset.kuriyama2000-05-242-0/+6
* Don't assume that the PCI BIOS is going to clear the unused bits in %ecxmsmith2000-05-042-2/+10
* Some more i386-only BIOS-friendliness:msmith2000-04-162-18/+224
* Add a workaround to allow us to detect the second pci bus on an HPdfr2000-02-232-2/+20
* Fix an uninitialised variable which affected probing on some machines.dfr2000-02-132-0/+2
* Allow allows peer pci buses which are directly connected to the RCC host pcigallatin2000-02-092-14/+44
* Add PCI Id's for i810 chipsets.n_hibma2000-02-072-0/+18
* Clean up the cfgmech/pci_mechanism debris. The reason for the existancepeter2000-01-082-12/+0
* Don't use a bogus bus number for Ross host-pci bridges.dfr1999-12-052-0/+4
* Remove the 'ivars' arguement to device_add_child() andmdodd1999-12-032-2/+2
* If we have found pci devices via pci_cfgopen(), but don't find apeter1999-11-182-0/+28
* Add text for the AMD-751 host-to-PCI and PCI-to-PCI (AGP) bridges.alc1999-10-252-0/+10
* $Id$ -> $FreeBSD$peter1999-08-282-2/+2
* Make the identify routine add itself with priority 100 to make sure itpeter1999-08-222-4/+12
* Hopefully fix the previous commit, it caused *all* bridges to be detectedpeter1999-08-102-12/+14
* Fix nexus_pcib_is_host_bridge() so that it detects my 486's PCI buswpaul1999-08-092-6/+18
* Don't probe if pci_cfgopen() fails to find pci hardware, like we used topeter1999-08-042-10/+8
* Add support for multiple PCI busses directly connected to the nexus.msmith1999-07-162-8/+360
* Move pcibus (host -> pci bus) probe/attach routines from nexuspeter1999-05-182-6/+94
* Make the class code checks in function pci_cfgcheck less strict.se1997-12-202-4/+4
* Removed unused #includes.bde1997-07-202-4/+2
* Yet another fix for configuration mechanism 1 register accesses:se1997-05-262-8/+10
* Fix previous fix: The enable bit is bit 31 (0x8000000) and not bit 15.se1997-05-262-4/+4
* Set enable bit when writing the configuration address in configurationse1997-05-262-4/+4
OpenPOWER on IntegriCloud