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* Back out all the pmap related stuff I've touched over the last few days.peter2002-02-273-13/+23
| | | | | | There is some unresolved badness that has been eluding me, particularly affecting uniprocessor kernels. Turning off PG_G helped (which is a bad sign) but didn't solve it entirely. Userland programs still crashed.
* revert last commit temporarily due to whining on the lists.dillon2002-02-268-734/+297
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* STAGE-1 of 3 commit - allow (but do not require) interrupts to remaindillon2002-02-268-297/+734
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | enabled in critical sections and streamline critical_enter() and critical_exit(). This commit allows an architecture to leave interrupts enabled inside critical sections if it so wishes. Architectures that do not wish to do this are not effected by this change. This commit implements the feature for the I386 architecture and provides a sysctl, debug.critical_mode, which defaults to 1 (use the feature). For now you can turn the sysctl on and off at any time in order to test the architectural changes or track down bugs. This commit is just the first stage. Some areas of the code, specifically the MACHINE_CRITICAL_ENTER #ifdef'd code, is strictly temporary and will be cleaned up in the STAGE-2 commit when the critical_*() functions are moved entirely into MD files. The following changes have been made: * critical_enter() and critical_exit() for I386 now simply increment and decrement curthread->td_critnest. They no longer disable hard interrupts. When critical_exit() decrements the counter to 0 it effectively calls a routine to deal with whatever interrupts were deferred during the time the code was operating in a critical section. Other architectures are unaffected. * fork_exit() has been conditionalized to remove MD assumptions for the new code. Old code will still use the old MD assumptions in regards to hard interrupt disablement. In STAGE-2 this will be turned into a subroutine call into MD code rather then hardcoded in MI code. The new code places the burden of entering the critical section in the trampoline code where it belongs. * I386: interrupts are now enabled while we are in a critical section. The interrupt vector code has been adjusted to deal with the fact. If it detects that we are in a critical section it currently defers the interrupt by adding the appropriate bit to an interrupt mask. * In order to accomplish the deferral, icu_lock is required. This is i386-specific. Thus icu_lock can only be obtained by mainline i386 code while interrupts are hard disabled. This change has been made. * Because interrupts may or may not be hard disabled during a context switch, cpu_switch() can no longer simply assume that PSL_I will be in a consistent state. Therefore, it now saves and restores eflags. * FAST INTERRUPT PROVISION. Fast interrupts are currently deferred. The intention is to eventually allow them to operate either while we are in a critical section or, if we are able to restrict the use of sched_lock, while we are not holding the sched_lock. * ICU and APIC vector assembly for I386 cleaned up. The ICU code has been cleaned up to match the APIC code in regards to format and macro availability. Additionally, the code has been adjusted to deal with deferred interrupts. * Deferred interrupts use a per-cpu boolean int_pending, and masks ipending, spending, and fpending. Being per-cpu variables it is not currently necessary to lock; bus cycles modifying them. Note that the same mechanism will enable preemption to be incorporated as a true software interrupt without having to further hack up the critical nesting code. * Note: the old critical_enter() code in kern/kern_switch.c is currently #ifdef to be compatible with both the old and new methodology. In STAGE-2 it will be moved entirely to MD code. Performance issues: One of the purposes of this commit is to enhance critical section performance, specifically to greatly reduce bus overhead to allow the critical section code to be used to protect per-cpu caches. These caches, such as Jeff's slab allocator work, can potentially operate very quickly making the effective savings of the new critical section code's performance very significant. The second purpose of this commit is to allow architectures to enable certain interrupts while in a critical section. Specifically, the intention is to eventually allow certain FAST interrupts to operate rather then defer. The third purpose of this commit is to begin to clean up the critical_enter()/critical_exit()/cpu_critical_enter()/ cpu_critical_exit() API which currently has serious cross pollution in MI code (in fork_exit() and ast() for example). The fourth purpose of this commit is to provide a framework that allows kernel-preempting software interrupts to be implemented cleanly. This is currently used for two forward interrupts in I386. Other architectures will have the choice of using this infrastructure or building the functionality directly into critical_enter()/ critical_exit(). Finally, this commit is designed to greatly improve the flexibility of various architectures to manage critical section handling, software interrupts, preemption, and other highly integrated architecture-specific details.
* Work-in-progress commit syncing up pmap cleanups that I have been workingpeter2002-02-253-23/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | on for a while: - fine grained TLB shootdown for SMP on i386 - ranged TLB shootdowns.. eg: specify a range of pages to shoot down with a single IPI, since the IPI is very expensive. Adjust some callers that used to trigger this inside tight loops to do a ranged shootdown at the end instead. - PG_G support for SMP on i386 (options ENABLE_PG_G) - defer PG_G activation till after we decide what we are going to do with PSE and the 4MB pages at the start of the kernel. This should solve some rumored strangeness about stale PG_G entries getting stuck underneath the 4MB pages. - add some instrumentation for the fine TLB shootdown - convert some asm instruction wrappers from functions to inlines. gcc seems to do a fair bit better with this. - [temporarily!] pessimize the tlb shootdown IPI handlers. I will fix this again shortly. This has been working fairly well for me for a while, but I have tweaked it again prior to commit since my last major testing round. The only outstanding problem that I know of is PG_G related, which is why there is an option for it (not on by default for SMP). I have seen a world speedups by a few percent (as much as 4 or 5% in one case) but I have *not* accurately measured this - I am a bit sceptical of these numbers.
* - Split the routine to initialize a bus_space_handle into the separatenyan2002-02-171-5/+7
| | | | | | | function. - Only access a bus_space_handle if the resource type is SYS_RES_MEMORY or SYS_RES_IOPORT. - Add the bus_space_subregion supports.
* Add needed include.nyan2002-02-101-0/+3
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* Don't grab the ICU lock while reading the current pending interrupts andjhb2002-02-082-4/+0
| | | | | | current masked interrupts from the AT PIC. Requested by: bde
* Don't include <isa/isavar.h> or compile code depending on it when isabde2002-01-304-1/+14
| | | | | | | | is not configured. Including <isa/isavar.h> when it is not used is harmful as well as bogus, since it includes "isa_if.h" which is not generated when isa is not configured. This was fixed in 1999 but was broken by unconditionalizing PNPBIOS.
* Removed unused includes. In particular, don't include <isa/isavar.h> sincebde2002-01-301-24/+2
| | | | | | its only effect is to break the optionality of the isa option. Sorted includes.
* Change the preemption code for software interrupt thread schedules andjhb2002-01-053-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mutex releases to not require flags for the cases when preemption is not allowed: The purpose of the MTX_NOSWITCH and SWI_NOSWITCH flags is to prevent switching to a higher priority thread on mutex releease and swi schedule, respectively when that switch is not safe. Now that the critical section API maintains a per-thread nesting count, the kernel can easily check whether or not it should switch without relying on flags from the programmer. This fixes a few bugs in that all current callers of swi_sched() used SWI_NOSWITCH, when in fact, only the ones called from fast interrupt handlers and the swi_sched of softclock needed this flag. Note that to ensure that swi_sched()'s in clock and fast interrupt handlers do not switch, these handlers have to be explicitly wrapped in critical_enter/exit pairs. Presently, just wrapping the handlers is sufficient, but in the future with the fully preemptive kernel, the interrupt must be EOI'd before critical_exit() is called. (critical_exit() can switch due to a deferred preemption in a fully preemptive kernel.) I've tested the changes to the interrupt code on i386 and alpha. I have not tested ia64, but the interrupt code is almost identical to the alpha code, so I expect it will work fine. PowerPC and ARM do not yet have interrupt code in the tree so they shouldn't be broken. Sparc64 is broken, but that's been ok'd by jake and tmm who will be fixing the interrupt code for sparc64 shortly. Reviewed by: peter Tested on: i386, alpha
* Use the new resource_list_print_type() function.tmm2001-12-211-1/+1
| | | | | Pass the bus device to isa_init() (this is needed for the sparc64 version).
* Introduce a standard name for the lock protecting an interrupt controllerjhb2001-12-207-25/+55
| | | | | | | | and it's associated state variables: icu_lock with the name "icu". This renames the imen_mtx for x86 SMP, but also uses the lock to protect access to the 8259 PIC on x86 UP. This also adds an appropriate lock to the various Alpha chipsets which fixes problems with Alpha SMP machines dropping interrupts with an SMP kernel.
* Axe stale extern for a non-existent variable.jhb2001-12-181-1/+0
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* Modify the critical section API as follows:jhb2001-12-181-8/+8
| | | | | | | | | | | | | | | | | | | - The MD functions critical_enter/exit are renamed to start with a cpu_ prefix. - MI wrapper functions critical_enter/exit maintain a per-thread nesting count and a per-thread critical section saved state set when entering a critical section while at nesting level 0 and restored when exiting to nesting level 0. This moves the saved state out of spin mutexes so that interlocking spin mutexes works properly. - Most low-level MD code that used critical_enter/exit now use cpu_critical_enter/exit. MI code such as device drivers and spin mutexes use the MI wrappers. Note that since the MI wrappers store the state in the current thread, they do not have any return values or arguments. - mtx_intr_enable() is replaced with a constant CRITICAL_FORK which is assigned to curthread->td_savecrit during fork_exit(). Tested on: i386, alpha
* Overhaul the per-CPU support a bit:jhb2001-12-111-17/+17
| | | | | | | | | | | | | | | | | | | | | | | | | - The MI portions of struct globaldata have been consolidated into a MI struct pcpu. The MD per-CPU data are specified via a macro defined in machine/pcpu.h. A macro was chosen over a struct mdpcpu so that the interface would be cleaner (PCPU_GET(my_md_field) vs. PCPU_GET(md.md_my_md_field)). - All references to globaldata are changed to pcpu instead. In a UP kernel, this data was stored as global variables which is where the original name came from. In an SMP world this data is per-CPU and ideally private to each CPU outside of the context of debuggers. This also included combining machine/globaldata.h and machine/globals.h into machine/pcpu.h. - The pointer to the thread using the FPU on i386 was renamed from npxthread to fpcurthread to be identical with other architectures. - Make the show pcpu ddb command MI with a MD callout to display MD fields. - The globaldata_register() function was renamed to pcpu_init() and now init's MI fields of a struct pcpu in addition to registering it with the internal array and list. - A pcpu_destroy() function was added to remove a struct pcpu from the internal array and list. Tested on: alpha, i386 Reviewed by: peter, jake
* Some fix for the recent apm module changes.iwasaki2001-11-011-7/+4
| | | | | | | | | | | | | | - Now that apm loadable module can inform its existence to other kernel components (e.g. i386/isa/clock.c:startrtclock()'s TCS hack). - Exchange priority of SI_SUB_CPU and SI_SUB_KLD for above purpose. - Add simple arbitration mechanism for APM vs. ACPI. This prevents the kernel enables both of them. - Remove obsolete `#ifdef DEV_APM' related code. - Add abstracted interface for Powermanagement operations. Public apm(4) functions, such as apm_suspend(), should be replaced new interfaces. Currently only power_pm_suspend (successor of apm_suspend) is implemented. Reviewed by: peter, arch@ and audit@
* Backout 1.61 -- both intrcnt and intrnames are already exportedluigi2001-10-252-12/+0
| | | | via sysctl under "hw".
* MFi386:bde2001-10-211-0/+2
| | | | | | | | | - sys/pc98/pc98/npx.c 1.87 (2001/09/15; author: imp) I don't think pc98 has acpi at all, so ifdef the acpi attachments for now. This completes merging sys/pc98/pc98/npx.c into sys/i386/isa/npx.c so that the former can be removed.
* MFpc98: fundamental differences. The magic numbers for the i/o portbde2001-10-211-0/+17
| | | | | | and the irq are different for pc98, and are not very well handled (we use a historical mess of hard-coded values, values from header files and values from hints).
* MFpc98: all changes in sys/pc98/pc98/npx.c related to FPU_ERROR_BROKEN.bde2001-10-211-0/+9
| | | | | | | | | | | | | | - 1.58 (2000/09/01; author: kato) Fixed FPU_ERROR_BROKEN code. It had old-isa code. - 1.33 (1998/03/09; author: kato) Make FPU_ERROR_BROKEN a new-style option. - 1.7 (1996/10/09; author: asami) Make sure FPU is recognized for non-Intel CPUs. The log for rev.1.7 should have said something like: Added FPU_ERROR_BROKEN option. This forces a successful probe for exception 16, so that hardware with a broken FPU error signal can sort of work.
* Deleted most of npxprobe(), and merged npxprobe1() back into npxprobe().bde2001-10-161-127/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | Use the normal interrupt handler (npx_intr()) instead of a special probe-time interrupt handler, although this causes problems due to the bus_teardown_intr() not actually even tearing down the interrupt (these problems were avoided by doing interrupt attachment for the special interrupt handler directly). Fixed minor bitrot in comments. The reason for the npxprobe()/npxprobe1() split mostly went away at about the same time it was made (in 1992 or 1993 just before the beginning of history). 386BSD ran all probes with interrupts completely masked, and I didn't want to disturb this when I added an irq probe to npxprobe(). An irq (not necessarily npx) must be acked for at least external npx's to take the cpu out of the wait state that it enters when an npx error occurs, so the probe must be done with a suitable irq unmasked. npxprobe() went to great lengths to unmask precisely the npx irq. Running probes with all interrupts masked was never really needed in FreeBSD, since FreeBSD always masked interrupts well enough using splhigh(), but it wasn't until rev.1.48 (1995/12/12) of autoconf.c that all probes were run with CPU interrupts enabled. This permits npxprobe() to probe its irq using normal interrupt resources. Note that most drivers still can't depend on this. It depends on the interrupt handler being fast and the irq not being shared.
* Commit my old fixes for cosmetic bugs in npxprobe() so that they aren'tbde2001-10-161-13/+8
| | | | | | | | | | | | | | | | lost when the buggy code goes away completely: - don't assume that the npx irq number is >= 8. Rev.1.73 only reversed part of the hard-coding of it to 13 in rev.1.66. - backed out the part of rev.1.84 that added a highly confused comment about an enable_intr() being "highly bogus". The whole reason for existence of npxprobe() (separate from the main probe, npxprobe1()) is to handle the complications to make this enable_intr() safe. - backed out the part of rev.1.94 that modified npxprobe(). It mainly broke the enable_intr() to restore_intr(). Restoring the interrupt state in a nested way is precisely what is not wanted here. It was harmless in practice because npxprobe() is called with interrupts enabled, so restoring the interrupt state enables interrupts. Most of npxprobe() is a no-op for the same reason...
* Explicitly initialize the fpu when SSE is enabled since this notegge2001-10-151-0/+5
| | | | | | longer happens as a side effect of calling npxsave. Reviewed by: peter, bde
* Add missing includes of sys/lock.h.jhb2001-10-111-0/+1
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* Remove the Xresume* labels from the i386 interrupt handlers; theiedowse2001-10-093-3/+0
| | | | | | | | | | | | | | | | | | code in ipl.s and icu_ipl.s that used them was removed when the interrupt thread system was committed. Debuggers also knew about Xresume* because these labels hide the real names of the interrupt handlers (Xintr*), and debuggers need to special-case interrupt handlers to get the interrupt frame. Both gdb and ddb will now use the Xintr* and Xfastintr* symbols to detect interrupt frames. Fast interrupt frames were never identified correctly before, so this fixes the problem of the running stack frame getting lost in a ddb or gdb trace generated from a fast interrupt - e.g. when debugging a simple infinite loop in the kernel using a serial console, the frame containing the loop would never appear in a gdb or ddb trace. Reviewed by: jhb, bde
* Remove an unneeded variable declaration and statement.robert2001-10-091-2/+0
| | | | Approved by: jake
* Export interrupt statistics via sysctl.luigi2001-10-072-0/+12
| | | | MFC-after: 3 days
* Rewrite the pc98 bus_space stuff.nyan2001-10-071-10/+13
| | | | | | | | | | | | | | | | The type of bus_space_tag_t is now a pointer to bus_space_tag structure, and the bus_space_tag structure saves pointers to functions for direct access and relocate access. Added bsh_bam member to the bus_space_handle structure, it saves access method either direct access or relocate access which is called by bus_space_* functions. Added the mecia device support. If the bs_da and bs_ra in bus tag are set NEPC_io_space_tag and NEPC_mem_space_tag respectively, new bus_space stuff changes the register of mecia automatically for 16bit access. Obtained from: NetBSD/pc98
* Disable the check in icu_setup() to see if a handler was already used asjhb2001-09-272-0/+4
| | | | | | | the current interrupt thread routines will guarantee the condition this is checking for at a higher level but inthand_add() and inthand_remove() as they currently exist don't satisfy this condition. (Which does need to be fixed but which will take a bit more work.) This fixes shared interrupts.
* Return EINVAL if the passed intr is out of bounds.jlemon2001-09-272-0/+2
| | | | | | PR: 30857 Submitted by: David Xu <davidx@viasoft.com.cn> MFC: 1 week
* Whitespace fixes.jhb2001-09-181-3/+3
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* s/thread'/thread's/imp2001-09-141-1/+1
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* KSE Milestone 2julian2001-09-124-60/+61
| | | | | | | | | | | | | | Note ALL MODULES MUST BE RECOMPILED make the kernel aware that there are smaller units of scheduling than the process. (but only allow one thread per process at this time). This is functionally equivalent to teh previousl -current except that there is a thread associated with each process. Sorry john! (your next MFC will be a doosie!) Reviewed by: peter@freebsd.org, dillon@freebsd.org X-MFC after: ha ha ha ha
* Reenable RTC interrupts after wakeup. Some laptops have a problemiwasaki2001-09-041-1/+22
| | | | | | | | | with system statistics monitoring tools (such as systat, vmstat...) because of stopping RTC interrupts generation. Restore all the timers (RTC and i8254) atomically. Reviewed by: bde MFC after: 1 week
* Add ACPI attachments.msmith2001-08-305-1/+6
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* Axe a commented, unused #define related to the old giant lock.jhb2001-08-241-1/+0
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* Dont compile in SSE fxsave/fxrstor instructions if CPU_ENABLE_SSE isn'tpeter2001-08-231-6/+15
| | | | active.
* - Close races with signals and other AST's being triggered while we are injhb2001-08-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | the process of exiting the kernel. The ast() function now loops as long as the PS_ASTPENDING or PS_NEEDRESCHED flags are set. It returns with preemption disabled so that any further AST's that arrive via an interrupt will be delayed until the low-level MD code returns to user mode. - Use u_int's to store the tick counts for profiling purposes so that we do not need sched_lock just to read p_sticks. This also closes a problem where the call to addupc_task() could screw up the arithmetic due to non-atomic reads of p_sticks. - Axe need_proftick(), aston(), astoff(), astpending(), need_resched(), clear_resched(), and resched_wanted() in favor of direct bit operations on p_sflag. - Fix up locking with sched_lock some. In addupc_intr(), use sched_lock to ensure pr_addr and pr_ticks are updated atomically with setting PS_OWEUPC. In ast() we clear pr_ticks atomically with clearing PS_OWEUPC. We also do not grab the lock just to test a flag. - Simplify the handling of Giant in ast() slightly. Reviewed by: bde (mostly)
* MASK_FPU_SW didn't do what it was expected to do.peter2001-07-261-7/+1
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* Add ACPI S2-S4BIOS Suspend/Resume code.takawata2001-07-203-2/+53
| | | | | | Some problems may remain. Reviewed by:iwasaki
* The per-cpu temporary buffers are not needed since the pcb_save areas havetegge2001-07-171-14/+5
| | | | | | | the proper alignment. Change dummy variable in npxinit from stack to bss to ensure proper alignment. Reviewed by: bde
* Use PCPU_GET(cpuid) instead of curproc->p_oncpu.tegge2001-07-161-9/+9
| | | | Reviewed by: peter
* Fix another missed pcb_savefpu reference (inside NPX_DEBUG)peter2001-07-121-2/+2
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* Activate SSE/SIMD. This is the extra context switching support thatpeter2001-07-121-11/+82
| | | | | | | | | | | | | | | we are required to do if we let user processes use the extra 128 bit registers etc. This is the base part of the diff I got from: http://www.issei.org/issei/FreeBSD/sse.html I believe this is by: Mr. SUZUKI Issei <issei@issei.org> SMP support apparently by: Takekazu KATO <kato@chino.it.okayama-u.ac.jp> Test code by: NAKAMURA Kazushi <kaz@kobe1995.net>, see http://kobe1995.net/~kaz/FreeBSD/SSE.en.html I have fixed a couple of style(9) deviations. I have some followup commits to fix a couple of non-style things.
* With Alfred's permission, remove vm_mtx in favor of a fine-grained approachdillon2001-07-041-7/+5
| | | | | | | | | (this commit is just the first stage). Also add various GIANT_ macros to formalize the removal of Giant, making it easy to test in a more piecemeal fashion. These macros will allow us to test fine-grained locks to a degree before removing Giant, and also after, and to remove Giant in a piecemeal fashion via sysctl's on those subsystems which the authors believe can operate without Giant.
* Repo copy i8237.h to dev/ic so we can get rid of some of the final vestigesimp2001-06-301-1/+1
| | | | of includes of i386 files from non-i386 ports.
* Don't assume that resource type is ioport and rid equal 0.nyan2001-06-171-5/+6
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* Fix warnings:peter2001-06-151-3/+3
| | | | | 908: warning: long unsigned int format, unsigned int arg (arg 3) 887: warning: `timezero' defined but not used
* Clean up the code exporting interrupt statistics via sysctl a bit:tmm2001-06-015-6/+2
| | | | | | | | | | | | | - move the sysctl code to kern_intr.c - do not use INTRCNT_COUNT, but rather eintrcnt - intrcnt to determine the length of the intrcnt array - move the declarations of intrnames, eintrnames, intrcnt and eintrcnt from machine-dependent include files to sys/interrupt.h - remove the hw.nintr sysctl, it is not needed. - fix various style bugs Requested by: bde Reviewed by: bde (some time ago)
* lock vm while playing with pmapalfred2001-05-231-0/+9
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