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* Rework how we wire up interrupt sources to CPUs:jhb2006-02-281-2/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Throw out all of the logical APIC ID stuff. The Intel docs are somewhat ambiguous, but it seems that the "flat" cluster model we are currently using is only supported on Pentium and P6 family CPUs. The other "hierarchy" cluster model that is supported on all Intel CPUs with local APICs is severely underdocumented. For example, it's not clear if the OS needs to glean the topology of the APIC hierarchy from somewhere (neither ACPI nor MP Table include it) and setup the logical clusters based on the physical hierarchy or not. Not only that, but on certain Intel chipsets, even though there were 4 CPUs in a logical cluster, all the interrupts were only sent to one CPU anyway. - We now bind interrupts to individual CPUs using physical addressing via the local APIC IDs. This code has also moved out of the ioapic PIC driver and into the common interrupt source code so that it can be shared with MSI interrupt sources since MSI is addressed to APICs the same way that I/O APIC pins are. - Interrupt source classes grow a new method pic_assign_cpu() to bind an interrupt source to a specific local APIC ID. - The SMP code now tells the interrupt code which CPUs are avaiable to handle interrupts in a simpler and more intuitive manner. For one thing, it means we could now choose to not route interrupts to HT cores if we wanted to (this code is currently in place in fact, but under an #if 0 for now). - For now we simply do static round-robin of IRQs to CPUs when the first interrupt handler just as before, with the change that IRQs are now bound to individual CPUs rather than groups of up to 4 CPUs. - Because the IRQ to CPU mapping has now been moved up a layer, it would be easier to manage this mapping from higher levels. For example, we could allow drivers to specify a CPU affinity map for their interrupts, or we could allow a userland tool to bind IRQs to specific CPUs. The MFC is tentative, but I want to see if this fixes problems some folks had with UP APIC kernels on 6.0 on SMP machines (an SMP kernel would work fine, but a UP APIC kernel (such as GENERIC in RELENG_6) would lose interrupts). MFC after: 1 week
* Tweak how the MD code calls the fooclock() methods some. Instead ofjhb2005-12-221-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | passing a pointer to an opaque clockframe structure and requiring the MD code to supply CLKF_FOO() macros to extract needed values out of the opaque structure, just pass the needed values directly. In practice this means passing the pair (usermode, pc) to hardclock() and profclock() and passing the boolean (usermode) to hardclock_cpu() and hardclock_process(). Other details: - Axe clockframe and CLKF_FOO() macros on all architectures. Basically, all the archs were taking a trapframe and converting it into a clockframe one way or another. Now they can just extract the PC and usermode values directly out of the trapframe and pass it to fooclock(). - Renamed hardclock_process() to hardclock_cpu() as the latter is more accurate. - On Alpha, we now run profclock() at hz (profhz == hz) rather than at the slower stathz. - On Alpha, for the TurboLaser machines that don't have an 8254 timecounter, call hardclock() directly. This removes an extra conditional check from every clock interrupt on Alpha on the BSP. There is probably room for even further pruning here by changing Alpha to use the simplified timecounter we use on x86 with the lapic timer since we don't get interrupts from the 8254 on Alpha anyway. - On x86, clkintr() shouldn't ever be called now unless using_lapic_timer is false, so add a KASSERT() to that affect and remove a condition to slightly optimize the non-lapic case. - Change prototypeof arm_handler_execute() so that it's first arg is a trapframe pointer rather than a void pointer for clarity. - Use KCOUNT macro in profclock() to lookup the kernel profiling bucket. Tested on: alpha, amd64, arm, i386, ia64, sparc64 Reviewed by: bde (mostly)
* For the amd64 platform, we can depend on the TSC being present. This patchpeter2005-12-121-0/+15
| | | | | | | changes DELAY to use the TSC once it has been calibrated. This does NOT use the TSC for long-term timekeeping. It only uses it to bound the DELAY() spinloop. This should not be affected by the Athlon64 X2 TSC quirks because the cpu is not halted while we use DELAY().
* MFi386:jhb2005-12-083-28/+8
| | | | | | | | | | | | | | | | | | | | | - Move PUSH_FRAME and POP_FRAME to asmacros.h and use PUSH_FRAME in atpic entry points. - Move PCPU_* asm macros out of the middle of the asm profiling macros. - Pass IRQ vector argument as an int rather than void * to reduce diffs with i386. - EOI the lapic in C for the lapic timer handler. - GC unused Xcpuast function. - Split IPI_STOP handling code of ipi_nmi_handler() out into a cpustop_handler() function and call it from Xcpustop rather than duplicating all the logic in assembly. - Fixup the list of symbols with interrupt frames in ddb traces. Xatpic_fastintr* have never existed on amd64, and the lapic timer handler and various IPI handlers were missing. - Use trapframe instead of intrframe for interrupt entry points (on amd64 the interrupt vector was already a separate argument, so the two frames were already identical) and GC intrframe. Submitted by: peter (3)
* Really slam the door on mixed mode now that we don't depend on it for ajhb2005-12-051-0/+15
| | | | | | | | | | | | | working IRQ0 with APIC anymore. Previously, it was possible to have some other ATPIC IRQS "leak" through in a few edge cases. For example, on my x86 test machine, ACPI re-routes the SCI (IRQ 9) to intpin 13 on the first I/O APIC. This leaves a hole for IRQ 13 (since the APIC doesn't provide a source for IRQ 13 in that case) with the result that the ATPIC IRQ13 source was registered instead. This changes the 8259A drivers to only register their interrupt sources if none of the 16 ISA IRQs have an interrupt source already installed. MFC after: 1 week
* Reorganize the interrupt handling code a bit to make a few things cleanerjhb2005-10-251-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | and increase flexibility to allow various different approaches to be tried in the future. - Split struct ithd up into two pieces. struct intr_event holds the list of interrupt handlers associated with interrupt sources. struct intr_thread contains the data relative to an interrupt thread. Currently we still provide a 1:1 relationship of events to threads with the exception that events only have an associated thread if there is at least one threaded interrupt handler attached to the event. This means that on x86 we no longer have 4 bazillion interrupt threads with no handlers. It also means that interrupt events with only INTR_FAST handlers no longer have an associated thread either. - Renamed struct intrhand to struct intr_handler to follow the struct intr_foo naming convention. This did require renaming the powerpc MD struct intr_handler to struct ppc_intr_handler. - INTR_FAST no longer implies INTR_EXCL on all architectures except for powerpc. This means that multiple INTR_FAST handlers can attach to the same interrupt and that INTR_FAST and non-INTR_FAST handlers can attach to the same interrupt. Sharing INTR_FAST handlers may not always be desirable, but having sio(4) and uhci(4) fight over an IRQ isn't fun either. Drivers can always still use INTR_EXCL to ask for an interrupt exclusively. The way this sharing works is that when an interrupt comes in, all the INTR_FAST handlers are executed first, and if any threaded handlers exist, the interrupt thread is scheduled afterwards. This type of layout also makes it possible to investigate using interrupt filters ala OS X where the filter determines whether or not its companion threaded handler should run. - Aside from the INTR_FAST changes above, the impact on MD interrupt code is mostly just 's/ithread/intr_event/'. - A new MI ddb command 'show intrs' walks the list of interrupt events dumping their state. It also has a '/v' verbose switch which dumps info about all of the handlers attached to each event. - We currently don't destroy an interrupt thread when the last threaded handler is removed because it would suck for things like ppbus(8)'s braindead behavior. The code is present, though, it is just under #if 0 for now. - Move the code to actually execute the threaded handlers for an interrrupt event into a separate function so that ithread_loop() becomes more readable. Previously this code was all in the middle of ithread_loop() and indented halfway across the screen. - Made struct intr_thread private to kern_intr.c and replaced td_ithd with a thread private flag TDP_ITHREAD. - In statclock, check curthread against idlethread directly rather than curthread's proc against idlethread's proc. (Not really related to intr changes) Tested on: alpha, amd64, i386, sparc64 Tested on: arm, ia64 (older version of patch by cognet and marcel)
* Fixup some more fallout from the lapic/i8254 changes:jhb2005-07-131-23/+15
| | | | | | | | | | | | - Make sure timer0_max_count is set to a correct value in the lapic case. - Revert i8254_restore() to explicitly reprogram timer 0 rather than calling set_timer_freq() to do it. set_timer_freq() only reprograms the counter if the max count changes which it never does on resume. This unbreaks suspend/resume for several people. Tested by: marks, others Reviewed by: bde MFC after: 3 days
* Remove a || 1 that crept into the i8254 commit and was subsequentlyjhb2005-07-051-1/+1
| | | | | | | | | copied and pasted. I had actually tested without this change in my trees as had the other testers. Reported by: bde, Rostislav Krasny rosti dot bsd at gmail dot com Approved by: re (scottl) Pointy hat to: jhb
* MFi386: r1.221: use simple timecounter that is aware of irq0 being off.peter2005-07-011-7/+34
| | | | Approved by: re
* - Move bus dependent defines to {isa,cbus}_dmareg.h.nyan2005-05-142-5/+2
| | | | | | - Use isa/isareg.h rather than <arch>/isa/isa.h. Tested on: i386, pc98
* - Move timerreg.h to <arch>/include and split i8253 specific defines intonyan2005-05-143-101/+8
| | | | | | | | | i8253reg.h, and add some defines to control a speaker. - Move PPI related defines from i386/isa/spkr.c into ppireg.h and use them. - Move IO_{PPI,TIMER} defines into ppireg.h and timerreg.h respectively. - Use isa/isareg.h rather than <arch>/isa/isa.h. Tested on: i386, pc98
* Remove unused IO_NPX* defines.nyan2005-05-121-2/+0
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* MFi386: sync rtc code - don't setup an interrupt handler for irq0 whenpeter2005-04-151-28/+32
| | | | | the lapic timer is active. Don't enable periodic interrupts unless we are using them. Replace spl protection with a spinlock.
* Remove comments relevant only to pc98 as there are no amd64 pc98 machines.imp2005-03-161-11/+1
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* Fix a mismerge of i386 rev 1.209peter2005-03-111-1/+1
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* MFi386: Bring over John's local apic timer codepeter2005-02-281-12/+11
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* MFi386: read from RTC_INTR after writing to RTC_STATUSBpeter2005-02-081-0/+2
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* Since we are quite unlikely to ever face another platform whichphk2005-02-061-16/+13
| | | | | | | | | uses the i8237 without trying to emulate the PC architecture move the register definitions for the i8237 chip into the central include file for the chip, except for the PC98 case which is magic. Add new isa_dmatc() function which tells us as cheaply as possible if the terminal count has been reached for a given channel.
* JumboMFi386: use bitmapped IPI handler. Update elcr and default mptablepeter2005-01-212-10/+4
| | | | config handler. Tidy up various local apic initialization.
* MFi386: whitespace, copyright header, etc updatespeter2005-01-211-1/+1
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* There are no PC98 amd64 machines, so gc a few stray ifdefs.imp2005-01-111-5/+0
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* Get rid of #ifdef for legacy system. Move that into the MD code.imp2004-12-241-0/+7
| | | | Export minimal symbols to allow this to happen.
* Add new a function isa_dma_init() which returns an errno when it failsphk2004-09-151-13/+11
| | | | | | | | | and which takes a M_WAITOK/M_NOWAIT flag argument. Add compatibility isa_dmainit() macro which whines loudly if isa_dma_init() fails. Problem uncovered by: tegge
* Remove now unused #include files.phk2004-09-151-52/+0
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* Sync with i386 - Optimize intr_execute_handlers a bit etc.peter2004-08-161-21/+50
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* Sync with i386 - cosmetic fixespeter2004-08-161-1/+2
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* Catch up with i386 - remove lots of no longer used symbolic constantspeter2004-08-161-76/+1
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* Sync with i386peter2004-08-161-3/+11
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* MFi386: rev 1.213 -- fix DELAY while the debugger is active.marcel2004-07-111-12/+23
| | | | | | This also fixes the (runtime) breakage introduced in the previous commit that was the result of a botched merge. This hasn't even been compile-tested...
* MFi386: don't fake the time counter when the debugger is active.marcel2004-07-101-20/+12
| | | | | This breaks the fundamental property of DELAY(). Instead, avoid grabbing clock_lock when kdb_active is non-zero.
* Move module.h include to the same place as on i386 for diff reduction.peter2004-06-031-1/+1
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* Add missing <sys/module.h> instances which were shadowed by the nestedphk2004-06-032-0/+2
| | | | include in <sys/kernel.h>
* Fixed profiling of trap, syscall and interrupt handlers and somebde2004-05-241-2/+0
| | | | | | | | | | | | | | | ordinary functions, essentially by backing out half of rev.1.115 of amd64/exception.S. The handlers must be between certain labels for the purposes of profiling, and this was broken by scattering them in separately compiled .S files, especially for ordinary functions that ended up between the labels. Merge the files by #including them as before, except with different pathnames and better comments and organization. Changes to the scattered files are minimal -- just move the labels to the file that does the #includes. This also partly fixes profiling of IPIs -- all IPI handlers are now correctly classified as interrupt handlers, but many are still missing mcount calls.
* Adjusted FAKE_MCOUNT()s for amd64. This is needed for both ordinarybde2004-05-231-1/+1
| | | | | | | | | and high resolution profiling of interrupt handlers. The adjustments are routine once the magic stack offset 13*4 is decoded to be TF_RIP (there were originally more types of stack frames so using TF_EIP for one of them wouldn't have been much simpler). Removed garbage comments attached to some of the FAKE_MCOUNT()s.
* MFi386: numerous interrupt and acpi updatespeter2004-05-165-66/+143
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* Add a simple mini-driver for the ELCR register. Originally, the ELCRjhb2004-05-041-0/+143
| | | | | | | | | | | | | | | register controlled the trigger mode and polarity of EISA interrupts. However, it appears that most (all?) PCI systems use the ELCR to manage the trigger mode and polarity of ISA interrupts as well since ISA IRQs used to route PCI interrupts need to be level triggered with active low polarity. We check to see if the ELCR exists by sanity checking the value we get back ensuring that IRQS 0 (8254), 1 (atkbd), 2 (the link from the slave PIC), and 8 (RTC) are all clear indicating edge trigger and active high polarity. This mini-driver will be used by the atpic driver to manage the trigger and polarity of ISA IRQs. Also, the mptable parsing code will use this mini driver rather than examining the ELCR directly.
* Remove advertising clause from University of California Regent's license,imp2004-04-058-32/+0
| | | | | | per letter dated July 22, 1999. Approved by: core
* sync comment with i386's isa.c.. This removes a comment that is YEARSjmg2004-03-171-3/+1
| | | | old...
* Convert callers to the new bus_alloc_resource_any(9) API.njl2004-03-171-1/+1
| | | | | Submitted by: Mark Santcroos <marks@ripe.net> Reviewed by: imp, dfr, bde
* Don't cast a pointer to an int that isn't big enough.peter2004-02-051-1/+1
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* Diff reduction with i386peter2004-01-281-4/+12
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* Use i8259A register defines from shared header sys/dev/ic/i8259.h insteadjhb2004-01-062-53/+4
| | | | of from the amd64-specific icu.h.
* Cosmetic and/or trivial sync up with i386.peter2003-11-212-4/+5
| | | | Approved by: re (rwatson)
* MFi386: pre-register idt slots for atpic so we catch any strays withoutpeter2003-11-211-6/+22
| | | | | | blowing up. Approved by: re (scottl)
* MFi386 rev 1.207 (phk): Don't mistakenly disable the TSC when usingpeter2003-11-211-10/+10
| | | | | | statclock_disable. Approved by: re (scottl)
* Add SMP changes as should have been committed as rev 1.28peter2003-11-171-26/+7
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* Restore file accidently killed in the crossfire from the smp commit.peter2003-11-171-0/+152
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* Initial landing of SMP support for FreeBSD/amd64.peter2003-11-1710-1296/+71
| | | | | | | | | | | | | | | | - This is heavily derived from John Baldwin's apic/pci cleanup on i386. - I have completely rewritten or drastically cleaned up some other parts. (in particular, bootstrap) - This is still a WIP. It seems that there are some highly bogus bioses on nVidia nForce3-150 boards. I can't stress how broken these boards are. I have a workaround in mind, but right now the Asus SK8N is broken. The Gigabyte K8NPro (nVidia based) is also mind-numbingly hosed. - Most of my testing has been with SCHED_ULE. SCHED_4BSD works. - the apic and acpi components are 'standard'. - If you have an nVidia nForce3-150 board, you are stuck with 'device atpic' in addition, because they somehow managed to forget to connect the 8254 timer to the apic, even though its in the same silicon! ARGH! This directly violates the ACPI spec.
* Oh, how embarresing. I broke my own platform. :-)peter2003-11-171-4/+4
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* Preemptively burn a bridges. The isa timer code is likely to bepeter2003-11-141-141/+0
| | | | | replaced by the HPET timer at some point, so dont even make a release with the aquire/release_timer0 functions.
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