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* Newer versions of gcc don't support treating structures passed by valuekmacy2006-12-171-0/+1
| | | | | | | | | | as if they were really passed by reference. Specifically, the dead stores elimination pass in the GCC 4.1 optimiser breaks the non-compliant behavior on which FreeBSD relied. This change brings FreeBSD up to date by switching trap frames to being explicitly passed by reference. Reviewed by: kan Tested by: kan
* Correct 'interrupt interrupt' -> 'interrupt' in the comment.wkoszek2006-09-201-1/+1
| | | | | Requested by: jhb Approved by: cognet (mentor)
* MFi386:jhb2005-12-081-20/+2
| | | | | | | | | | | | | | | | | | | | | - Move PUSH_FRAME and POP_FRAME to asmacros.h and use PUSH_FRAME in atpic entry points. - Move PCPU_* asm macros out of the middle of the asm profiling macros. - Pass IRQ vector argument as an int rather than void * to reduce diffs with i386. - EOI the lapic in C for the lapic timer handler. - GC unused Xcpuast function. - Split IPI_STOP handling code of ipi_nmi_handler() out into a cpustop_handler() function and call it from Xcpustop rather than duplicating all the logic in assembly. - Fixup the list of symbols with interrupt frames in ddb traces. Xatpic_fastintr* have never existed on amd64, and the lapic timer handler and various IPI handlers were missing. - Use trapframe instead of intrframe for interrupt entry points (on amd64 the interrupt vector was already a separate argument, so the two frames were already identical) and GC intrframe. Submitted by: peter (3)
* Fixed profiling of trap, syscall and interrupt handlers and somebde2004-05-241-2/+0
| | | | | | | | | | | | | | | ordinary functions, essentially by backing out half of rev.1.115 of amd64/exception.S. The handlers must be between certain labels for the purposes of profiling, and this was broken by scattering them in separately compiled .S files, especially for ordinary functions that ended up between the labels. Merge the files by #including them as before, except with different pathnames and better comments and organization. Changes to the scattered files are minimal -- just move the labels to the file that does the #includes. This also partly fixes profiling of IPIs -- all IPI handlers are now correctly classified as interrupt handlers, but many are still missing mcount calls.
* Adjusted FAKE_MCOUNT()s for amd64. This is needed for both ordinarybde2004-05-231-1/+1
| | | | | | | | | and high resolution profiling of interrupt handlers. The adjustments are routine once the magic stack offset 13*4 is decoded to be TF_RIP (there were originally more types of stack frames so using TF_EIP for one of them wouldn't have been much simpler). Removed garbage comments attached to some of the FAKE_MCOUNT()s.
* MFi386: numerous interrupt and acpi updatespeter2004-05-161-2/+0
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* Remove advertising clause from University of California Regent's license,imp2004-04-051-4/+0
| | | | | | per letter dated July 22, 1999. Approved by: core
* Initial landing of SMP support for FreeBSD/amd64.peter2003-11-171-21/+22
| | | | | | | | | | | | | | | | - This is heavily derived from John Baldwin's apic/pci cleanup on i386. - I have completely rewritten or drastically cleaned up some other parts. (in particular, bootstrap) - This is still a WIP. It seems that there are some highly bogus bioses on nVidia nForce3-150 boards. I can't stress how broken these boards are. I have a workaround in mind, but right now the Asus SK8N is broken. The Gigabyte K8NPro (nVidia based) is also mind-numbingly hosed. - Most of my testing has been with SCHED_ULE. SCHED_4BSD works. - the apic and acpi components are 'standard'. - If you have an nVidia nForce3-150 board, you are stuck with 'device atpic' in addition, because they somehow managed to forget to connect the 8254 timer to the apic, even though its in the same silicon! ARGH! This directly violates the ACPI spec.
* "opt_auto_eoi.h" is not used here anymore. See atpic.c.peter2003-11-141-2/+0
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* - Move manipulation of td_intr_nesting_level out of assembly interruptjhb2003-11-121-71/+18
| | | | | | | | | | | | | | | | | | | vector stubs and into the C functions they call. - Move disabling and EOIing of interrupt sources out of PIC driver entry points and into intr_execute_handlers(). Intr_execute_handlers() only disables a source for an interrupt if it is a stray interrupt or has threaded handlers. Sources with fast handlers no longer disable (mask) the source while executing the handlers. - Move the setting of clkintr_pending into intr_execute_handlers() and set the variable for any interrupt source with a vector of 0. (Should only be true for IRQ 0.) This fixes clkintr_pending in the NO_MIXED_MODE case. - Implement lapic_eoi() and use it to implement ioapic_eoi_source(). - Rename atpic_sched_ithd() to atpic_handle_intr() since it is used to handle all atpic interrupts and not just threaded ones. Inspired by: peter's changes to amd64 in p4 (1) Requested by: bde (2)
* Add the new atpic(4) driver for the 8259A master and slave PICs. Byjhb2003-11-031-178/+77
| | | | | | | | | | | | default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
* Move ICU_* defines into icu.h.nyan2002-04-061-12/+0
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* Stage-2 commit of the critical*() code. This re-inlines cpu_critical_enter()dillon2002-04-011-2/+2
| | | | | | | | | | | | | | | | | | | | | and cpu_critical_exit() and moves associated critical prototypes into their own header file, <arch>/<arch>/critical.h, which is only included by the three MI source files that need it. Backout and re-apply improperly comitted syntactical cleanups made to files that were still under active development. Backout improperly comitted program structure changes that moved localized declarations to the top of two procedures. Partially re-apply one of the program structure changes to move 'mask' into an intermediate block rather then in three separate sub-blocks to make the code more readable. Re-integrate bug fixes that Jake made to the sparc64 code. Note: In general, developers should not gratuitously move declarations out of sub-blocks. They are where they are for reasons of structure, grouping, readability, compiler-localizability, and to avoid developer-introduced bugs similar to several found in recent years in the VFS and VM code. Reviewed by: jake
* Tab-out the backslashes in icu_vector.s to make it more readable and todillon2002-03-271-122/+122
| | | | match it up with apic_vector.s.
* Compromise for critical*()/cpu_critical*() recommit. Cleanup the interruptdillon2002-03-271-57/+164
| | | | | | | | | | | | | | | | | | | disablement assumptions in kern_fork.c by adding another API call, cpu_critical_fork_exit(). Cleanup the td_savecrit field by moving it from MI to MD. Temporarily move cpu_critical*() from <arch>/include/cpufunc.h to <arch>/<arch>/critical.c (stage-2 will clean this up). Implement interrupt deferral for i386 that allows interrupts to remain enabled inside critical sections. This also fixes an IPI interlock bug, and requires uses of icu_lock to be enclosed in a true interrupt disablement. This is the stage-1 commit. Stage-2 will occur after stage-1 has stabilized, and will move cpu_critical*() into its own header file(s) + other things. This commit may break non-i386 architectures in trivial ways. This should be temporary. Reviewed by: core Approved by: core
* revert last commit temporarily due to whining on the lists.dillon2002-02-261-202/+98
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* STAGE-1 of 3 commit - allow (but do not require) interrupts to remaindillon2002-02-261-98/+202
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | enabled in critical sections and streamline critical_enter() and critical_exit(). This commit allows an architecture to leave interrupts enabled inside critical sections if it so wishes. Architectures that do not wish to do this are not effected by this change. This commit implements the feature for the I386 architecture and provides a sysctl, debug.critical_mode, which defaults to 1 (use the feature). For now you can turn the sysctl on and off at any time in order to test the architectural changes or track down bugs. This commit is just the first stage. Some areas of the code, specifically the MACHINE_CRITICAL_ENTER #ifdef'd code, is strictly temporary and will be cleaned up in the STAGE-2 commit when the critical_*() functions are moved entirely into MD files. The following changes have been made: * critical_enter() and critical_exit() for I386 now simply increment and decrement curthread->td_critnest. They no longer disable hard interrupts. When critical_exit() decrements the counter to 0 it effectively calls a routine to deal with whatever interrupts were deferred during the time the code was operating in a critical section. Other architectures are unaffected. * fork_exit() has been conditionalized to remove MD assumptions for the new code. Old code will still use the old MD assumptions in regards to hard interrupt disablement. In STAGE-2 this will be turned into a subroutine call into MD code rather then hardcoded in MI code. The new code places the burden of entering the critical section in the trampoline code where it belongs. * I386: interrupts are now enabled while we are in a critical section. The interrupt vector code has been adjusted to deal with the fact. If it detects that we are in a critical section it currently defers the interrupt by adding the appropriate bit to an interrupt mask. * In order to accomplish the deferral, icu_lock is required. This is i386-specific. Thus icu_lock can only be obtained by mainline i386 code while interrupts are hard disabled. This change has been made. * Because interrupts may or may not be hard disabled during a context switch, cpu_switch() can no longer simply assume that PSL_I will be in a consistent state. Therefore, it now saves and restores eflags. * FAST INTERRUPT PROVISION. Fast interrupts are currently deferred. The intention is to eventually allow them to operate either while we are in a critical section or, if we are able to restrict the use of sched_lock, while we are not holding the sched_lock. * ICU and APIC vector assembly for I386 cleaned up. The ICU code has been cleaned up to match the APIC code in regards to format and macro availability. Additionally, the code has been adjusted to deal with deferred interrupts. * Deferred interrupts use a per-cpu boolean int_pending, and masks ipending, spending, and fpending. Being per-cpu variables it is not currently necessary to lock; bus cycles modifying them. Note that the same mechanism will enable preemption to be incorporated as a true software interrupt without having to further hack up the critical nesting code. * Note: the old critical_enter() code in kern/kern_switch.c is currently #ifdef to be compatible with both the old and new methodology. In STAGE-2 it will be moved entirely to MD code. Performance issues: One of the purposes of this commit is to enhance critical section performance, specifically to greatly reduce bus overhead to allow the critical section code to be used to protect per-cpu caches. These caches, such as Jeff's slab allocator work, can potentially operate very quickly making the effective savings of the new critical section code's performance very significant. The second purpose of this commit is to allow architectures to enable certain interrupts while in a critical section. Specifically, the intention is to eventually allow certain FAST interrupts to operate rather then defer. The third purpose of this commit is to begin to clean up the critical_enter()/critical_exit()/cpu_critical_enter()/ cpu_critical_exit() API which currently has serious cross pollution in MI code (in fork_exit() and ast() for example). The fourth purpose of this commit is to provide a framework that allows kernel-preempting software interrupts to be implemented cleanly. This is currently used for two forward interrupts in I386. Other architectures will have the choice of using this infrastructure or building the functionality directly into critical_enter()/ critical_exit(). Finally, this commit is designed to greatly improve the flexibility of various architectures to manage critical section handling, software interrupts, preemption, and other highly integrated architecture-specific details.
* Change the preemption code for software interrupt thread schedules andjhb2002-01-051-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mutex releases to not require flags for the cases when preemption is not allowed: The purpose of the MTX_NOSWITCH and SWI_NOSWITCH flags is to prevent switching to a higher priority thread on mutex releease and swi schedule, respectively when that switch is not safe. Now that the critical section API maintains a per-thread nesting count, the kernel can easily check whether or not it should switch without relying on flags from the programmer. This fixes a few bugs in that all current callers of swi_sched() used SWI_NOSWITCH, when in fact, only the ones called from fast interrupt handlers and the swi_sched of softclock needed this flag. Note that to ensure that swi_sched()'s in clock and fast interrupt handlers do not switch, these handlers have to be explicitly wrapped in critical_enter/exit pairs. Presently, just wrapping the handlers is sufficient, but in the future with the fully preemptive kernel, the interrupt must be EOI'd before critical_exit() is called. (critical_exit() can switch due to a deferred preemption in a fully preemptive kernel.) I've tested the changes to the interrupt code on i386 and alpha. I have not tested ia64, but the interrupt code is almost identical to the alpha code, so I expect it will work fine. PowerPC and ARM do not yet have interrupt code in the tree so they shouldn't be broken. Sparc64 is broken, but that's been ok'd by jake and tmm who will be fixing the interrupt code for sparc64 shortly. Reviewed by: peter Tested on: i386, alpha
* Remove the Xresume* labels from the i386 interrupt handlers; theiedowse2001-10-091-1/+0
| | | | | | | | | | | | | | | | | | code in ipl.s and icu_ipl.s that used them was removed when the interrupt thread system was committed. Debuggers also knew about Xresume* because these labels hide the real names of the interrupt handlers (Xintr*), and debuggers need to special-case interrupt handlers to get the interrupt frame. Both gdb and ddb will now use the Xintr* and Xfastintr* symbols to detect interrupt frames. Fast interrupt frames were never identified correctly before, so this fixes the problem of the running stack frame getting lost in a ddb or gdb trace generated from a fast interrupt - e.g. when debugging a simple infinite loop in the kernel using a serial console, the frame containing the loop would never appear in a gdb or ddb trace. Reviewed by: jhb, bde
* KSE Milestone 2julian2001-09-121-6/+6
| | | | | | | | | | | | | | Note ALL MODULES MUST BE RECOMPILED make the kernel aware that there are smaller units of scheduling than the process. (but only allow one thread per process at this time). This is functionally equivalent to teh previousl -current except that there is a thread associated with each process. Sorry john! (your next MFC will be a doosie!) Reviewed by: peter@freebsd.org, dillon@freebsd.org X-MFC after: ha ha ha ha
* Don't enable interrupts before calling sched_ithd for threaded interrupts.jhb2001-03-051-1/+0
| | | | Tested by: obrien
* Remove the leading underscore from all symbols defined in x86 asmjake2001-02-251-10/+10
| | | | | | | | | | | and used in C or vice versa. The elf compiler uses the same names for both. Remove asnames.h with great prejudice; it has served its purpose. Note that this does not affect the ability to generate an aout kernel due to gcc's -mno-underscores option. moral support from: peter, jhb
* Make intr_nesting_level per-process, rather than per-cpu. Setupjake2001-01-211-2/+6
| | | | | | | | interrupt threads to run with it always >= 1, so that malloc can detect M_WAITOK from "interrupt" context. This is also necessary in order to context switch from sched_ithd() directly. Reviewed By: peter
* Use %fs to access per-cpu variables in uni-processor kernels the samejake2001-01-061-0/+2
| | | | | | | | | | | | | | | | | as multi-processor kernels. The old way made it difficult for kernel modules to be portable between uni-processor and multi-processor kernels. It is no longer necessary to jump through hoops. - always load %fs with the private segment on entry to the kernel - change the type of the self referntial pointer from struct privatespace to struct globaldata - make the globaldata symbol have value 0 in all cases, so the symbols in globals.s are always offsets, not aliases for fields in globaldata - define the globaldata space used for uniprocessor kernels in C, rather than assembler - change the assmebly language accessors to use %fs, add a macro PCPU_ADDR(member, reg), which loads the register reg with the address of the per-cpu variable member
* Introduce a new potientially cleaner interface for accessing per-cpujake2000-12-131-2/+2
| | | | | | | | | | | variables from i386 assembly language. The syntax is PCPU(member) where member is the capitalized name of the per-cpu variable, without the gd_ prefix. Example: movl %eax,PCPU(CURPROC). The capitalization is due to using the offsets generated by genassym rather than the symbols provided by linking with globals.o. asmacros.h is the wrong place for this but it seemed as good a place as any for now. The old implementation in asnames.h has not been removed because it is still used to de-mangle the symbols used by the C variables for the UP case.
* Cleanup some leftover lint from the old interrupt system.peter2000-12-041-31/+0
| | | | | | | | Also, while here, run up to 32 interrupt sources on APIC systems. Normalize INTREN/INTRDIS so they are the same on both UP and SMP systems rather than sometimes a macro, and sometimes a function. Reviewed by: jhb, jakeb
* Change doreti to take a trapframe instead of an intrframe.jake2000-12-011-2/+2
| | | | | | Remove associated pushes of dummy units to convert frame. Reviewed by: jhb
* - Change fast interrupts on x86 to push a full interrupt frame and tojhb2000-10-061-39/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | return through doreti to handle ast's. This is necessary for the clock interrupts to work properly. - Change the clock interrupts on the x86 to be fast instead of threaded. This is needed because both hardclock() and statclock() need to run in the context of the current process, not in a separate thread context. - Kill the prevproc hack as it is no longer needed. - We really need Giant when we call psignal(), but we don't want to block during the clock interrupt. Instead, use two p_flag's in the proc struct to mark the current process as having a pending SIGVTALRM or a SIGPROF and let them be delivered during ast() when hardclock() has finished running. - Remove CLKF_BASEPRI, which was #ifdef'd out on the x86 anyways. It was broken on the x86 if it was turned on since cpl is gone. It's only use was to bogusly run softclock() directly during hardclock() rather than scheduling an SWI. - Remove the COM_LOCK simplelock and replace it with a clock_lock spin mutex. Since the spin mutex already handles disabling/restoring interrupts appropriately, this also lets us axe all the *_intr() fu. - Back out the hacks in the APIC_IO x86 cpu_initclocks() code to use temporary fast interrupts for the APIC trial. - Add two new process flags P_ALRMPEND and P_PROFPEND to mark the pending signals in hardclock() that are to be delivered in ast(). Submitted by: jakeb (making statclock safe in a fast interrupt) Submitted by: cp (concept of delaying signals until ast())
* - Heavyweight interrupt threads on the alpha for device I/O interrupts.jhb2000-10-051-13/+0
| | | | | | | | | | | - Make softinterrupts (SWI's) almost completely MI, and divorce them completely from the x86 hardware interrupt code. - The ihandlers array is now gone. Instead, there is a MI shandlers array that just contains SWI handlers. - Most of the former machine/ipl.h files have moved to a new sys/ipl.h. - Stub out all the spl*() functions on all architectures. Submitted by: dfr
* Major update to the way synchronization is done in the kernel. Highlightsjasone2000-09-071-43/+49
| | | | | | | | | | | | | | | include: * Mutual exclusion is used instead of spl*(). See mutex(9). (Note: The alpha port is still in transition and currently uses both.) * Per-CPU idle processes. * Interrupts are run in their own separate kernel threads and can be preempted (i386 only). Partially contributed by: BSDi (BSD/OS) Submissions by (at least): cp, dfr, dillon, grog, jake, jhb, sheldonh
* Pack the SWI bits to save some time and space.bde2000-05-311-6/+2
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* Add SWI_TQ_MASK to imask definition.dfr2000-05-291-1/+1
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* 1. `movl' is for use with 32-bit operands. Do NOT use it with 16-bitobrien2000-05-101-9/+9
| | | | | | | operands. `movw' could be used, but instead let the assembler decide the right instruction to use. 2. AT&T asm syntax requires a leading '*' in front of the operand for indirect calls and jumps.
* $Id$ -> $FreeBSD$peter1999-08-281-1/+1
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* Go back to the old (icu.s rev.1.7 1993) way of keeping the AST-pendingbde1999-07-101-3/+3
| | | | | | | bit separate from ipending, since this is simpler and/or necessary for SMP and may even be better for UP. Reviewed by: alc, luoqi, tegge
* Fixed glitches (jumps) of about 1/HZ seconds for the i8254 timecounter.bde1999-05-281-18/+20
| | | | | | | | | | | | | | | | The old version only worked right when the time was read strictly more often than every 1/HZ seconds, but we only guarantee reading it every (1/HZ + epsilon) seconds. Part of rev.1.126-1.127 attempted to fix this but didn't succeed. Detect counter rollover using the heuristic from the old version of microtime() with additional complications for supporting calls from fast interrupt handlers. This works provided i8254 interrupts are not delayed by more than 1/(2*HZ) seconds. This needs more comments, and cleanups for the SMP case, and more testing of the SMP case before it is merged into RELENG_3. Tested by: jhay
* Enable vmspace sharing on SMP. Major changes are,luoqi1999-04-281-5/+10
| | | | | | | | | | | | | | | | | - %fs register is added to trapframe and saved/restored upon kernel entry/exit. - Per-cpu pages are no longer mapped at the same virtual address. - Each cpu now has a separate gdt selector table. A new segment selector is added to point to per-cpu pages, per-cpu global variables are now accessed through this new selector (%fs). The selectors in gdt table are rearranged for cache line optimization. - fask_vfork is now on as default for both UP and SMP. - Some aio code cleanup. Reviewed by: Alan Cox <alc@cs.rice.edu> John Dyson <dyson@iquest.net> Julian Elischer <julian@whistel.com> Bruce Evans <bde@zeta.org.au> David Greenman <dg@root.com>
* Generate intrnames[] dynamically. This should be new-bus friendly.bde1999-04-141-34/+1
| | | | Old version reviewed by: se
* Register tty software interrupt handlers at run time using register_swi()bde1998-08-111-2/+2
| | | | | | | instead of at compile time using ifdefs. Use _swi_null instead of dummycamisr. CAM and dpt should call register_swi() instead of hacking on ihandlers[] directly.
* Implemented dynamic registration of software interrupt handlers. Notbde1998-08-111-6/+5
| | | | | | used yet. Use dummy SWI handlers to avoid some checks for null pointers.
* Addition of splsoftvm and a VM SWI to handle bus dma related callbacks.gibbs1998-01-151-3/+3
| | | | This SWI may be useful for other, defered, VM tasks.
* Fix a serious bug I introduced while adding in support for CAM interrupts.gibbs1997-09-281-5/+7
| | | | | | | | | | | | It seems I didn't count my 0's properly when adding the new masks into icu_vector.s pushing SWI_AST_MASK off the end of the array and screwing up the indexing for SWI_CLOCK_MASK. Fix the bug icu_vector.s and also reformat the code in both icu_vector.s and apic_vector.s so that it will be much harder to make the same mistake in the future. Submitted by: Bruce Evans <bde@zeta.org.au>
* aha1542.c aic6360.c cy.c fd.c ft.cgibbs1997-09-211-4/+6
| | | | | | | | | | | | if_ie.c if_wl.c if_zp.c isa.c isa_device.h labpc.c mcd.c ncr5380.c scd.c seagate.c si.c sio.c tw.c ultra14f.c wcd.c wd.c: Update for changes in the callout interface. apic_vector.s icu_vector.s ipl.s ipl_funcs.c: Add CAM software/hardware interrupt support.
* Change an assemble-time divide into a shift. Under binutils-2.8 gas in elfpeter1997-09-081-2/+2
| | | | | | mode, the slash is a comment leader, while under non-elf it is a divide symbol (what a concept! :-). Theoretically, #APP/#NO_APP can change this but that doesn't seem to mesh too well with macros and line continuation.
* Removed the defunct GET_MPLOCK/REL_MPLOCK macros.fsmp1997-07-241-5/+1
| | | | | These are no-ops for UP, and should have been removed when vector.s was split into UP and SMP subsets.
* The SWI_NET_MASK and SWI_TTY_MASK handlers are now back adjacent to thepeter1997-05-311-3/+5
| | | | | | | | top of the hardware interrupt handlers. Apparently this is slightly faster with the bit scanning instruction that looks these up - this set of changes reverts the original change. Reviewed by: bde
* Split vector.s into UP and SMP specific files:fsmp1997-05-261-0/+249
- vector.s <- stub called by i386/exception.s - icu_vector.s <- UP - apic_vector.s <- SMP Split icu.s into UP and SMP specific files: - ipl.s <- stub called by i386/exception.s (formerly icu.s) - icu_ipl.s <- UP - apic_ipl.s <- SMP This was done in preparation for massive changes to the SMP INTerrupt mechanisms. More fine tuning, such as merging ipl.s into exception.s, may be appropriate.
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