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* Re-add user_dbreg_trap() for debug register supportpeter2004-01-291-0/+1
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* We can simplify a lot of things now that we don't have to worry aboutpeter2004-01-281-1/+0
| | | | hardware bugs on external 386 cpus and now that we can depend on SSE.
* Add dbreg struct definitions for /proc/*/dbregs and a place to store thepeter2004-01-282-3/+23
| | | | registers in the pcb
* Re-add debug register functionspeter2004-01-281-2/+129
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* MFi386: mp_topology().peter2004-01-281-0/+1
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* MFi386: add THERMTRIP msr valuespeter2004-01-281-0/+3
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* remove elan_mmcr, I'm not sure I understand what it did here in thephk2004-01-171-1/+0
| | | | first place.
* Provide sysarch(2) prototypes in the MD sysarch.h headers. While I'mnectar2004-01-091-1/+2
| | | | | | | | | | at it, use the ANSI C generic pointer type for the second argument, thus matching the documentation. Remove the now extraneous (and now conflicting) function declarations in various libc sources. Remove now unnecessary casts. Reviewed by: bde
* Remove `static' prototype from header file.nectar2004-01-061-1/+0
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* GC the unused <machine/kse.h> file.peter2003-12-241-42/+0
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* Since we have additional kernel virtual address space, allow the bufferalc2003-12-201-1/+1
| | | | cache to grow to 400M bytes.
* MFi386: remove APIC_IRQ* defines that are no longer used.peter2003-12-111-32/+0
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* Add just enough of i386/include/pcvt_ioctl.h to amd64/include/pcvt_ioctl.hobrien2003-12-101-0/+109
| | | | | | such that 'ispcvt' can build. Unforunately 'ispcvt' is needed in order for /etc/rc.d/syscons to run. This fixes the bug where I could not get my keymap effective at boot.
* Increase VM_KMEM_SIZE_MAX from 200MB to 400MB.alc2003-12-071-1/+1
| | | | Discussed with: peter
* Reconfigure the runq macros to use the 64 bit ffs/bsf routines insteadpeter2003-12-061-5/+5
| | | | | | | of doing a loop and taking two 32 bit passes at the runqueue bits. All the 64 bit platforms should probably do this since there are 64 run queues. Approved by: re (scottl)
* Add 64 bit bsf*/ffs* routines. Have the ffs() inline use gcc's builtinpeter2003-12-061-1/+40
| | | | because it uses the better cmove instructions to avoid branches.
* Kill the ASM versions of the mtx_lock_spin and friends. They were neverpeter2003-12-061-31/+0
| | | | | | | used on amd64, and were actually totally broken. They had the wrong calling conventions. I believe the i386 versions are going away too. Approved by: re (scottl)
* Revert some amd64 changes that cached curthread and converge back to thepeter2003-12-061-8/+2
| | | | | | | | i386 version. The curthread special case in pcpu.h solves my complaint about the verbose macro expansion in this case. Note that the i386 version still has some OBE comments, I didn't re-add them back again. Approved by: re (scottl)
* Cosmetic and/or trivial sync up with i386.peter2003-11-219-35/+36
| | | | Approved by: re (rwatson)
* Argh! Followup to previous commit. I checked in the patch with anpeter2003-11-201-1/+1
| | | | unintended local change. Change Xurthread back to curthread.
* Provide a streamlined '#define curthread __curthread()' for amd64 to avoidpeter2003-11-201-0/+10
| | | | | | | | | | | | the compiler having to parse and optimize the PCPU_GET(curthread) so often. __curthread() is an inline optimized version of PCPU_GET(curthread) that knows that pc_curthread is at offset zero in the pcpu struct. Add a CTASSERT() to catch any possible changes to this. This accounts for just over a 1% wall clock speedup for total kernel compile/link time, and 20% compile time speedup on some specific files depending on which compile options are used. Approved by: re (jhb)
* Initial landing of SMP support for FreeBSD/amd64.peter2003-11-1711-5/+91
| | | | | | | | | | | | | | | | - This is heavily derived from John Baldwin's apic/pci cleanup on i386. - I have completely rewritten or drastically cleaned up some other parts. (in particular, bootstrap) - This is still a WIP. It seems that there are some highly bogus bioses on nVidia nForce3-150 boards. I can't stress how broken these boards are. I have a workaround in mind, but right now the Asus SK8N is broken. The Gigabyte K8NPro (nVidia based) is also mind-numbingly hosed. - Most of my testing has been with SCHED_ULE. SCHED_4BSD works. - the apic and acpi components are 'standard'. - If you have an nVidia nForce3-150 board, you are stuck with 'device atpic' in addition, because they somehow managed to forget to connect the 8254 timer to the apic, even though its in the same silicon! ARGH! This directly violates the ACPI spec.
* Fixed pedantic warnings for statement-expressions using __extension__bde2003-11-171-4/+4
| | | | | and by not using a statement-expression for the non-expression __PCPU_SET().
* Fixed a pedantic syntax error (a stray semicolon at the end ofbde2003-11-171-1/+1
| | | | PCPU_MD_FIELDS).
* - Modify alpha's sf_buf implementation to use the direct virtual-to-alc2003-11-161-0/+57
| | | | | | | | | physical mapping. - Move the sf_buf API to its own header file; make struct sf_buf's definition machine dependent. In this commit, we remove an unnecessary field from struct sf_buf on the alpha, amd64, and ia64. Ultimately, we may eliminate struct sf_buf on those architecures except as an opaque pointer that references a vm page.
* Add the pc_acpi_id PCPU member. The new acpi_cpu driver uses this tonjl2003-11-151-1/+2
| | | | dereference the softc.
* Preemptively burn a bridges. The isa timer code is likely to bepeter2003-11-141-4/+0
| | | | | replaced by the HPET timer at some point, so dont even make a release with the aquire/release_timer0 functions.
* Convert a couple of pointers to integers for source compatability withpeter2003-11-141-4/+4
| | | | amd64.
* Whitespace nit (sorry, couldn't help it)peter2003-11-141-1/+1
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* Shuffle the APIC interrupt vectors around a bit:jhb2003-11-142-13/+15
| | | | | | | | | | | | | | | - Move the IPI and local APIC interrupt vectors up into the 0xf0 - 0xff range. The pmap lazyfix IPI was reordered down next to the TLB shootdowns to avoid conflicting with the spurious interrupt vector. - Move the base of APIC interrupts up 16 so that the first 16 APIC interrupts do not overlap the vectors used by the ATPIC. - Remove bogus interrupt vector reservations for LINT[01]. - Now that 0xc0 - 0xef are available, use them for device interrupts. This increases the number of APIC device interrupts to 191. - Increase the system-wide number of global interrupts to 191 to catch up to more APIC interrupts. Requested by: peter (2)
* Fix a typo.jhb2003-11-131-1/+1
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* - Move manipulation of td_intr_nesting_level out of assembly interruptjhb2003-11-121-0/+1
| | | | | | | | | | | | | | | | | | | vector stubs and into the C functions they call. - Move disabling and EOIing of interrupt sources out of PIC driver entry points and into intr_execute_handlers(). Intr_execute_handlers() only disables a source for an interrupt if it is a stray interrupt or has threaded handlers. Sources with fast handlers no longer disable (mask) the source while executing the handlers. - Move the setting of clkintr_pending into intr_execute_handlers() and set the variable for any interrupt source with a vector of 0. (Should only be true for IRQ 0.) This fixes clkintr_pending in the NO_MIXED_MODE case. - Implement lapic_eoi() and use it to implement ioapic_eoi_source(). - Rename atpic_sched_ithd() to atpic_handle_intr() since it is used to handle all atpic interrupts and not just threaded ones. Inspired by: peter's changes to amd64 in p4 (1) Requested by: bde (2)
* Update the graffiti.peter2003-11-089-3/+13
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* Switch from having a fpu "device" to something that is more like thepeter2003-11-081-1/+1
| | | | integrated part of the cpu core that it is.
* The great s/npx/fpu/gipeter2003-11-083-20/+17
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* Rename npx* to fpu*. I haven't done the flags/function names yet.peter2003-11-085-122/+7
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* Document the lockfunc and lockfuncarg arguments to bus_dma_tag_create() inscottl2003-11-071-0/+4
| | | | the busdma headers.
* Add the MP Table APIC enumerator. This code uses the BIOS MP Table tojhb2003-11-031-2764/+45
| | | | | enumerate I/O APICs as well as local APICs. It also provides Host-PCI and PCI-PCI bridge drivers to use the MP Table to route PCI interrupts.
* New APIC support code:jhb2003-11-032-7/+186
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - The apic interrupt entry points have been rewritten so that each entry point can serve 32 different vectors. When the entry is executed, it uses one of the 32-bit ISR registers to determine which vector in its assigned range was triggered. Thus, the apic code can support 159 different interrupt vectors with only 5 entry points. - We now always to disable the local APIC to work around an errata in certain PPros and then re-enable it again if we decide to use the APICs to route interrupts. - We no longer map IO APICs or local APICs using special page table entries. Instead, we just use pmap_mapdev(). We also no longer export the virtual address of the local APIC as a global symbol to the rest of the system, but only in local_apic.c. To aid this, the APIC ID of each CPU is exported as a per-CPU variable. - Interrupt sources are provided for each intpin on each IO APIC. Currently, each source is given a unique interrupt vector meaning that PCI interrupts are not shared on most machines with an I/O APIC. That mapping for interrupt sources to interrupt vectors is up to the APIC enumerator driver however. - We no longer probe to see if we need to use mixed mode to route IRQ 0, instead we always use mixed mode to route IRQ 0 for now. This can be disabled via the 'NO_MIXED_MODE' kernel option. - The npx(4) driver now always probes to see if a built-in FPU is present since this test can now be performed with the new APIC code. However, an SMP kernel will panic if there is more than one CPU and a built-in FPU is not found. - PCI interrupts are now properly routed when using APICs to route interrupts, so remove the hack to psuedo-route interrupts when the intpin register was read. - The apic.h header was moved to apicreg.h and a new apicvar.h header that declares the APIs used by the new APIC code was added.
* New device interrupt code. This defines an interrupt source abstractionjhb2003-11-031-0/+91
| | | | | | | | | | | | | | | | | | that provides methods via a PIC driver to do things like mask a source, unmask a source, enable it when the first interrupt handler is added, etc. The interrupt code provides a table of interrupt sources indexed by IRQ numbers, or vectors. These vectors are what new-bus uses for its IRQ resources and for bus_setup_intr()/bus_teardown_intr(). The interrupt code then maps that vector a given interrupt source object. When an interrupt comes in, the low-level interrupt code looks up the interrupt source for the source that triggered the interrupt and hands it off to this code to execute the appropriate handlers. By having an interrupt source abstraction, this allows us to have different types of interrupt source providers within the shared IRQ address space. For example, IRQ 0 may map to pin 0 of the master 8259A PIC, IRQs 1 through 60 may map to pins on various I/O APICs, and IRQs 120 through 128 may map to MSI interrupts for various PCI devices.
* Always export r_gdt and r_idt and give them extern declarations injhb2003-10-301-3/+0
| | | | machine/segments.h.
* A few whitespace and comment tweaks.jhb2003-10-241-6/+3
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* Add __va_copy and make it always visible, in spite of the __ISO_C_VISIBLEpeter2003-10-241-1/+4
| | | | | | | | | setting. Make va_copy be an alias if __ISO_C_VISIBLE >= 1999. Why? more than a few ports have an autoconf that looks for __va_copy because it is available on glibc. It is critical that we use it if at all possible on amd64. It generally isn't a problem for i386 and its ilk because autoconf driven code tends to fall back to an assignment.
* Use a more robust API altogether for the amd64_get_fsbase() etc functions.peter2003-10-231-4/+4
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* Renumber the sysarch vectors for amd64 specific syscalls so that I canpeter2003-10-231-6/+5
| | | | | | | implement i386 compat numbers where it makes sense. This would save a syscall translation layer. Yes, this breaks the abi slightly again, but fortunately its just a recompile rather than tweaking the source. I will be fixing the libc stubs while I'm here.
* Pull the tier-2 card one last time and break the get/setcontext andpeter2003-10-153-4/+7
| | | | | | | | | | | | | | | | | | | | | | sigreturn() ABI and the signal context on the stack. Make the trapframe (and its shadows in the ucontext and sigframe etc) 8 bytes larger in order to preserve 16 byte stack alignment for the following C code calls. I could have done some padding after the trapframe was saved, but some of the C code still expects an argument of 'struct trapframe'. Anyway, this gives me a spare field that can be used to store things like 'partial trapframe' status or something else in the future. The runtime impact is fairly small, *except* for threaded apps and things that decode contexts and the signal stack (eg: cvsup binary). Signal delivery isn't too badly affected because the kernel generates the sigframe that sigreturn uses after the handler has been called. The size of mcontext_t and struct sigframe hasn't changed. Only the last few fields (sc_eip etc) got moved a little and I eliminated a spare field. mc_len/sc_len did change location though so the sanity checks there will still trap it.
* Move pmap_resident_count() from the MD pmap.h to the MI pmap.h.bms2003-10-061-1/+0
| | | | | | | | Add a definition of pmap_wired_count(). Add a definition of vmspace_wired_count(). Reviewed by: truckman Discussed with: peter
* Commit Bosko's patch to clean up the PSE/PG_G initialization to andpeter2003-10-011-8/+2
| | | | | | | | | | | | | | | | | | | | | avoid problems with some Pentium 4 cpus and some older PPro/Pentium2 cpus. There are several problems, some documented in Intel errata. This patch: 1) moves the kernel to the second page in the PSE case. There is an errata that says that you Must Not point a 4MB page at physical address zero on older cpus. We avoided bugs here due to sheer luck. 2) sets up PSE page tables right from the start in locore, rather than trying to switch from 4K to 4M (or 2M) pages part way through the boot sequence at the same time that we're messing with PG_G. For some reason, the pmap work over the last 18 months seems to tickle the problems, and the PAE infrastructure changes disturb the cpu bugs even more. A couple of people have reported a problem with APM bios calls during boot. I'll work with people to get this resolved. Obtained from: bmilekic
* Use __register_t instead of register_t, otherwise <sys/types.h> is apeter2003-10-011-24/+24
| | | | prerequisite for <ucontext.h> on amd64. Oops.
* MFi386: BURN_BRIDGES around timer0 functionspeter2003-09-301-1/+3
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