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* Initial PG_NX support (no-execute page bit)peter2004-06-081-0/+16
| | | | | | | | - export the rest of the cpu features (and amd's features). - turn on EFER_NXE, depending on the NX amd feature bit - reorg the identcpu stuff a bit in order to stop treating the amd features as second class features (since it is now a primary feature bit set) and make it easier to export.
* Remove advertising clause from University of California Regent's license,imp2004-04-051-4/+0
| | | | | | per letter dated July 22, 1999. Approved by: core
* MFi386: add THERMTRIP msr valuespeter2004-01-281-0/+3
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* Cosmetic and/or trivial sync up with i386.peter2003-11-211-3/+3
| | | | Approved by: re (rwatson)
* The great s/npx/fpu/gipeter2003-11-081-5/+2
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* MFi386 rev 1.25 by jhb: add new MSR's and some missing older ones andpeter2003-09-221-3/+25
| | | | APICBASE MSR constants.
* Commit MD parts of a loosely functional AMD64 port. This is based onpeter2003-05-011-79/+38
| | | | | | | | | | | | | | | | | | | | | | a heavily stripped down FreeBSD/i386 (brutally stripped down actually) to attempt to get a stable base to start from. There is a lot missing still. Worth noting: - The kernel runs at 1GB in order to cheat with the pmap code. pmap uses a variation of the PAE code in order to avoid having to worry about 4 levels of page tables yet. - It boots in 64 bit "long mode" with a tiny trampoline embedded in the i386 loader. This simplifies locore.s greatly. - There are still quite a few fragments of i386-specific code that have not been translated yet, and some that I cheated and wrote dumb C versions of (bcopy etc). - It has both int 0x80 for syscalls (but using registers for argument passing, as is native on the amd64 ABI), and the 'syscall' instruction for syscalls. int 0x80 preserves all registers, 'syscall' does not. - I have tried to minimize looking at the NetBSD code, except in a couple of places (eg: to find which register they use to replace the trashed %rcx register in the syscall instruction). As a result, there is not a lot of similarity. I did look at NetBSD a few times while debugging to get some ideas about what I might have done wrong in my first attempt.
* Bah, add in a missing space char I noticed when MFC'ing this.jhb2003-01-221-1/+1
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* - Fix the name of the hyperthreading cpuid feature flag to be HTT insteadjhb2003-01-081-1/+9
| | | | | of HHT. - Document fields returned in %ebx by a cpuid with %eax of 1.
* Add additional cpuid feature flags and put into a canonical format.mp2002-06-221-18/+33
| | | | MFC after: 1 week
* Activate SSE/SIMD. This is the extra context switching support thatpeter2001-07-121-0/+2
| | | | | | | | | | | | | | | we are required to do if we let user processes use the extra 128 bit registers etc. This is the base part of the diff I got from: http://www.issei.org/issei/FreeBSD/sse.html I believe this is by: Mr. SUZUKI Issei <issei@issei.org> SMP support apparently by: Takekazu KATO <kato@chino.it.okayama-u.ac.jp> Test code by: NAKAMURA Kazushi <kaz@kobe1995.net>, see http://kobe1995.net/~kaz/FreeBSD/SSE.en.html I have fixed a couple of style(9) deviations. I have some followup commits to fix a couple of non-style things.
* Add the CR4 values for P3 SIMD enabling support. FXSR tells the cpu thatpeter1999-09-101-0/+2
| | | | | | | | the OS does FXSAVE/FXRESTOR instructions (fast FPU save/restore) during context switching and also enables SIMD since this enables saving the extra CPU context that isn't saved with normal FPU regs. The other enables the SIMD instructions to use exception 16 (FPU) error reporting. Note, this doesn't turn on SIMD, just defines the bits.
* $Id$ -> $FreeBSD$peter1999-08-281-1/+1
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* Add defines for the P6 model-specific registers.msmith1999-04-071-1/+58
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* - Implement enabling write allocate on AMD K5/K6/K6-2 cpus.kato1998-10-061-1/+6
| | | | | | | | | | | | The code was originaly contributed by Kelly Yancey <kbyanc@freedomnet.com> in PR i386/6269 and revised by Akio Morita <amorita@meadow.scphys.kyoto-u.ac.jp> and me. Test was performed by Akio Morita and Toshiomi Moriki <moriki@db.is.kyushu-u.ac.jp>. - Fix stylistic bug in identcpu.c. - Update copyright in initcpu.c - Fix typo in LINT. PR: 6269 and 6270
* Defined CCR6 and CCR7 (configuration registers of M2 CPU.)kato1998-03-041-1/+5
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* Enabled the FPU emilaute bit define: CR0_EMfsmp1997-07-211-3/+1
| | | | Reviewed by: Bruce Evans <bde@zeta.org.au>
* Improved CPU identification and initialization routines. Thiskato1997-03-221-44/+172
| | | | | | | | | | | | | supports All Cyrix CPUs, IBM Blue Lightning CPU and NexGen (now AMD) Nx586 CPU, and initialize special registers of Cyrix CPU and msr of IBM Blue Lightning CPU. If revision of Cyrix 6x86 CPU < 2.7, CPU cache is enabled in write-through mode. This can be disabled by kernel configuration options. Reviewed by: Bruce Evans <bde@freebsd.org> and Jordan K. Hubbard <jkh@freebsd.org>
* Back out part 1 of the MCFH that changed $Id$ to $FreeBSD$. We are notpeter1997-02-221-1/+1
| | | | ready for it yet.
* Make the long-awaited change from $Id$ to $FreeBSD$jkh1997-01-141-1/+1
| | | | | | | | This will make a number of things easier in the future, as well as (finally!) avoiding the Id-smashing problem which has plagued developers for so long. Boy, I'm glad we're not using sup anymore. This update would have been insane otherwise.
* Support the PG_G flag on Pentium-Pro processors. This prettydyson1996-11-111-1/+34
| | | | | much eliminates the unnecessary unmapping of the kernel during context switches and during invtlb...
* Added missing CR0_NW define for Cyrix 486DLC support. It's still notsos1996-06-031-1/+3
| | | | | | stable on my hardware, but its better... *sigh* Obtained from: NetBSD
* Fix a bunch of spelling errors in the comment fields ofmpp1996-01-301-3/+3
| | | | a bunch of system include files.
* Remove trailing whitespace.rgrimes1995-05-301-2/+2
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* Enable define of CR0_AM to prepare for implementing alignment checking.bde1995-01-141-7/+3
| | | | Uniformize idempotency ifdef.
* Improved some comments.dg1994-09-041-2/+2
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* Detect if we're running on a Cyrix 486DLC and enable automatic cachepst1994-09-041-1/+54
| | | | | | | | | negation whenever we access memory between 640k and 1M. Original code from NetBSD 1.0-BETA. The exact origins are unclear but Theo de Raadt, Charles, and Michael V. may have contributed to it. Submitted by: pst
* Made all header files idempotent and moved incorrect common data fromwollman1993-11-071-1/+5
| | | | | headers into a related source file. Added cons.h as first step towards moving i386/i386/cons.h to machine/cons.h where it belongs.
* Removed all patch kit headers, sccsid and rcsid strings, put $Id$ in, somergrimes1993-10-161-9/+2
| | | | minor cleanup. Added $Id$ to files that did not have any version info, etc
* Initial import, 0.1 + pk 0.2.4-B1rgrimes1993-06-121-0/+67
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