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* Add basic amd64 support for VIA Nano processors.jkim2009-01-121-0/+36
* Add Centaur/IDT/VIA vendor ID for Nano family, which has long mode support.jkim2009-01-051-0/+1
* Add more CPUID bits from AMD CPUID Specification Rev. 2.28.jkim2008-12-121-0/+8
* Introduce cpu_vendor_id and replace a lot of strcmp(cpu_vendor, "...").jkim2008-11-261-2/+2
* Simplify AMD64_CPU_MODEL() and AMD64_CPU_FAMILY() macros as the base familyjkim2008-10-221-4/+2
* Set kern.timecounter.invariant_tsc to 1 for AMD CPU family 10h and higherjkim2008-10-221-0/+17
* Detect Advanced Power Management Information for AMD CPUs.jkim2008-10-211-0/+13
* - Add cpuctl(4) pseudo-device driver to provide access to some low-levelstas2008-08-081-0/+7
* The variable MTRR registers actually have variable-sized PhysBase andjhb2008-03-121-2/+2
* Add constants for the various fields in MTRR registers.jhb2008-03-111-0/+15
* Add a few more CPUID feature bits while here. We don't support thesedas2008-02-021-0/+2
* SSE4 CPUID bitsdas2008-02-021-0/+3
* Recognize architectural support for 1GB virtual pages.alc2007-12-081-0/+1
* Add a driver for the on-die digital thermal sensor found on Intel Coredes2007-08-151-0/+1
* Add CPUID2_PDCMdes2007-05-311-0/+1
* - Add macros for newly added CPUID bits in the corresponding header files.jkim2007-03-201-0/+2
* Add another CPUID for AMD CPUs and fix style(9) while I am here.jkim2007-03-121-82/+83
* Add SSSE3 extensions and correct CNXT-ID spelling for Intel processors.jkim2007-01-091-1/+2
* Sync specialreg.h changes between amd64 and i386 with few fixes.jkim2006-07-131-2/+5
* Add two new CPUID bits for AMD CPUs, i. e., SVM and extended APIC register.jkim2006-07-121-0/+2
* Add various constants for the PAT MSR and the PAT PTE and PDE flags.jhb2006-05-011-0/+12
* Correct few MSR addresses.jkim2005-10-151-8/+8
* - Print number of physical/logical cores and more CPUID info.jkim2005-10-141-0/+14
* Initial PG_NX support (no-execute page bit)peter2004-06-081-0/+16
* Remove advertising clause from University of California Regent's license,imp2004-04-051-4/+0
* MFi386: add THERMTRIP msr valuespeter2004-01-281-0/+3
* Cosmetic and/or trivial sync up with i386.peter2003-11-211-3/+3
* The great s/npx/fpu/gipeter2003-11-081-5/+2
* MFi386 rev 1.25 by jhb: add new MSR's and some missing older ones andpeter2003-09-221-3/+25
* Commit MD parts of a loosely functional AMD64 port. This is based onpeter2003-05-011-79/+38
* Bah, add in a missing space char I noticed when MFC'ing this.jhb2003-01-221-1/+1
* - Fix the name of the hyperthreading cpuid feature flag to be HTT insteadjhb2003-01-081-1/+9
* Add additional cpuid feature flags and put into a canonical format.mp2002-06-221-18/+33
* Activate SSE/SIMD. This is the extra context switching support thatpeter2001-07-121-0/+2
* Add the CR4 values for P3 SIMD enabling support. FXSR tells the cpu thatpeter1999-09-101-0/+2
* $Id$ -> $FreeBSD$peter1999-08-281-1/+1
* Add defines for the P6 model-specific registers.msmith1999-04-071-1/+58
* - Implement enabling write allocate on AMD K5/K6/K6-2 cpus.kato1998-10-061-1/+6
* Defined CCR6 and CCR7 (configuration registers of M2 CPU.)kato1998-03-041-1/+5
* Enabled the FPU emilaute bit define: CR0_EMfsmp1997-07-211-3/+1
* Improved CPU identification and initialization routines. Thiskato1997-03-221-44/+172
* Back out part 1 of the MCFH that changed $Id$ to $FreeBSD$. We are notpeter1997-02-221-1/+1
* Make the long-awaited change from $Id$ to $FreeBSD$jkh1997-01-141-1/+1
* Support the PG_G flag on Pentium-Pro processors. This prettydyson1996-11-111-1/+34
* Added missing CR0_NW define for Cyrix 486DLC support. It's still notsos1996-06-031-1/+3
* Fix a bunch of spelling errors in the comment fields ofmpp1996-01-301-3/+3
* Remove trailing whitespace.rgrimes1995-05-301-2/+2
* Enable define of CR0_AM to prepare for implementing alignment checking.bde1995-01-141-7/+3
* Improved some comments.dg1994-09-041-2/+2
* Detect if we're running on a Cyrix 486DLC and enable automatic cachepst1994-09-041-1/+54
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