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* Begin all license/copyright comments with /*-imp2005-01-051-1/+1
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* MFi386: remove APIC_IRQ* defines that are no longer used.peter2003-12-111-32/+0
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* New APIC support code:jhb2003-11-031-7/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - The apic interrupt entry points have been rewritten so that each entry point can serve 32 different vectors. When the entry is executed, it uses one of the 32-bit ISR registers to determine which vector in its assigned range was triggered. Thus, the apic code can support 159 different interrupt vectors with only 5 entry points. - We now always to disable the local APIC to work around an errata in certain PPros and then re-enable it again if we decide to use the APICs to route interrupts. - We no longer map IO APICs or local APICs using special page table entries. Instead, we just use pmap_mapdev(). We also no longer export the virtual address of the local APIC as a global symbol to the rest of the system, but only in local_apic.c. To aid this, the APIC ID of each CPU is exported as a per-CPU variable. - Interrupt sources are provided for each intpin on each IO APIC. Currently, each source is given a unique interrupt vector meaning that PCI interrupts are not shared on most machines with an I/O APIC. That mapping for interrupt sources to interrupt vectors is up to the APIC enumerator driver however. - We no longer probe to see if we need to use mixed mode to route IRQ 0, instead we always use mixed mode to route IRQ 0 for now. This can be disabled via the 'NO_MIXED_MODE' kernel option. - The npx(4) driver now always probes to see if a built-in FPU is present since this test can now be performed with the new APIC code. However, an SMP kernel will panic if there is more than one CPU and a built-in FPU is not found. - PCI interrupts are now properly routed when using APICs to route interrupts, so remove the hack to psuedo-route interrupts when the intpin register was read. - The apic.h header was moved to apicreg.h and a new apicvar.h header that declares the APIs used by the new APIC code was added.
* Fix a typo.jhb2003-09-101-1/+1
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* - Fix a duplicated typo.jhb2003-08-151-3/+3
| | | | | | - Add a macro for the logical shift needed to extract an APIC ID from either from the local APIC ICR Hi register or the APIC ID registers of the local and IO APICs.
* Add a new macro APIC_ICRLO_RESV_MASK that contains all of the reservedjhb2003-07-231-0/+1
| | | | | | | | fields in the low 32 bits of the local APIC ICR register. Use this macro in place of APIC_RESV2_MASK when masking off existing bits from the ICR when writing to it to send an IPI. Tested by: scottl
* - Document the thermal and performance counter LVT entries in the localjhb2003-06-061-3/+5
| | | | | | APIC. - Add a lvt_thermal member to the LAPIC struct. - Add constants for the SMI and INIT LVT delivery modes.
* Expand the APIC ID mask field of the ICR register to 8 bits intead of justjhb2003-03-171-1/+1
| | | | | | | | | 4 bits. This reportedly fixes booting on the SW7500CW2. Much thanks to the submitter for tracking this down! Submitted by: Brian Buchanan <brian@ncircle.com> Reviewed by: peter MFC after: 3 days
* Nuke CHEAP_TPR stuff, including LOPRIO_LEVEL (bogus) and ALLHWI_LEVELpeter2003-01-231-17/+0
| | | | | (which we never used). There is no need to tweak the TPR anymore and only causes problems.
* Introduce a standard name for the lock protecting an interrupt controllerjhb2001-12-201-24/+0
| | | | | | | | and it's associated state variables: icu_lock with the name "icu". This renames the imen_mtx for x86 SMP, but also uses the lock to protect access to the 8259 PIC on x86 UP. This also adds an appropriate lock to the various Alpha chipsets which fixes problems with Alpha SMP machines dropping interrupts with an SMP kernel.
* Remove constants defining the bitmasks of the old giant kernel lock.jhb2001-04-101-5/+0
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* Remove the leading underscore from all symbols defined in x86 asmjake2001-02-251-2/+2
| | | | | | | | | | | and used in C or vice versa. The elf compiler uses the same names for both. Remove asnames.h with great prejudice; it has served its purpose. Note that this does not affect the ability to generate an aout kernel due to gcc's -mno-underscores option. moral support from: peter, jhb
* RIP <machine/lock.h>.markm2001-02-111-0/+24
| | | | | | | Some things needed bits of <i386/include/lock.h> - cy.c now has its own (only) copy of the COM_(UN)LOCK() macros, and IMASK_(UN)LOCK() has been moved to <i386/include/apic.h> (AKA <machine/apic.h>). Reviewed by: jhb
* Optimize two cases in the MP locking code. First, it is not necessarydillon1999-11-191-0/+1
| | | | | | | | | | | | | | | to use a locked cmpexg when unlocking a lock that we already hold, since nobody else can touch the lock while we hold it. Second, it is not necessary to use a locked cmpexg when locking a lock that we already hold, for the same reason. These changes will allow MP locks to be used recursively without impacting performance. Modify two procedures that are called only by assembly and are already NOPROF entries to pass a critical argument in %edx instead of on the stack, removing a significant amount of code from the critical path as a consequence. Reviewed by: Alfred Perlstein <bright@wintelcom.net>, Peter Wemm <peter@netplex.com.au>
* $Id$ -> $FreeBSD$peter1999-08-281-1/+1
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* Maintain a mapping from irq number to (ioapic number, int pin) tuple,tegge1998-09-061-7/+1
| | | | | | | | | | | | and use this when masking/unmasking interrupts. Maintain a mapping from (iopaic number, int pin) tuple to irq number, and use this when configuring devices and programming the ioapics. Previous code assumed that irq number was equal to int pin number, and that the ioapic number was 0. Don't let an AP enter _cpu_switch before all local apics are initialized.
* Eliminate frequent silo overflows by restoring the TEST_LOPRIO code.fsmp1997-08-041-2/+6
| | | | | | | | This code was eliminated when the PEND_INTS algorithm was added. But it was discovered that PEND_INTS only worsen latency for FAST_INTR() routines, which can't be marked pending. Noticed & debugged by: dave adkins <adkin003@gold.tc.umn.edu>
* Converted the TEST_LOPRIO code to default.fsmp1997-07-311-4/+2
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* Split TEST_CPUSTOP code into CPUSTOP_ON_DDBBREAK and mainline code.fsmp1997-07-181-1/+4
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* Removed a stale "FIXME:".fsmp1997-07-151-3/+1
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* New defines to eliminate "magic numbers" in various places.fsmp1997-07-151-2/+22
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* General cleanup of APIC code.fsmp1997-07-081-1/+6
| | | | stop_cpus/restart_cpus STILL not working!
* Added fields to the LVT1/2 group.fsmp1997-06-271-1/+10
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* Preliminary support for per-cpu data pages.peter1997-06-221-112/+1
| | | | | | | | | | | | | | | | This eliminates a lot of #ifdef SMP type code. Things like _curproc reside in a data page that is unique on each cpu, eliminating the expensive macros like: #define curproc (SMPcurproc[cpunumber()]) There are some unresolved bootstrap and address space sharing issues at present, but Steve is waiting on this for other work. There is still some strictly temporary code present that isn't exactly pretty. This is part of a larger change that has run into some bumps, this part is standalone so it should be safe. The temporary code goes away when the full idle cpu support is finished. Reviewed by: fsmp, dyson
* apic.h now has structure definitions for both the local APIC and io APIC.fsmp1997-05-291-1/+140
| | | | | | | | | | | | | apic.h has defines like: #define lapic__id lapic->id Once private pages and "known virtual addr" mapping of the APICs is ready all 'lapic__XXX' will be changed to 'lapic.XXX', and the defines will be removed. Changes to smp.h for lapic_t lapic && ioapic_t ioapic pointers, currently equal to apic_base && io_apic_base, will stand alone with the private page mapping.
* informal discussion between Bruce Evans <bde@zeta.org.au>,fsmp1997-04-271-4/+1
| | | | | | | Peter Wemm <peter@spinner.DIALix.COM>, Steve Passe <smp@csn.net> removed all the IPI_INTS code. made the XFAST_IPI32 code default, renaming Xfastipi32 to Xinvltlb.
* Man the liferafts! Here comes the long awaited SMP -> -current merge!peter1997-04-261-0/+409
There are various options documented in i386/conf/LINT, there is more to come over the next few days. The kernel should run pretty much "as before" without the options to activate SMP mode. There are a handful of known "loose ends" that need to be fixed, but have been put off since the SMP kernel is in a moderately good condition at the moment. This commit is the result of the tinkering and testing over the last 14 months by many people. A special thanks to Steve Passe for implementing the APIC code!
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