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path: root/sys/amd64/amd64/initcpu.c
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* Add basic amd64 support for VIA Nano processors.jkim2009-01-121-0/+75
* Introduce cpu_vendor_id and replace a lot of strcmp(cpu_vendor, "...").jkim2008-11-261-0/+1
* Detect Advanced Power Management Information for AMD CPUs.jkim2008-10-211-0/+1
* Add variable cpu_mxcsr_mask to save valid bits of mxcsr register.davidxu2006-06-191-0/+1
* - Print number of physical/logical cores and more CPUID info.jkim2005-10-141-1/+3
* Initial PG_NX support (no-execute page bit)peter2004-06-081-13/+13
* Cosmetic and/or trivial sync up with i386.peter2003-11-211-1/+1
* Use __FBSDID().obrien2003-07-251-2/+3
* Commit MD parts of a loosely functional AMD64 port. This is based onpeter2003-05-011-810/+6
* Extend CPU_ATHLON_SSE_HACK to cover a few more revisions of Athlon CPUs.dwmalone2003-03-201-1/+2
* - Move enable_sse()'s prototype to machine/md_var.h.jhb2003-01-221-7/+6
* Rename cpuid_cpuinfo to cpu_procinfo. bde requested that I rename thisjhb2003-01-221-1/+1
* Rework part of the previous processor name changes so that we readjhb2003-01-091-2/+0
* - Add a cpu_exthigh variable to hold the highest extended cpuid valuejhb2003-01-081-0/+2
* Add a cpuid_cpuinfo variable to hold the results of %ebx from cpuid withjhb2003-01-081-0/+1
* Be consistent about functions being static.phk2002-10-161-1/+1
* Be consistent about "static" functions: if the function is markedphk2002-09-281-1/+1
* Automatically enable CPU_ENABLE_SSE (detect and enable SSE instructions)peter2002-09-071-0/+7
* Fix abuses of cpu_critical_{enter,exit} by converting toimp2002-03-211-4/+3
* Add an option CPU_ATHLON_SSE_HACK which attempts to enable the SSEdwmalone2002-02-121-0/+18
* Modify the critical section API as follows:jhb2001-12-181-2/+2
* Mostly cosmetic. Move various variables from .s files to .c files so thatpeter2001-09-041-1/+7
* Move cpu_fxsr definition to C code (so debug info is generated) and wherepeter2001-08-241-0/+4
* There is nothing special that requires SSE to be only on 686 class cpus.peter2001-08-181-6/+4
* Unbroke kernel if I686_CPU is not defined.sobomax2001-07-131-0/+2
* Forgot this fix from another tree. make enable_sse() a real prototype.peter2001-07-121-1/+1
* Move init_sse() out of the "GenuineIntel" section, my AthlonMP systempeter2001-07-121-1/+1
* Activate SSE/SIMD. This is the extra context switching support thatpeter2001-07-121-0/+22
* Switch from save/disable/restore_intr() to critical_enter/exit().jhb2001-03-281-4/+3
* Fix some further english grammar and typo's.asmodai2000-11-081-3/+3
* Fix typo's: UPGRADE_CPU_HW_CACHE -> CPU_UPGRADE_HW_CACHEasmodai2000-11-081-2/+2
* Major update to the way synchronization is done in the kernel. Highlightsjasone2000-09-071-3/+3
* Improved Cyrix 486DX supports for NEC PC-98.kato2000-08-311-0/+15
* Added new options CPU_PPRO2CELERON and CPU_L2_LATENCY to supportkato2000-06-131-3/+52
* $Id$ -> $FreeBSD$peter1999-08-281-1/+1
* Kill option FAILSAFE.des1999-06-151-6/+1
* There are two models of AMD K6-2 Model 8 (c.f. AMD's document), so thekato1999-01-161-10/+8
* From the submitter:msmith1998-12-271-3/+67
* Get rid of uninitialized variable warnings. No bugs found, justdillon1998-12-141-2/+3
* - Implement enabling write allocate on AMD K5/K6/K6-2 cpus.kato1998-10-061-3/+123
* Disable local APIC in UP kernel. Intel specification update describeskato1998-05-161-1/+22
* Make FAILSAFE a new-style option.eivind1998-02-041-1/+2
* Fix typo. Option `CPU_SUSP_HLT' didn't work on Cyrix 486DX box.kato1998-01-031-3/+3
* Correct CPU_CYRIX_NO_LOCK fix.jlemon1997-11-211-5/+5
* Removed unused #includes.bde1997-10-281-2/+1
* Added two Cyrix 6x86/6x86MX options.kato1997-10-061-7/+35
* Treat 6x86MX CPU as 686-class CPU instead of 586-class CPU.kato1997-07-241-5/+5
* Added CPU_DIRECT_MAPPED_CACHE option which sets L1 cache in directkato1997-06-271-1/+4
* - Use `6x86MX' instead of `M2'. Cyrix officially use `6x86MX' for thekato1997-05-311-1/+65
* Add new cpu type, CPU_CY486DX, which shows Cyrix 486S/DX series CPUs,kato1997-04-261-4/+30
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