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* Re-implement FPU suspend/resume for amd64. This removes superfluous usesjkim2010-07-262-6/+15
| | | | | | | of critical_enter(9) and critical_exit(9) by fpugetregs() and fpusetregs(). Also, we do not touch PCB flags any more. MFC after: 1 month
* Move i386-inherited logic of building ACPI headers for acpi_wakeup.c intojkim2010-07-124-50/+0
| | | | | better places and remove intermediate makefile and shell scripts. This makes parallel kernel build little bit safer for amd64.
* Restore the machine check register banks on resume. For banks beingjhb2010-06-151-0/+2
| | | | | | | monitored via CMCI, reset the interrupt threshold to 1 on resume. Reviewed by: jkim MFC after: 2 weeks
* Fix ACPI suspend/resume on amd64, which was broken since r208833.jkim2010-06-141-1/+1
| | | | We need actual storage for FPU state to save and restore.
* Update several places that iterate over CPUs to use CPU_FOREACH().jhb2010-06-111-3/+1
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* Introduce the x86 kernel interfaces to allow kernel code to usekib2010-06-051-1/+1
| | | | | | | | | | | | | | | | FPU/SSE hardware. Caller should provide a save area that is chained into the stack of the areas; pcb save_area for usermode FPU state is on top. The pcb now contains a pointer to the current FPU saved area, used during FPUDNA handling and context switches. There is also a facility to allow the kernel thread to use pcb save_area. Change the dreaded warnings "npxdna in kernel mode!" into the panics when FPU usage is not registered. KPI discussed with: fabient Tested by: pho, fabient Hardware provided by: Sentex Communications MFC after: 1 month
* Use the same policy for rejecting / not-reject ACPI tables with incorrectjhb2010-03-191-0/+2
| | | | | | | | | | checksums as the base acpi(4) driver. This fixes a problem where the MADT parser would reject the MADT table during early boot causing the MP Table to be, but then the acpi(4) driver would attach and use non-SMP interrupt routing. Tested by: Alastair Hogge agh of coolrhaug com MFC after: 1 week
* Simplify a macro not to generate unncessary symbols.jkim2009-12-081-14/+1
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* Tweak memory allocation for amd64 suspend/resume CPU context.jkim2009-11-041-16/+14
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* Try hiding annoying text cursor after the video controller is reset.jkim2009-10-231-0/+5
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* Clean up amd64 suspend/resume code.jkim2009-10-083-33/+35
| | | | | | | | - Allocate memory for wakeup code after ACPI bus is attached. The early memory allocation hack was inherited from i386 but amd64 does not need it. - Exclude real mode IVT and BDA explicitly. Improve comments about memory allocation and reason for the exclusions. It is a no-op in reality, though. - Remove an unnecessary CLD from wakeup code and re-align.
* Copy apm(4) emulation from sys/i386/acpica/acpi_machdep.c andjkim2009-09-271-8/+448
| | | | install apm(8) and apm_bios.h on amd64.
* Extract the code to find and map the MADT ACPI table during early kerneljhb2009-09-232-223/+254
| | | | | | | | | startup and genericize it so it can be reused to map other tables as well: - Add a routine to walk a list of ACPI subtables such as those used in the APIC and SRAT tables in the MI acpi(4) driver. - Move the routines for mapping and unmapping an ACPI table as well as mapping the RSDT or XSDT and searching for a table with a given signature out into acpica_machdep.c for both amd64 and i386.
* Import ACPICA 20090521.jkim2009-06-054-7/+11
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* Reduce code duplcations from r190620. While I am here, tweak a comment.jkim2009-04-021-3/+1
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* Chase GDT layout changes and unbreak suspend/resume on amd64.jkim2009-04-023-18/+18
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* Save and restore segment registers on amd64 when entering and leavingkib2009-04-011-6/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | the kernel on amd64. Fill and read segment registers for mcontext and signals. Handle traps caused by restoration of the invalidated selectors. Implement user-mode creation and manipulation of the process-specific LDT descriptors for amd64, see sysarch(2). Implement support for TSS i/o port access permission bitmap for amd64. Context-switch LDT and TSS. Do not save and restore segment registers on the context switch, that is handled by kernel enter/leave trampolines now. Remove segment restore code from the signal trampolines for freebsd/amd64, freebsd/ia32 and linux/i386 for the same reason. Implement amd64-specific compat shims for sysarch. Linuxolator (temporary ?) switched to use gsbase for thread_area pointer. TODO: Currently, gdb is not adapted to show segment registers from struct reg. Also, no machine-depended ptrace command is added to set segment registers for debugged process. In collaboration with: pho Discussed with: peter Reviewed by: jhb Linuxolator tested by: dchagin
* - Clean up suspend/resume code for amd64.jkim2009-03-234-31/+29
| | | | | | | | - Call acpi_resync_clock() to reset system time before hardclock is ready to tick. Note we assume the current timecounter hardware and RTC are already available for read operation. Tested by: mav
* Initial suspend/resume support for amd64.jkim2009-03-177-2/+925
| | | | | | This code is heavily inspired by Takanori Watanabe's experimental SMP patch for i386 and large portion was shamelessly cut and pasted from Peter Wemm's AP boot code.
* At least one BIOS bogusly includes duplicate entries for I/O APICs. Thejhb2009-03-051-0/+4
| | | | | | | | | bogus entries have a starting IRQ that is invalid (> 255, so won't fit into a PCI intline config register). It had the side effect of breaking MSI by "claiming" several IRQs in the MSI range. Fix this by ignoring such I/O APICs. MFC after: 2 weeks
* In keeping with style(9)'s recommendations on macros, use a ';'rwatson2008-03-161-2/+2
| | | | | | | | | after each SYSINIT() macro invocation. This makes a number of lightweight C parsers much happier with the FreeBSD kernel source, including cflow's prcc and lxr. MFC after: 1 month Discussed with: imp, rink
* Rework how the nexus(4) device works on x86 to better handle the idea ofjhb2008-03-131-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | different "platforms" on x86 machines. The existing code already handles having two platforms: ACPI and legacy. However, the existing approach was rather hardcoded and difficult to extend. These changes take the approach that each x86 hardware platform should provide its own nexus(4) driver (it can inherit most of its behavior from the default legacy nexus(4) driver) which is responsible for probing for the platform and performing appropriate platform-specific setup during attach (such as adding a platform-specific bus device). This does mean changing the x86 platform busses to no longer use an identify routine for probing, but to move that logic into their matching nexus(4) driver instead. - Make the default nexus(4) driver in nexus.c on i386 and amd64 handle the legacy platform. It's probe routine now returns BUS_PROBE_GENERIC so it can be overriden. - Expose a nexus_init_resources() routine which initializes the various resource managers so that subclassed nexus(4) drivers can invoke it from their attach routine. - The legacy nexus(4) driver explicitly adds a legacy0 device in its attach routine. - The ACPI driver no longer contains an new-bus identify method. Instead it exposes a public function (acpi_identify()) which is a probe routine that the MD nexus(4) drivers can use to probe for ACPI. All of the probe logic in acpi_probe() is now moved into acpi_identify() and acpi_probe() is just a stub. - On i386 and amd64, an ACPI-specific nexus(4) driver checks for ACPI via acpi_identify() and claims the nexus0 device if the probe succeeds. It then explicitly adds an acpi0 device in its attach routine. - The legacy(4) driver no longer knows anything about the acpi0 device. - On ia64 if acpi_identify() fails you basically end up with no devices. This matches the previous behavior where the old acpi_identify() would fail to add an acpi0 device again leaving you with no devices. Discussed with: imp Silence on: arch@
* For no good reason I had assumed that ACPI table headers would be pagejhb2008-01-311-5/+7
| | | | | | | | | | | | | | | | | | | | aligned (or at least not cross a page boundary). However, it turns out that on at least one machine one table header does cross a page boundary. This caused problems with the MADT early probe as it uses the crash dump map to load ACPI tables by loading the RSDT/XSDT into pages 1 ... N and loading the header of each ACPI table header into page 0 looking for the MADT. However, if a table header crossed a page boundary, then page 1 would get trashed resulting in a panic. Fix this by reserving the first 2 pages for ACPI table headers (headers are less than a page in size, so 2 pages will be sufficient) and use pages 2 .. N for the RSDT and XSDT. Note: amd64 should probably be simplified to just use pmap_mapbios() for all these tables which will use the direct map and not need the crash dump hack. MFC after: 5 days Tested on: i386 Reported by: Pete French petefrench of ticketswitch.com
* Handle CPUs with APIC IDs higher than 32 (at least one IBM server usesjhb2007-05-081-10/+7
| | | | | | | | | | | | | an APIC ID of 38 for its second CPU): - Add a new MAX_APIC_ID constant for the highest valid APIC ID for modern systems. - Size the various arrays in the MADT, MP Table, and SMP code that are indexed by APIC IDs to allow for up to MAX_APIC_ID. - Explicitly go through and assign logical cpu ids to local APICs before starting any of the APs up rather than doing it while starting up the APs. This step is now where we honor MAXCPU. MFC after: 1 week
* Catch up with ACPI-CA 20070320 import.jkim2007-03-222-142/+137
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* Use vm_paddr_t rather than uintptr_t when passing the physical address ofjhb2007-03-051-4/+3
| | | | APICs to lapic_init() and ioapic_create().
* First pass at allowing memory to be mapped using cache modes other thanjhb2006-08-111-5/+5
| | | | | | | | | | | | | | | | | | | | WB (write-back) on x86 via control bits in PTEs and PDEs (including making use of the PAT MSR). Changes include: - A new pmap_mapdev_attr() function for amd64 and i386 which takes an additional parameter (relative to pmap_mapdev()) specifying the cache mode for this mapping. Note that on amd64 only WB mappings are done with the direct map, all other modes result in a private mapping. - pmap_mapdev() on i386 and amd64 now defaults to using UC (uncached) mappings rather than WB. Previously we relied on the BIOS setting up MTRR's to enforce memio regions being treated as UC. This might make hw.cbb_start_memory unnecessary in some cases now for example. - A new pmap_mapbios()/pmap_unmapbios() API has been added to allow places that used pmap_mapdev() to map non-device memory (such as ACPI tables) to do so using WB as before. - A new pmap_change_attr() function for amd64 and i386 that changes the caching mode for a range of KVA. Reviewed by: alc
* If the XSDT address in the RSDP for an ACPI 2.0 machine is NULL, then falljhb2006-03-271-4/+5
| | | | | | | | back to using the RSDT instead. ACPI-CA already follows this same strategy as a workaround for yet another instance of brain-damaged BIOS writers. PR: i386/93963 Submitted by: Masayuki FUKUI <fukui.FreeBSD@fanet.net>
* Catch up with ACPI-CA 20051021 importjkim2005-11-011-1/+1
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* Normalize a significant number of kernel malloc type names:rwatson2005-10-311-1/+1
| | | | | | | | | | | | | | | | | | | - Prefer '_' to ' ', as it results in more easily parsed results in memory monitoring tools such as vmstat. - Remove punctuation that is incompatible with using memory type names as file names, such as '/' characters. - Disambiguate some collisions by adding subsystem prefixes to some memory types. - Generally prefer lower case to upper case. - If the same type is defined in multiple architecture directories, attempt to use the same name in additional cases. Not all instances were caught in this change, so more work is required to finish this conversion. Similar changes are required for UMA zone names.
* Canonize the include of acpi.h.obrien2005-09-114-4/+4
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* MFi386: use the lapic timer for UP systems that are using the apic so thatpeter2005-04-151-2/+0
| | | | | IRQ0 and mixed mode isn't a problem anymore. This removes mixed mode support because nothing is left that uses it.
* - Add a new quirk to indicate that pin 0 of the first I/O APIC is reallyjhb2005-02-221-2/+8
| | | | | | | | | IRQ 0 and not an ExtINT pin. The MADT enumerators ignore the PC-AT flag and ignore overrides that map IRQ 0 to pin 2 when this quirk is present. - Add a block comment above the quirks to document each quirk so that we can use more verbose descriptions quirks. MFC after: 2 weeks
* Move the code for halting the CPU (acpi_cpu_c1) into machdep files.njl2004-10-111-0/+6
| | | | | | This removes the last MD portion of acpi_cpu.c. MFC after: 2 weeks
* Sync with i386 - get the softc via the devclass rather than caching the devpeter2004-08-161-2/+1
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* Add machdep quirks functions. On i386, this disables acpi on systems withnjl2004-06-301-0/+6
| | | | BIOS dates earlier than Jan 1, 1999. Add prototypes and quirks flags.
* Insta-MFi386: ignore disabled cpu apic id's entirelypeter2004-06-101-13/+8
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* MFi386: apic intpin programming updates etc.peter2004-06-031-28/+30
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* MFi386: numerous interrupt and acpi updatespeter2004-05-161-41/+122
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* Make unnecessary globals static and remove unused includes.njl2004-05-061-1/+1
| | | | Pointed out by: cscout
* Don't check for NULL, device_get_softc() always succeeds.njl2004-04-211-2/+1
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* Merge some more changes from i386.peter2004-01-301-7/+43
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* Use the ACPI-CA definitions for the various APIC tables instead of ournjl2003-12-091-59/+55
| | | | own.
* MFi386: put the apic disable hook in a better place.peter2003-12-061-1/+1
| | | | Approved by: re (scottl)
* Add an additional knob to just disable the apic code without also havingpeter2003-12-031-1/+1
| | | | | | | to resort to disabling acpi as well. I'll document this in the release notes for amd64. Approved by: re (scottl)
* Minor source sync with amd64. For %.*s printf formats, pass in anpeter2003-11-141-3/+5
| | | | | int rather than a size_t. cast the ioapicaddress variable via uintptr_t before going to void *.
* Some motherboards like to remap the SCI (normally IRQ 9) up to a PCIjhb2003-11-111-1/+6
| | | | | | | | | | | | | | | | | interrupt such as IRQ 22 or 19. However, the ACPI BIOS still routes interrupts from some PCI devices to the same intpin calling the pin IRQ 22. Thus, ACPI expects to address a single interrupt source via two different names. To work around this, if the SCI is remapped to a non-ISA interrupt (i.e., greater than 15), then we use acpi_OverrideInterruptLevel() function to tell ACPI to use IRQ 22 or 19 rather than IRQ 9 for the SCI. Previously we would change IRQ 22 or 19's name to IRQ 9 when we encountered such an Interrupt Source Override entry in the MADT which routed the SCI properly but left PCI devices mapped to IRQ 22 or 19 w/o a routable interrupt. Tested by: sos
* Bump APIC ID limits up to 32 since a machine with 16 CPUs will have APICjhb2003-11-101-2/+2
| | | | | | IDs for the I/O APICs that are greater than 16. Reported by: John Cagle <john.cagle@hp.com>
* Only disable the old pin when doing a remap if it's current vector is stilljhb2003-11-061-1/+2
| | | | | | the old vector. Reported by: sam
* When remapping an ISA interrupt from one intpin to another, disable thejhb2003-11-051-8/+16
| | | | | | | | | pin that is used by the default identity mapping if it still maps to the old vector. The ACPI case might need some tweaking for the SCI interrupt case since ACPI likes to address the intpin using both the IRQ remapped to it as well as the previous existing PCI IRQ mapped to it. Reported by: kan
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