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* Implement and document remquo() and remquof().das2005-03-253-1/+131
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* Spell 'fedisableexcept' correctly.das2005-03-161-1/+1
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* Replace fegetmask() and fesetmask() with feenableexcept(),das2005-03-162-8/+26
| | | | | | | | | | fedisableexcept(), and fegetexcept(). These two sets of routines provide the same functionality. I implemented the former as an undocumented internal interface to make the regression test easier to write. However, fe(enable|disable|get)except() is already part of glibc, and I would like to avoid gratuitous differences. The only major flaw in the glibc API is that there's no good way to report errors on processors that don't support all the unmasked exceptions.
* Define the LDBL_PREC to be the number of significant bits in a longdas2005-03-071-0/+1
| | | | double's mantissa.
* Move machine-dependent crud to its own makefile.das2005-02-041-0/+3
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* Remove wrappers and other cruft intended to support SVID, mistakes indas2005-02-041-1/+1
| | | | | | | C90, and other arcana. Most of these features were never fully supported or enabled by default. Ok: bde, stefanf
* amd64 assembly versions of sqrt(), lrint(), and llrint() using SSE2.das2005-01-153-0/+75
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* Mark all inline asms that read the floating-point control or statusdas2005-01-141-3/+3
| | | | | | | registers as volatile. Instructions that *wrote* to FP state were already marked volatile, but apparently gcc has license to move non-volatile asms past volatile asms. This broke amd64's feupdateenv at -O2 due to a WAR conflict between fnstsw and fldenv there.
* Mark inline stmxcsr instructions as volatile, since this appears to bedas2005-01-111-1/+1
| | | | | the only way to convince gcc that they read the MXCSR. The volatile annotation may be needed elsewhere as well.
* Insert a missing '~' in feholdexcept(), so that it correctly clearsdas2004-06-111-1/+1
| | | | the exception flags in the mxcsr as well as the x87 FPU.
* Add an fenv.h implementation for the amd64 port.das2004-06-062-0/+333
Reviewed by: standards@
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