| Commit message (Collapse) | Author | Age | Files | Lines |
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Sampling is in progress.
Approved by: nwhitehorn (mentor)
MFC after: 9.0-RELEASE
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be of type 'enum pmc_cputype', not 'enum pmc_class'.
MFC after: 1 week
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As the underlying block is 4KB if the PMC throughput is low the measurement
will be reported on the next tick. pmcstat(8) use the modified flush API to
reclaim current buffer before displaying next top.
MFC after: 1 month
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- change "the the" to "the"
Approved by: lstewart
Approved by: sahil (mentor)
MFC after: 3 days
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They have no effect when coming in pairs, or before .Bl/.Bd
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MFC after: 1 day
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Keep IAF class with 0 PMC and change the alias in libpmc to IAP.
MFC after: 1 week
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Prefer MACHNE_CPUARCH to MACHINE_ARCH in most contexts where you want
to test of all the CPUs of a given family conform.
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translating these manual pages. Minor corrections by me.
Submitted by: Nobuyuki Koganemaru <n-kogane@syd.odn.ne.jp>
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Found with: Coverity Prevent(tm)
MFC after: 1 month
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Garbage collect unused sections, macros and arguments. Fix prologue and
remove empty lines.
Found by: mdocml
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While here, also drop the unneeded quotes
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bottom of the manpages and order them consistently.
GNU groff doesn't care about the ordering, and doesn't even mention
CAVEATS and SECURITY CONSIDERATIONS as common sections and where to put
them.
Found by: mdocml lint run
Reviewed by: ru
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cachestate qualifier on the Atom processor. Other Intel processors do not accept a cachestate qualifier and currently hwpmc will return EINVAL if you try to use the EXT_SNOOP event on those processors
Approved by: jkoshy (mentor)
MFC after: 2 weeks
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Although groff_mdoc(7) gives another impression, this is the ordering
most widely used and also required by mdocml/mandoc.
Reviewed by: ru
Approved by: philip, ed (mentors)
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domain clock, 8 programmable PMC.
- Westmere based CPU (Xeon 5600, Corei7 980X) support.
- New man pages with events list for core and uncore.
- Updated Corei7 events with Intel 253669-033US December 2009 doc.
There is some removed events in the documentation, they have been
kept in the code but documented in the man page as obsolete.
- Offcore response events can be setup with rsp token.
Sponsored by: NETASQ
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Add macros for properly accessing coprocessor 0 registers that
support performance counters.
Reviewed by: jkoshy rpaulo fabien imp
MFC after: 1 month
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Submitted by: Luca Pizzamiglio <luca.pizzamiglio at gmail dot com>
PR: i386/142742
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Similar to libexec/, do the same with lib/. Make WARNS=6 the norm and
lower it when needed.
I'm setting WARNS?=0 for secure/. It seems secure/ includes the
Makefile.inc provided by lib/. I'm not going to touch that directory.
Most of the code there is contributed anyway.
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This brings hwpmc(4) support for 2nd and 3rd generation XScale cores.
Right now it's enabled by default to make sure we test this a bit.
When the time comes it can be disabled by default.
Tested on Gateworks boards.
A man page is coming.
Obtained from: //depot/user/rpaulo/xscalepmc/...
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Submitted by: Ulrich Spoerlein
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counters. For such CPUs, use an alternate mapping of convenience
names to events supported by PMC_CLASS_IAP programmable counters.
Testing and review by: fabient
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Reviewed by: jkoshy
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Submitted by: danfe
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Reported by: John McCullough <jmccullo at cs.ucsd.edu>
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Reported by: Harald Servat <redcrash at gmail dot com>
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Submitted by: Nikola K <laladelausanne at gmail dot com>
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Approved by: jkoshy (mentor)
MFC after: 3 days
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counters defined in the reference manual. It does not support the
'uncore' events.
Reviewed by: jkoshy
Sponsored by: Nokia
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Submitted by: "Artem Belevich" <artemb at gmail dot com>
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Submitted by: "Verplanke, Edwin" <edwin dot verplanke at intel dot com>
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and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and
model 0x1C (Atom).
In these CPUs, the actual numbers, kinds and widths of PMCs present
need to queried at run time. Support for specific "architectural"
events also needs to be queried at run time.
Model 0xE CPUs support programmable PMCs, subsequent CPUs
additionally support "fixed-function" counters.
- Use event names that are close to vendor documentation, taking in
account that:
- events with identical semantics on two or more CPUs in this family
can have differing names in vendor documentation,
- identical vendor event names may map to differing events across
CPUs,
- each type of CPU supports a different subset of measurable
events.
Fixed-function and programmable counters both use the same vendor
names for events. The use of a class name prefix ("iaf-" or
"iap-" respectively) permits these to be distinguished.
- In libpmc, refactor pmc_name_of_event() into a public interface
and an internal helper function, for use by log handling code.
- Minor code tweaks: staticize a global, freshen a few comments.
Tested by: gnn
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