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* mdoc: remove literal tabs where they don't belonguqs2010-06-083-5/+5
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* Fix memory leak on error.fabient2010-06-051-1/+3
| | | | | Found with: Coverity Prevent(tm) MFC after: 1 month
* mdoc cleanupuqs2010-06-021-2/+0
| | | | | | | Garbage collect unused sections, macros and arguments. Fix prologue and remove empty lines. Found by: mdocml
* mdoc: Use mdoc macro for the (R) symboluqs2010-05-271-8/+8
| | | | While here, also drop the unneeded quotes
* mdoc: move CAVEATS, BUGS and SECURITY CONSIDERATIONS sections to theuqs2010-05-132-4/+4
| | | | | | | | | | | bottom of the manpages and order them consistently. GNU groff doesn't care about the ordering, and doesn't even mention CAVEATS and SECURITY CONSIDERATIONS as common sections and where to put them. Found by: mdocml lint run Reviewed by: ru
* When configuring hwpmc to use the EXT_SNOOP event, only send a default ↵rstone2010-05-011-1/+8
| | | | | | | cachestate qualifier on the Atom processor. Other Intel processors do not accept a cachestate qualifier and currently hwpmc will return EINVAL if you try to use the EXT_SNOOP event on those processors Approved by: jkoshy (mentor) MFC after: 2 weeks
* mdoc: order prologue macros consistently by Dd/Dt/Osuqs2010-04-1430-30/+30
| | | | | | | | Although groff_mdoc(7) gives another impression, this is the ordering most widely used and also required by mdocml/mandoc. Reviewed by: ru Approved by: philip, ed (mentors)
* - Support for uncore counting events: one fixed PMC with the uncorefabient2010-04-027-7/+5167
| | | | | | | | | | | | domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
* Finish the much belated Intel XScale hwpmc(4) man page.rpaulo2010-03-231-2/+119
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* Add support for hwpmc(4) on the MIPS 24K, 32 bit, embedded processor.gnn2010-03-032-2/+475
| | | | | | | | Add macros for properly accessing coprocessor 0 registers that support performance counters. Reviewed by: jkoshy rpaulo fabien imp MFC after: 1 month
* Bug fix: add a missing initializer.jkoshy2010-01-121-0/+1
| | | | | Submitted by: Luca Pizzamiglio <luca.pizzamiglio at gmail dot com> PR: i386/142742
* Build lib/ with WARNS=6 by default.ed2010-01-021-2/+0
| | | | | | | | | Similar to libexec/, do the same with lib/. Make WARNS=6 the norm and lower it when needed. I'm setting WARNS?=0 for secure/. It seems secure/ includes the Makefile.inc provided by lib/. I'm not going to touch that directory. Most of the code there is contributed anyway.
* Intel XScale hwpmc(4) support.rpaulo2009-12-233-0/+86
| | | | | | | | | | | This brings hwpmc(4) support for 2nd and 3rd generation XScale cores. Right now it's enabled by default to make sure we test this a bit. When the time comes it can be disabled by default. Tested on Gateworks boards. A man page is coming. Obtained from: //depot/user/rpaulo/xscalepmc/...
* Use our canonical .Dd format.brueffer2009-11-021-1/+1
| | | | Submitted by: Ulrich Spoerlein
* Not all Intel Core (TM) CPUs implement PMC_CLASS_IAF fixed-functionjkoshy2009-10-241-12/+47
| | | | | | | counters. For such CPUs, use an alternate mapping of convenience names to events supported by PMC_CLASS_IAP programmable counters. Testing and review by: fabient
* Install x86 related man pages on x86 systems only.rpaulo2009-10-041-0/+2
| | | | Reviewed by: jkoshy
* Use a more appropriate choice of words.jkoshy2009-08-231-1/+1
| | | | Submitted by: danfe
* Use US spellings, fix typos.jkoshy2009-08-233-18/+18
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* Fix typos.jkoshy2009-08-231-7/+7
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* Fix a typo.jkoshy2009-08-231-1/+1
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* Fix typos, use American English spellings.jkoshy2009-08-234-22/+22
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* Fix typos.jkoshy2009-08-231-9/+9
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* Correct typos.jkoshy2009-08-231-2/+2
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* Correct grammar.jkoshy2009-08-231-2/+2
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* Fix a typo.jkoshy2009-08-231-1/+1
| | | | Reported by: John McCullough <jmccullo at cs.ucsd.edu>
* Fix typos.jkoshy2009-08-233-4/+4
| | | | Reported by: Harald Servat <redcrash at gmail dot com>
* Document the fact that some Core2 family CPUs lack fixed-function counters.jkoshy2009-06-091-3/+4
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* Fix parsing of Core2 event qualifiers.jkoshy2009-06-091-7/+7
| | | | Submitted by: Nikola K <laladelausanne at gmail dot com>
* Allow compile from c++ for libpmcfabient2009-03-242-0/+6
| | | | | Approved by: jkoshy (mentor) MFC after: 3 days
* - Add support for nehalem/corei7 cpus. This supports all of the corejeff2009-01-271-1/+23
| | | | | | | | counters defined in the reference manual. It does not support the 'uncore' events. Reviewed by: jkoshy Sponsored by: Nokia
* Document processor errata that affect performance measurement.jkoshy2008-12-081-0/+52
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* Fixes for Core2 Extreme support.jkoshy2008-12-031-1/+5
| | | | Submitted by: "Artem Belevich" <artemb at gmail dot com>
* Update description of an event.jkoshy2008-11-271-2/+1
| | | | Submitted by: "Verplanke, Edwin" <edwin dot verplanke at intel dot com>
* - Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solojkoshy2008-11-273-37/+447
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
* Fix buglets.jkoshy2008-11-261-2/+2
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* Correction: these PMCs do not support a "umask" modifier.jkoshy2008-11-243-9/+0
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* - Document the rules used to determine when spellings of eventsjkoshy2008-11-241-16/+24
| | | | | are equivalent. - Reorder text to make the manual page more coherent.
* - Document the class name prefix for these PMCs.jkoshy2008-11-151-1/+22
| | | | | - Document the "anythread" qualifier, available on Atom CPUs. - Add examples.
* Tweak -mdoc usage.jkoshy2008-11-133-7/+7
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* Document UMASK values, fix errors.jkoshy2008-11-131-62/+62
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* Fix typos, document UMASK values.jkoshy2008-11-131-53/+54
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* Remove duplicates, fix errors and document UMASK values.jkoshy2008-11-131-54/+47
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* Document the alternate event names supported for "architectural" PMC events.jkoshy2008-11-123-25/+74
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* Use spellings that are close to vendor documentation.jkoshy2008-11-121-3/+3
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* - Sparsely number enumerations 'pmc_cputype' and 'pmc_event' in order tojkoshy2008-10-091-101/+287
| | | | | | | | | | | reduce ABI disruptions when new cpu types and new PMC events are added in the future. - Support alternate spellings for PMC events. Derive the canonical spelling of an event name from its enumeration name in 'enum pmc_event'. - Provide a way for users to disambiguate between identically named events supported by multiple classes of PMCs in a CPU. - Change libpmc's machine-dependent event specifier parsing code to better support CPUs containing two or more classes of PMC resources.
* Correct a typo.jkoshy2008-10-061-1/+1
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* - Add cross-references.jkoshy2008-10-041-3/+6
| | | | - Tweak -mdoc use.
* Add cross-references.jkoshy2008-10-041-1/+5
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* Cross-reference new manual pages.jkoshy2008-10-044-4/+20
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* - Cross-reference new manual pages.jkoshy2008-10-041-8/+14
| | | | - Spell new PMC class names correctly.
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