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* | Enable wireless Atheros cards in ARMADA38Xwma2017-09-061-0/+8
| | | | | | | | | | | | | | | | | | | | Submitted by: Bartosz Szczepanek <bsz@semihalf.com> Dominik Ermel <der@semihalf.com> Obtained from: Semihalf Sponsored by: Stormshield Differential revision: https://reviews.freebsd.org/D10904 (cherry picked from commit 49790a540092a7bb8e8914a83aa502601f9c246a)
* | Reduce kmem_arena maximum size for Armada38xzbb2017-09-061-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | VM_KMEM_SIZE_MAX allows to limit kmem arena size. In our case this was necessary, as decreasing size of kmem_arena leaves more space for kernel_arena. kernel_arena is pool used for contigmalloc (in effect, DMA) allocations, which failed on Armada38x. This resulted in 'no memory errors' (e.g. USB_ERR_NOMEM errors) and failure of whole system. The need for greater size of kernel_arena probably comes from more peripherals making use of busdma. Value used as upper limit is half of the default value (0x1399a000). Submitted by: Wojciech Macek <wma@semihalf.com> Obtained from: Semihalf Sponsored by: Stormshield Differential revision: https://reviews.freebsd.org/D10216 (cherry picked from commit 1de67b38984892e529ea435824d8f179ccd1cca3)
* | Include e6000sw driver in ARMADA38X configurationzbb2017-09-062-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | e6000sw Marvell switch driver was added to files and Armada38x kernel configuration file. Submitted by: Bartosz Szczepanek <bsz@semihalf.com> Obtained from: Semihalf Sponsored by: Stormshield Differential revision: https://reviews.freebsd.org/D8178 (cherry picked from commit 8a5482eb9f90034c0273122560721b6a01c3aaf1)
* | Enable parsing simple-bus 'ranges' with multiple entriesmw2017-09-061-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes possible to boot with up to 8 ranges in soc. Dynamic allocation cannot be used, because ftd_get_ranges function is called early, when malloc is not available. Change is required for the alignment of Marvell Armada 38x device trees present in sys/gnu/dts/arm - originally the platform has 6 entries in simple-bus 'ranges'. Submitted by: Patryk Duda <pdk@semihalf.com> Reviewed by: manu, nwhitehorn, cognet (mentor) Approved by: cognet (mentor) Obtained from: Semihalf Differential Revision: https://reviews.freebsd.org/D11876 (cherry picked from commit 6ab1e86ae3ea3159e2dd8fae140549a71d5386e5)
* | Set the correct default for #address-cells variable when the property doesloos2017-09-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | not exist. This has never caused any issue because #address-cells is mandatory. Sponsored by: Rubicon Communications, LLC (Netgate) MFC after: 2 weeks (cherry picked from commit 1bbed8ea99021d00324e8429e59b5f80b4328d06)
* | Replace OF_getprop ... fdt32_to_cpu with OF_getencprop. The latterandrew2017-09-061-7/+7
| | | | | | | | | | | | | | | | | | correctly adjusts for the endian. MFC after: 1 week Sponsored by: ABT Systems Ltd (cherry picked from commit 813addbf2cfa303aa2c7515a34cc731222d30d46)
* | Update comment ot reflect realilty, we know also take care of CPUs thatcognet2017-09-061-1/+2
| | | | | | | | | | | | | | | | provide a enable-method. Suggested by: jhibbits (cherry picked from commit 98ed6b1ee8ba9d265f4189bfdf133086ad342ca8)
* | ePAPR states that any non-boot CPU will come in "disabled" state. So we shouldcognet2017-09-061-2/+4
| | | | | | | | | | | | | | | | | | | | | | not consider a "disabled" cpu as a CPU we have to ignore, and we should use them if they provide a "enable-method". While I'm there, support "ok" as well as "okay", while ePAPR only accepts "okay", linux accepts "ok" too so we can expect it to be used. Reviewed by: andrew (partially) (cherry picked from commit 84ab3df4adf9b27d11793de058ed4c2f8d03f48c)
* | Remove NULL checks after M_WAITOK allocations from sys/dev/ofw/.trasz2017-09-062-18/+0
| | | | | | | | | | | | MFC after: 1 month (cherry picked from commit 0b7d27d494774c0baf3fafce4fe3e895818f9d90)
* | Enable OF_setprop API function to add property in FDTmw2017-09-061-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch modifies function ofw_fdt_setprop (called by OF_setprop), so that it can add property, when replacing is not possible. Adding property is needed to fixup FDT's that have missing properties. Submitted by: Patryk Duda <pdk@semihalf.com> Reviewed by: nwhitehorn, cognet (mentor) Approved by: cognet (mentor) Obtained from: Semihalf Differential Revision: https://reviews.freebsd.org/D11879 (cherry picked from commit 2fa55a61fb4c0037d48eeadbb04fccd9bff8949c)
* | Enable using ofw_bus_find_compatible in early platform codemw2017-09-061-10/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this patch function ofw_bus_find_compatible was using memory allocations in order to find compatible node and the property's length. This way there was always a suited buffer for property, however this approach had also disadvantages - ofw_bus_find_compatible couldn't be used when malloc is not available, e.g. during fdt fixup stage. In order to remove the usage limitation of ofw_bus_find_compatible(), this patch modifies the function to use ofw_bus_node_is_compatible() (instead of the one without _int suffix), which uses a fixed buffer on stack instead of dynamic allocations. Submitted by: Patryk Duda <pdk@semihalf.com> Reviewed by: nwhitehorn, cognet (mentor) Approved by: cognet (mentor) Obtained from: Semihalf Differential Revision: https://reviews.freebsd.org/D11880 (cherry picked from commit 60a68b05b32d206444247424d5c90b308f590d64)
* | Add support for "compatible" parameter in ofw_fdt_fixupmw2017-09-061-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sometimes it's convenient to provide fixup to many boards that use the same SoC family (eg. Marvell Armada 38x). Instead of putting multiple entries in fdt_fixup_table, use one entry which refers to all boards with given SoC. Submitted by: Patryk Duda <pdk@semihalf.com> Reviewed by: nwhitehorn, cognet (mentor) Approved by: cognet (mentor) Obtained from: Semihalf Differential Revision: https://reviews.freebsd.org/D11878 (cherry picked from commit c689953ee81351fb116da8e05e5df8ff777963cb)
* | Fix a hardcoded value.Luiz Souza2017-09-061-1/+1
| | | | | | | | (cherry picked from commit 1c3557fa39adee20222b5acd4c3eba78606b7382)
* | Enable color changes.Luiz Souza2017-09-061-0/+6
| | | | | | | | (cherry picked from commit 923a6ff4c0a60466abedecfbb945a3c290b9b1c3)
* | Setup a basic breath sequence on startup.Luiz Souza2017-09-062-18/+42
| | | | | | | | (cherry picked from commit f213dad2443a52a8e53f0ec95ac5b927b496a4b0)
* | Add a missing label.Luiz Souza2017-09-061-2/+2
| | | | | | | | (cherry picked from commit a27e0fa7123658fb226b9e2b4e515ee3d615f255)
* | Enhance Armada 38x SoC identification stringzbb2017-09-068-2/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add hw_clockrate and CPU frequency, basing on sample-at-reset configuration. Submitted by: Arnaud Ysmal <arnaud.ysmal@stormshield.eu> Marcin Wojtas <mw@semihalf.com> Obtained from: Stormshield, Semihalf Sponsored by: Stormshield Reviewed by: andrew Differential revision: https://reviews.freebsd.org/D10899 (cherry picked from commit 2fca7c984486fdc4650ecaf3b9b8a3109c6e00f2)
* | Enable HWPMC overflow IRQ on both CPUs in MPICzbb2017-09-062-2/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit enables usage of HWPMC interrupts for the Marvell SoCs, which use MPIC (Armada38x and ArmadaXP). Those interrupts require extra unmasking, comparing to others. Also, in order to process counters per-CPU, they are masked/unmasked using separate registers' sets for each core. Submitted by: Michal Mazur <mkm@semihalf.com> Marcin Wojtas <mw@semihalf.com> Obtained from: Semihalf Sponsored by: Stormshield, Netgate Differential revision: https://reviews.freebsd.org/D10913 (cherry picked from commit 9d6e7340c6b8293f3655371bbab9b1e4dc2fdb4f)
* | Introduce Armada 38x/XP network controller supportzbb2017-09-068-0/+5076
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch contains a new driver for the network unit of Marvell Armada 38x/XP SoCs, called NETA. This support was thoroughly tested and optimised in terms of stability and performance. Additional hardware features, like Buffer Management (BM) or Parser and Classifier (PnC) will be progressively supported as needed. Submitted by: Fabien Thomas <fabien.thomas@stormshield.eu> Arnaud Ysmal <arnaud.ysmal@stormshield.eu> Zbigniew Bodek <zbb@semihalf.com> Michal Mazur <mkm@semihalf.com> Bartosz Szczepanek <bsz@semihalf.com> Marcin Wojtas <mw@semihalf.com> Obtained from: Semihalf Sponsored by: Stormshield (main development) Netgate (cleanup and upstreaming) Differential revision: https://reviews.freebsd.org/D10706 (cherry picked from commit 3e7c6ed5082a0bc9bd208a60cc4f54c43c1b4ef7)
* | Add function to dump PCIE MBUS decoding windows and barszbb2017-09-061-1/+20
| | | | | | | | | | | | | | | | | | | | | | | | This commit allows to dump PCIE MBUS and bars configuration for Marvell platforms. Submitted by: Michal Mazur <mkm@semihalf.com> Obtained from: Semihalf Sponsored by: Netgate Differential revision: https://reviews.freebsd.org/D10908 (cherry picked from commit 3086783967281c5ed4f76508424074a7c1527ba6)
* | Support multi-port PCIe hierarchy in Marvell boards DTSzbb2017-09-063-8/+367
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit is another part of preparation for PCIe multi-port support for Marvell SoCs. Some device trees include pcie-controller node as a bus-parent of pcie nodes. This patch adds support for new bus, collects and configures device informations and finally adds PCIB devices as a childs of pcie-controller in Newbus hierarchy. Submitted by: Marcin Mazurek <mma@semihalf.com> Obtained form: Semihalf Sponsored by: Stormshield Reviewed by: https://reviews.freebsd.org/D10906 (cherry picked from commit 5dfa5d72e7cddc0a3078209cfcea38d9c436a9da)
* | Fix PCIe window decoding on Armada 38xzbb2017-09-061-26/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Original PCIe nodes for Marvell SoCs consists of ports' nodes under main controller node. In order to properly parse this kind of representation in DT a mechanism for traversing through the tree required an update. Moreover, processing FDT data consisting of more than 2 cells had to be fixed, because the 'reg' property of mrvl,pcie node have additional parameter in front of 64-bit address. It should be skipped by default. This commit works properly with old mrvl,pcie representation for Kirkwood and ArmadaXP SoCs. Submitted by: Wojciech Macek <wma@semihalf.com> Michal Mazur <mkm@semihalf.com> Obtained from: Semihalf Sponsored by: Stormshield, Netgate Differential revision: https://reviews.freebsd.org/D10905 (cherry picked from commit 1326a8a13d9c15b6bccd1f8039bbf8417d664d06)
* | Enable MBUS bridge configuration in mv_rtc driverzbb2017-09-061-12/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes sporadic problems with updating time with mv_rtc driver by configuring access to it via MBUS. For this purpose already existing second set of resources in rtc@3800 node of Armada 38x DT is used. Submitted by: Dominik Ermel <der@semihalf.com> Obtained from: Semihalf Sponsored by: Stormshield Differential revision: https://reviews.freebsd.org/D10901 (cherry picked from commit 553d3e55f3c7478a0531f47f4a50d437c7b03f80)
* | Add reset capability to mv_rtc driverzbb2017-09-061-0/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit enables optional reset of the RTC, in case its registers' contents did not sustain the reboot or power-off/on sequence. Without it, further usage of RTC is impossible (e.g. writing values to RTC_TIME register will not succeed). The reset is performed only if Clock Correction register does not comprise RTC_NOMINAL_TIMING, what helps to distinguish, whether the software configured RTC before or it comprises the default value. Submitted by: Bartosz Szczepanek <bsz@semihalf.com> Obtained from: Semihalf Sponsored by: Stormshield Differential revision: https://reviews.freebsd.org/D10900 (cherry picked from commit 15a9261debaaa6a9a0b6726589097f74c1171e8e)
* | Unmask legacy interrupts on Marvell PCIE controllerzbb2017-09-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes a bug introduced with commit: r294510 "Remove an extra '!' found by clang 3.8." '!' was removed without inverting the logic, which broke PCIe legacy interrupts operation for Marvell controllers. Submitted by: Michal Mazur <mkm@semihalf.com> Obtained from: Semihalf Sponsored by: Netgate (cherry picked from commit 359ab6c10b617f6e871ddf618ad5240463f62e27)
* | Add workaround for CESA MBUS windows with 4GB DRAMzbb2017-09-061-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Armada 38x SoC's equipped with 4GB DRAM suffer freeze during CESA operation, if MBUS window opened at given DRAM CS reaches end of the address space. Apply a workaround by setting the window size to the closest possible value, i.e. divide it by 2 (it has to be power-of-2). Submitted by: Marcin Wojtas <mw@semihalf.com> Obtained from: Semihalf Sponsored by: Stormshield Differential revision: https://reviews.freebsd.org/D10724 (cherry picked from commit 5fe68cd90c3b9cb2930e07d16f46cd91b1f05798)
* | Fix PM recognition on recent Marvell boardszbb2017-09-061-5/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | PM status is only supported on Kirkwood and Disvovery. Cleanup the code to properly report its state on other platforms. Submitted by: Wojciech Macek <wma@semihalf.com> Obtained from: Semihalf Sponsored by: Stormshield Differential revision: https://reviews.freebsd.org/D10718 (cherry picked from commit 235f0e77ca3a49c7d9891ea5e571656cffc0aa30)
* | Introduce separate watchdog driver for Armada to fix phony DELAYzbb2017-09-063-1/+287
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DELAY is a problematic routine called all over the kernel. Armada38x using CA-9 CPUs are using mpcore timer to count events and measure time but DELAY in the mpcore timer code is a weak function reference and therefore will be replaced by the platform implementation if the one is introduced. Since Armada38x uses on-chip watchdog to which the driver is merged with the on-chip timer driver there will be a platform DELAY implementation. The latter however will not use any HW timers as it will not attempt to configure any. Phony busy loop will be used instead. To fix that we introduce a separate watchdog driver for Armada platforms, (currently only A38X) and stop using Marvell timer driver. That switches DELAY to the desired implementation. Submitted by: Zbigniew Bodek <zbb@semihalf.com> Obtained from: Semihalf Sponsored by: Stormshield Differential revision: https://reviews.freebsd.org/D10710 (cherry picked from commit c43f8e7fa44b073c662d5fc0127b37d81300d8ef)
* | Enable SCU Speculative linefills to L2 on Armada 38xzbb2017-09-062-2/+7
| | | | | | | | | | | | | | | | | | Submitted by: Marcin Wojtas <mw@semihalf.com> Obtained from: Semihalf Sponsored by: Stormshield Differential revision: https://reviews.freebsd.org/D10709 (cherry picked from commit 97a43b91559c24c013107a1d55339d512975990a)
* | Fix memory corruption while configuring CPU windows on Marvell SoCszbb2017-09-061-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | Resolving CPU windows from localbus entry caused buffer overflow and memory corruption. Fix wrong indexing and ensure the index does not exceed table size. Submitted by: Wojciech Macek <wma@semihalf.com> Obtained from: Semihalf Sponsored by: Stormshield Differential revision: https://reviews.freebsd.org/D10720 (cherry picked from commit 2b25a3b2c3f4ee5c25038fd9e98e03fa04b8886e)
* | Fix boot up on ARMADA38X uniprocessor variantwma2017-09-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Marvell Armada 380 is a uni-processor variant of the 38x SoC family. A function platform_mp_setmaxid() was setting a hardcoded value, which caused boot fail on A380. Fix this by relying on the CPU count obtained from device tree nodes. Submitted by: Marcin Wojtas <mw@semihalf.com Obtained from: Semihalf Sponsored by: Netgate Reviewed by: loos Differential revision: https://reviews.freebsd.org/D10783 (cherry picked from commit e77dc5266b5a252931a0f7302a09776485840053)
* | Fix MPIC mask/unmaskwma2017-09-061-6/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | Before the fix for single interrupt, both percpu and non-percpu routes were enabled/disable at the same time. Submitted by: Marcin Wojtas <mw@semihalf.com Obtained from: Semihalf Sponsored by: Stormshield, Netgate Reviewed by: loos Differential revision: https://reviews.freebsd.org/D10716 (cherry picked from commit 910ae5e9b5b7a13cff3654d96e0300fc3294eac9)
* | Enable proper configuration of CESA MBUS windowswma2017-09-064-62/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For all Marvell devices, MBUS windows configuration is done in a common place. Only CESA was an exception, so move its related code from driver to mv_common.c. This way it uses same proper DRAM information, same as all other interfaces instead of parsing DT /memory node directly. Submitted by: Marcin Wojtas <mw@semihalf.com> Obtained from: Semihalf Sponsored by: Stormshield Reviewed by: loos Differential revision: https://reviews.freebsd.org/D10723 (cherry picked from commit d2baf237b6e2746345ef05787ad32aa5f4d82fdb)
* | Remove code for Marvell SoCs that lack a kernel config.andrew2017-09-065-123/+10
| | | | | | | | | | | | | | | | | | | | | | It seems to be old code from the armv6 project branch that never had a kernel config. Reviewed by: mmel Sponsored by: ABT Systems Lrd Differential Revision: https://reviews.freebsd.org/D7166 (cherry picked from commit 8222ebf9418922bf855c63b6ab194d97a57da266)
* | Use the MACROS to access the Global mpic registers. Makes the codeloos2017-09-061-31/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | consistent and easier to read. While here, remove two unused static functions and fix a unused function warning when building !INTRNG. No functional changes. Sponsored by: Rubicon Communications, LLC (Netgate) (cherry picked from commit cad66fd322c0b8cd11cef08d2fd21d9ef3129c92)
* | Fix registration of MPIC driverzbb2017-09-061-0/+3
| | | | | | | | | | | | | | | | | | | | Submitted by: Michal Mazur <mkm@semihalf.com> Obtained from: Semihalf Sponsored by: Netgate Reviewed by: loos Differential revision: https://reviews.freebsd.org/D10717 (cherry picked from commit 254aea0839072bee0564ecf4cd0ca98b1ddf4c3f)
* | Correct MPIC order of attachmentzbb2017-09-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If MPIC happens to be a slave interrupt controller (as on Armada38x), it should be attached after primary interrupt controller. Thus BUS_PASS_ORDER_LATE was added to default BUS_PASS_INTERRUPT. This change doesn't affect the cases when MPIC is standalone IC. Submitted by: Bartosz Szczepanek <bsz@semihalf.com> Obtained from: Semihalf Sponsored by: Stormshield, Netgate Reviewed by: loos Differential revision: https://reviews.freebsd.org/D10715 (cherry picked from commit 19cc118b1fef30a90f205f6d75f86a8069b5594e)
* | Enable proper parsing of nested simlpe-buses on Marvell platformszbb2017-09-061-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | OF_finddevice doesn't find the "simple-bus" node, which is problematic for Marvell platforms, using nested buses in Device Tree, like Armada 38x SoC. Submitted by: Arnaud Ysmal <arnaud.ysmal@stormshield.eu> Obtained from: Stormshield Sponsored by: Stormshield Reviewed by: loos Differential revision: https://reviews.freebsd.org/D10719 (cherry picked from commit ba51542898f2b1b3251d828766db2e888803229f)
* | Parse EHCI windows on Marvell platformszbb2017-09-061-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Add missing compatibility string to allow proper window configuration for EHCI devices. Submitted by: Wojciech Macek <wma@semihalf.com> Obtained from: Semihalf Sponsored by: Stormshield Reviewed by: loos Differential revision: https://reviews.freebsd.org/D10722 (cherry picked from commit b7d47a1821299aed903befda7938cf57fef41e63)
* | Fix USB3.0 decoding windows on Armada38xzbb2017-09-061-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Set correct offset for MBUS windows configuration in USB3.0 interface. Submitted by: Marcin Wojtas <mw@semihalf.com> Obtained from: Semihalf Sponsored by: Stormshield Reviewed by: loos Differential revision: https://reviews.freebsd.org/D10721 (cherry picked from commit e17167eae3edaaf148d536e5b8ff465c6b1c623a)
* | Move the IO Window Control Register defines out of the ARMADA38X ifdef.loos2017-09-061-12/+12
| | | | | | | | | | | | | | | | Fixes the build of Marvell kernels (other than ARMADA38X) after r318336. Reported by: mmel (cherry picked from commit 3ed60ab87519141541888838ef7a341a794b4c6a)
* | Add the Marvell SDHCI controller to the list of supported devices inloos2017-09-063-4/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | sdhci_fdt. Enable the SDHCI controller, bus and devices on ARMADA38X kernel. Tested on: ClearFog Pro Reviewed by: Marcin Wojtas <mw at semihalf.com> Sponsored by: Rubicon Communications, LLC (Netgate) Differential Revision: https://reviews.freebsd.org/D10606 (cherry picked from commit 6eed58e1e7a446d544071e71438ff60592bfa246)
* | Add the SDHCI Address Decoder registers and routines for ARMADA 38X.loos2017-09-062-1/+69
| | | | | | | | | | | | | | | | | | Tested on: ClearFog Pro Reviewed by: Marcin Wojtas <mw at semihalf.com> Sponsored by: Rubicon Communications, LLC (Netgate) Differential Revision: https://reviews.freebsd.org/D10601 (cherry picked from commit 4137b139d931bc3a5a5e2d84b5de3d0e9566df1e)
* | Optimize Armada38x low-level MBUS settingszbb2017-09-063-0/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add early init handler, which comprises various internal bus optimisations for Armada 38x SoC's. Magic values used due to undocumented registers. Submitted by: Marcin Wojtas <mw@semihalf.com>, Arnaud Ysmal <arnaud.ysmal@stormshield.eu> Obtained from: Semihalf, Stormshield Sponsored by: Stormshield Differential revision: https://reviews.freebsd.org/D10219 (cherry picked from commit 7d6a36a63bdfb8ffc82b06de7b79b89980ad26bf)
* | Add PL310 platform initialization for Armada 38xzbb2017-09-062-0/+75
| | | | | | | | | | | | | | | | | | | | | | | | Introduce machine-dependent part of the arm/pl310 driver for Armada 38x SoCs. Add prefetch and power savings configuration. Submitted by: <arnaud.ysmal@stormshield.eu> Obtained from: Stormshield Sponsored by: Stormshield Differential revision: https://reviews.freebsd.org/D10220 (cherry picked from commit a12ea9b1d6d0766e3eece3377ff411ad1dff7120)
* | Make fdt_pm_mask_table internal to the Marvell code, it's unued anywhereandrew2017-09-062-7/+6
| | | | | | | | | | | | | | | | else. Sponsored by: ABT Systems Ltd (cherry picked from commit 78000f6960a3b3bd50ac7ce7d2514e9a5f07a237)
* | Add dummy functions for Marvell SoC's not equipped with AHCIwma2017-09-061-3/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit r312747 ("Setup decoding windows for ARMADA38X") resulted in build failing for Marvell platforms, which don't have AHCI controller. This patch provides a fix by adding dummy functions for such cases. On the occasion rename register dump routine to decode_win_ahci_dump, in order to avoid confusion. Submitted by: Marcin Wojtas <mw@semihalf.com> Obtained from: Semihalf Sponsored by: Stormshield (cherry picked from commit 60cc8a6c2eb69d1feb1bc8028c78eb5aedc7434f)
* | Add support for AHCI on ARMADA38Xwma2017-09-063-0/+160
| | | | | | | | | | | | | | | | | | | | | | | | | | This file provides support for AHCI mode on Armada38x and adds new optional AHCI device to arm/mv/files.mv. Submitted by: Konrad Adamczyk <ka@semihalf.com> Obtained from: Semihalf Sponsored by: Stormshield Reviewed by: zbb Differential revision: https://reviews.freebsd.org/D9222 (cherry picked from commit fe61d0f11bd46101781aaf1c4c8bea8f63b91a7b)
* | Setup decoding windows for ARMADA38Xwma2017-09-062-0/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | It is necesarry to open memory windows on internal bus for AHCI driver to work correctly. Submitted by: Konrad Adamczyk <ka@semihalf.com> Obtained from: Semihalf Sponsored by: Stormshield Reviewed by: zbb Differential revision: https://reviews.freebsd.org/D9220 (cherry picked from commit 505dcaf940283419400d42e3a8d2f2ccbd44b648)
* | Fix node detection for MBUS windows configurationwma2017-09-061-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | Configure decoding windows only for devices with enabled nodes in FDT. Submitted by: Konrad Adamczyk <ka@semihalf.com> Obtained from: Semihalf Sponsored by: Stormshield Reviewed by: zbb Differential revision: https://reviews.freebsd.org/D9219 (cherry picked from commit decc77502736796658c1b60b647b02dfdd1c448a)
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