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* When we return with an error we cannot unlock the mutex, becausegnn2012-08-011-1/+2
| | | | | | | it's been freed. Protect against that, hopefully unlikely, case. Reviewed by: rpaulo MFC after: 2 weeks
* replace inet_ntoa_r with the more standard inet_ntop().luigi2012-08-012-10/+12
| | | | | | | | As discussed on -current, inet_ntoa_r() is non standard, has different arguments in userspace and kernel, and almost unused (no clients in userspace, only net/flowtable.c, net/if_llatbl.c, netinet/in_pcb.c, netinet/tcp_subr.c in the kernel)
* add a cast to avoid a signed/unsigned warning (to be removedluigi2012-08-011-1/+1
| | | | when we will have TUNABLE_UINT constructors)
* - Add myself to calendar.freebsdbdrewery2012-08-012-0/+4
| | | | | | - Add my mentor relationships to committers-ports.dot Approved by: eadler (mentor)
* Do a trivial reformatting of the comment, to record the proper commitkib2012-08-011-2/+1
| | | | | | | | | | | | | | | | | | | | | | | message for r238973: Rdtsc instruction is not synchronized, it seems on some Intel cores it can bypass even the locked instructions. As a result, rdtsc executed on different cores may return unordered TSC values even when the rdtsc appearance in the instruction sequences is provably ordered. Similarly to what has been done in r238755 for TSC synchronization test, add explicit fences right before rdtsc in the timecounters 'get' functions. Intel recommends to use LFENCE, while AMD refers to MFENCE. For VIA follow what Linux does and use LFENCE. With this change, I see no reordered reads of TSC on Nehalem. Change the rmb() to inlined CPUID in the SMP TSC synchronization test. On i386, locked instruction is used for rmb(), and as noted earlier, it is not enough. Since i386 machine may not support SSE2, do simplest possible synchronization with CPUID. MFC after: 1 week Discussed with: avg, bde, jkim
* Several fixes to allow firmware/BIOS flash access from user-level:mav2012-08-014-64/+41
| | | | | | | | | | | | | | - remove special handling of zero length transfers in mpi_pre_fw_upload(); - add missing MPS_CM_FLAGS_DATAIN flag in mpi_pre_fw_upload(); - move mps_user_setup_request() call into proper place; - increase user command timeout from 30 to 60 seconds; - avoid NULL dereference panic in case of firmware crash. Set max DMA segment size to 24bit, as MPI SGE supports it. Use mps_add_dmaseg() to add empty SGE instead of custom code. Tune endianness safety. Reviewed by: Desai, Kashyap <Kashyap.Desai@lsi.com> Sponsored by: iXsystems, Inc.
* diff --git a/sys/x86/x86/tsc.c b/sys/x86/x86/tsc.ckib2012-08-011-14/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | index c253a96..3d8bd30 100644 --- a/sys/x86/x86/tsc.c +++ b/sys/x86/x86/tsc.c @@ -82,7 +82,11 @@ static void tsc_freq_changed(void *arg, const struct cf_level *level, static void tsc_freq_changing(void *arg, const struct cf_level *level, int *status); static unsigned tsc_get_timecount(struct timecounter *tc); -static unsigned tsc_get_timecount_low(struct timecounter *tc); +static inline unsigned tsc_get_timecount_low(struct timecounter *tc); +static unsigned tsc_get_timecount_lfence(struct timecounter *tc); +static unsigned tsc_get_timecount_low_lfence(struct timecounter *tc); +static unsigned tsc_get_timecount_mfence(struct timecounter *tc); +static unsigned tsc_get_timecount_low_mfence(struct timecounter *tc); static void tsc_levels_changed(void *arg, int unit); static struct timecounter tsc_timecounter = { @@ -262,6 +266,10 @@ probe_tsc_freq(void) (vm_guest == VM_GUEST_NO && CPUID_TO_FAMILY(cpu_id) >= 0x10)) tsc_is_invariant = 1; + if (cpu_feature & CPUID_SSE2) { + tsc_timecounter.tc_get_timecount = + tsc_get_timecount_mfence; + } break; case CPU_VENDOR_INTEL: if ((amd_pminfo & AMDPM_TSC_INVARIANT) != 0 || @@ -271,6 +279,10 @@ probe_tsc_freq(void) (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x3)))) tsc_is_invariant = 1; + if (cpu_feature & CPUID_SSE2) { + tsc_timecounter.tc_get_timecount = + tsc_get_timecount_lfence; + } break; case CPU_VENDOR_CENTAUR: if (vm_guest == VM_GUEST_NO && @@ -278,6 +290,10 @@ probe_tsc_freq(void) CPUID_TO_MODEL(cpu_id) >= 0xf && (rdmsr(0x1203) & 0x100000000ULL) == 0) tsc_is_invariant = 1; + if (cpu_feature & CPUID_SSE2) { + tsc_timecounter.tc_get_timecount = + tsc_get_timecount_lfence; + } break; } @@ -328,16 +344,31 @@ init_TSC(void) #ifdef SMP -/* rmb is required here because rdtsc is not a serializing instruction. */ -#define TSC_READ(x) \ -static void \ -tsc_read_##x(void *arg) \ -{ \ - uint32_t *tsc = arg; \ - u_int cpu = PCPU_GET(cpuid); \ - \ - rmb(); \ - tsc[cpu * 3 + x] = rdtsc32(); \ +/* + * RDTSC is not a serializing instruction, and does not drain + * instruction stream, so we need to drain the stream before executing + * it. It could be fixed by use of RDTSCP, except the instruction is + * not available everywhere. + * + * Use CPUID for draining in the boot-time SMP constistency test. The + * timecounters use MFENCE for AMD CPUs, and LFENCE for others (Intel + * and VIA) when SSE2 is present, and nothing on older machines which + * also do not issue RDTSC prematurely. There, testing for SSE2 and + * vendor is too cumbersome, and we learn about TSC presence from + * CPUID. + * + * Do not use do_cpuid(), since we do not need CPUID results, which + * have to be written into memory with do_cpuid(). + */ +#define TSC_READ(x) \ +static void \ +tsc_read_##x(void *arg) \ +{ \ + uint32_t *tsc = arg; \ + u_int cpu = PCPU_GET(cpuid); \ + \ + __asm __volatile("cpuid" : : : "eax", "ebx", "ecx", "edx"); \ + tsc[cpu * 3 + x] = rdtsc32(); \ } TSC_READ(0) TSC_READ(1) @@ -487,7 +518,16 @@ init: for (shift = 0; shift < 31 && (tsc_freq >> shift) > max_freq; shift++) ; if (shift > 0) { - tsc_timecounter.tc_get_timecount = tsc_get_timecount_low; + if (cpu_feature & CPUID_SSE2) { + if (cpu_vendor_id == CPU_VENDOR_AMD) { + tsc_timecounter.tc_get_timecount = + tsc_get_timecount_low_mfence; + } else { + tsc_timecounter.tc_get_timecount = + tsc_get_timecount_low_lfence; + } + } else + tsc_timecounter.tc_get_timecount = tsc_get_timecount_low; tsc_timecounter.tc_name = "TSC-low"; if (bootverbose) printf("TSC timecounter discards lower %d bit(s)\n", @@ -599,16 +639,48 @@ tsc_get_timecount(struct timecounter *tc __unused) return (rdtsc32()); } -static u_int +static inline u_int tsc_get_timecount_low(struct timecounter *tc) { uint32_t rv; __asm __volatile("rdtsc; shrd %%cl, %%edx, %0" - : "=a" (rv) : "c" ((int)(intptr_t)tc->tc_priv) : "edx"); + : "=a" (rv) : "c" ((int)(intptr_t)tc->tc_priv) : "edx"); return (rv); } +static u_int +tsc_get_timecount_lfence(struct timecounter *tc __unused) +{ + + lfence(); + return (rdtsc32()); +} + +static u_int +tsc_get_timecount_low_lfence(struct timecounter *tc) +{ + + lfence(); + return (tsc_get_timecount_low(tc)); +} + +static u_int +tsc_get_timecount_mfence(struct timecounter *tc __unused) +{ + + mfence(); + return (rdtsc32()); +} + +static u_int +tsc_get_timecount_low_mfence(struct timecounter *tc) +{ + + mfence(); + return (tsc_get_timecount_low(tc)); +} + uint32_t cpu_fill_vdso_timehands(struct vdso_timehands *vdso_th) {
* Add lfence().kib2012-08-012-0/+14
| | | | MFC after: 1 week
* Revise pmap_enter()'s handling of mapping updates that change thealc2012-08-011-22/+30
| | | | | | | | | | | | | | PTE's PG_M and PG_RW bits but not the physical page frame. First, only perform vm_page_dirty() on a managed vm_page when the PG_M bit is being cleared. If the updated PTE continues to have PG_M set, then there is no requirement to perform vm_page_dirty(). Second, flush the mapping from the TLB when PG_M alone is cleared, not just when PG_M and PG_RW are cleared. Otherwise, a stale TLB entry may stop PG_M from being set again on the next store to the virtual page. However, since the vm_page's dirty field already shows the physical page as being dirty, no actual harm comes from the PG_M bit not being set. Nonetheless, it is potentially confusing to someone expecting to see the PTE change after a store to the virtual page.
* Fix kernel panic on `camcontrol reset` for specific target, caused bymav2012-08-011-0/+1
| | | | | | | | uninitialized cm_targ in mpssas_action_resetdev(). Reviewed by: Desai, Kashyap <Kashyap.Desai@lsi.com> Sponsored by: iXsystems, Inc. MFC after: 3 days
* Restore a piece of BSD history.des2012-08-011-3/+3
| | | | | | PR: 169127 Submitted by: Ruben de Groot <ruben@hacktor.com> MFC after: 1 week
* Some more whitespace cleanup.glebius2012-08-014-21/+21
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* Add the chip select glue.imp2012-08-012-0/+6
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* Teach md5(1) about sha512.delphij2012-08-013-10/+36
| | | | MFC after: 1 month
* Use calloc().delphij2012-08-011-2/+1
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* Fix a case of "mis-located braces".adrian2012-08-011-2/+2
| | | | PR: kern/170302
* Allow 802.11n hardware to support multi-rate retry when RTS/CTS isadrian2012-07-314-7/+24
| | | | | | | | | | | | | | | | enabled. The legacy (pre-802.11n) hardware doesn't support this - although the AR5212 era hardware supports MRR, it doesn't have all the bits needed to support MRR + RTS/CTS. The AR5416 and later support a packet duration and RTS/CTS flags per rate scenario, so we should support it. Tested: * AR9280, STA PR: kern/170302
* In case of IPsec he have to do delayed checksum calculations beforebz2012-07-311-0/+14
| | | | | | | | | adding any extension header, or rather before calling into IPsec processing as we may send the packet and not return to IPv6 output processing here. PR: kern/170116 MFC After: 3 days
* Prefer ate over macb. macb doesn't work anymore, and ate has moreimp2012-07-314-4/+1
| | | | errata workarounds in it.
* Note about where we can boot this.imp2012-07-311-1/+2
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* Allow chip selects other than 0. The SAM9260EK boardimp2012-07-311-4/+14
| | | | has its dataflash on CS1.
* Restore the PCI bridge configuration upon resume.adrian2012-07-311-0/+5
| | | | | | | | | | | This allows my TI1510 cardbus/PCI bridge to work after a suspend/resume, without having to unload/reload the cbb driver. I've also tested this on stable/9. I'll MFC it shortly. PR: kern/170058 Reviewed by: jhb MFC after: 1 day
* Clean up some unused leftover code from emjfv2012-07-311-74/+30
| | | | | | | Make IRQ style a tuneable Fix lock handling in the interrupt handler MFC after:3 days
* Reorder the managament of advisory locks on open files so that the advisoryjhb2012-07-312-43/+61
| | | | | | | | | | | | | | | | | | | | | | lock is obtained before the write count is increased during open() and the lock is released after the write count is decreased during close(). The first change closes a race where an open() that will block with O_SHLOCK or O_EXLOCK can increase the write count while it waits. If the process holding the current lock on the file then tries to call exec() on the file it has locked, it can fail with ETXTBUSY even though the advisory lock is preventing other threads from succesfully completeing a writable open(). The second change closes a race where a read-only open() with O_SHLOCK or O_EXLOCK may return successfully while the write count is non-zero due to another descriptor that had the advisory lock and was blocking the open() still being in the process of closing. If the process that completed the open() then attempts to call exec() on the file it locked, it can fail with ETXTBUSY even though the other process that held a write lock has closed the file and released the lock. Reviewed by: kib MFC after: 1 month
* Fix wrong indent according to style(9)mm2012-07-311-2/+2
| | | | | | | | | | | | | | | MFC after: 2 weeks > Description of fields to fill in above: 76 columns --| > PR: If a GNATS PR is affected by the change. > Submitted by: If someone else sent in the change. > Reviewed by: If someone else reviewed your modification. > Approved by: If you needed approval for this commit. > Obtained from: If the change is from a third party. > MFC after: N [day[s]|week[s]|month[s]]. Request a reminder email. > Security: Vulnerability reference (one per line) or description. > Empty fields above will be automatically removed. M zpool_main.c
* Fix reporting of root pool upgrade notice.mm2012-07-311-19/+19
| | | | MFC after: 2 weeks
* Shuffle the call to ath_hal_setuplasttxdesc() to _after_ the rate controladrian2012-07-312-31/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | code is called and remove it from ath_buf_set_rate(). For the legacy (non-11n API) TX routines, ath_hal_filltxdesc() takes care of setting up the intermediary and final descriptors right, complete with copying the rate control info into the final descriptor so the rate modules can grab it. The 11n version doesn't do this - ath_hal_chaintxdesc() doesn't copy the rate control bits over, nor does it clear isaggr/moreaggr/ pad delimiters. So the call to setuplasttxdesc() is needed here. So: * legacy NICs - never call the 11n rate control stuff, so filltxdesc copies the rate control info right; * 11n NICs transmitting legacy or 11n non-aggregate frames - ath_hal_set11nratescenario() is called to setup rate control and then ath_hal_filltxdesc() chains them together - so the rate control info is right; * 11n aggregate frames - set11nratescenario() is called, then ath_hal_chaintxdesc() is called to chain a list of aggregate and subframes together. This requires a call to ath_hal_setuplasttxdesc() to complete things. Tested: * AR9280 in station mode TODO: * I really should make sure that the descriptor contents get blanked out correctly or garbage left over from aggregate frames may show up in non-aggregate frames, leading to badness.
* find: Remove unnecessary and inconsistent initialization.jilles2012-07-311-1/+1
| | | | Submitted by: jhb
* Push the rate control and descriptor chaining into the descriptor "set"adrian2012-07-311-61/+52
| | | | | | | | | | | | | | | | | | | | | | | functions, for both legacy and 802.11n. This will simplify supporting the EDMA chipsets as these two descriptor setup functions can just be overridden in their entirety, hiding all of the subtle differences in setting things up. It's not a permanent solution, as eventually the AR5416 HAL should grow similar versions of the 11n descriptor functions and then those can be used. TODO: * Push the "clr11naggr" call into the legacy setds, just to ensure that retried frames don't end up with the aggregate bits set inappropriately; * Remove the "setlasttxdesc" call from the 11n TX path and push it into setds_11n. * Ensure that setds_11n will work correctly for non-aggregate frames; * .. and then when it does, just unconditionally call "setds_11n" for 11n NICs and "setds" for non-11n NICs.
* Some style(9) and whitespace changes.glebius2012-07-315-126/+116
| | | | Together with: Andrey Zonov <andrey zonov.org>
* Add several performance optimizations to acpi_cpu_idle().mav2012-07-311-11/+21
| | | | | | | | | | | | | | | | | | | | | | For C1 and C2 states use cpu_ticks() to measure sleep time instead of much slower ACPI timer. We can't do it for C3, as TSC may stop there. But it is less important there as wake up latency is high any way. For C1 and C2 states do not check/clear bus mastering activity status, as it is important only for C3. As side effect it can make CPU enter C2 instead of C3 if last BM activity was two sleeps back (unlike one before), but that may be even good because of collecting more statistics. Premature BM wakeup from C3, entered because of overestimation, can easily be worse then entering C2 from both performance and power consumption points of view. Together on dual Xeon E5645 system on sequential 512 bytes read test this change makes cpu_idle_acpi() as fast as simplest cpu_idle_hlt() and only few percents slower then cpu_idle_mwait(), while deeper states are still actively used during idle periods. To help with diagnostics, add C-state type into dev.cpu.X.cx_supported. Sponsored by: iXsystems, Inc.
* Fixed some debug output in hwmp_recv_prep.monthadar2012-07-311-3/+3
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* nobody uses this file except the userspace ipfw code, but the castluigi2012-07-311-1/+1
| | | | | | | of a pointer to an integer needs a cast to prevent a warning for size mismatch. MFC after: 1 week
* Fix a PREQ comparison error in 11s HWMP.monthadar2012-07-311-3/+4
| | | | | | | | * Earlier we compared two not equal metrics, one was what we recevied in the 'new PREQ' while the other was what we already have saved which was 'old PREQ' + link metric for the last hop; * Fixed by adding 'new PREQ' + link metric for the last hop in a temporary variable;
* Fix bugs in net80211s found with wtap simulator.monthadar2012-07-311-4/+6
| | | | | | | For description of the test scripts refer to projects/net80211_testsuite/wtap. * Test 007 showed a bug in intermediate PREP for a proxy entry. Resolved; * Test 002 showed a bug in the Addressing Mode flag for a PREQ. Resolved;
* Fix wtap to not panic in wtap_beacon_intrp.monthadar2012-07-311-2/+6
| | | | | | | * Changed KASSERT to be debug printf (DWTAP_PRINTF). If state is not IEEE80211_S_RUN we return without scheduling a new callout; * When net80211 stack changes state to IEEE802_11_INIT we stop the beacon callout task;
* remove a redundant MALLOC_DECLAREluigi2012-07-311-4/+0
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* I am comparing current pipe code with the one in 8.3-STABLE r236165,davidxu2012-07-313-19/+6
| | | | | | | | | | | | | | | | | | | | | | | | I found 8.3 is a history BSD version using socket to implement FIFO pipe, it uses per-file seqcount to compare with writer generation stored in per-pipe object. The concept is after all writers are gone, the pipe enters next generation, all old readers have not closed the pipe should get the indication that the pipe is disconnected, result is they should get EPIPE, SIGPIPE or get POLLHUP in poll(). But newcomer should not know that previous writters were gone, it should treat it as a fresh session. I am trying to bring back FIFO pipe to history behavior. It is still unclear that if single EOF flag can represent SBS_CANTSENDMORE and SBS_CANTRCVMORE which socket-based version is using, but I have run the poll regression test in tool directory, output is same as the one on 8.3-STABLE now. I think the output "not ok 18 FIFO state 6b: poll result 0 expected 1. expected POLLHUP; got 0" might be bogus, because newcomer should not know that old writers were gone. I got the same behavior on Linux. Our implementation always return POLLIN for disconnected pipe even it should return POLLHUP, but I think it is not wise to remove POLLIN for compatible reason, this is our history behavior. Regression test: /usr/src/tools/regression/poll
* Properly apply #ifdef INET and leave a comment that we are (will) applybz2012-07-311-3/+3
| | | | | | | delayed IPv6 checksum processing in ip6_output.c when doing IPsec. PR: kern/170116 MFC after: 3 days
* Improve the should-never-hit printf to ease debugging in case we'd ever hitbz2012-07-311-2/+3
| | | | | | it again when doing the delayed IPv6 checksum calculations. MFC after: 3 days
* - Change back "d_ofs" to int8_t to not pessimize padding and size of "struct ↵fjoe2012-07-312-6/+15
| | | | | | | | | puc_cfg". - Use "puc_config_moxa" for Moxa boards that need d_ofs greater than 0x7f Prodded by: marcel@, gavin@ MFC after: 3 days
* macb doesn't work, switch to ate.imp2012-07-311-2/+1
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* Migrate some more TX side setup routines to be methods.adrian2012-07-316-18/+86
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* Break out the hardware handoff and TX DMA restart code into methods.adrian2012-07-313-4/+70
| | | | | | | | These (and a few others) will differ based on the underlying DMA implementation. For the EDMA NICs, simply stub them out in a fashion which will let me focus on implementing the necessary descriptor API changes.
* Placeholder ioctl for an upcoming rate control statistics API change.adrian2012-07-311-0/+1
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* When a thread is blocked in direct write state, it only sets PIPE_DIRECTWdavidxu2012-07-313-6/+12
| | | | | | | | | | | | | | | | | | | | | flag but not PIPE_WANTW, but FIFO pipe code does not understand this internal state, when a FIFO peer reader closes the pipe, it wants to notify the writer, it checks PIPE_WANTW, if not set, it skips calling wakeup(), so blocked writer never noticed the case, but in general, the writer should return from the syscall with EPIPE error code and may get SIGPIPE signal. Setting the PIPE_WANTW fixed problem, or you can turn off direct write, it should fix the problem too. This bug is found by PR/170203. Another bug in FIFO pipe code is when peer closes the pipe, another end which is being blocked in select() or poll() is not notified, it missed to call pipeselwakeup(). Third problem is found in poll regression test, the existing code can not pass 6b,6c,6d tests, but FreeBSD-4 works. This commit does not fix the problem, I still need to study more to find the cause. PR: 170203 Tested by: Garrett Copper &lt; yanegomi at gmail dot com &gt;
* Partial MFV (illumos-gate 13753:2aba784c276b)mm2012-07-3011-119/+417
| | | | | | | | | 2762 zpool command should have better support for feature flags References: https://www.illumos.org/issues/2762 MFC after: 2 weeks
* Until now KTR_ENTRIES, which defines the size of circular buffer used indavide2012-07-302-3/+3
| | | | | | | | | ktr(4), was constrained to be a power of two. Remove this constraint and update sys/conf/NOTES accordingly. Reviewed by: jhb Approved by: gnn (mentor) Sponsored by: Google Summer of Code 2012
* ieeefp.h is only needed on i386 class hardware.kargl2012-07-301-0/+2
| | | | | Submitted by: bde Approved by: das (pre-approved)
* Whitespace.kargl2012-07-303-4/+3
| | | | | Submitted by: bde Approved by: das (pre-approved)
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