diff options
Diffstat (limited to 'utils/TableGen')
47 files changed, 1928 insertions, 844 deletions
diff --git a/utils/TableGen/ARMDecoderEmitter.cpp b/utils/TableGen/ARMDecoderEmitter.cpp index a8de745..62bd1c6 100644 --- a/utils/TableGen/ARMDecoderEmitter.cpp +++ b/utils/TableGen/ARMDecoderEmitter.cpp @@ -607,7 +607,7 @@ void ARMFilter::recurse() { for (bitIndex = 0; bitIndex < NumBits; bitIndex++) BitValueArray[StartBit + bitIndex] = BIT_UNSET; - // Delegates to an inferior filter chooser for futher processing on this + // Delegates to an inferior filter chooser for further processing on this // group of instructions whose segment values are variable. FilterChooserMap.insert(std::pair<unsigned, ARMFilterChooser*>( (unsigned)-1, @@ -639,7 +639,7 @@ void ARMFilter::recurse() { BitValueArray[StartBit + bitIndex] = BIT_FALSE; } - // Delegates to an inferior filter chooser for futher processing on this + // Delegates to an inferior filter chooser for further processing on this // category of instructions. FilterChooserMap.insert(std::pair<unsigned, ARMFilterChooser*>( mapIterator->first, @@ -1382,7 +1382,7 @@ bool ARMFilterChooser::emit(raw_ostream &o, unsigned &Indentation) { // 2. source registers are identical => VMOVQ; otherwise => VORRq // 3. LDR, LDRcp => return LDR for now. // FIXME: How can we distinguish between LDR and LDRcp? Do we need to? - // 4. tLDM, tLDM_UPD => Rn = Inst{10-8}, reglist = Inst{7-0}, + // 4. tLDMIA, tLDMIA_UPD => Rn = Inst{10-8}, reglist = Inst{7-0}, // wback = registers<Rn> = 0 // NOTE: (tLDM, tLDM_UPD) resolution must come before Advanced SIMD // addressing mode resolution!!! @@ -1423,7 +1423,7 @@ bool ARMFilterChooser::emit(raw_ostream &o, unsigned &Indentation) { << "; // Returning LDR for {LDR, LDRcp}\n"; return true; } - if (name1 == "tLDM" && name2 == "tLDM_UPD") { + if (name1 == "tLDMIA" && name2 == "tLDMIA_UPD") { // Inserting the opening curly brace for this case block. --Indentation; --Indentation; o.indent(Indentation) << "{\n"; @@ -1570,9 +1570,7 @@ ARMDEBackend::populateInstruction(const CodeGenInstruction &CGI, return false; if (TN == TARGET_ARM) { - // FIXME: what about Int_MemBarrierV6 and Int_SyncBarrierV6? - if ((Name != "Int_MemBarrierV7" && Name != "Int_SyncBarrierV7") && - Form == ARM_FORMAT_PSEUDO) + if (Form == ARM_FORMAT_PSEUDO) return false; if (thumbInstruction(Form)) return false; @@ -1586,61 +1584,18 @@ ARMDEBackend::populateInstruction(const CodeGenInstruction &CGI, Name == "MOVr_TC") return false; + // Delegate ADR disassembly to the more generic ADDri/SUBri instructions. + if (Name == "ADR") + return false; + // // The following special cases are for conflict resolutions. // - // NEON NLdStFrm conflict resolutions: - // - // 1. Ignore suffix "odd" and "odd_UPD", prefer the "even" register- - // numbered ones which have the same Asm format string. - // 2. Ignore VST2d64_UPD, which conflicts with VST1q64_UPD. - // 3. Ignore VLD2d64_UPD, which conflicts with VLD1q64_UPD. - // 4. Ignore VLD1q[_UPD], which conflicts with VLD1q64[_UPD]. - // 5. Ignore VST1q[_UPD], which conflicts with VST1q64[_UPD]. - if (Name.endswith("odd") || Name.endswith("odd_UPD") || - Name == "VST2d64_UPD" || Name == "VLD2d64_UPD" || - Name == "VLD1q" || Name == "VLD1q_UPD" || - Name == "VST1q" || Name == "VST1q_UPD") - return false; - // RSCSri and RSCSrs set the 's' bit, but are not predicated. We are // better off using the generic RSCri and RSCrs instructions. if (Name == "RSCSri" || Name == "RSCSrs") return false; - // MOVCCr, MOVCCs, MOVCCi, MOVCCi16, FCYPScc, FCYPDcc, FNEGScc, and - // FNEGDcc are used in the compiler to implement conditional moves. - // We can ignore them in favor of their more generic versions of - // instructions. See also SDNode *ARMDAGToDAGISel::Select(SDValue Op). - if (Name == "MOVCCr" || Name == "MOVCCs" || Name == "MOVCCi" || - Name == "MOVCCi16" || Name == "FCPYScc" || Name == "FCPYDcc" || - Name == "FNEGScc" || Name == "FNEGDcc") - return false; - - // Ditto for VMOVDcc, VMOVScc, VNEGDcc, and VNEGScc. - if (Name == "VMOVDcc" || Name == "VMOVScc" || Name == "VNEGDcc" || - Name == "VNEGScc") - return false; - - // LDMIA_RET is a special case of LDM (Load Multiple) where the registers - // loaded include the PC, causing a branch to a loaded address. Ignore - // the LDMIA_RET instruction when decoding. - if (Name == "LDMIA_RET") return false; - - // Bcc is in a more generic form than B. Ignore B when decoding. - if (Name == "B") return false; - - // Ignore the non-Darwin BL instructions and the TPsoft (TLS) instruction. - if (Name == "BL" || Name == "BL_pred" || Name == "BLX" || Name == "BX" || - Name == "TPsoft") - return false; - - // Ignore VDUPf[d|q] instructions known to conflict with VDUP32[d-q] for - // decoding. The instruction duplicates an element from an ARM core - // register into every element of the destination vector. There is no - // distinction between data types. - if (Name == "VDUPfd" || Name == "VDUPfq") return false; - // A8-598: VEXT // Vector Extract extracts elements from the bottom end of the second // operand vector and the top end of the first, concatenates them and @@ -1656,34 +1611,23 @@ ARMDEBackend::populateInstruction(const CodeGenInstruction &CGI, if (Name == "VEXTd16" || Name == "VEXTd32" || Name == "VEXTdf" || Name == "VEXTq16" || Name == "VEXTq32" || Name == "VEXTqf") return false; - - // Vector Reverse is similar to Vector Extract. There is no distinction - // between data types, other than size. - // - // VREV64df is equivalent to VREV64d32. - // VREV64qf is equivalent to VREV64q32. - if (Name == "VREV64df" || Name == "VREV64qf") return false; - - // VDUPLNfd is equivalent to VDUPLN32d. - // VDUPLNfq is equivalent to VDUPLN32q. - // VLD1df is equivalent to VLD1d32. - // VLD1qf is equivalent to VLD1q32. - // VLD2d64 is equivalent to VLD1q64. - // VST1df is equivalent to VST1d32. - // VST1qf is equivalent to VST1q32. - // VST2d64 is equivalent to VST1q64. - if (Name == "VDUPLNfd" || Name == "VDUPLNfq" || - Name == "VLD1df" || Name == "VLD1qf" || Name == "VLD2d64" || - Name == "VST1df" || Name == "VST1qf" || Name == "VST2d64") - return false; } else if (TN == TARGET_THUMB) { if (!thumbInstruction(Form)) return false; + // A8.6.189 STM / STMIA / STMEA -- Encoding T1 + // There's only STMIA_UPD for Thumb1. + if (Name == "tSTMIA") + return false; + // On Darwin R9 is call-clobbered. Ignore the non-Darwin counterparts. if (Name == "tBL" || Name == "tBLXi" || Name == "tBLXr") return false; + // A8.6.25 BX. Use the generic tBX_Rm, ignore tBX_RET and tBX_RET_vararg. + if (Name == "tBX_RET" || Name == "tBX_RET_vararg") + return false; + // Ignore the TPsoft (TLS) instructions, which conflict with tBLr9. if (Name == "tTPsoft" || Name == "t2TPsoft") return false; @@ -1692,6 +1636,11 @@ ARMDEBackend::populateInstruction(const CodeGenInstruction &CGI, if (Name == "tADR") return false; + // Delegate t2ADR disassembly to the more generic t2ADDri12/t2SUBri12 + // instructions. + if (Name == "t2ADR") + return false; + // Ignore tADDrSP, tADDspr, and tPICADD, prefer the generic tADDhirr. // Ignore t2SUBrSPs, prefer the t2SUB[S]r[r|s]. // Ignore t2ADDrSPs, prefer the t2ADD[S]r[r|s]. @@ -1703,6 +1652,11 @@ ARMDEBackend::populateInstruction(const CodeGenInstruction &CGI, Name == "t2ADDrSPi12" || Name == "t2SUBrSPi12") return false; + // FIXME: Use ldr.n to work around a Darwin assembler bug. + // Introduce a workaround with tLDRpciDIS opcode. + if (Name == "tLDRpci") + return false; + // Ignore t2LDRDpci, prefer the generic t2LDRDi8, t2LDRD_PRE, t2LDRD_POST. if (Name == "t2LDRDpci") return false; diff --git a/utils/TableGen/AsmMatcherEmitter.cpp b/utils/TableGen/AsmMatcherEmitter.cpp index e3def41..1d14037 100644 --- a/utils/TableGen/AsmMatcherEmitter.cpp +++ b/utils/TableGen/AsmMatcherEmitter.cpp @@ -88,7 +88,7 @@ // 2. The operand matcher will try every possible entry with the same // mnemonic and will check if the target feature for this mnemonic also // matches. After that, if the operand to be matched has its index -// present in the mask, a successfull match occurs. Otherwise, fallback +// present in the mask, a successful match occurs. Otherwise, fallback // to the regular operand parsing. // // 3. For a match success, each operand class that has a 'ParserMethod' @@ -258,7 +258,7 @@ public: return ValueName < RHS.ValueName; default: - // This class preceeds the RHS if it is a proper subset of the RHS. + // This class precedes the RHS if it is a proper subset of the RHS. if (isSubsetOf(RHS)) return true; if (RHS.isSubsetOf(*this)) @@ -1265,7 +1265,7 @@ void AsmMatcherInfo::BuildInfo() { II->BuildAliasResultOperands(); } - // Reorder classes so that classes preceed super classes. + // Reorder classes so that classes precede super classes. std::sort(Classes.begin(), Classes.end(), less_ptr<ClassInfo>()); } @@ -1483,10 +1483,10 @@ static void EmitConvertToMCInst(CodeGenTarget &Target, StringRef ClassName, MatchableInfo &II = **it; // Check if we have a custom match function. - StringRef AsmMatchConverter = II.getResultInst()->TheDef->getValueAsString( - "AsmMatchConverter"); + std::string AsmMatchConverter = + II.getResultInst()->TheDef->getValueAsString("AsmMatchConverter"); if (!AsmMatchConverter.empty()) { - std::string Signature = "ConvertCustom_" + AsmMatchConverter.str(); + std::string Signature = "ConvertCustom_" + AsmMatchConverter; II.ConversionFnKind = Signature; // Check if we have already generated this signature. @@ -1538,7 +1538,7 @@ static void EmitConvertToMCInst(CodeGenTarget &Target, StringRef ClassName, // operand from the earlier one.We can only tie single MCOperand values. //assert(OpInfo.MINumOperands == 1 && "Not a singular MCOperand"); unsigned TiedOp = OpInfo.TiedOperandNum; - assert(i > TiedOp && "Tied operand preceeds its target!"); + assert(i > TiedOp && "Tied operand precedes its target!"); CaseOS << " Inst.addOperand(Inst.getOperand(" << TiedOp << "));\n"; Signature += "__Tie" + utostr(TiedOp); break; diff --git a/utils/TableGen/AsmMatcherEmitter.h b/utils/TableGen/AsmMatcherEmitter.h index 729c938..c13adf3 100644 --- a/utils/TableGen/AsmMatcherEmitter.h +++ b/utils/TableGen/AsmMatcherEmitter.h @@ -16,8 +16,6 @@ #define ASMMATCHER_EMITTER_H #include "TableGenBackend.h" -#include <map> -#include <vector> #include <cassert> namespace llvm { diff --git a/utils/TableGen/AsmWriterEmitter.cpp b/utils/TableGen/AsmWriterEmitter.cpp index cd31e0c..2b1a4cc 100644 --- a/utils/TableGen/AsmWriterEmitter.cpp +++ b/utils/TableGen/AsmWriterEmitter.cpp @@ -542,12 +542,220 @@ void AsmWriterEmitter::EmitGetInstructionName(raw_ostream &O) { << "}\n\n#endif\n"; } -void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { - CodeGenTarget Target(Records); - Record *AsmWriter = Target.getAsmWriter(); +namespace { - O << "\n#ifdef PRINT_ALIAS_INSTR\n"; - O << "#undef PRINT_ALIAS_INSTR\n\n"; +/// SubtargetFeatureInfo - Helper class for storing information on a subtarget +/// feature which participates in instruction matching. +struct SubtargetFeatureInfo { + /// \brief The predicate record for this feature. + const Record *TheDef; + + /// \brief An unique index assigned to represent this feature. + unsigned Index; + + SubtargetFeatureInfo(const Record *D, unsigned Idx) : TheDef(D), Index(Idx) {} + + /// \brief The name of the enumerated constant identifying this feature. + std::string getEnumName() const { + return "Feature_" + TheDef->getName(); + } +}; + +struct AsmWriterInfo { + /// Map of Predicate records to their subtarget information. + std::map<const Record*, SubtargetFeatureInfo*> SubtargetFeatures; + + /// getSubtargetFeature - Lookup or create the subtarget feature info for the + /// given operand. + SubtargetFeatureInfo *getSubtargetFeature(const Record *Def) const { + assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!"); + std::map<const Record*, SubtargetFeatureInfo*>::const_iterator I = + SubtargetFeatures.find(Def); + return I == SubtargetFeatures.end() ? 0 : I->second; + } + + void addReqFeatures(const std::vector<Record*> &Features) { + for (std::vector<Record*>::const_iterator + I = Features.begin(), E = Features.end(); I != E; ++I) { + const Record *Pred = *I; + + // Ignore predicates that are not intended for the assembler. + if (!Pred->getValueAsBit("AssemblerMatcherPredicate")) + continue; + + if (Pred->getName().empty()) + throw TGError(Pred->getLoc(), "Predicate has no name!"); + + // Don't add the predicate again. + if (getSubtargetFeature(Pred)) + continue; + + unsigned FeatureNo = SubtargetFeatures.size(); + SubtargetFeatures[Pred] = new SubtargetFeatureInfo(Pred, FeatureNo); + assert(FeatureNo < 32 && "Too many subtarget features!"); + } + } + + const SubtargetFeatureInfo *getFeatureInfo(const Record *R) { + return SubtargetFeatures[R]; + } +}; + +// IAPrinter - Holds information about an InstAlias. Two InstAliases match if +// they both have the same conditionals. In which case, we cannot print out the +// alias for that pattern. +class IAPrinter { + AsmWriterInfo &AWI; + std::vector<std::string> Conds; + std::map<StringRef, unsigned> OpMap; + std::string Result; + std::string AsmString; + std::vector<Record*> ReqFeatures; +public: + IAPrinter(AsmWriterInfo &Info, std::string R, std::string AS) + : AWI(Info), Result(R), AsmString(AS) {} + + void addCond(const std::string &C) { Conds.push_back(C); } + void addReqFeatures(const std::vector<Record*> &Features) { + AWI.addReqFeatures(Features); + ReqFeatures = Features; + } + + void addOperand(StringRef Op, unsigned Idx) { OpMap[Op] = Idx; } + unsigned getOpIndex(StringRef Op) { return OpMap[Op]; } + bool isOpMapped(StringRef Op) { return OpMap.find(Op) != OpMap.end(); } + + bool print(raw_ostream &O) { + if (Conds.empty() && ReqFeatures.empty()) { + O.indent(6) << "return true;\n"; + return false; + } + + O << "if ("; + + for (std::vector<std::string>::iterator + I = Conds.begin(), E = Conds.end(); I != E; ++I) { + if (I != Conds.begin()) { + O << " &&\n"; + O.indent(8); + } + + O << *I; + } + + if (!ReqFeatures.empty()) { + if (Conds.begin() != Conds.end()) { + O << " &&\n"; + O.indent(8); + } else { + O << "if ("; + } + + std::string Req; + raw_string_ostream ReqO(Req); + + for (std::vector<Record*>::iterator + I = ReqFeatures.begin(), E = ReqFeatures.end(); I != E; ++I) { + if (I != ReqFeatures.begin()) ReqO << " | "; + ReqO << AWI.getFeatureInfo(*I)->getEnumName(); + } + + O << "(AvailableFeatures & (" << ReqO.str() << ")) == (" + << ReqO.str() << ')'; + } + + O << ") {\n"; + O.indent(6) << "// " << Result << "\n"; + O.indent(6) << "AsmString = \"" << AsmString << "\";\n"; + + for (std::map<StringRef, unsigned>::iterator + I = OpMap.begin(), E = OpMap.end(); I != E; ++I) + O.indent(6) << "OpMap[\"" << I->first << "\"] = " + << I->second << ";\n"; + + O.indent(6) << "break;\n"; + O.indent(4) << '}'; + return !ReqFeatures.empty(); + } + + bool operator==(const IAPrinter &RHS) { + if (Conds.size() != RHS.Conds.size()) + return false; + + unsigned Idx = 0; + for (std::vector<std::string>::iterator + I = Conds.begin(), E = Conds.end(); I != E; ++I) + if (*I != RHS.Conds[Idx++]) + return false; + + return true; + } + + bool operator()(const IAPrinter &RHS) { + if (Conds.size() < RHS.Conds.size()) + return true; + + unsigned Idx = 0; + for (std::vector<std::string>::iterator + I = Conds.begin(), E = Conds.end(); I != E; ++I) + if (*I != RHS.Conds[Idx++]) + return *I < RHS.Conds[Idx++]; + + return false; + } +}; + +} // end anonymous namespace + +/// EmitSubtargetFeatureFlagEnumeration - Emit the subtarget feature flag +/// definitions. +static void EmitSubtargetFeatureFlagEnumeration(AsmWriterInfo &Info, + raw_ostream &O) { + O << "namespace {\n\n"; + O << "// Flags for subtarget features that participate in " + << "alias instruction matching.\n"; + O << "enum SubtargetFeatureFlag {\n"; + + for (std::map<const Record*, SubtargetFeatureInfo*>::const_iterator + I = Info.SubtargetFeatures.begin(), + E = Info.SubtargetFeatures.end(); I != E; ++I) { + SubtargetFeatureInfo &SFI = *I->second; + O << " " << SFI.getEnumName() << " = (1 << " << SFI.Index << "),\n"; + } + + O << " Feature_None = 0\n"; + O << "};\n\n"; + O << "} // end anonymous namespace\n\n"; +} + +/// EmitComputeAvailableFeatures - Emit the function to compute the list of +/// available features given a subtarget. +static void EmitComputeAvailableFeatures(AsmWriterInfo &Info, + Record *AsmWriter, + CodeGenTarget &Target, + raw_ostream &O) { + std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName"); + + O << "unsigned " << Target.getName() << ClassName << "::\n" + << "ComputeAvailableFeatures(const " << Target.getName() + << "Subtarget *Subtarget) const {\n"; + O << " unsigned Features = 0;\n"; + + for (std::map<const Record*, SubtargetFeatureInfo*>::const_iterator + I = Info.SubtargetFeatures.begin(), + E = Info.SubtargetFeatures.end(); I != E; ++I) { + SubtargetFeatureInfo &SFI = *I->second; + O << " if (" << SFI.TheDef->getValueAsString("CondString") + << ")\n"; + O << " Features |= " << SFI.getEnumName() << ";\n"; + } + + O << " return Features;\n"; + O << "}\n\n"; +} + +void AsmWriterEmitter::EmitRegIsInRegClass(raw_ostream &O) { + CodeGenTarget Target(Records); // Enumerate the register classes. const std::vector<CodeGenRegisterClass> &RegisterClasses = @@ -606,6 +814,16 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { O << " }\n\n"; O << " return false;\n"; O << "}\n\n"; +} + +void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { + CodeGenTarget Target(Records); + Record *AsmWriter = Target.getAsmWriter(); + + O << "\n#ifdef PRINT_ALIAS_INSTR\n"; + O << "#undef PRINT_ALIAS_INSTR\n\n"; + + EmitRegIsInRegClass(O); // Emit the method that prints the alias instruction. std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName"); @@ -613,10 +831,6 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { bool isMC = AsmWriter->getValueAsBit("isMCAsmWriter"); const char *MachineInstrClassName = isMC ? "MCInst" : "MachineInstr"; - O << "bool " << Target.getName() << ClassName - << "::printAliasInstr(const " << MachineInstrClassName - << " *MI, raw_ostream &OS) {\n"; - std::vector<Record*> AllInstAliases = Records.getAllDerivedDefinitions("InstAlias"); @@ -626,44 +840,35 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { I = AllInstAliases.begin(), E = AllInstAliases.end(); I != E; ++I) { CodeGenInstAlias *Alias = new CodeGenInstAlias(*I, Target); const Record *R = *I; + if (!R->getValueAsBit("EmitAlias")) + continue; // We were told not to emit the alias, but to emit the aliasee. const DagInit *DI = R->getValueAsDag("ResultInst"); const DefInit *Op = dynamic_cast<const DefInit*>(DI->getOperator()); AliasMap[getQualifiedName(Op->getDef())].push_back(Alias); } - if (AliasMap.empty() || !isMC) { - // FIXME: Support MachineInstr InstAliases? - O << " return true;\n"; - O << "}\n\n"; - O << "#endif // PRINT_ALIAS_INSTR\n"; - return; - } - - O << " StringRef AsmString;\n"; - O << " std::map<StringRef, unsigned> OpMap;\n"; - O << " switch (MI->getOpcode()) {\n"; - O << " default: return true;\n"; + // A map of which conditions need to be met for each instruction operand + // before it can be matched to the mnemonic. + std::map<std::string, std::vector<IAPrinter*> > IAPrinterMap; + AsmWriterInfo AWI; for (std::map<std::string, std::vector<CodeGenInstAlias*> >::iterator I = AliasMap.begin(), E = AliasMap.end(); I != E; ++I) { std::vector<CodeGenInstAlias*> &Aliases = I->second; - std::map<std::string, unsigned> CondCount; - std::map<std::string, std::string> BodyMap; - - std::string AsmString = ""; - for (std::vector<CodeGenInstAlias*>::iterator II = Aliases.begin(), IE = Aliases.end(); II != IE; ++II) { const CodeGenInstAlias *CGA = *II; - AsmString = CGA->AsmString; - unsigned Indent = 8; + IAPrinter *IAP = new IAPrinter(AWI, CGA->Result->getAsString(), + CGA->AsmString); + + IAP->addReqFeatures(CGA->TheDef->getValueAsListOfDefs("Predicates")); + unsigned LastOpNo = CGA->ResultInstOperandIndex.size(); std::string Cond; - raw_string_ostream CondO(Cond); - - CondO << "if (MI->getNumOperands() == " << LastOpNo; + Cond = std::string("MI->getNumOperands() == ") + llvm::utostr(LastOpNo); + IAP->addCond(Cond); std::map<StringRef, unsigned> OpMap; bool CantHandle = false; @@ -678,23 +883,26 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { StringRef ROName = RO.getName(); if (Rec->isSubClassOf("RegisterClass")) { - CondO << " &&\n"; - CondO.indent(Indent) << "MI->getOperand(" << i << ").isReg() &&\n"; - if (OpMap.find(ROName) == OpMap.end()) { - OpMap[ROName] = i; - CondO.indent(Indent) - << "regIsInRegisterClass(RC_" - << CGA->ResultOperands[i].getRecord()->getName() - << ", MI->getOperand(" << i << ").getReg())"; + Cond = std::string("MI->getOperand(")+llvm::utostr(i)+").isReg()"; + IAP->addCond(Cond); + + if (!IAP->isOpMapped(ROName)) { + IAP->addOperand(ROName, i); + Cond = std::string("regIsInRegisterClass(RC_") + + CGA->ResultOperands[i].getRecord()->getName() + + ", MI->getOperand(" + llvm::utostr(i) + ").getReg())"; + IAP->addCond(Cond); } else { - CondO.indent(Indent) - << "MI->getOperand(" << i - << ").getReg() == MI->getOperand(" - << OpMap[ROName] << ").getReg()"; + Cond = std::string("MI->getOperand(") + + llvm::utostr(i) + ").getReg() == MI->getOperand(" + + llvm::utostr(IAP->getOpIndex(ROName)) + ").getReg()"; + IAP->addCond(Cond); } } else { assert(Rec->isSubClassOf("Operand") && "Unexpected operand!"); // FIXME: We need to handle these situations. + delete IAP; + IAP = 0; CantHandle = true; break; } @@ -702,67 +910,92 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { break; } case CodeGenInstAlias::ResultOperand::K_Imm: - CondO << " &&\n"; - CondO.indent(Indent) << "MI->getOperand(" << i << ").getImm() == "; - CondO << CGA->ResultOperands[i].getImm(); + Cond = std::string("MI->getOperand(") + + llvm::utostr(i) + ").getImm() == " + + llvm::utostr(CGA->ResultOperands[i].getImm()); + IAP->addCond(Cond); break; case CodeGenInstAlias::ResultOperand::K_Reg: - CondO << " &&\n"; - CondO.indent(Indent) << "MI->getOperand(" << i << ").getReg() == "; - CondO << Target.getName() << "::" - << CGA->ResultOperands[i].getRegister()->getName(); + Cond = std::string("MI->getOperand(") + + llvm::utostr(i) + ").getReg() == " + Target.getName() + + "::" + CGA->ResultOperands[i].getRegister()->getName(); + IAP->addCond(Cond); break; } - if (CantHandle) break; + if (!IAP) break; } if (CantHandle) continue; + IAPrinterMap[I->first].push_back(IAP); + } + } - CondO << ")"; - - std::string Body; - raw_string_ostream BodyO(Body); + EmitSubtargetFeatureFlagEnumeration(AWI, O); + EmitComputeAvailableFeatures(AWI, AsmWriter, Target, O); - BodyO << " // " << CGA->Result->getAsString() << "\n"; - BodyO << " AsmString = \"" << AsmString << "\";\n"; + O << "bool " << Target.getName() << ClassName + << "::printAliasInstr(const " << MachineInstrClassName + << " *MI, raw_ostream &OS) {\n"; - for (std::map<StringRef, unsigned>::iterator - III = OpMap.begin(), IIE = OpMap.end(); III != IIE; ++III) - BodyO << " OpMap[\"" << III->first << "\"] = " - << III->second << ";\n"; + std::string Cases; + raw_string_ostream CasesO(Cases); + bool NeedAvailableFeatures = false; + + for (std::map<std::string, std::vector<IAPrinter*> >::iterator + I = IAPrinterMap.begin(), E = IAPrinterMap.end(); I != E; ++I) { + std::vector<IAPrinter*> &IAPs = I->second; + std::vector<IAPrinter*> UniqueIAPs; + + for (std::vector<IAPrinter*>::iterator + II = IAPs.begin(), IE = IAPs.end(); II != IE; ++II) { + IAPrinter *LHS = *II; + bool IsDup = false; + for (std::vector<IAPrinter*>::iterator + III = IAPs.begin(), IIE = IAPs.end(); III != IIE; ++III) { + IAPrinter *RHS = *III; + if (LHS != RHS && *LHS == *RHS) { + IsDup = true; + break; + } + } - ++CondCount[CondO.str()]; - BodyMap[CondO.str()] = BodyO.str(); + if (!IsDup) UniqueIAPs.push_back(LHS); } - std::string Code; - raw_string_ostream CodeO(Code); - - bool EmitElse = false; - for (std::map<std::string, unsigned>::iterator - II = CondCount.begin(), IE = CondCount.end(); II != IE; ++II) { - if (II->second != 1) continue; - CodeO << " "; - if (EmitElse) CodeO << "} else "; - CodeO << II->first << " {\n"; - CodeO << BodyMap[II->first]; - EmitElse = true; + if (UniqueIAPs.empty()) continue; + + CasesO.indent(2) << "case " << I->first << ":\n"; + + for (std::vector<IAPrinter*>::iterator + II = UniqueIAPs.begin(), IE = UniqueIAPs.end(); II != IE; ++II) { + IAPrinter *IAP = *II; + CasesO.indent(4); + NeedAvailableFeatures |= IAP->print(CasesO); + CasesO << '\n'; } - if (CodeO.str().empty()) continue; + CasesO.indent(4) << "return false;\n"; + } - O << " case " << I->first << ":\n"; - O << CodeO.str(); - O << " }\n"; - O << " break;\n"; + if (CasesO.str().empty() || !isMC) { + O << " return false;\n"; + O << "}\n\n"; + O << "#endif // PRINT_ALIAS_INSTR\n"; + return; } - O << " }\n\n"; + O.indent(2) << "StringRef AsmString;\n"; + O.indent(2) << "std::map<StringRef, unsigned> OpMap;\n"; + if (NeedAvailableFeatures) + O.indent(2) << "unsigned AvailableFeatures = getAvailableFeatures();\n\n"; + O.indent(2) << "switch (MI->getOpcode()) {\n"; + O.indent(2) << "default: return false;\n"; + O << CasesO.str(); + O.indent(2) << "}\n\n"; // Code that prints the alias, replacing the operands with the ones from the // MCInst. - O << " if (AsmString.empty()) return true;\n"; O << " std::pair<StringRef, StringRef> ASM = AsmString.split(' ');\n"; O << " OS << '\\t' << ASM.first;\n"; @@ -786,7 +1019,7 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { O << " }\n"; O << " }\n\n"; - O << " return false;\n"; + O << " return true;\n"; O << "}\n\n"; O << "#endif // PRINT_ALIAS_INSTR\n"; diff --git a/utils/TableGen/AsmWriterEmitter.h b/utils/TableGen/AsmWriterEmitter.h index 5e8d6f5..84c925b 100644 --- a/utils/TableGen/AsmWriterEmitter.h +++ b/utils/TableGen/AsmWriterEmitter.h @@ -38,6 +38,7 @@ private: void EmitPrintInstruction(raw_ostream &o); void EmitGetRegisterName(raw_ostream &o); void EmitGetInstructionName(raw_ostream &o); + void EmitRegIsInRegClass(raw_ostream &O); void EmitPrintAliasInstruction(raw_ostream &O); AsmWriterInst *getAsmWriterInstByID(unsigned ID) const { diff --git a/utils/TableGen/CallingConvEmitter.h b/utils/TableGen/CallingConvEmitter.h index 7fc2507..431c33b 100644 --- a/utils/TableGen/CallingConvEmitter.h +++ b/utils/TableGen/CallingConvEmitter.h @@ -16,8 +16,6 @@ #define CALLINGCONV_EMITTER_H #include "TableGenBackend.h" -#include <map> -#include <vector> #include <cassert> namespace llvm { diff --git a/utils/TableGen/ClangASTNodesEmitter.cpp b/utils/TableGen/ClangASTNodesEmitter.cpp index 187ab46..d9d5a3c 100644 --- a/utils/TableGen/ClangASTNodesEmitter.cpp +++ b/utils/TableGen/ClangASTNodesEmitter.cpp @@ -155,10 +155,13 @@ void ClangDeclContextEmitter::run(raw_ostream &OS) { } } - for (RecordSet::iterator i = DeclContexts.begin(), e = DeclContexts.end(); - i != e; ++i) { - OS << "DECL_CONTEXT(" << (*i)->getName() << ")\n"; - } + // To keep identical order, RecordVector may be used + // instead of RecordSet. + for (RecordVector::iterator + i = DeclContextsVector.begin(), e = DeclContextsVector.end(); + i != e; ++i) + if (DeclContexts.find(*i) != DeclContexts.end()) + OS << "DECL_CONTEXT(" << (*i)->getName() << ")\n"; OS << "#undef DECL_CONTEXT\n"; OS << "#undef DECL_CONTEXT_BASE\n"; diff --git a/utils/TableGen/ClangAttrEmitter.cpp b/utils/TableGen/ClangAttrEmitter.cpp index 27e1e02..26bd878 100644 --- a/utils/TableGen/ClangAttrEmitter.cpp +++ b/utils/TableGen/ClangAttrEmitter.cpp @@ -46,6 +46,7 @@ std::string ReadPCHRecord(StringRef type) { ">(GetDecl(Record[Idx++]))") .Case("QualType", "GetType(Record[Idx++])") .Case("Expr *", "ReadSubExpr()") + .Case("IdentifierInfo *", "GetIdentifierInfo(Record, Idx)") .Default("Record[Idx++]"); } @@ -56,6 +57,8 @@ std::string WritePCHRecord(StringRef type, StringRef name) { ", Record);\n") .Case("QualType", "AddTypeRef(" + std::string(name) + ", Record);\n") .Case("Expr *", "AddStmt(" + std::string(name) + ");\n") + .Case("IdentifierInfo *", + "AddIdentifierRef(" + std::string(name) + ", Record);\n") .Default("Record.push_back(" + std::string(name) + ");\n"); } @@ -415,6 +418,47 @@ namespace { OS << "Record.push_back(SA->get" << getUpperName() << "());\n"; } }; + + class VersionArgument : public Argument { + public: + VersionArgument(Record &Arg, StringRef Attr) + : Argument(Arg, Attr) + {} + + void writeAccessors(raw_ostream &OS) const { + OS << " VersionTuple get" << getUpperName() << "() const {\n"; + OS << " return " << getLowerName() << ";\n"; + OS << " }\n"; + OS << " void set" << getUpperName() + << "(ASTContext &C, VersionTuple V) {\n"; + OS << " " << getLowerName() << " = V;\n"; + OS << " }"; + } + void writeCloneArgs(raw_ostream &OS) const { + OS << "get" << getUpperName() << "()"; + } + void writeCtorBody(raw_ostream &OS) const { + } + void writeCtorInitializers(raw_ostream &OS) const { + OS << getLowerName() << "(" << getUpperName() << ")"; + } + void writeCtorParameters(raw_ostream &OS) const { + OS << "VersionTuple " << getUpperName(); + } + void writeDeclarations(raw_ostream &OS) const { + OS << "VersionTuple " << getLowerName() << ";\n"; + } + void writePCHReadDecls(raw_ostream &OS) const { + OS << " VersionTuple " << getLowerName() + << "= ReadVersionTuple(Record, Idx);\n"; + } + void writePCHReadArgs(raw_ostream &OS) const { + OS << getLowerName(); + } + void writePCHWrite(raw_ostream &OS) const { + OS << " AddVersionTuple(SA->get" << getUpperName() << "(), Record);\n"; + } + }; } static Argument *createArgument(Record &Arg, StringRef Attr, @@ -433,6 +477,8 @@ static Argument *createArgument(Record &Arg, StringRef Attr, Ptr = new SimpleArgument(Arg, Attr, "FunctionDecl *"); else if (ArgName == "IdentifierArgument") Ptr = new SimpleArgument(Arg, Attr, "IdentifierInfo *"); + else if (ArgName == "BoolArgument") Ptr = new SimpleArgument(Arg, Attr, + "bool"); else if (ArgName == "IntArgument") Ptr = new SimpleArgument(Arg, Attr, "int"); else if (ArgName == "StringArgument") Ptr = new StringArgument(Arg, Attr); else if (ArgName == "TypeArgument") @@ -441,6 +487,8 @@ static Argument *createArgument(Record &Arg, StringRef Attr, Ptr = new SimpleArgument(Arg, Attr, "unsigned"); else if (ArgName == "VariadicUnsignedArgument") Ptr = new VariadicArgument(Arg, Attr, "unsigned"); + else if (ArgName == "VersionArgument") + Ptr = new VersionArgument(Arg, Attr); if (!Ptr) { std::vector<Record*> Bases = Search->getSuperClasses(); @@ -589,23 +637,37 @@ void ClangAttrListEmitter::run(raw_ostream &OS) { OS << "#define LAST_INHERITABLE_ATTR(NAME) INHERITABLE_ATTR(NAME)\n"; OS << "#endif\n\n"; + OS << "#ifndef INHERITABLE_PARAM_ATTR\n"; + OS << "#define INHERITABLE_PARAM_ATTR(NAME) ATTR(NAME)\n"; + OS << "#endif\n\n"; + + OS << "#ifndef LAST_INHERITABLE_PARAM_ATTR\n"; + OS << "#define LAST_INHERITABLE_PARAM_ATTR(NAME)" + " INHERITABLE_PARAM_ATTR(NAME)\n"; + OS << "#endif\n\n"; + Record *InhClass = Records.getClass("InheritableAttr"); + Record *InhParamClass = Records.getClass("InheritableParamAttr"); std::vector<Record*> Attrs = Records.getAllDerivedDefinitions("Attr"), - NonInhAttrs, InhAttrs; + NonInhAttrs, InhAttrs, InhParamAttrs; for (std::vector<Record*>::iterator i = Attrs.begin(), e = Attrs.end(); i != e; ++i) { - if ((*i)->isSubClassOf(InhClass)) + if ((*i)->isSubClassOf(InhParamClass)) + InhParamAttrs.push_back(*i); + else if ((*i)->isSubClassOf(InhClass)) InhAttrs.push_back(*i); else NonInhAttrs.push_back(*i); } + EmitAttrList(OS, "INHERITABLE_PARAM_ATTR", InhParamAttrs); EmitAttrList(OS, "INHERITABLE_ATTR", InhAttrs); EmitAttrList(OS, "ATTR", NonInhAttrs); OS << "#undef LAST_ATTR\n"; OS << "#undef INHERITABLE_ATTR\n"; OS << "#undef LAST_INHERITABLE_ATTR\n"; + OS << "#undef LAST_INHERITABLE_PARAM_ATTR\n"; OS << "#undef ATTR\n"; } diff --git a/utils/TableGen/ClangDiagnosticsEmitter.cpp b/utils/TableGen/ClangDiagnosticsEmitter.cpp index 60e67c4..0f4b606 100644 --- a/utils/TableGen/ClangDiagnosticsEmitter.cpp +++ b/utils/TableGen/ClangDiagnosticsEmitter.cpp @@ -19,8 +19,9 @@ #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/StringMap.h" #include "llvm/ADT/VectorExtras.h" -#include <set> #include <map> +#include <algorithm> +#include <functional> using namespace llvm; //===----------------------------------------------------------------------===// @@ -121,7 +122,6 @@ namespace { } // end anonymous namespace. - //===----------------------------------------------------------------------===// // Warning Tables (.inc file) generation. //===----------------------------------------------------------------------===// @@ -179,6 +179,14 @@ void ClangDiagsDefsEmitter::run(raw_ostream &OS) { // Category number. OS << ", " << CategoryIDs.getID(getDiagnosticCategory(&R, DGParentMap)); + + // Brief + OS << ", \""; + OS.write_escaped(R.getValueAsString("Brief")) << '"'; + + // Explanation + OS << ", \""; + OS.write_escaped(R.getValueAsString("Explanation")) << '"'; OS << ")\n"; } } @@ -294,3 +302,49 @@ void ClangDiagGroupsEmitter::run(raw_ostream &OS) { OS << "CATEGORY(\"" << *I << "\")\n"; OS << "#endif // GET_CATEGORY_TABLE\n\n"; } + +//===----------------------------------------------------------------------===// +// Diagnostic name index generation +//===----------------------------------------------------------------------===// + +namespace { +struct RecordIndexElement +{ + RecordIndexElement() {} + explicit RecordIndexElement(Record const &R): + Name(R.getName()) {} + + std::string Name; +}; + +struct RecordIndexElementSorter : + public std::binary_function<RecordIndexElement, RecordIndexElement, bool> { + + bool operator()(RecordIndexElement const &Lhs, + RecordIndexElement const &Rhs) const { + return Lhs.Name < Rhs.Name; + } + +}; + +} // end anonymous namespace. + +void ClangDiagsIndexNameEmitter::run(raw_ostream &OS) { + const std::vector<Record*> &Diags = + Records.getAllDerivedDefinitions("Diagnostic"); + + std::vector<RecordIndexElement> Index; + Index.reserve(Diags.size()); + for (unsigned i = 0, e = Diags.size(); i != e; ++i) { + const Record &R = *(Diags[i]); + Index.push_back(RecordIndexElement(R)); + } + + std::sort(Index.begin(), Index.end(), RecordIndexElementSorter()); + + for (unsigned i = 0, e = Index.size(); i != e; ++i) { + const RecordIndexElement &R = Index[i]; + + OS << "DIAG_NAME_INDEX(" << R.Name << ")\n"; + } +} diff --git a/utils/TableGen/ClangDiagnosticsEmitter.h b/utils/TableGen/ClangDiagnosticsEmitter.h index edd062a..1e4c8b7 100644 --- a/utils/TableGen/ClangDiagnosticsEmitter.h +++ b/utils/TableGen/ClangDiagnosticsEmitter.h @@ -33,13 +33,21 @@ public: }; class ClangDiagGroupsEmitter : public TableGenBackend { - RecordKeeper &Records; + RecordKeeper &Records; public: explicit ClangDiagGroupsEmitter(RecordKeeper &R) : Records(R) {} void run(raw_ostream &OS); }; +class ClangDiagsIndexNameEmitter : public TableGenBackend { + RecordKeeper &Records; +public: + explicit ClangDiagsIndexNameEmitter(RecordKeeper &R) : Records(R) {} + + void run(raw_ostream &OS); +}; + } // End llvm namespace diff --git a/utils/TableGen/ClangSACheckersEmitter.cpp b/utils/TableGen/ClangSACheckersEmitter.cpp index 8865db3..97739c6 100644 --- a/utils/TableGen/ClangSACheckersEmitter.cpp +++ b/utils/TableGen/ClangSACheckersEmitter.cpp @@ -71,7 +71,7 @@ static std::string getStringValue(const Record &R, StringRef field) { namespace { struct GroupInfo { - std::vector<const Record*> Checkers; + llvm::DenseSet<const Record*> Checkers; llvm::DenseSet<const Record *> SubGroups; bool Hidden; unsigned Index; @@ -80,33 +80,24 @@ struct GroupInfo { }; } +static void addPackageToCheckerGroup(const Record *package, const Record *group, + llvm::DenseMap<const Record *, GroupInfo *> &recordGroupMap) { + llvm::DenseSet<const Record *> &checkers = recordGroupMap[package]->Checkers; + for (llvm::DenseSet<const Record *>::iterator + I = checkers.begin(), E = checkers.end(); I != E; ++I) + recordGroupMap[group]->Checkers.insert(*I); + + llvm::DenseSet<const Record *> &subGroups = recordGroupMap[package]->SubGroups; + for (llvm::DenseSet<const Record *>::iterator + I = subGroups.begin(), E = subGroups.end(); I != E; ++I) + addPackageToCheckerGroup(*I, group, recordGroupMap); +} + void ClangSACheckersEmitter::run(raw_ostream &OS) { std::vector<Record*> checkers = Records.getAllDerivedDefinitions("Checker"); llvm::DenseMap<const Record *, unsigned> checkerRecIndexMap; for (unsigned i = 0, e = checkers.size(); i != e; ++i) checkerRecIndexMap[checkers[i]] = i; - - OS << "\n#ifdef GET_CHECKERS\n"; - for (unsigned i = 0, e = checkers.size(); i != e; ++i) { - const Record &R = *checkers[i]; - - OS << "CHECKER(" << "\""; - std::string name; - if (isCheckerNamed(&R)) - name = getCheckerFullName(&R); - OS.write_escaped(name) << "\", "; - OS << R.getName() << ", "; - OS << getStringValue(R, "DescFile") << ", "; - OS << "\""; - OS.write_escaped(getStringValue(R, "HelpText")) << "\", "; - // Hidden bit - if (isHidden(R)) - OS << "true"; - else - OS << "false"; - OS << ")\n"; - } - OS << "#endif // GET_CHECKERS\n\n"; // Invert the mapping of checkers to package/group into a one to many // mapping of packages/groups to checkers. @@ -150,9 +141,9 @@ void ClangSACheckersEmitter::run(raw_ostream &OS) { GroupInfo &info = groupInfoByName[fullName]; info.Hidden = R->getValueAsBit("Hidden"); recordGroupMap[R] = &info; - info.Checkers.push_back(R); + info.Checkers.insert(R); } else { - recordGroupMap[package]->Checkers.push_back(R); + recordGroupMap[package]->Checkers.insert(R); } Record *currR = isCheckerNamed(R) ? R : package; @@ -166,8 +157,93 @@ void ClangSACheckersEmitter::run(raw_ostream &OS) { } // Insert the checker into the set of its group. if (DefInit *DI = dynamic_cast<DefInit*>(R->getValueInit("Group"))) - recordGroupMap[DI->getDef()]->Checkers.push_back(R); + recordGroupMap[DI->getDef()]->Checkers.insert(R); + } + + // If a package is in group, add all its checkers and its sub-packages + // checkers into the group. + for (unsigned i = 0, e = packages.size(); i != e; ++i) + if (DefInit *DI = dynamic_cast<DefInit*>(packages[i]->getValueInit("Group"))) + addPackageToCheckerGroup(packages[i], DI->getDef(), recordGroupMap); + + typedef std::map<std::string, const Record *> SortedRecords; + typedef llvm::DenseMap<const Record *, unsigned> RecToSortIndex; + + SortedRecords sortedGroups; + RecToSortIndex groupToSortIndex; + OS << "\n#ifdef GET_GROUPS\n"; + { + for (unsigned i = 0, e = checkerGroups.size(); i != e; ++i) + sortedGroups[checkerGroups[i]->getValueAsString("GroupName")] + = checkerGroups[i]; + + unsigned sortIndex = 0; + for (SortedRecords::iterator + I = sortedGroups.begin(), E = sortedGroups.end(); I != E; ++I) { + const Record *R = I->second; + + OS << "GROUP(" << "\""; + OS.write_escaped(R->getValueAsString("GroupName")) << "\""; + OS << ")\n"; + + groupToSortIndex[R] = sortIndex++; + } } + OS << "#endif // GET_GROUPS\n\n"; + + OS << "\n#ifdef GET_PACKAGES\n"; + { + SortedRecords sortedPackages; + for (unsigned i = 0, e = packages.size(); i != e; ++i) + sortedPackages[getPackageFullName(packages[i])] = packages[i]; + + for (SortedRecords::iterator + I = sortedPackages.begin(), E = sortedPackages.end(); I != E; ++I) { + const Record &R = *I->second; + + OS << "PACKAGE(" << "\""; + OS.write_escaped(getPackageFullName(&R)) << "\", "; + // Group index + if (DefInit *DI = dynamic_cast<DefInit*>(R.getValueInit("Group"))) + OS << groupToSortIndex[DI->getDef()] << ", "; + else + OS << "-1, "; + // Hidden bit + if (isHidden(R)) + OS << "true"; + else + OS << "false"; + OS << ")\n"; + } + } + OS << "#endif // GET_PACKAGES\n\n"; + + OS << "\n#ifdef GET_CHECKERS\n"; + for (unsigned i = 0, e = checkers.size(); i != e; ++i) { + const Record &R = *checkers[i]; + + OS << "CHECKER(" << "\""; + std::string name; + if (isCheckerNamed(&R)) + name = getCheckerFullName(&R); + OS.write_escaped(name) << "\", "; + OS << R.getName() << ", "; + OS << getStringValue(R, "DescFile") << ", "; + OS << "\""; + OS.write_escaped(getStringValue(R, "HelpText")) << "\", "; + // Group index + if (DefInit *DI = dynamic_cast<DefInit*>(R.getValueInit("Group"))) + OS << groupToSortIndex[DI->getDef()] << ", "; + else + OS << "-1, "; + // Hidden bit + if (isHidden(R)) + OS << "true"; + else + OS << "false"; + OS << ")\n"; + } + OS << "#endif // GET_CHECKERS\n\n"; unsigned index = 0; for (std::map<std::string, GroupInfo>::iterator @@ -182,21 +258,34 @@ void ClangSACheckersEmitter::run(raw_ostream &OS) { for (std::map<std::string, GroupInfo>::iterator I = groupInfoByName.begin(), E = groupInfoByName.end(); I != E; ++I) { maxLen = std::max(maxLen, (unsigned)I->first.size()); - - std::vector<const Record*> &V = I->second.Checkers; - if (!V.empty()) { + + llvm::DenseSet<const Record *> &checkers = I->second.Checkers; + if (!checkers.empty()) { OS << "static const short CheckerArray" << I->second.Index << "[] = { "; - for (unsigned i = 0, e = V.size(); i != e; ++i) - OS << checkerRecIndexMap[V[i]] << ", "; + // Make the output order deterministic. + std::map<int, const Record *> sorted; + for (llvm::DenseSet<const Record *>::iterator + I = checkers.begin(), E = checkers.end(); I != E; ++I) + sorted[(*I)->getID()] = *I; + + for (std::map<int, const Record *>::iterator + I = sorted.begin(), E = sorted.end(); I != E; ++I) + OS << checkerRecIndexMap[I->second] << ", "; OS << "-1 };\n"; } llvm::DenseSet<const Record *> &subGroups = I->second.SubGroups; if (!subGroups.empty()) { OS << "static const short SubPackageArray" << I->second.Index << "[] = { "; + // Make the output order deterministic. + std::map<int, const Record *> sorted; for (llvm::DenseSet<const Record *>::iterator - I = subGroups.begin(), E = subGroups.end(); I != E; ++I) { - OS << recordGroupMap[*I]->Index << ", "; + I = subGroups.begin(), E = subGroups.end(); I != E; ++I) + sorted[(*I)->getID()] = *I; + + for (std::map<int, const Record *>::iterator + I = sorted.begin(), E = sorted.end(); I != E; ++I) { + OS << recordGroupMap[I->second]->Index << ", "; } OS << "-1 };\n"; } diff --git a/utils/TableGen/CodeEmitterGen.cpp b/utils/TableGen/CodeEmitterGen.cpp index 957dd19..9d4dc5c4 100644 --- a/utils/TableGen/CodeEmitterGen.cpp +++ b/utils/TableGen/CodeEmitterGen.cpp @@ -63,10 +63,14 @@ void CodeEmitterGen::reverseBits(std::vector<Record*> &Insts) { // return the variable bit position. Otherwise return -1. int CodeEmitterGen::getVariableBit(const std::string &VarName, BitsInit *BI, int bit) { - if (VarBitInit *VBI = dynamic_cast<VarBitInit*>(BI->getBit(bit))) + if (VarBitInit *VBI = dynamic_cast<VarBitInit*>(BI->getBit(bit))) { if (VarInit *VI = dynamic_cast<VarInit*>(VBI->getVariable())) if (VI->getName() == VarName) return VBI->getBitNum(); + } else if (VarInit *VI = dynamic_cast<VarInit*>(BI->getBit(bit))) { + if (VI->getName() == VarName) + return 0; + } return -1; } diff --git a/utils/TableGen/CodeGenDAGPatterns.cpp b/utils/TableGen/CodeGenDAGPatterns.cpp index aa60f87..a08cde6 100644 --- a/utils/TableGen/CodeGenDAGPatterns.cpp +++ b/utils/TableGen/CodeGenDAGPatterns.cpp @@ -580,34 +580,29 @@ typedef std::map<std::string, int> DepVarMap; /// Const iterator shorthand for DepVarMap typedef DepVarMap::const_iterator DepVarMap_citer; -namespace { -void FindDepVarsOf(TreePatternNode *N, DepVarMap &DepMap) { +static void FindDepVarsOf(TreePatternNode *N, DepVarMap &DepMap) { if (N->isLeaf()) { - if (dynamic_cast<DefInit*>(N->getLeafValue()) != NULL) { + if (dynamic_cast<DefInit*>(N->getLeafValue()) != NULL) DepMap[N->getName()]++; - } } else { for (size_t i = 0, e = N->getNumChildren(); i != e; ++i) FindDepVarsOf(N->getChild(i), DepMap); } } - -//! Find dependent variables within child patterns -/*! - */ -void FindDepVars(TreePatternNode *N, MultipleUseVarSet &DepVars) { + +/// Find dependent variables within child patterns +static void FindDepVars(TreePatternNode *N, MultipleUseVarSet &DepVars) { DepVarMap depcounts; FindDepVarsOf(N, depcounts); for (DepVarMap_citer i = depcounts.begin(); i != depcounts.end(); ++i) { - if (i->second > 1) { // std::pair<std::string, int> + if (i->second > 1) // std::pair<std::string, int> DepVars.insert(i->first); - } } } -//! Dump the dependent variable set: #ifndef NDEBUG -void DumpDepVars(MultipleUseVarSet &DepVars) { +/// Dump the dependent variable set: +static void DumpDepVars(MultipleUseVarSet &DepVars) { if (DepVars.empty()) { DEBUG(errs() << "<empty set>"); } else { @@ -621,6 +616,66 @@ void DumpDepVars(MultipleUseVarSet &DepVars) { } #endif + +//===----------------------------------------------------------------------===// +// TreePredicateFn Implementation +//===----------------------------------------------------------------------===// + +/// TreePredicateFn constructor. Here 'N' is a subclass of PatFrag. +TreePredicateFn::TreePredicateFn(TreePattern *N) : PatFragRec(N) { + assert((getPredCode().empty() || getImmCode().empty()) && + ".td file corrupt: can't have a node predicate *and* an imm predicate"); +} + +std::string TreePredicateFn::getPredCode() const { + return PatFragRec->getRecord()->getValueAsCode("PredicateCode"); +} + +std::string TreePredicateFn::getImmCode() const { + return PatFragRec->getRecord()->getValueAsCode("ImmediateCode"); +} + + +/// isAlwaysTrue - Return true if this is a noop predicate. +bool TreePredicateFn::isAlwaysTrue() const { + return getPredCode().empty() && getImmCode().empty(); +} + +/// Return the name to use in the generated code to reference this, this is +/// "Predicate_foo" if from a pattern fragment "foo". +std::string TreePredicateFn::getFnName() const { + return "Predicate_" + PatFragRec->getRecord()->getName(); +} + +/// getCodeToRunOnSDNode - Return the code for the function body that +/// evaluates this predicate. The argument is expected to be in "Node", +/// not N. This handles casting and conversion to a concrete node type as +/// appropriate. +std::string TreePredicateFn::getCodeToRunOnSDNode() const { + // Handle immediate predicates first. + std::string ImmCode = getImmCode(); + if (!ImmCode.empty()) { + std::string Result = + " int64_t Imm = cast<ConstantSDNode>(Node)->getSExtValue();\n"; + return Result + ImmCode; + } + + // Handle arbitrary node predicates. + assert(!getPredCode().empty() && "Don't have any predicate code!"); + std::string ClassName; + if (PatFragRec->getOnlyTree()->isLeaf()) + ClassName = "SDNode"; + else { + Record *Op = PatFragRec->getOnlyTree()->getOperator(); + ClassName = PatFragRec->getDAGPatterns().getSDNodeInfo(Op).getSDClassName(); + } + std::string Result; + if (ClassName == "SDNode") + Result = " SDNode *N = Node;\n"; + else + Result = " " + ClassName + "*N = cast<" + ClassName + ">(Node);\n"; + + return Result + getPredCode(); } //===----------------------------------------------------------------------===// @@ -1015,7 +1070,7 @@ void TreePatternNode::print(raw_ostream &OS) const { } for (unsigned i = 0, e = PredicateFns.size(); i != e; ++i) - OS << "<<P:" << PredicateFns[i] << ">>"; + OS << "<<P:" << PredicateFns[i].getFnName() << ">>"; if (TransformFn) OS << "<<X:" << TransformFn->getName() << ">>"; if (!getName().empty()) @@ -1150,9 +1205,9 @@ TreePatternNode *TreePatternNode::InlinePatternFragments(TreePattern &TP) { TreePatternNode *FragTree = Frag->getOnlyTree()->clone(); - std::string Code = Op->getValueAsCode("Predicate"); - if (!Code.empty()) - FragTree->addPredicateFn("Predicate_"+Op->getName()); + TreePredicateFn PredFn(Frag); + if (!PredFn.isAlwaysTrue()) + FragTree->addPredicateFn(PredFn); // Resolve formal arguments to their actual value. if (Frag->getNumArgs()) { @@ -2063,9 +2118,9 @@ void CodeGenDAGPatterns::ParsePatternFragments() { // If there is a code init for this fragment, keep track of the fact that // this fragment uses it. - std::string Code = Fragments[i]->getValueAsCode("Predicate"); - if (!Code.empty()) - P->getOnlyTree()->addPredicateFn("Predicate_"+Fragments[i]->getName()); + TreePredicateFn PredFn(P); + if (!PredFn.isAlwaysTrue()) + P->getOnlyTree()->addPredicateFn(PredFn); // If there is a node transformation corresponding to this, keep track of // it. @@ -2288,13 +2343,14 @@ class InstAnalyzer { const CodeGenDAGPatterns &CDP; bool &mayStore; bool &mayLoad; + bool &IsBitcast; bool &HasSideEffects; bool &IsVariadic; public: InstAnalyzer(const CodeGenDAGPatterns &cdp, - bool &maystore, bool &mayload, bool &hse, bool &isv) - : CDP(cdp), mayStore(maystore), mayLoad(mayload), HasSideEffects(hse), - IsVariadic(isv) { + bool &maystore, bool &mayload, bool &isbc, bool &hse, bool &isv) + : CDP(cdp), mayStore(maystore), mayLoad(mayload), IsBitcast(isbc), + HasSideEffects(hse), IsVariadic(isv) { } /// Analyze - Analyze the specified instruction, returning true if the @@ -2313,6 +2369,29 @@ public: } private: + bool IsNodeBitcast(const TreePatternNode *N) const { + if (HasSideEffects || mayLoad || mayStore || IsVariadic) + return false; + + if (N->getNumChildren() != 2) + return false; + + const TreePatternNode *N0 = N->getChild(0); + if (!N0->isLeaf() || !dynamic_cast<DefInit*>(N0->getLeafValue())) + return false; + + const TreePatternNode *N1 = N->getChild(1); + if (N1->isLeaf()) + return false; + if (N1->getNumChildren() != 1 || !N1->getChild(0)->isLeaf()) + return false; + + const SDNodeInfo &OpInfo = CDP.getSDNodeInfo(N1->getOperator()); + if (OpInfo.getNumResults() != 1 || OpInfo.getNumOperands() != 1) + return false; + return OpInfo.getEnumName() == "ISD::BITCAST"; + } + void AnalyzeNode(const TreePatternNode *N) { if (N->isLeaf()) { if (DefInit *DI = dynamic_cast<DefInit*>(N->getLeafValue())) { @@ -2333,8 +2412,10 @@ private: AnalyzeNode(N->getChild(i)); // Ignore set nodes, which are not SDNodes. - if (N->getOperator()->getName() == "set") + if (N->getOperator()->getName() == "set") { + IsBitcast = IsNodeBitcast(N); return; + } // Get information about the SDNode for the operator. const SDNodeInfo &OpInfo = CDP.getSDNodeInfo(N->getOperator()); @@ -2363,12 +2444,13 @@ private: static void InferFromPattern(const CodeGenInstruction &Inst, bool &MayStore, bool &MayLoad, + bool &IsBitcast, bool &HasSideEffects, bool &IsVariadic, const CodeGenDAGPatterns &CDP) { - MayStore = MayLoad = HasSideEffects = IsVariadic = false; + MayStore = MayLoad = IsBitcast = HasSideEffects = IsVariadic = false; bool HadPattern = - InstAnalyzer(CDP, MayStore, MayLoad, HasSideEffects, IsVariadic) + InstAnalyzer(CDP, MayStore, MayLoad, IsBitcast, HasSideEffects, IsVariadic) .Analyze(Inst.TheDef); // InstAnalyzer only correctly analyzes mayStore/mayLoad so far. @@ -2714,11 +2796,12 @@ void CodeGenDAGPatterns::InferInstructionFlags() { CodeGenInstruction &InstInfo = const_cast<CodeGenInstruction &>(*Instructions[i]); // Determine properties of the instruction from its pattern. - bool MayStore, MayLoad, HasSideEffects, IsVariadic; - InferFromPattern(InstInfo, MayStore, MayLoad, HasSideEffects, IsVariadic, - *this); + bool MayStore, MayLoad, IsBitcast, HasSideEffects, IsVariadic; + InferFromPattern(InstInfo, MayStore, MayLoad, IsBitcast, + HasSideEffects, IsVariadic, *this); InstInfo.mayStore = MayStore; InstInfo.mayLoad = MayLoad; + InstInfo.isBitcast = IsBitcast; InstInfo.hasSideEffects = HasSideEffects; InstInfo.Operands.isVariadic = IsVariadic; } diff --git a/utils/TableGen/CodeGenDAGPatterns.h b/utils/TableGen/CodeGenDAGPatterns.h index 946dcee..e4e8574 100644 --- a/utils/TableGen/CodeGenDAGPatterns.h +++ b/utils/TableGen/CodeGenDAGPatterns.h @@ -239,6 +239,57 @@ public: return MadeChange; } }; + +/// TreePredicateFn - This is an abstraction that represents the predicates on +/// a PatFrag node. This is a simple one-word wrapper around a pointer to +/// provide nice accessors. +class TreePredicateFn { + /// PatFragRec - This is the TreePattern for the PatFrag that we + /// originally came from. + TreePattern *PatFragRec; +public: + /// TreePredicateFn constructor. Here 'N' is a subclass of PatFrag. + TreePredicateFn(TreePattern *N); + + + TreePattern *getOrigPatFragRecord() const { return PatFragRec; } + + /// isAlwaysTrue - Return true if this is a noop predicate. + bool isAlwaysTrue() const; + + bool isImmediatePattern() const { return !getImmCode().empty(); } + + /// getImmediatePredicateCode - Return the code that evaluates this pattern if + /// this is an immediate predicate. It is an error to call this on a + /// non-immediate pattern. + std::string getImmediatePredicateCode() const { + std::string Result = getImmCode(); + assert(!Result.empty() && "Isn't an immediate pattern!"); + return Result; + } + + + bool operator==(const TreePredicateFn &RHS) const { + return PatFragRec == RHS.PatFragRec; + } + + bool operator!=(const TreePredicateFn &RHS) const { return !(*this == RHS); } + + /// Return the name to use in the generated code to reference this, this is + /// "Predicate_foo" if from a pattern fragment "foo". + std::string getFnName() const; + + /// getCodeToRunOnSDNode - Return the code for the function body that + /// evaluates this predicate. The argument is expected to be in "Node", + /// not N. This handles casting and conversion to a concrete node type as + /// appropriate. + std::string getCodeToRunOnSDNode() const; + +private: + std::string getPredCode() const; + std::string getImmCode() const; +}; + /// FIXME: TreePatternNode's can be shared in some cases (due to dag-shaped /// patterns), and as such should be ref counted. We currently just leak all @@ -263,7 +314,7 @@ class TreePatternNode { /// PredicateFns - The predicate functions to execute on this node to check /// for a match. If this list is empty, no predicate is involved. - std::vector<std::string> PredicateFns; + std::vector<TreePredicateFn> PredicateFns; /// TransformFn - The transformation function to execute on this node before /// it can be substituted into the resulting instruction on a pattern match. @@ -323,14 +374,18 @@ public: return false; } - const std::vector<std::string> &getPredicateFns() const {return PredicateFns;} + bool hasAnyPredicate() const { return !PredicateFns.empty(); } + + const std::vector<TreePredicateFn> &getPredicateFns() const { + return PredicateFns; + } void clearPredicateFns() { PredicateFns.clear(); } - void setPredicateFns(const std::vector<std::string> &Fns) { + void setPredicateFns(const std::vector<TreePredicateFn> &Fns) { assert(PredicateFns.empty() && "Overwriting non-empty predicate list!"); PredicateFns = Fns; } - void addPredicateFn(const std::string &Fn) { - assert(!Fn.empty() && "Empty predicate string!"); + void addPredicateFn(const TreePredicateFn &Fn) { + assert(!Fn.isAlwaysTrue() && "Empty predicate string!"); if (std::find(PredicateFns.begin(), PredicateFns.end(), Fn) == PredicateFns.end()) PredicateFns.push_back(Fn); diff --git a/utils/TableGen/CodeGenInstruction.cpp b/utils/TableGen/CodeGenInstruction.cpp index f37d3ea..5b0aedf 100644 --- a/utils/TableGen/CodeGenInstruction.cpp +++ b/utils/TableGen/CodeGenInstruction.cpp @@ -288,6 +288,7 @@ CodeGenInstruction::CodeGenInstruction(Record *R) : TheDef(R), Operands(R) { isIndirectBranch = R->getValueAsBit("isIndirectBranch"); isCompare = R->getValueAsBit("isCompare"); isMoveImm = R->getValueAsBit("isMoveImm"); + isBitcast = R->getValueAsBit("isBitcast"); isBarrier = R->getValueAsBit("isBarrier"); isCall = R->getValueAsBit("isCall"); canFoldAsLoad = R->getValueAsBit("canFoldAsLoad"); diff --git a/utils/TableGen/CodeGenInstruction.h b/utils/TableGen/CodeGenInstruction.h index 58913b9..5f1e0be 100644 --- a/utils/TableGen/CodeGenInstruction.h +++ b/utils/TableGen/CodeGenInstruction.h @@ -26,7 +26,7 @@ namespace llvm { class DagInit; class CodeGenTarget; class StringRef; - + class CGIOperandList { public: class ConstraintInfo { @@ -34,25 +34,25 @@ namespace llvm { unsigned OtherTiedOperand; public: ConstraintInfo() : Kind(None) {} - + static ConstraintInfo getEarlyClobber() { ConstraintInfo I; I.Kind = EarlyClobber; I.OtherTiedOperand = 0; return I; } - + static ConstraintInfo getTied(unsigned Op) { ConstraintInfo I; I.Kind = Tied; I.OtherTiedOperand = Op; return I; } - + bool isNone() const { return Kind == None; } bool isEarlyClobber() const { return Kind == EarlyClobber; } bool isTied() const { return Kind == Tied; } - + unsigned getTiedOperand() const { assert(isTied()); return OtherTiedOperand; @@ -65,19 +65,19 @@ namespace llvm { /// Rec - The definition this operand is declared as. /// Record *Rec; - + /// Name - If this operand was assigned a symbolic name, this is it, /// otherwise, it's empty. std::string Name; - + /// PrinterMethodName - The method used to print operands of this type in /// the asmprinter. std::string PrinterMethodName; - + /// EncoderMethodName - The method used to get the machine operand value /// for binary encoding. "getMachineOpValue" by default. std::string EncoderMethodName; - + /// MIOperandNo - Currently (this is meant to be phased out), some logical /// operands correspond to multiple MachineInstr operands. In the X86 /// target for example, one address operand is represented as 4 @@ -86,27 +86,27 @@ namespace llvm { /// does, this contains the MI operand index of this operand. unsigned MIOperandNo; unsigned MINumOperands; // The number of operands. - + /// DoNotEncode - Bools are set to true in this vector for each operand in /// the DisableEncoding list. These should not be emitted by the code /// emitter. std::vector<bool> DoNotEncode; - + /// MIOperandInfo - Default MI operand type. Note an operand may be made /// up of multiple MI operands. DagInit *MIOperandInfo; - + /// Constraint info for this operand. This operand can have pieces, so we /// track constraint info for each. std::vector<ConstraintInfo> Constraints; - + OperandInfo(Record *R, const std::string &N, const std::string &PMN, const std::string &EMN, unsigned MION, unsigned MINO, DagInit *MIOI) : Rec(R), Name(N), PrinterMethodName(PMN), EncoderMethodName(EMN), MIOperandNo(MION), MINumOperands(MINO), MIOperandInfo(MIOI) {} - - + + /// getTiedOperand - If this operand is tied to another one, return the /// other operand number. Otherwise, return -1. int getTiedRegister() const { @@ -117,43 +117,44 @@ namespace llvm { return -1; } }; - + CGIOperandList(Record *D); - + Record *TheDef; // The actual record containing this OperandList. /// NumDefs - Number of def operands declared, this is the number of /// elements in the instruction's (outs) list. /// unsigned NumDefs; - + /// OperandList - The list of declared operands, along with their declared /// type (which is a record). std::vector<OperandInfo> OperandList; - + // Information gleaned from the operand list. bool isPredicable; bool hasOptionalDef; bool isVariadic; - + // Provide transparent accessors to the operand list. + bool empty() const { return OperandList.empty(); } unsigned size() const { return OperandList.size(); } const OperandInfo &operator[](unsigned i) const { return OperandList[i]; } OperandInfo &operator[](unsigned i) { return OperandList[i]; } OperandInfo &back() { return OperandList.back(); } const OperandInfo &back() const { return OperandList.back(); } - - + + /// getOperandNamed - Return the index of the operand with the specified /// non-empty name. If the instruction does not have an operand with the /// specified name, throw an exception. unsigned getOperandNamed(StringRef Name) const; - + /// hasOperandNamed - Query whether the instruction has an operand of the /// given name. If so, return true and set OpIdx to the index of the /// operand. Otherwise, return false. bool hasOperandNamed(StringRef Name, unsigned &OpIdx) const; - + /// ParseOperandName - Parse an operand name like "$foo" or "$foo.bar", /// where $foo is a whole operand and $foo.bar refers to a suboperand. /// This throws an exception if the name is invalid. If AllowWholeOp is @@ -161,13 +162,13 @@ namespace llvm { /// not. std::pair<unsigned,unsigned> ParseOperandName(const std::string &Op, bool AllowWholeOp = true); - + /// getFlattenedOperandNumber - Flatten a operand/suboperand pair into a /// flat machineinstr operand #. unsigned getFlattenedOperandNumber(std::pair<unsigned,unsigned> Op) const { return OperandList[Op.first].MIOperandNo + Op.second; } - + /// getSubOperandNumber - Unflatten a operand number into an /// operand/suboperand pair. std::pair<unsigned,unsigned> getSubOperandNumber(unsigned Op) const { @@ -177,8 +178,8 @@ namespace llvm { return std::make_pair(i, Op-OperandList[i].MIOperandNo); } } - - + + /// isFlatOperandNotEmitted - Return true if the specified flat operand # /// should not be emitted with the code emitter. bool isFlatOperandNotEmitted(unsigned FlatOpNo) const { @@ -187,10 +188,10 @@ namespace llvm { return OperandList[Op.first].DoNotEncode[Op.second]; return false; } - + void ProcessDisableEncoding(std::string Value); }; - + class CodeGenInstruction { public: @@ -215,6 +216,7 @@ namespace llvm { bool isIndirectBranch; bool isCompare; bool isMoveImm; + bool isBitcast; bool isBarrier; bool isCall; bool canFoldAsLoad; @@ -242,45 +244,45 @@ namespace llvm { /// MVT::Other. MVT::SimpleValueType HasOneImplicitDefWithKnownVT(const CodeGenTarget &TargetInfo) const; - - + + /// FlattenAsmStringVariants - Flatten the specified AsmString to only /// include text from the specified variant, returning the new string. static std::string FlattenAsmStringVariants(StringRef AsmString, unsigned Variant); }; - - + + /// CodeGenInstAlias - This represents an InstAlias definition. class CodeGenInstAlias { public: Record *TheDef; // The actual record defining this InstAlias. - + /// AsmString - The format string used to emit a .s file for the /// instruction. std::string AsmString; - + /// Result - The result instruction. DagInit *Result; - + /// ResultInst - The instruction generated by the alias (decoded from /// Result). CodeGenInstruction *ResultInst; - - + + struct ResultOperand { private: StringRef Name; Record *R; - + int64_t Imm; - public: + public: enum { K_Record, K_Imm, K_Reg } Kind; - + ResultOperand(StringRef N, Record *r) : Name(N), R(r), Kind(K_Record) {} ResultOperand(int64_t I) : Imm(I), Kind(K_Imm) {} ResultOperand(Record *r) : R(r), Kind(K_Reg) {} @@ -288,13 +290,13 @@ namespace llvm { bool isRecord() const { return Kind == K_Record; } bool isImm() const { return Kind == K_Imm; } bool isReg() const { return Kind == K_Reg; } - + StringRef getName() const { assert(isRecord()); return Name; } Record *getRecord() const { assert(isRecord()); return R; } int64_t getImm() const { assert(isImm()); return Imm; } Record *getRegister() const { assert(isReg()); return R; } }; - + /// ResultOperands - The decoded operands for the result instruction. std::vector<ResultOperand> ResultOperands; @@ -304,13 +306,13 @@ namespace llvm { /// index specifies the suboperand. If there are no suboperands or if all /// of them are matched by the operand, the second value should be -1. std::vector<std::pair<unsigned, int> > ResultInstOperandIndex; - + CodeGenInstAlias(Record *R, CodeGenTarget &T); bool tryAliasOpMatch(DagInit *Result, unsigned AliasOpNo, Record *InstOpRec, bool hasSubOps, SMLoc Loc, CodeGenTarget &T, ResultOperand &ResOp); - }; + }; } #endif diff --git a/utils/TableGen/CodeGenRegisters.h b/utils/TableGen/CodeGenRegisters.h index bbd0cef..39b92c5 100644 --- a/utils/TableGen/CodeGenRegisters.h +++ b/utils/TableGen/CodeGenRegisters.h @@ -29,7 +29,8 @@ namespace llvm { struct CodeGenRegister { Record *TheDef; const std::string &getName() const; - unsigned DeclaredSpillSize, DeclaredSpillAlignment; + unsigned EnumValue; + unsigned CostPerUse; CodeGenRegister(Record *R); }; @@ -49,23 +50,23 @@ namespace llvm { const std::string &getName() const; const std::vector<MVT::SimpleValueType> &getValueTypes() const {return VTs;} unsigned getNumValueTypes() const { return VTs.size(); } - + MVT::SimpleValueType getValueTypeNum(unsigned VTNum) const { if (VTNum < VTs.size()) return VTs[VTNum]; assert(0 && "VTNum greater than number of ValueTypes in RegClass!"); abort(); } - + bool containsRegister(Record *R) const { for (unsigned i = 0, e = Elements.size(); i != e; ++i) if (Elements[i] == R) return true; return false; } - + // Returns true if RC is a strict subclass. // RC is a sub-class of this class if it is a valid replacement for any - // instruction operand where a register of this classis required. It must + // instruction operand where a register of this classis required. It must // satisfy these conditions: // // 1. All RC registers are also in this. diff --git a/utils/TableGen/CodeGenTarget.cpp b/utils/TableGen/CodeGenTarget.cpp index d0f7d8b..57f7fdc 100644 --- a/utils/TableGen/CodeGenTarget.cpp +++ b/utils/TableGen/CodeGenTarget.cpp @@ -164,11 +164,13 @@ void CodeGenTarget::ReadRegisters() const { Registers.reserve(Regs.size()); Registers.assign(Regs.begin(), Regs.end()); + // Assign the enumeration values. + for (unsigned i = 0, e = Registers.size(); i != e; ++i) + Registers[i].EnumValue = i + 1; } CodeGenRegister::CodeGenRegister(Record *R) : TheDef(R) { - DeclaredSpillSize = R->getValueAsInt("SpillSize"); - DeclaredSpillAlignment = R->getValueAsInt("SpillAlignment"); + CostPerUse = R->getValueAsInt("CostPerUse"); } const std::string &CodeGenRegister::getName() const { @@ -199,7 +201,7 @@ const CodeGenRegister *CodeGenTarget::getRegisterByName(StringRef Name) const { if (Reg.TheDef->getValueAsString("AsmName") == Name) return &Reg; } - + return 0; } @@ -216,7 +218,7 @@ getRegisterVTs(Record *R) const { } } } - + // Remove duplicates. array_pod_sort(Result.begin(), Result.end()); Result.erase(std::unique(Result.begin(), Result.end()), Result.end()); @@ -229,8 +231,8 @@ CodeGenRegisterClass::CodeGenRegisterClass(Record *R) : TheDef(R) { if (R->getName().size() > 9 && R->getName()[9] == '.') { static unsigned AnonCounter = 0; R->setName("AnonRegClass_"+utostr(AnonCounter++)); - } - + } + std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes"); for (unsigned i = 0, e = TypeList.size(); i != e; ++i) { Record *Type = TypeList[i]; @@ -240,7 +242,7 @@ CodeGenRegisterClass::CodeGenRegisterClass(Record *R) : TheDef(R) { VTs.push_back(getValueType(Type)); } assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!"); - + std::vector<Record*> RegList = R->getValueAsListOfDefs("MemberList"); for (unsigned i = 0, e = RegList.size(); i != e; ++i) { Record *Reg = RegList[i]; @@ -293,7 +295,7 @@ void CodeGenTarget::ReadLegalValueTypes() const { for (unsigned i = 0, e = RCs.size(); i != e; ++i) for (unsigned ri = 0, re = RCs[i].VTs.size(); ri != re; ++ri) LegalValueTypes.push_back(RCs[i].VTs[ri]); - + // Remove duplicates. std::sort(LegalValueTypes.begin(), LegalValueTypes.end()); LegalValueTypes.erase(std::unique(LegalValueTypes.begin(), @@ -314,10 +316,10 @@ void CodeGenTarget::ReadInstructions() const { static const CodeGenInstruction * GetInstByName(const char *Name, - const DenseMap<const Record*, CodeGenInstruction*> &Insts, + const DenseMap<const Record*, CodeGenInstruction*> &Insts, RecordKeeper &Records) { const Record *Rec = Records.getDef(Name); - + DenseMap<const Record*, CodeGenInstruction*>::const_iterator I = Insts.find(Rec); if (Rec == 0 || I == Insts.end()) @@ -434,7 +436,7 @@ ComplexPattern::ComplexPattern(Record *R) { std::vector<CodeGenIntrinsic> llvm::LoadIntrinsics(const RecordKeeper &RC, bool TargetOnly) { std::vector<Record*> I = RC.getAllDerivedDefinitions("Intrinsic"); - + std::vector<CodeGenIntrinsic> Result; for (unsigned i = 0, e = I.size(); i != e; ++i) { @@ -451,8 +453,8 @@ CodeGenIntrinsic::CodeGenIntrinsic(Record *R) { ModRef = ReadWriteMem; isOverloaded = false; isCommutative = false; - - if (DefName.size() <= 4 || + + if (DefName.size() <= 4 || std::string(DefName.begin(), DefName.begin() + 4) != "int_") throw "Intrinsic '" + DefName + "' does not start with 'int_'!"; @@ -472,11 +474,11 @@ CodeGenIntrinsic::CodeGenIntrinsic(Record *R) { Name += (EnumName[i] == '_') ? '.' : EnumName[i]; } else { // Verify it starts with "llvm.". - if (Name.size() <= 5 || + if (Name.size() <= 5 || std::string(Name.begin(), Name.begin() + 5) != "llvm.") throw "Intrinsic '" + DefName + "'s name does not start with 'llvm.'!"; } - + // If TargetPrefix is specified, make sure that Name starts with // "llvm.<targetprefix>.". if (!TargetPrefix.empty()) { @@ -486,7 +488,7 @@ CodeGenIntrinsic::CodeGenIntrinsic(Record *R) { throw "Intrinsic '" + DefName + "' does not start with 'llvm." + TargetPrefix + ".'!"; } - + // Parse the list of return types. std::vector<MVT::SimpleValueType> OverloadedVTs; ListInit *TypeList = R->getValueAsListInit("RetTypes"); @@ -517,11 +519,11 @@ CodeGenIntrinsic::CodeGenIntrinsic(Record *R) { // Reject invalid types. if (VT == MVT::isVoid) throw "Intrinsic '" + DefName + " has void in result type list!"; - + IS.RetVTs.push_back(VT); IS.RetTypeDefs.push_back(TyEl); } - + // Parse the list of parameter types. TypeList = R->getValueAsListInit("ParamTypes"); for (unsigned i = 0, e = TypeList->getSize(); i != e; ++i) { @@ -542,16 +544,16 @@ CodeGenIntrinsic::CodeGenIntrinsic(Record *R) { "Expected iAny or vAny type"); } else VT = getValueType(TyEl->getValueAsDef("VT")); - + if (EVT(VT).isOverloaded()) { OverloadedVTs.push_back(VT); isOverloaded = true; } - + // Reject invalid types. if (VT == MVT::isVoid && i != e-1 /*void at end means varargs*/) throw "Intrinsic '" + DefName + " has void in result type list!"; - + IS.ParamVTs.push_back(VT); IS.ParamTypeDefs.push_back(TyEl); } @@ -562,7 +564,7 @@ CodeGenIntrinsic::CodeGenIntrinsic(Record *R) { Record *Property = PropList->getElementAsRecord(i); assert(Property->isSubClassOf("IntrinsicProperty") && "Expected a property!"); - + if (Property->getName() == "IntrNoMem") ModRef = NoMem; else if (Property->getName() == "IntrReadArgMem") diff --git a/utils/TableGen/CodeGenTarget.h b/utils/TableGen/CodeGenTarget.h index f1058eb..4e04154 100644 --- a/utils/TableGen/CodeGenTarget.h +++ b/utils/TableGen/CodeGenTarget.h @@ -32,8 +32,8 @@ class CodeGenTarget; // SDNPMemOperand: indicates that a node touches memory and therefore must // have an associated memory operand that describes the access. enum SDNP { - SDNPCommutative, - SDNPAssociative, + SDNPCommutative, + SDNPAssociative, SDNPHasChain, SDNPOutGlue, SDNPInGlue, @@ -57,7 +57,7 @@ std::string getEnumName(MVT::SimpleValueType T); /// getQualifiedName - Return the name of the specified record, with a /// namespace qualifier if the record contains one. std::string getQualifiedName(const Record *R); - + /// CodeGenTarget - This class corresponds to the Target class in the .td files. /// class CodeGenTarget { @@ -74,7 +74,7 @@ class CodeGenTarget { void ReadRegisterClasses() const; void ReadInstructions() const; void ReadLegalValueTypes() const; - + mutable std::vector<const CodeGenInstruction*> InstrsByEnum; public: CodeGenTarget(RecordKeeper &Records); @@ -102,7 +102,7 @@ public: if (Registers.empty()) ReadRegisters(); return Registers; } - + /// getRegisterByName - If there is a register with the specific AsmName, /// return it. const CodeGenRegister *getRegisterByName(StringRef Name) const; @@ -134,7 +134,7 @@ public: assert(0 && "Didn't find the register class"); abort(); } - + /// getRegisterClassForRegister - Find the register class that contains the /// specified physical register. If the register is not in a register /// class, return null. If the register is in multiple classes, and the @@ -192,19 +192,19 @@ public: /// getRegisterVTs - Find the union of all possible SimpleValueTypes for the /// specified physical register. std::vector<MVT::SimpleValueType> getRegisterVTs(Record *R) const; - + const std::vector<MVT::SimpleValueType> &getLegalValueTypes() const { if (LegalValueTypes.empty()) ReadLegalValueTypes(); return LegalValueTypes; } - + /// isLegalValueType - Return true if the specified value type is natively /// supported by the target (i.e. there are registers that directly hold it). bool isLegalValueType(MVT::SimpleValueType VT) const { const std::vector<MVT::SimpleValueType> &LegalVTs = getLegalValueTypes(); for (unsigned i = 0, e = LegalVTs.size(); i != e; ++i) if (LegalVTs[i] == VT) return true; - return false; + return false; } private: @@ -213,7 +213,7 @@ private: return Instructions; } public: - + CodeGenInstruction &getInstruction(const Record *InstRec) const { if (Instructions.empty()) ReadInstructions(); DenseMap<const Record*, CodeGenInstruction*>::iterator I = @@ -233,12 +233,12 @@ public: typedef std::vector<const CodeGenInstruction*>::const_iterator inst_iterator; inst_iterator inst_begin() const{return getInstructionsByEnumValue().begin();} inst_iterator inst_end() const { return getInstructionsByEnumValue().end(); } - - + + /// isLittleEndianEncoding - are instruction bit patterns defined as [0..n]? /// bool isLittleEndianEncoding() const; - + private: void ComputeInstrsByEnum() const; }; diff --git a/utils/TableGen/DAGISelEmitter.cpp b/utils/TableGen/DAGISelEmitter.cpp index 8a73404..d66ae96 100644 --- a/utils/TableGen/DAGISelEmitter.cpp +++ b/utils/TableGen/DAGISelEmitter.cpp @@ -27,7 +27,7 @@ using namespace llvm; static unsigned getResultPatternCost(TreePatternNode *P, CodeGenDAGPatterns &CGP) { if (P->isLeaf()) return 0; - + unsigned Cost = 0; Record *Op = P->getOperator(); if (Op->isSubClassOf("Instruction")) { @@ -43,7 +43,7 @@ static unsigned getResultPatternCost(TreePatternNode *P, /// getResultPatternCodeSize - Compute the code size of instructions for this /// pattern. -static unsigned getResultPatternSize(TreePatternNode *P, +static unsigned getResultPatternSize(TreePatternNode *P, CodeGenDAGPatterns &CGP) { if (P->isLeaf()) return 0; @@ -64,21 +64,21 @@ namespace { struct PatternSortingPredicate { PatternSortingPredicate(CodeGenDAGPatterns &cgp) : CGP(cgp) {} CodeGenDAGPatterns &CGP; - + bool operator()(const PatternToMatch *LHS, const PatternToMatch *RHS) { const TreePatternNode *LHSSrc = LHS->getSrcPattern(); const TreePatternNode *RHSSrc = RHS->getSrcPattern(); - + if (LHSSrc->getNumTypes() != 0 && RHSSrc->getNumTypes() != 0 && LHSSrc->getType(0) != RHSSrc->getType(0)) { MVT::SimpleValueType V1 = LHSSrc->getType(0), V2 = RHSSrc->getType(0); if (MVT(V1).isVector() != MVT(V2).isVector()) return MVT(V2).isVector(); - + if (MVT(V1).isFloatingPoint() != MVT(V2).isFloatingPoint()) return MVT(V2).isFloatingPoint(); } - + // Otherwise, if the patterns might both match, sort based on complexity, // which means that we prefer to match patterns that cover more nodes in the // input over nodes that cover fewer. @@ -86,18 +86,18 @@ struct PatternSortingPredicate { unsigned RHSSize = RHS->getPatternComplexity(CGP); if (LHSSize > RHSSize) return true; // LHS -> bigger -> less cost if (LHSSize < RHSSize) return false; - + // If the patterns have equal complexity, compare generated instruction cost unsigned LHSCost = getResultPatternCost(LHS->getDstPattern(), CGP); unsigned RHSCost = getResultPatternCost(RHS->getDstPattern(), CGP); if (LHSCost < RHSCost) return true; if (LHSCost > RHSCost) return false; - + unsigned LHSPatSize = getResultPatternSize(LHS->getDstPattern(), CGP); unsigned RHSPatSize = getResultPatternSize(RHS->getDstPattern(), CGP); if (LHSPatSize < RHSPatSize) return true; if (LHSPatSize > RHSPatSize) return false; - + // Sort based on the UID of the pattern, giving us a deterministic ordering // if all other sorting conditions fail. assert(LHS == RHS || LHS->ID != RHS->ID); @@ -110,7 +110,7 @@ struct PatternSortingPredicate { void DAGISelEmitter::run(raw_ostream &OS) { EmitSourceFileHeader("DAG Instruction Selector for the " + CGP.getTargetInfo().getName() + " target", OS); - + OS << "// *** NOTE: This file is #included into the middle of the target\n" << "// *** instruction selector class. These functions are really " << "methods.\n\n"; @@ -132,8 +132,8 @@ void DAGISelEmitter::run(raw_ostream &OS) { // We want to process the matches in order of minimal cost. Sort the patterns // so the least cost one is at the start. std::sort(Patterns.begin(), Patterns.end(), PatternSortingPredicate(CGP)); - - + + // Convert each variant of each pattern into a Matcher. std::vector<Matcher*> PatternMatchers; for (unsigned i = 0, e = Patterns.size(); i != e; ++i) { @@ -144,7 +144,7 @@ void DAGISelEmitter::run(raw_ostream &OS) { break; } } - + Matcher *TheMatcher = new ScopeMatcher(&PatternMatchers[0], PatternMatchers.size()); diff --git a/utils/TableGen/DAGISelEmitter.h b/utils/TableGen/DAGISelEmitter.h index 2117e65..35ab550 100644 --- a/utils/TableGen/DAGISelEmitter.h +++ b/utils/TableGen/DAGISelEmitter.h @@ -16,7 +16,6 @@ #include "TableGenBackend.h" #include "CodeGenDAGPatterns.h" -#include <set> namespace llvm { diff --git a/utils/TableGen/DAGISelMatcher.cpp b/utils/TableGen/DAGISelMatcher.cpp index 2afa2b9..b12e101 100644 --- a/utils/TableGen/DAGISelMatcher.cpp +++ b/utils/TableGen/DAGISelMatcher.cpp @@ -83,6 +83,15 @@ ScopeMatcher::~ScopeMatcher() { } +CheckPredicateMatcher::CheckPredicateMatcher(const TreePredicateFn &pred) + : Matcher(CheckPredicate), Pred(pred.getOrigPatFragRecord()) {} + +TreePredicateFn CheckPredicateMatcher::getPredicate() const { + return TreePredicateFn(Pred); +} + + + // printImpl methods. void ScopeMatcher::printImpl(raw_ostream &OS, unsigned indent) const { @@ -129,7 +138,7 @@ printImpl(raw_ostream &OS, unsigned indent) const { } void CheckPredicateMatcher::printImpl(raw_ostream &OS, unsigned indent) const { - OS.indent(indent) << "CheckPredicate " << PredName << '\n'; + OS.indent(indent) << "CheckPredicate " << getPredicate().getFnName() << '\n'; } void CheckOpcodeMatcher::printImpl(raw_ostream &OS, unsigned indent) const { @@ -263,7 +272,7 @@ unsigned CheckPatternPredicateMatcher::getHashImpl() const { } unsigned CheckPredicateMatcher::getHashImpl() const { - return HashString(PredName); + return HashString(getPredicate().getFnName()); } unsigned CheckOpcodeMatcher::getHashImpl() const { @@ -301,7 +310,6 @@ bool CheckOpcodeMatcher::isEqualImpl(const Matcher *M) const { Opcode.getEnumName(); } - bool EmitNodeMatcherCommon::isEqualImpl(const Matcher *m) const { const EmitNodeMatcherCommon *M = cast<EmitNodeMatcherCommon>(m); return M->OpcodeName == OpcodeName && M->VTs == VTs && diff --git a/utils/TableGen/DAGISelMatcher.h b/utils/TableGen/DAGISelMatcher.h index 8e6e446..dcb8da7 100644 --- a/utils/TableGen/DAGISelMatcher.h +++ b/utils/TableGen/DAGISelMatcher.h @@ -17,6 +17,7 @@ #include "llvm/Support/Casting.h" namespace llvm { + struct CodeGenRegister; class CodeGenDAGPatterns; class Matcher; class PatternToMatch; @@ -24,6 +25,8 @@ namespace llvm { class ComplexPattern; class Record; class SDNodeInfo; + class TreePredicateFn; + class TreePattern; Matcher *ConvertPatternToMatcher(const PatternToMatch &Pattern,unsigned Variant, const CodeGenDAGPatterns &CGP); @@ -418,12 +421,11 @@ private: /// CheckPredicateMatcher - This checks the target-specific predicate to /// see if the node is acceptable. class CheckPredicateMatcher : public Matcher { - StringRef PredName; + TreePattern *Pred; public: - CheckPredicateMatcher(StringRef predname) - : Matcher(CheckPredicate), PredName(predname) {} + CheckPredicateMatcher(const TreePredicateFn &pred); - StringRef getPredicateName() const { return PredName; } + TreePredicateFn getPredicate() const; static inline bool classof(const Matcher *N) { return N->getKind() == CheckPredicate; @@ -435,7 +437,7 @@ public: private: virtual void printImpl(raw_ostream &OS, unsigned indent) const; virtual bool isEqualImpl(const Matcher *M) const { - return cast<CheckPredicateMatcher>(M)->PredName == PredName; + return cast<CheckPredicateMatcher>(M)->Pred == Pred; } virtual unsigned getHashImpl() const; }; @@ -816,13 +818,13 @@ private: class EmitRegisterMatcher : public Matcher { /// Reg - The def for the register that we're emitting. If this is null, then /// this is a reference to zero_reg. - Record *Reg; + const CodeGenRegister *Reg; MVT::SimpleValueType VT; public: - EmitRegisterMatcher(Record *reg, MVT::SimpleValueType vt) + EmitRegisterMatcher(const CodeGenRegister *reg, MVT::SimpleValueType vt) : Matcher(EmitRegister), Reg(reg), VT(vt) {} - Record *getReg() const { return Reg; } + const CodeGenRegister *getReg() const { return Reg; } MVT::SimpleValueType getVT() const { return VT; } static inline bool classof(const Matcher *N) { diff --git a/utils/TableGen/DAGISelMatcherEmitter.cpp b/utils/TableGen/DAGISelMatcherEmitter.cpp index 0b7fbf7..acb0135 100644 --- a/utils/TableGen/DAGISelMatcherEmitter.cpp +++ b/utils/TableGen/DAGISelMatcherEmitter.cpp @@ -33,8 +33,12 @@ OmitComments("omit-comments", cl::desc("Do not generate comments"), namespace { class MatcherTableEmitter { const CodeGenDAGPatterns &CGP; - StringMap<unsigned> NodePredicateMap, PatternPredicateMap; - std::vector<std::string> NodePredicates, PatternPredicates; + + DenseMap<TreePattern *, unsigned> NodePredicateMap; + std::vector<TreePredicateFn> NodePredicates; + + StringMap<unsigned> PatternPredicateMap; + std::vector<std::string> PatternPredicates; DenseMap<const ComplexPattern*, unsigned> ComplexPatternMap; std::vector<const ComplexPattern*> ComplexPatterns; @@ -44,26 +48,28 @@ class MatcherTableEmitter { std::vector<Record*> NodeXForms; public: - MatcherTableEmitter(const CodeGenDAGPatterns &cgp) : CGP(cgp) {} + MatcherTableEmitter(const CodeGenDAGPatterns &cgp) + : CGP(cgp) {} unsigned EmitMatcherList(const Matcher *N, unsigned Indent, unsigned StartIdx, formatted_raw_ostream &OS); - + void EmitPredicateFunctions(formatted_raw_ostream &OS); - + void EmitHistogram(const Matcher *N, formatted_raw_ostream &OS); private: unsigned EmitMatcher(const Matcher *N, unsigned Indent, unsigned CurrentIdx, formatted_raw_ostream &OS); - - unsigned getNodePredicate(StringRef PredName) { - unsigned &Entry = NodePredicateMap[PredName]; + + unsigned getNodePredicate(TreePredicateFn Pred) { + unsigned &Entry = NodePredicateMap[Pred.getOrigPatFragRecord()]; if (Entry == 0) { - NodePredicates.push_back(PredName.str()); + NodePredicates.push_back(Pred); Entry = NodePredicates.size(); } return Entry-1; } + unsigned getPatternPredicate(StringRef PredName) { unsigned &Entry = PatternPredicateMap[PredName]; if (Entry == 0) { @@ -72,7 +78,6 @@ private: } return Entry-1; } - unsigned getComplexPat(const ComplexPattern &P) { unsigned &Entry = ComplexPatternMap[&P]; if (Entry == 0) { @@ -81,7 +86,7 @@ private: } return Entry-1; } - + unsigned getNodeXFormID(Record *Rec) { unsigned &Entry = NodeXFormMap[Rec]; if (Entry == 0) { @@ -90,13 +95,13 @@ private: } return Entry-1; } - + }; } // end anonymous namespace. static unsigned GetVBRSize(unsigned Val) { if (Val <= 127) return 1; - + unsigned NumBytes = 0; while (Val >= 128) { Val >>= 7; @@ -112,7 +117,7 @@ static uint64_t EmitVBRValue(uint64_t Val, raw_ostream &OS) { OS << Val << ", "; return 1; } - + uint64_t InVal = Val; unsigned NumBytes = 0; while (Val >= 128) { @@ -133,14 +138,14 @@ unsigned MatcherTableEmitter:: EmitMatcher(const Matcher *N, unsigned Indent, unsigned CurrentIdx, formatted_raw_ostream &OS) { OS.PadToColumn(Indent*2); - + switch (N->getKind()) { case Matcher::Scope: { const ScopeMatcher *SM = cast<ScopeMatcher>(N); assert(SM->getNext() == 0 && "Shouldn't have next after scope"); - + unsigned StartIdx = CurrentIdx; - + // Emit all of the children. for (unsigned i = 0, e = SM->getNumChildren(); i != e; ++i) { if (i == 0) { @@ -164,29 +169,29 @@ EmitMatcher(const Matcher *N, unsigned Indent, unsigned CurrentIdx, unsigned VBRSize = 0; do { VBRSize = GetVBRSize(ChildSize); - + TmpBuf.clear(); raw_svector_ostream OS(TmpBuf); formatted_raw_ostream FOS(OS); ChildSize = EmitMatcherList(SM->getChild(i), Indent+1, CurrentIdx+VBRSize, FOS); } while (GetVBRSize(ChildSize) != VBRSize); - + assert(ChildSize != 0 && "Should not have a zero-sized child!"); - + CurrentIdx += EmitVBRValue(ChildSize, OS); if (!OmitComments) { OS << "/*->" << CurrentIdx+ChildSize << "*/"; - + if (i == 0) OS.PadToColumn(CommentIndent) << "// " << SM->getNumChildren() << " children in Scope"; } - + OS << '\n' << TmpBuf.str(); CurrentIdx += ChildSize; } - + // Emit a zero as a sentinel indicating end of 'Scope'. if (!OmitComments) OS << "/*" << CurrentIdx << "*/"; @@ -196,7 +201,7 @@ EmitMatcher(const Matcher *N, unsigned Indent, unsigned CurrentIdx, OS << '\n'; return CurrentIdx - StartIdx + 1; } - + case Matcher::RecordNode: OS << "OPC_RecordNode,"; if (!OmitComments) @@ -215,30 +220,30 @@ EmitMatcher(const Matcher *N, unsigned Indent, unsigned CurrentIdx, << cast<RecordChildMatcher>(N)->getWhatFor(); OS << '\n'; return 1; - + case Matcher::RecordMemRef: OS << "OPC_RecordMemRef,\n"; return 1; - + case Matcher::CaptureGlueInput: OS << "OPC_CaptureGlueInput,\n"; return 1; - + case Matcher::MoveChild: OS << "OPC_MoveChild, " << cast<MoveChildMatcher>(N)->getChildNo() << ",\n"; return 2; - + case Matcher::MoveParent: OS << "OPC_MoveParent,\n"; return 1; - + case Matcher::CheckSame: OS << "OPC_CheckSame, " << cast<CheckSameMatcher>(N)->getMatchNumber() << ",\n"; return 2; case Matcher::CheckPatternPredicate: { - StringRef Pred = cast<CheckPatternPredicateMatcher>(N)->getPredicate(); + StringRef Pred =cast<CheckPatternPredicateMatcher>(N)->getPredicate(); OS << "OPC_CheckPatternPredicate, " << getPatternPredicate(Pred) << ','; if (!OmitComments) OS.PadToColumn(CommentIndent) << "// " << Pred; @@ -246,23 +251,23 @@ EmitMatcher(const Matcher *N, unsigned Indent, unsigned CurrentIdx, return 2; } case Matcher::CheckPredicate: { - StringRef Pred = cast<CheckPredicateMatcher>(N)->getPredicateName(); + TreePredicateFn Pred = cast<CheckPredicateMatcher>(N)->getPredicate(); OS << "OPC_CheckPredicate, " << getNodePredicate(Pred) << ','; if (!OmitComments) - OS.PadToColumn(CommentIndent) << "// " << Pred; + OS.PadToColumn(CommentIndent) << "// " << Pred.getFnName(); OS << '\n'; return 2; } case Matcher::CheckOpcode: - OS << "OPC_CheckOpcode, TARGET_OPCODE(" + OS << "OPC_CheckOpcode, TARGET_VAL(" << cast<CheckOpcodeMatcher>(N)->getOpcode().getEnumName() << "),\n"; return 3; - + case Matcher::SwitchOpcode: case Matcher::SwitchType: { unsigned StartIdx = CurrentIdx; - + unsigned NumCases; if (const SwitchOpcodeMatcher *SOM = dyn_cast<SwitchOpcodeMatcher>(N)) { OS << "OPC_SwitchOpcode "; @@ -276,7 +281,7 @@ EmitMatcher(const Matcher *N, unsigned Indent, unsigned CurrentIdx, OS << "/*" << NumCases << " cases */"; OS << ", "; ++CurrentIdx; - + // For each case we emit the size, then the opcode, then the matcher. for (unsigned i = 0, e = NumCases; i != e; ++i) { const Matcher *Child; @@ -288,7 +293,7 @@ EmitMatcher(const Matcher *N, unsigned Indent, unsigned CurrentIdx, Child = cast<SwitchTypeMatcher>(N)->getCaseMatcher(i); IdxSize = 1; // size of type in table is 1 byte. } - + // We need to encode the opcode and the offset of the case code before // emitting the case code. Handle this by buffering the output into a // string while we get the size. Unfortunately, the offset of the @@ -299,29 +304,29 @@ EmitMatcher(const Matcher *N, unsigned Indent, unsigned CurrentIdx, unsigned VBRSize = 0; do { VBRSize = GetVBRSize(ChildSize); - + TmpBuf.clear(); raw_svector_ostream OS(TmpBuf); formatted_raw_ostream FOS(OS); ChildSize = EmitMatcherList(Child, Indent+1, CurrentIdx+VBRSize+IdxSize, FOS); } while (GetVBRSize(ChildSize) != VBRSize); - + assert(ChildSize != 0 && "Should not have a zero-sized child!"); - + if (i != 0) { OS.PadToColumn(Indent*2); if (!OmitComments) OS << (isa<SwitchOpcodeMatcher>(N) ? "/*SwitchOpcode*/ " : "/*SwitchType*/ "); } - + // Emit the VBR. CurrentIdx += EmitVBRValue(ChildSize, OS); - + OS << ' '; if (const SwitchOpcodeMatcher *SOM = dyn_cast<SwitchOpcodeMatcher>(N)) - OS << "TARGET_OPCODE(" << SOM->getCaseOpcode(i).getEnumName() << "),"; + OS << "TARGET_VAL(" << SOM->getCaseOpcode(i).getEnumName() << "),"; else OS << getEnumName(cast<SwitchTypeMatcher>(N)->getCaseType(i)) << ','; @@ -351,13 +356,13 @@ EmitMatcher(const Matcher *N, unsigned Indent, unsigned CurrentIdx, OS << "OPC_CheckType, " << getEnumName(cast<CheckTypeMatcher>(N)->getType()) << ",\n"; return 2; - + case Matcher::CheckChildType: OS << "OPC_CheckChild" << cast<CheckChildTypeMatcher>(N)->getChildNo() << "Type, " << getEnumName(cast<CheckChildTypeMatcher>(N)->getType()) << ",\n"; return 2; - + case Matcher::CheckInteger: { OS << "OPC_CheckInteger, "; unsigned Bytes=1+EmitVBRValue(cast<CheckIntegerMatcher>(N)->getValue(), OS); @@ -368,7 +373,7 @@ EmitMatcher(const Matcher *N, unsigned Indent, unsigned CurrentIdx, OS << "OPC_CheckCondCode, ISD::" << cast<CheckCondCodeMatcher>(N)->getCondCodeName() << ",\n"; return 2; - + case Matcher::CheckValueType: OS << "OPC_CheckValueType, MVT::" << cast<CheckValueTypeMatcher>(N)->getTypeName() << ",\n"; @@ -379,20 +384,20 @@ EmitMatcher(const Matcher *N, unsigned Indent, unsigned CurrentIdx, const ComplexPattern &Pattern = CCPM->getPattern(); OS << "OPC_CheckComplexPat, /*CP*/" << getComplexPat(Pattern) << ", /*#*/" << CCPM->getMatchNumber() << ','; - + if (!OmitComments) { OS.PadToColumn(CommentIndent) << "// " << Pattern.getSelectFunc(); OS << ":$" << CCPM->getName(); for (unsigned i = 0, e = Pattern.getNumOperands(); i != e; ++i) OS << " #" << CCPM->getFirstResult()+i; - + if (Pattern.hasProperty(SDNPHasChain)) OS << " + chain result"; } OS << '\n'; return 3; } - + case Matcher::CheckAndImm: { OS << "OPC_CheckAndImm, "; unsigned Bytes=1+EmitVBRValue(cast<CheckAndImmMatcher>(N)->getValue(), OS); @@ -406,11 +411,11 @@ EmitMatcher(const Matcher *N, unsigned Indent, unsigned CurrentIdx, OS << '\n'; return Bytes; } - + case Matcher::CheckFoldableChainNode: OS << "OPC_CheckFoldableChainNode,\n"; return 1; - + case Matcher::EmitInteger: { int64_t Val = cast<EmitIntegerMatcher>(N)->getValue(); OS << "OPC_EmitInteger, " @@ -427,35 +432,45 @@ EmitMatcher(const Matcher *N, unsigned Indent, unsigned CurrentIdx, << Val << ",\n"; return 3; } - - case Matcher::EmitRegister: - OS << "OPC_EmitRegister, " - << getEnumName(cast<EmitRegisterMatcher>(N)->getVT()) << ", "; - if (Record *R = cast<EmitRegisterMatcher>(N)->getReg()) - OS << getQualifiedName(R) << ",\n"; - else { - OS << "0 "; - if (!OmitComments) - OS << "/*zero_reg*/"; - OS << ",\n"; + + case Matcher::EmitRegister: { + const EmitRegisterMatcher *Matcher = cast<EmitRegisterMatcher>(N); + const CodeGenRegister *Reg = Matcher->getReg(); + // If the enum value of the register is larger than one byte can handle, + // use EmitRegister2. + if (Reg && Reg->EnumValue > 255) { + OS << "OPC_EmitRegister2, " << getEnumName(Matcher->getVT()) << ", "; + OS << "TARGET_VAL(" << getQualifiedName(Reg->TheDef) << "),\n"; + return 4; + } else { + OS << "OPC_EmitRegister, " << getEnumName(Matcher->getVT()) << ", "; + if (Reg) { + OS << getQualifiedName(Reg->TheDef) << ",\n"; + } else { + OS << "0 "; + if (!OmitComments) + OS << "/*zero_reg*/"; + OS << ",\n"; + } + return 3; } - return 3; - + } + case Matcher::EmitConvertToTarget: OS << "OPC_EmitConvertToTarget, " << cast<EmitConvertToTargetMatcher>(N)->getSlot() << ",\n"; return 2; - + case Matcher::EmitMergeInputChains: { const EmitMergeInputChainsMatcher *MN = cast<EmitMergeInputChainsMatcher>(N); - + // Handle the specialized forms OPC_EmitMergeInputChains1_0 and 1_1. if (MN->getNumNodes() == 1 && MN->getNode(0) < 2) { OS << "OPC_EmitMergeInputChains1_" << MN->getNode(0) << ",\n"; return 1; } - + OS << "OPC_EmitMergeInputChains, " << MN->getNumNodes() << ", "; for (unsigned i = 0, e = MN->getNumNodes(); i != e; ++i) OS << MN->getNode(i) << ", "; @@ -477,13 +492,13 @@ EmitMatcher(const Matcher *N, unsigned Indent, unsigned CurrentIdx, OS <<'\n'; return 3; } - + case Matcher::EmitNode: case Matcher::MorphNodeTo: { const EmitNodeMatcherCommon *EN = cast<EmitNodeMatcherCommon>(N); OS << (isa<EmitNodeMatcher>(EN) ? "OPC_EmitNode" : "OPC_MorphNodeTo"); - OS << ", TARGET_OPCODE(" << EN->getOpcodeName() << "), 0"; - + OS << ", TARGET_VAL(" << EN->getOpcodeName() << "), 0"; + if (EN->hasChain()) OS << "|OPFL_Chain"; if (EN->hasInFlag()) OS << "|OPFL_GlueInput"; if (EN->hasOutFlag()) OS << "|OPFL_GlueOutput"; @@ -491,7 +506,7 @@ EmitMatcher(const Matcher *N, unsigned Indent, unsigned CurrentIdx, if (EN->getNumFixedArityOperands() != -1) OS << "|OPFL_Variadic" << EN->getNumFixedArityOperands(); OS << ",\n"; - + OS.PadToColumn(Indent*2+4) << EN->getNumVTs(); if (!OmitComments) OS << "/*#VTs*/"; @@ -506,7 +521,7 @@ EmitMatcher(const Matcher *N, unsigned Indent, unsigned CurrentIdx, unsigned NumOperandBytes = 0; for (unsigned i = 0, e = EN->getNumOperands(); i != e; ++i) NumOperandBytes += EmitVBRValue(EN->getOperand(i), OS); - + if (!OmitComments) { // Print the result #'s for EmitNode. if (const EmitNodeMatcher *E = dyn_cast<EmitNodeMatcher>(EN)) { @@ -521,14 +536,14 @@ EmitMatcher(const Matcher *N, unsigned Indent, unsigned CurrentIdx, if (const MorphNodeToMatcher *SNT = dyn_cast<MorphNodeToMatcher>(N)) { OS.PadToColumn(Indent*2) << "// Src: " - << *SNT->getPattern().getSrcPattern() << " - Complexity = " + << *SNT->getPattern().getSrcPattern() << " - Complexity = " << SNT->getPattern().getPatternComplexity(CGP) << '\n'; OS.PadToColumn(Indent*2) << "// Dst: " << *SNT->getPattern().getDstPattern() << '\n'; } } else OS << '\n'; - + return 6+EN->getNumVTs()+NumOperandBytes; } case Matcher::MarkGlueResults: { @@ -549,7 +564,7 @@ EmitMatcher(const Matcher *N, unsigned Indent, unsigned CurrentIdx, OS << '\n'; if (!OmitComments) { OS.PadToColumn(Indent*2) << "// Src: " - << *CM->getPattern().getSrcPattern() << " - Complexity = " + << *CM->getPattern().getSrcPattern() << " - Complexity = " << CM->getPattern().getPatternComplexity(CGP) << '\n'; OS.PadToColumn(Indent*2) << "// Dst: " << *CM->getPattern().getDstPattern(); @@ -573,7 +588,7 @@ EmitMatcherList(const Matcher *N, unsigned Indent, unsigned CurrentIdx, unsigned MatcherSize = EmitMatcher(N, Indent, CurrentIdx, OS); Size += MatcherSize; CurrentIdx += MatcherSize; - + // If there are other nodes in this list, iterate to them, otherwise we're // done. N = N->getNext(); @@ -592,44 +607,32 @@ void MatcherTableEmitter::EmitPredicateFunctions(formatted_raw_ostream &OS) { OS << " }\n"; OS << "}\n\n"; } - + // Emit Node predicates. // FIXME: Annoyingly, these are stored by name, which we never even emit. Yay? StringMap<TreePattern*> PFsByName; - + for (CodeGenDAGPatterns::pf_iterator I = CGP.pf_begin(), E = CGP.pf_end(); I != E; ++I) PFsByName[I->first->getName()] = I->second; - + if (!NodePredicates.empty()) { OS << "bool CheckNodePredicate(SDNode *Node, unsigned PredNo) const {\n"; OS << " switch (PredNo) {\n"; OS << " default: assert(0 && \"Invalid predicate in table?\");\n"; for (unsigned i = 0, e = NodePredicates.size(); i != e; ++i) { - // FIXME: Storing this by name is horrible. - TreePattern *P =PFsByName[NodePredicates[i].substr(strlen("Predicate_"))]; - assert(P && "Unknown name?"); - // Emit the predicate code corresponding to this pattern. - std::string Code = P->getRecord()->getValueAsCode("Predicate"); - assert(!Code.empty() && "No code in this predicate"); - OS << " case " << i << ": { // " << NodePredicates[i] << '\n'; - std::string ClassName; - if (P->getOnlyTree()->isLeaf()) - ClassName = "SDNode"; - else - ClassName = - CGP.getSDNodeInfo(P->getOnlyTree()->getOperator()).getSDClassName(); - if (ClassName == "SDNode") - OS << " SDNode *N = Node;\n"; - else - OS << " " << ClassName << "*N = cast<" << ClassName << ">(Node);\n"; - OS << Code << "\n }\n"; + TreePredicateFn PredFn = NodePredicates[i]; + + assert(!PredFn.isAlwaysTrue() && "No code in this predicate"); + OS << " case " << i << ": { // " << NodePredicates[i].getFnName() <<'\n'; + + OS << PredFn.getCodeToRunOnSDNode() << "\n }\n"; } OS << " }\n"; OS << "}\n\n"; } - + // Emit CompletePattern matchers. // FIXME: This should be const. if (!ComplexPatterns.empty()) { @@ -645,7 +648,7 @@ void MatcherTableEmitter::EmitPredicateFunctions(formatted_raw_ostream &OS) { if (P.hasProperty(SDNPHasChain)) ++NumOps; // Get the chained node too. - + OS << " case " << i << ":\n"; OS << " Result.resize(NextRes+" << NumOps << ");\n"; OS << " return " << P.getSelectFunc(); @@ -655,12 +658,12 @@ void MatcherTableEmitter::EmitPredicateFunctions(formatted_raw_ostream &OS) { // first argument. if (P.hasProperty(SDNPWantRoot)) OS << "Root, "; - + // If the complex pattern wants the parent of the operand being matched, // pass it in as the next argument. if (P.hasProperty(SDNPWantParent)) OS << "Parent, "; - + OS << "N"; for (unsigned i = 0; i != NumOps; ++i) OS << ", Result[NextRes+" << i << "].first"; @@ -669,28 +672,28 @@ void MatcherTableEmitter::EmitPredicateFunctions(formatted_raw_ostream &OS) { OS << " }\n"; OS << "}\n\n"; } - - + + // Emit SDNodeXForm handlers. // FIXME: This should be const. if (!NodeXForms.empty()) { OS << "SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) {\n"; OS << " switch (XFormNo) {\n"; OS << " default: assert(0 && \"Invalid xform # in table?\");\n"; - + // FIXME: The node xform could take SDValue's instead of SDNode*'s. for (unsigned i = 0, e = NodeXForms.size(); i != e; ++i) { const CodeGenDAGPatterns::NodeXForm &Entry = CGP.getSDNodeTransform(NodeXForms[i]); - + Record *SDNode = Entry.first; const std::string &Code = Entry.second; - + OS << " case " << i << ": { "; if (!OmitComments) OS << "// " << NodeXForms[i]->getName(); OS << '\n'; - + std::string ClassName = CGP.getSDNodeInfo(SDNode).getSDClassName(); if (ClassName == "SDNode") OS << " SDNode *N = V.getNode();\n"; @@ -710,12 +713,12 @@ static void BuildHistogram(const Matcher *M, std::vector<unsigned> &OpcodeFreq){ if (unsigned(M->getKind()) >= OpcodeFreq.size()) OpcodeFreq.resize(M->getKind()+1); OpcodeFreq[M->getKind()]++; - + // Handle recursive nodes. if (const ScopeMatcher *SM = dyn_cast<ScopeMatcher>(M)) { for (unsigned i = 0, e = SM->getNumChildren(); i != e; ++i) BuildHistogram(SM->getChild(i), OpcodeFreq); - } else if (const SwitchOpcodeMatcher *SOM = + } else if (const SwitchOpcodeMatcher *SOM = dyn_cast<SwitchOpcodeMatcher>(M)) { for (unsigned i = 0, e = SOM->getNumCases(); i != e; ++i) BuildHistogram(SOM->getCaseMatcher(i), OpcodeFreq); @@ -730,16 +733,16 @@ void MatcherTableEmitter::EmitHistogram(const Matcher *M, formatted_raw_ostream &OS) { if (OmitComments) return; - + std::vector<unsigned> OpcodeFreq; BuildHistogram(M, OpcodeFreq); - + OS << " // Opcode Histogram:\n"; for (unsigned i = 0, e = OpcodeFreq.size(); i != e; ++i) { OS << " // #"; switch ((Matcher::KindTy)i) { - case Matcher::Scope: OS << "OPC_Scope"; break; - case Matcher::RecordNode: OS << "OPC_RecordNode"; break; + case Matcher::Scope: OS << "OPC_Scope"; break; + case Matcher::RecordNode: OS << "OPC_RecordNode"; break; case Matcher::RecordChild: OS << "OPC_RecordChild"; break; case Matcher::RecordMemRef: OS << "OPC_RecordMemRef"; break; case Matcher::CaptureGlueInput: OS << "OPC_CaptureGlueInput"; break; @@ -772,9 +775,9 @@ void MatcherTableEmitter::EmitHistogram(const Matcher *M, case Matcher::MorphNodeTo: OS << "OPC_MorphNodeTo"; break; case Matcher::EmitNodeXForm: OS << "OPC_EmitNodeXForm"; break; case Matcher::MarkGlueResults: OS << "OPC_MarkGlueResults"; break; - case Matcher::CompleteMatch: OS << "OPC_CompleteMatch"; break; + case Matcher::CompleteMatch: OS << "OPC_CompleteMatch"; break; } - + OS.PadToColumn(40) << " = " << OpcodeFreq[i] << '\n'; } OS << '\n'; @@ -782,26 +785,28 @@ void MatcherTableEmitter::EmitHistogram(const Matcher *M, void llvm::EmitMatcherTable(const Matcher *TheMatcher, - const CodeGenDAGPatterns &CGP, raw_ostream &O) { + const CodeGenDAGPatterns &CGP, + raw_ostream &O) { formatted_raw_ostream OS(O); - + OS << "// The main instruction selector code.\n"; OS << "SDNode *SelectCode(SDNode *N) {\n"; MatcherTableEmitter MatcherEmitter(CGP); - OS << " // Opcodes are emitted as 2 bytes, TARGET_OPCODE handles this.\n"; - OS << " #define TARGET_OPCODE(X) X & 255, unsigned(X) >> 8\n"; + OS << " // Some target values are emitted as 2 bytes, TARGET_VAL handles\n"; + OS << " // this.\n"; + OS << " #define TARGET_VAL(X) X & 255, unsigned(X) >> 8\n"; OS << " static const unsigned char MatcherTable[] = {\n"; unsigned TotalSize = MatcherEmitter.EmitMatcherList(TheMatcher, 5, 0, OS); OS << " 0\n }; // Total Array size is " << (TotalSize+1) << " bytes\n\n"; - + MatcherEmitter.EmitHistogram(TheMatcher, OS); - - OS << " #undef TARGET_OPCODE\n"; + + OS << " #undef TARGET_VAL\n"; OS << " return SelectCodeCommon(N, MatcherTable,sizeof(MatcherTable));\n}\n"; OS << '\n'; - + // Next up, emit the function for node and pattern predicates: MatcherEmitter.EmitPredicateFunctions(OS); } diff --git a/utils/TableGen/DAGISelMatcherGen.cpp b/utils/TableGen/DAGISelMatcherGen.cpp index 7c0bade..393ac69 100644 --- a/utils/TableGen/DAGISelMatcherGen.cpp +++ b/utils/TableGen/DAGISelMatcherGen.cpp @@ -9,7 +9,9 @@ #include "DAGISelMatcher.h" #include "CodeGenDAGPatterns.h" +#include "CodeGenRegisters.h" #include "Record.h" +#include "llvm/ADT/DenseMap.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringMap.h" #include <utility> @@ -91,6 +93,10 @@ namespace { /// CurPredicate - As we emit matcher nodes, this points to the latest check /// which should have future checks stuck into its Next position. Matcher *CurPredicate; + + /// RegisterDefMap - A map of register record definitions to the + /// corresponding target CodeGenRegister entry. + DenseMap<const Record *, const CodeGenRegister *> RegisterDefMap; public: MatcherGen(const PatternToMatch &pattern, const CodeGenDAGPatterns &cgp); @@ -159,6 +165,12 @@ MatcherGen::MatcherGen(const PatternToMatch &pattern, // If there are types that are manifestly known, infer them. InferPossibleTypes(); + + // Populate the map from records to CodeGenRegister entries. + const CodeGenTarget &CGT = CGP.getTargetInfo(); + const std::vector<CodeGenRegister> &Registers = CGT.getRegisters(); + for (unsigned i = 0, e = Registers.size(); i != e; ++i) + RegisterDefMap[Registers[i].TheDef] = &Registers[i]; } /// InferPossibleTypes - As we emit the pattern, we end up generating type @@ -578,7 +590,8 @@ void MatcherGen::EmitResultLeafAsOperand(const TreePatternNode *N, // If this is an explicit register reference, handle it. if (DefInit *DI = dynamic_cast<DefInit*>(N->getLeafValue())) { if (DI->getDef()->isSubClassOf("Register")) { - AddMatcher(new EmitRegisterMatcher(DI->getDef(), N->getType(0))); + AddMatcher(new EmitRegisterMatcher(RegisterDefMap[DI->getDef()], + N->getType(0))); ResultOps.push_back(NextRecordedOperandNo++); return; } diff --git a/utils/TableGen/DAGISelMatcherOpt.cpp b/utils/TableGen/DAGISelMatcherOpt.cpp index 3169ea1..f996422 100644 --- a/utils/TableGen/DAGISelMatcherOpt.cpp +++ b/utils/TableGen/DAGISelMatcherOpt.cpp @@ -18,7 +18,6 @@ #include "llvm/ADT/StringSet.h" #include "llvm/Support/Debug.h" #include "llvm/Support/raw_ostream.h" -#include <vector> using namespace llvm; /// ContractNodes - Turn multiple matcher node patterns like 'MoveChild+Record' diff --git a/utils/TableGen/DisassemblerEmitter.cpp b/utils/TableGen/DisassemblerEmitter.cpp index 90a2af2..d68d3b0 100644 --- a/utils/TableGen/DisassemblerEmitter.cpp +++ b/utils/TableGen/DisassemblerEmitter.cpp @@ -40,12 +40,12 @@ using namespace llvm::X86Disassembler; /// all cases as a 64-bit instruction with only OPSIZE set. (The XS prefix /// may have effects on its execution, but does not change the instruction /// returned.) This allows considerable space savings in other tables. -/// - Four tables (ONEBYTE_SYM, TWOBYTE_SYM, THREEBYTE38_SYM, and -/// THREEBYTE3A_SYM) contain the hierarchy that the decoder traverses while -/// decoding an instruction. At the lowest level of this hierarchy are -/// instruction UIDs, 16-bit integers that can be used to uniquely identify -/// the instruction and correspond exactly to its position in the list of -/// CodeGenInstructions for the target. +/// - Six tables (ONEBYTE_SYM, TWOBYTE_SYM, THREEBYTE38_SYM, THREEBYTE3A_SYM, +/// THREEBYTEA6_SYM, and THREEBYTEA7_SYM contain the hierarchy that the +/// decoder traverses while decoding an instruction. At the lowest level of +/// this hierarchy are instruction UIDs, 16-bit integers that can be used to +/// uniquely identify the instruction and correspond exactly to its position +/// in the list of CodeGenInstructions for the target. /// - One table (INSTRUCTIONS_SYM) contains information about the operands of /// each instruction and how to decode them. /// diff --git a/utils/TableGen/EDEmitter.cpp b/utils/TableGen/EDEmitter.cpp index 020a4a3..5358c0c 100644 --- a/utils/TableGen/EDEmitter.cpp +++ b/utils/TableGen/EDEmitter.cpp @@ -24,7 +24,6 @@ #include "llvm/Support/Format.h" #include "llvm/Support/raw_ostream.h" -#include <map> #include <string> #include <vector> @@ -598,6 +597,11 @@ static int ARMFlagFromOpName(LiteralConstantEmitter *type, IMM("t2adrlabel"); IMM("shift_imm"); IMM("neon_vcvt_imm32"); + IMM("shr_imm8"); + IMM("shr_imm16"); + IMM("shr_imm32"); + IMM("shr_imm64"); + IMM("t2ldrlabel"); MISC("brtarget", "kOperandTypeARMBranchTarget"); // ? MISC("uncondbrtarget", "kOperandTypeARMBranchTarget"); // ? @@ -632,10 +636,12 @@ static int ARMFlagFromOpName(LiteralConstantEmitter *type, MISC("am6offset", "kOperandTypeARMAddrMode6Offset"); // R, I, I MISC("addrmode6dup", "kOperandTypeARMAddrMode6"); // R, R, I, I MISC("addrmodepc", "kOperandTypeARMAddrModePC"); // R, I + MISC("addrmode7", "kOperandTypeARMAddrMode7"); // R MISC("reglist", "kOperandTypeARMRegisterList"); // I, R, ... MISC("dpr_reglist", "kOperandTypeARMDPRRegisterList"); // I, R, ... MISC("spr_reglist", "kOperandTypeARMSPRRegisterList"); // I, R, ... MISC("it_mask", "kOperandTypeThumbITMask"); // I + MISC("t2addrmode_reg", "kOperandTypeThumb2AddrModeReg"); // R MISC("t2addrmode_imm8", "kOperandTypeThumb2AddrModeImm8"); // R, I MISC("t2am_imm8_offset", "kOperandTypeThumb2AddrModeImm8Offset");//I MISC("t2addrmode_imm12", "kOperandTypeThumb2AddrModeImm12"); // R, I @@ -853,6 +859,7 @@ static void emitCommonEnums(raw_ostream &o, unsigned int &i) { operandTypes.addEntry("kOperandTypeARMAddrMode5"); operandTypes.addEntry("kOperandTypeARMAddrMode6"); operandTypes.addEntry("kOperandTypeARMAddrMode6Offset"); + operandTypes.addEntry("kOperandTypeARMAddrMode7"); operandTypes.addEntry("kOperandTypeARMAddrModePC"); operandTypes.addEntry("kOperandTypeARMRegisterList"); operandTypes.addEntry("kOperandTypeARMDPRRegisterList"); @@ -864,6 +871,7 @@ static void emitCommonEnums(raw_ostream &o, unsigned int &i) { operandTypes.addEntry("kOperandTypeThumbAddrModeRR"); operandTypes.addEntry("kOperandTypeThumbAddrModeSP"); operandTypes.addEntry("kOperandTypeThumbAddrModePC"); + operandTypes.addEntry("kOperandTypeThumb2AddrModeReg"); operandTypes.addEntry("kOperandTypeThumb2SoReg"); operandTypes.addEntry("kOperandTypeThumb2SoImm"); operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8"); diff --git a/utils/TableGen/FastISelEmitter.cpp b/utils/TableGen/FastISelEmitter.cpp index f01de1d..9c11bf6 100644 --- a/utils/TableGen/FastISelEmitter.cpp +++ b/utils/TableGen/FastISelEmitter.cpp @@ -35,36 +35,150 @@ struct InstructionMemo { std::string SubRegNo; std::vector<std::string>* PhysRegs; }; + +/// ImmPredicateSet - This uniques predicates (represented as a string) and +/// gives them unique (small) integer ID's that start at 0. +class ImmPredicateSet { + DenseMap<TreePattern *, unsigned> ImmIDs; + std::vector<TreePredicateFn> PredsByName; +public: + + unsigned getIDFor(TreePredicateFn Pred) { + unsigned &Entry = ImmIDs[Pred.getOrigPatFragRecord()]; + if (Entry == 0) { + PredsByName.push_back(Pred); + Entry = PredsByName.size(); + } + return Entry-1; + } + + const TreePredicateFn &getPredicate(unsigned i) { + assert(i < PredsByName.size()); + return PredsByName[i]; + } + + typedef std::vector<TreePredicateFn>::const_iterator iterator; + iterator begin() const { return PredsByName.begin(); } + iterator end() const { return PredsByName.end(); } + +}; /// OperandsSignature - This class holds a description of a list of operand /// types. It has utility methods for emitting text based on the operands. /// struct OperandsSignature { - std::vector<std::string> Operands; + class OpKind { + enum { OK_Reg, OK_FP, OK_Imm, OK_Invalid = -1 }; + char Repr; + public: + + OpKind() : Repr(OK_Invalid) {} + + bool operator<(OpKind RHS) const { return Repr < RHS.Repr; } + bool operator==(OpKind RHS) const { return Repr == RHS.Repr; } + + static OpKind getReg() { OpKind K; K.Repr = OK_Reg; return K; } + static OpKind getFP() { OpKind K; K.Repr = OK_FP; return K; } + static OpKind getImm(unsigned V) { + assert((unsigned)OK_Imm+V < 128 && + "Too many integer predicates for the 'Repr' char"); + OpKind K; K.Repr = OK_Imm+V; return K; + } + + bool isReg() const { return Repr == OK_Reg; } + bool isFP() const { return Repr == OK_FP; } + bool isImm() const { return Repr >= OK_Imm; } + + unsigned getImmCode() const { assert(isImm()); return Repr-OK_Imm; } + + void printManglingSuffix(raw_ostream &OS, ImmPredicateSet &ImmPredicates, + bool StripImmCodes) const { + if (isReg()) + OS << 'r'; + else if (isFP()) + OS << 'f'; + else { + OS << 'i'; + if (!StripImmCodes) + if (unsigned Code = getImmCode()) + OS << "_" << ImmPredicates.getPredicate(Code-1).getFnName(); + } + } + }; + + + SmallVector<OpKind, 3> Operands; bool operator<(const OperandsSignature &O) const { return Operands < O.Operands; } + bool operator==(const OperandsSignature &O) const { + return Operands == O.Operands; + } bool empty() const { return Operands.empty(); } + bool hasAnyImmediateCodes() const { + for (unsigned i = 0, e = Operands.size(); i != e; ++i) + if (Operands[i].isImm() && Operands[i].getImmCode() != 0) + return true; + return false; + } + + /// getWithoutImmCodes - Return a copy of this with any immediate codes forced + /// to zero. + OperandsSignature getWithoutImmCodes() const { + OperandsSignature Result; + for (unsigned i = 0, e = Operands.size(); i != e; ++i) + if (!Operands[i].isImm()) + Result.Operands.push_back(Operands[i]); + else + Result.Operands.push_back(OpKind::getImm(0)); + return Result; + } + + void emitImmediatePredicate(raw_ostream &OS, ImmPredicateSet &ImmPredicates) { + bool EmittedAnything = false; + for (unsigned i = 0, e = Operands.size(); i != e; ++i) { + if (!Operands[i].isImm()) continue; + + unsigned Code = Operands[i].getImmCode(); + if (Code == 0) continue; + + if (EmittedAnything) + OS << " &&\n "; + + TreePredicateFn PredFn = ImmPredicates.getPredicate(Code-1); + + // Emit the type check. + OS << "VT == " + << getEnumName(PredFn.getOrigPatFragRecord()->getTree(0)->getType(0)) + << " && "; + + + OS << PredFn.getFnName() << "(imm" << i <<')'; + EmittedAnything = true; + } + } + /// initialize - Examine the given pattern and initialize the contents /// of the Operands array accordingly. Return true if all the operands /// are supported, false otherwise. /// - bool initialize(TreePatternNode *InstPatNode, - const CodeGenTarget &Target, - MVT::SimpleValueType VT) { - - if (!InstPatNode->isLeaf()) { - if (InstPatNode->getOperator()->getName() == "imm") { - Operands.push_back("i"); - return true; - } - if (InstPatNode->getOperator()->getName() == "fpimm") { - Operands.push_back("f"); - return true; - } + bool initialize(TreePatternNode *InstPatNode, const CodeGenTarget &Target, + MVT::SimpleValueType VT, + ImmPredicateSet &ImmediatePredicates) { + if (InstPatNode->isLeaf()) + return false; + + if (InstPatNode->getOperator()->getName() == "imm") { + Operands.push_back(OpKind::getImm(0)); + return true; + } + + if (InstPatNode->getOperator()->getName() == "fpimm") { + Operands.push_back(OpKind::getFP()); + return true; } const CodeGenRegisterClass *DstRC = 0; @@ -72,35 +186,65 @@ struct OperandsSignature { for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) { TreePatternNode *Op = InstPatNode->getChild(i); + // Handle imm operands specially. + if (!Op->isLeaf() && Op->getOperator()->getName() == "imm") { + unsigned PredNo = 0; + if (!Op->getPredicateFns().empty()) { + TreePredicateFn PredFn = Op->getPredicateFns()[0]; + // If there is more than one predicate weighing in on this operand + // then we don't handle it. This doesn't typically happen for + // immediates anyway. + if (Op->getPredicateFns().size() > 1 || + !PredFn.isImmediatePattern()) + return false; + // Ignore any instruction with 'FastIselShouldIgnore', these are + // not needed and just bloat the fast instruction selector. For + // example, X86 doesn't need to generate code to match ADD16ri8 since + // ADD16ri will do just fine. + Record *Rec = PredFn.getOrigPatFragRecord()->getRecord(); + if (Rec->getValueAsBit("FastIselShouldIgnore")) + return false; + + PredNo = ImmediatePredicates.getIDFor(PredFn)+1; + } + + // Handle unmatched immediate sizes here. + //if (Op->getType(0) != VT) + // return false; + + Operands.push_back(OpKind::getImm(PredNo)); + continue; + } + + // For now, filter out any operand with a predicate. // For now, filter out any operand with multiple values. - if (!Op->getPredicateFns().empty() || - Op->getNumTypes() != 1) - return false; - - assert(Op->hasTypeSet(0) && "Type infererence not done?"); - // For now, all the operands must have the same type. - if (Op->getType(0) != VT) + if (!Op->getPredicateFns().empty() || Op->getNumTypes() != 1) return false; if (!Op->isLeaf()) { - if (Op->getOperator()->getName() == "imm") { - Operands.push_back("i"); - continue; - } - if (Op->getOperator()->getName() == "fpimm") { - Operands.push_back("f"); + if (Op->getOperator()->getName() == "fpimm") { + Operands.push_back(OpKind::getFP()); continue; } // For now, ignore other non-leaf nodes. return false; } + + assert(Op->hasTypeSet(0) && "Type infererence not done?"); + + // For now, all the operands must have the same type (if they aren't + // immediates). Note that this causes us to reject variable sized shifts + // on X86. + if (Op->getType(0) != VT) + return false; + DefInit *OpDI = dynamic_cast<DefInit*>(Op->getLeafValue()); if (!OpDI) return false; Record *OpLeafRec = OpDI->getDef(); + // For now, the only other thing we accept is register operands. - const CodeGenRegisterClass *RC = 0; if (OpLeafRec->isSubClassOf("RegisterClass")) RC = &Target.getRegisterClass(OpLeafRec); @@ -120,18 +264,18 @@ struct OperandsSignature { return false; } else DstRC = RC; - Operands.push_back("r"); + Operands.push_back(OpKind::getReg()); } return true; } void PrintParameters(raw_ostream &OS) const { for (unsigned i = 0, e = Operands.size(); i != e; ++i) { - if (Operands[i] == "r") { + if (Operands[i].isReg()) { OS << "unsigned Op" << i << ", bool Op" << i << "IsKill"; - } else if (Operands[i] == "i") { + } else if (Operands[i].isImm()) { OS << "uint64_t imm" << i; - } else if (Operands[i] == "f") { + } else if (Operands[i].isFP()) { OS << "ConstantFP *f" << i; } else { assert("Unknown operand kind!"); @@ -143,7 +287,7 @@ struct OperandsSignature { } void PrintArguments(raw_ostream &OS, - const std::vector<std::string>& PR) const { + const std::vector<std::string> &PR) const { assert(PR.size() == Operands.size()); bool PrintedArg = false; for (unsigned i = 0, e = Operands.size(); i != e; ++i) { @@ -153,13 +297,13 @@ struct OperandsSignature { if (PrintedArg) OS << ", "; - if (Operands[i] == "r") { + if (Operands[i].isReg()) { OS << "Op" << i << ", Op" << i << "IsKill"; PrintedArg = true; - } else if (Operands[i] == "i") { + } else if (Operands[i].isImm()) { OS << "imm" << i; PrintedArg = true; - } else if (Operands[i] == "f") { + } else if (Operands[i].isFP()) { OS << "f" << i; PrintedArg = true; } else { @@ -171,11 +315,11 @@ struct OperandsSignature { void PrintArguments(raw_ostream &OS) const { for (unsigned i = 0, e = Operands.size(); i != e; ++i) { - if (Operands[i] == "r") { + if (Operands[i].isReg()) { OS << "Op" << i << ", Op" << i << "IsKill"; - } else if (Operands[i] == "i") { + } else if (Operands[i].isImm()) { OS << "imm" << i; - } else if (Operands[i] == "f") { + } else if (Operands[i].isFP()) { OS << "f" << i; } else { assert("Unknown operand kind!"); @@ -187,8 +331,9 @@ struct OperandsSignature { } - void PrintManglingSuffix(raw_ostream &OS, - const std::vector<std::string>& PR) const { + void PrintManglingSuffix(raw_ostream &OS, const std::vector<std::string> &PR, + ImmPredicateSet &ImmPredicates, + bool StripImmCodes = false) const { for (unsigned i = 0, e = Operands.size(); i != e; ++i) { if (PR[i] != "") // Implicit physical register operand. e.g. Instruction::Mul expect to @@ -197,14 +342,14 @@ struct OperandsSignature { // like a binary instruction except for the very inner FastEmitInst_* // call. continue; - OS << Operands[i]; + Operands[i].printManglingSuffix(OS, ImmPredicates, StripImmCodes); } } - void PrintManglingSuffix(raw_ostream &OS) const { - for (unsigned i = 0, e = Operands.size(); i != e; ++i) { - OS << Operands[i]; - } + void PrintManglingSuffix(raw_ostream &OS, ImmPredicateSet &ImmPredicates, + bool StripImmCodes = false) const { + for (unsigned i = 0, e = Operands.size(); i != e; ++i) + Operands[i].printManglingSuffix(OS, ImmPredicates, StripImmCodes); } }; @@ -218,13 +363,17 @@ class FastISelMap { OperandsOpcodeTypeRetPredMap SimplePatterns; + std::map<OperandsSignature, std::vector<OperandsSignature> > + SignaturesWithConstantForms; + std::string InstNS; - + ImmPredicateSet ImmediatePredicates; public: explicit FastISelMap(std::string InstNS); - void CollectPatterns(CodeGenDAGPatterns &CGP); - void PrintFunctionDefinitions(raw_ostream &OS); + void collectPatterns(CodeGenDAGPatterns &CGP); + void printImmediatePredicates(raw_ostream &OS); + void printFunctionDefinitions(raw_ostream &OS); }; } @@ -244,7 +393,34 @@ FastISelMap::FastISelMap(std::string instns) : InstNS(instns) { } -void FastISelMap::CollectPatterns(CodeGenDAGPatterns &CGP) { +static std::string PhyRegForNode(TreePatternNode *Op, + const CodeGenTarget &Target) { + std::string PhysReg; + + if (!Op->isLeaf()) + return PhysReg; + + DefInit *OpDI = dynamic_cast<DefInit*>(Op->getLeafValue()); + Record *OpLeafRec = OpDI->getDef(); + if (!OpLeafRec->isSubClassOf("Register")) + return PhysReg; + + PhysReg += static_cast<StringInit*>(OpLeafRec->getValue( \ + "Namespace")->getValue())->getValue(); + PhysReg += "::"; + + std::vector<CodeGenRegister> Regs = Target.getRegisters(); + for (unsigned i = 0; i < Regs.size(); ++i) { + if (Regs[i].TheDef == OpLeafRec) { + PhysReg += Regs[i].getName(); + break; + } + } + + return PhysReg; +} + +void FastISelMap::collectPatterns(CodeGenDAGPatterns &CGP) { const CodeGenTarget &Target = CGP.getTargetInfo(); // Determine the target's namespace name. @@ -264,7 +440,7 @@ void FastISelMap::CollectPatterns(CodeGenDAGPatterns &CGP) { if (!Op->isSubClassOf("Instruction")) continue; CodeGenInstruction &II = CGP.getTargetInfo().getInstruction(Op); - if (II.Operands.size() == 0) + if (II.Operands.empty()) continue; // For now, ignore multi-instruction patterns. @@ -322,54 +498,45 @@ void FastISelMap::CollectPatterns(CodeGenDAGPatterns &CGP) { VT = InstPatNode->getChild(0)->getType(0); } - // For now, filter out instructions which just set a register to - // an Operand or an immediate, like MOV32ri. - if (InstPatOp->isSubClassOf("Operand")) - continue; - // For now, filter out any instructions with predicates. if (!InstPatNode->getPredicateFns().empty()) continue; // Check all the operands. OperandsSignature Operands; - if (!Operands.initialize(InstPatNode, Target, VT)) + if (!Operands.initialize(InstPatNode, Target, VT, ImmediatePredicates)) continue; std::vector<std::string>* PhysRegInputs = new std::vector<std::string>(); - if (!InstPatNode->isLeaf() && - (InstPatNode->getOperator()->getName() == "imm" || - InstPatNode->getOperator()->getName() == "fpimmm")) + if (InstPatNode->getOperator()->getName() == "imm" || + InstPatNode->getOperator()->getName() == "fpimmm") PhysRegInputs->push_back(""); - else if (!InstPatNode->isLeaf()) { + else { + // Compute the PhysRegs used by the given pattern, and check that + // the mapping from the src to dst patterns is simple. + bool FoundNonSimplePattern = false; + unsigned DstIndex = 0; for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) { - TreePatternNode *Op = InstPatNode->getChild(i); - if (!Op->isLeaf()) { - PhysRegInputs->push_back(""); - continue; - } - - DefInit *OpDI = dynamic_cast<DefInit*>(Op->getLeafValue()); - Record *OpLeafRec = OpDI->getDef(); - std::string PhysReg; - if (OpLeafRec->isSubClassOf("Register")) { - PhysReg += static_cast<StringInit*>(OpLeafRec->getValue( \ - "Namespace")->getValue())->getValue(); - PhysReg += "::"; - - std::vector<CodeGenRegister> Regs = Target.getRegisters(); - for (unsigned i = 0; i < Regs.size(); ++i) { - if (Regs[i].TheDef == OpLeafRec) { - PhysReg += Regs[i].getName(); - break; - } + std::string PhysReg = PhyRegForNode(InstPatNode->getChild(i), Target); + if (PhysReg.empty()) { + if (DstIndex >= Dst->getNumChildren() || + Dst->getChild(DstIndex)->getName() != + InstPatNode->getChild(i)->getName()) { + FoundNonSimplePattern = true; + break; } + ++DstIndex; } PhysRegInputs->push_back(PhysReg); } - } else - PhysRegInputs->push_back(""); + + if (Op->getName() != "EXTRACT_SUBREG" && DstIndex < Dst->getNumChildren()) + FoundNonSimplePattern = true; + + if (FoundNonSimplePattern) + continue; + } // Get the predicate that guards this pattern. std::string PredicateCheck = Pattern.getPredicateCheck(); @@ -381,15 +548,39 @@ void FastISelMap::CollectPatterns(CodeGenDAGPatterns &CGP) { SubRegNo, PhysRegInputs }; - if (SimplePatterns[Operands][OpcodeName][VT][RetVT] - .count(PredicateCheck)) - throw TGError(Pattern.getSrcRecord()->getLoc(), "Duplicate record!"); + + if (SimplePatterns[Operands][OpcodeName][VT][RetVT].count(PredicateCheck)) + throw TGError(Pattern.getSrcRecord()->getLoc(), + "Duplicate record in FastISel table!"); SimplePatterns[Operands][OpcodeName][VT][RetVT][PredicateCheck] = Memo; + + // If any of the operands were immediates with predicates on them, strip + // them down to a signature that doesn't have predicates so that we can + // associate them with the stripped predicate version. + if (Operands.hasAnyImmediateCodes()) { + SignaturesWithConstantForms[Operands.getWithoutImmCodes()] + .push_back(Operands); + } } } -void FastISelMap::PrintFunctionDefinitions(raw_ostream &OS) { +void FastISelMap::printImmediatePredicates(raw_ostream &OS) { + if (ImmediatePredicates.begin() == ImmediatePredicates.end()) + return; + + OS << "\n// FastEmit Immediate Predicate functions.\n"; + for (ImmPredicateSet::iterator I = ImmediatePredicates.begin(), + E = ImmediatePredicates.end(); I != E; ++I) { + OS << "static bool " << I->getFnName() << "(int64_t Imm) {\n"; + OS << I->getImmediatePredicateCode() << "\n}\n"; + } + + OS << "\n\n"; +} + + +void FastISelMap::printFunctionDefinitions(raw_ostream &OS) { // Now emit code for all the patterns that we collected. for (OperandsOpcodeTypeRetPredMap::const_iterator OI = SimplePatterns.begin(), OE = SimplePatterns.end(); OI != OE; ++OI) { @@ -420,7 +611,7 @@ void FastISelMap::PrintFunctionDefinitions(raw_ostream &OS) { << getLegalCName(Opcode) << "_" << getLegalCName(getName(VT)) << "_" << getLegalCName(getName(RetVT)) << "_"; - Operands.PrintManglingSuffix(OS); + Operands.PrintManglingSuffix(OS, ImmediatePredicates); OS << "("; Operands.PrintParameters(OS); OS << ") {\n"; @@ -451,7 +642,8 @@ void FastISelMap::PrintFunctionDefinitions(raw_ostream &OS) { OS << " return FastEmitInst_"; if (Memo.SubRegNo.empty()) { - Operands.PrintManglingSuffix(OS, *Memo.PhysRegs); + Operands.PrintManglingSuffix(OS, *Memo.PhysRegs, + ImmediatePredicates, true); OS << "(" << InstNS << Memo.Name << ", "; OS << InstNS << Memo.RC->getName() << "RegisterClass"; if (!Operands.empty()) @@ -460,9 +652,7 @@ void FastISelMap::PrintFunctionDefinitions(raw_ostream &OS) { OS << ");\n"; } else { OS << "extractsubreg(" << getName(RetVT); - OS << ", Op0, Op0IsKill, "; - OS << Memo.SubRegNo; - OS << ");\n"; + OS << ", Op0, Op0IsKill, " << Memo.SubRegNo << ");\n"; } if (HasPred) @@ -480,7 +670,7 @@ void FastISelMap::PrintFunctionDefinitions(raw_ostream &OS) { OS << "unsigned FastEmit_" << getLegalCName(Opcode) << "_" << getLegalCName(getName(VT)) << "_"; - Operands.PrintManglingSuffix(OS); + Operands.PrintManglingSuffix(OS, ImmediatePredicates); OS << "(MVT RetVT"; if (!Operands.empty()) OS << ", "; @@ -492,7 +682,7 @@ void FastISelMap::PrintFunctionDefinitions(raw_ostream &OS) { OS << " case " << getName(RetVT) << ": return FastEmit_" << getLegalCName(Opcode) << "_" << getLegalCName(getName(VT)) << "_" << getLegalCName(getName(RetVT)) << "_"; - Operands.PrintManglingSuffix(OS); + Operands.PrintManglingSuffix(OS, ImmediatePredicates); OS << "("; Operands.PrintArguments(OS); OS << ");\n"; @@ -504,7 +694,7 @@ void FastISelMap::PrintFunctionDefinitions(raw_ostream &OS) { OS << "unsigned FastEmit_" << getLegalCName(Opcode) << "_" << getLegalCName(getName(VT)) << "_"; - Operands.PrintManglingSuffix(OS); + Operands.PrintManglingSuffix(OS, ImmediatePredicates); OS << "(MVT RetVT"; if (!Operands.empty()) OS << ", "; @@ -544,7 +734,8 @@ void FastISelMap::PrintFunctionDefinitions(raw_ostream &OS) { OS << " return FastEmitInst_"; if (Memo.SubRegNo.empty()) { - Operands.PrintManglingSuffix(OS, *Memo.PhysRegs); + Operands.PrintManglingSuffix(OS, *Memo.PhysRegs, + ImmediatePredicates, true); OS << "(" << InstNS << Memo.Name << ", "; OS << InstNS << Memo.RC->getName() << "RegisterClass"; if (!Operands.empty()) @@ -572,7 +763,7 @@ void FastISelMap::PrintFunctionDefinitions(raw_ostream &OS) { // Emit one function for the opcode that demultiplexes based on the type. OS << "unsigned FastEmit_" << getLegalCName(Opcode) << "_"; - Operands.PrintManglingSuffix(OS); + Operands.PrintManglingSuffix(OS, ImmediatePredicates); OS << "(MVT VT, MVT RetVT"; if (!Operands.empty()) OS << ", "; @@ -585,7 +776,7 @@ void FastISelMap::PrintFunctionDefinitions(raw_ostream &OS) { std::string TypeName = getName(VT); OS << " case " << TypeName << ": return FastEmit_" << getLegalCName(Opcode) << "_" << getLegalCName(TypeName) << "_"; - Operands.PrintManglingSuffix(OS); + Operands.PrintManglingSuffix(OS, ImmediatePredicates); OS << "(RetVT"; if (!Operands.empty()) OS << ", "; @@ -604,12 +795,44 @@ void FastISelMap::PrintFunctionDefinitions(raw_ostream &OS) { // Emit one function for the operand signature that demultiplexes based // on opcode and type. OS << "unsigned FastEmit_"; - Operands.PrintManglingSuffix(OS); + Operands.PrintManglingSuffix(OS, ImmediatePredicates); OS << "(MVT VT, MVT RetVT, unsigned Opcode"; if (!Operands.empty()) OS << ", "; Operands.PrintParameters(OS); OS << ") {\n"; + + // If there are any forms of this signature available that operand on + // constrained forms of the immediate (e.g. 32-bit sext immediate in a + // 64-bit operand), check them first. + + std::map<OperandsSignature, std::vector<OperandsSignature> >::iterator MI + = SignaturesWithConstantForms.find(Operands); + if (MI != SignaturesWithConstantForms.end()) { + // Unique any duplicates out of the list. + std::sort(MI->second.begin(), MI->second.end()); + MI->second.erase(std::unique(MI->second.begin(), MI->second.end()), + MI->second.end()); + + // Check each in order it was seen. It would be nice to have a good + // relative ordering between them, but we're not going for optimality + // here. + for (unsigned i = 0, e = MI->second.size(); i != e; ++i) { + OS << " if ("; + MI->second[i].emitImmediatePredicate(OS, ImmediatePredicates); + OS << ")\n if (unsigned Reg = FastEmit_"; + MI->second[i].PrintManglingSuffix(OS, ImmediatePredicates); + OS << "(VT, RetVT, Opcode"; + if (!MI->second[i].empty()) + OS << ", "; + MI->second[i].PrintArguments(OS); + OS << "))\n return Reg;\n\n"; + } + + // Done with this, remove it. + SignaturesWithConstantForms.erase(MI); + } + OS << " switch (Opcode) {\n"; for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end(); I != E; ++I) { @@ -617,7 +840,7 @@ void FastISelMap::PrintFunctionDefinitions(raw_ostream &OS) { OS << " case " << Opcode << ": return FastEmit_" << getLegalCName(Opcode) << "_"; - Operands.PrintManglingSuffix(OS); + Operands.PrintManglingSuffix(OS, ImmediatePredicates); OS << "(VT, RetVT"; if (!Operands.empty()) OS << ", "; @@ -629,6 +852,8 @@ void FastISelMap::PrintFunctionDefinitions(raw_ostream &OS) { OS << "}\n"; OS << "\n"; } + + // TODO: SignaturesWithConstantForms should be empty here. } void FastISelEmitter::run(raw_ostream &OS) { @@ -642,12 +867,12 @@ void FastISelEmitter::run(raw_ostream &OS) { Target.getName() + " target", OS); FastISelMap F(InstNS); - F.CollectPatterns(CGP); - F.PrintFunctionDefinitions(OS); + F.collectPatterns(CGP); + F.printImmediatePredicates(OS); + F.printFunctionDefinitions(OS); } FastISelEmitter::FastISelEmitter(RecordKeeper &R) - : Records(R), - CGP(R) { + : Records(R), CGP(R) { } diff --git a/utils/TableGen/FixedLenDecoderEmitter.cpp b/utils/TableGen/FixedLenDecoderEmitter.cpp index 2c222b3..9312fe8 100644 --- a/utils/TableGen/FixedLenDecoderEmitter.cpp +++ b/utils/TableGen/FixedLenDecoderEmitter.cpp @@ -438,7 +438,7 @@ void Filter::recurse() { for (bitIndex = 0; bitIndex < NumBits; bitIndex++) BitValueArray[StartBit + bitIndex] = BIT_UNSET; - // Delegates to an inferior filter chooser for futher processing on this + // Delegates to an inferior filter chooser for further processing on this // group of instructions whose segment values are variable. FilterChooserMap.insert(std::pair<unsigned, FilterChooser*>( (unsigned)-1, @@ -471,7 +471,7 @@ void Filter::recurse() { BitValueArray[StartBit + bitIndex] = BIT_FALSE; } - // Delegates to an inferior filter chooser for futher processing on this + // Delegates to an inferior filter chooser for further processing on this // category of instructions. FilterChooserMap.insert(std::pair<unsigned, FilterChooser*>( mapIterator->first, @@ -611,7 +611,8 @@ void FilterChooser::emitTop(raw_ostream &o, unsigned Indentation) { o << '\n'; o.indent(Indentation) << - "static bool decodeInstruction(MCInst &MI, field_t insn) {\n"; + "static bool decodeInstruction(MCInst &MI, field_t insn, " + "uint64_t Address, const void *Decoder) {\n"; o.indent(Indentation) << " unsigned tmp = 0;\n"; ++Indentation; ++Indentation; @@ -795,7 +796,8 @@ bool FilterChooser::emitSingletonDecoder(raw_ostream &o, unsigned &Indentation, I = InsnOperands.begin(), E = InsnOperands.end(); I != E; ++I) { // If a custom instruction decoder was specified, use that. if (I->FieldBase == ~0U && I->FieldLength == ~0U) { - o.indent(Indentation) << " " << I->Decoder << "(MI, insn);\n"; + o.indent(Indentation) << " " << I->Decoder + << "(MI, insn, Address, Decoder);\n"; break; } @@ -803,7 +805,8 @@ bool FilterChooser::emitSingletonDecoder(raw_ostream &o, unsigned &Indentation, << " tmp = fieldFromInstruction(insn, " << I->FieldBase << ", " << I->FieldLength << ");\n"; if (I->Decoder != "") { - o.indent(Indentation) << " " << I->Decoder << "(MI, tmp);\n"; + o.indent(Indentation) << " " << I->Decoder + << "(MI, tmp, Address, Decoder);\n"; } else { o.indent(Indentation) << " MI.addOperand(MCOperand::CreateImm(tmp));\n"; @@ -846,7 +849,8 @@ bool FilterChooser::emitSingletonDecoder(raw_ostream &o, unsigned &Indentation, I = InsnOperands.begin(), E = InsnOperands.end(); I != E; ++I) { // If a custom instruction decoder was specified, use that. if (I->FieldBase == ~0U && I->FieldLength == ~0U) { - o.indent(Indentation) << " " << I->Decoder << "(MI, insn);\n"; + o.indent(Indentation) << " " << I->Decoder + << "(MI, insn, Address, Decoder);\n"; break; } @@ -854,7 +858,8 @@ bool FilterChooser::emitSingletonDecoder(raw_ostream &o, unsigned &Indentation, << " tmp = fieldFromInstruction(insn, " << I->FieldBase << ", " << I->FieldLength << ");\n"; if (I->Decoder != "") { - o.indent(Indentation) << " " << I->Decoder << "(MI, tmp);\n"; + o.indent(Indentation) << " " << I->Decoder + << "(MI, tmp, Address, Decoder);\n"; } else { o.indent(Indentation) << " MI.addOperand(MCOperand::CreateImm(tmp));\n"; @@ -1224,7 +1229,8 @@ bool FixedLenDecoderEmitter::populateInstruction(const CodeGenInstruction &CGI, if (Bits.allInComplete()) return false; // Ignore "asm parser only" instructions. - if (Def.getValueAsBit("isAsmParserOnly")) + if (Def.getValueAsBit("isAsmParserOnly") || + Def.getValueAsBit("isCodeGenOnly")) return false; std::vector<OperandInfo> InsnOperands; diff --git a/utils/TableGen/InstrInfoEmitter.cpp b/utils/TableGen/InstrInfoEmitter.cpp index 2b684be..67cce0e 100644 --- a/utils/TableGen/InstrInfoEmitter.cpp +++ b/utils/TableGen/InstrInfoEmitter.cpp @@ -272,6 +272,7 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num, if (Inst.isIndirectBranch) OS << "|(1<<TID::IndirectBranch)"; if (Inst.isCompare) OS << "|(1<<TID::Compare)"; if (Inst.isMoveImm) OS << "|(1<<TID::MoveImm)"; + if (Inst.isBitcast) OS << "|(1<<TID::Bitcast)"; if (Inst.isBarrier) OS << "|(1<<TID::Barrier)"; if (Inst.hasDelaySlot) OS << "|(1<<TID::DelaySlot)"; if (Inst.isCall) OS << "|(1<<TID::Call)"; diff --git a/utils/TableGen/LLVMCConfigurationEmitter.cpp b/utils/TableGen/LLVMCConfigurationEmitter.cpp index c40a39d..6572595 100644 --- a/utils/TableGen/LLVMCConfigurationEmitter.cpp +++ b/utils/TableGen/LLVMCConfigurationEmitter.cpp @@ -3028,6 +3028,8 @@ void CheckDriverData(DriverData& Data) { FilterNotInGraph(Data.Edges, Data.ToolDescs); // Typecheck the compilation graph. + // TODO: use a genuine graph representation instead of a vector and check for + // multiple edges. TypecheckGraph(Data.Edges, Data.ToolDescs); // Check that there are no options without side effects (specified diff --git a/utils/TableGen/NeonEmitter.cpp b/utils/TableGen/NeonEmitter.cpp index 64224d9..123abef 100644 --- a/utils/TableGen/NeonEmitter.cpp +++ b/utils/TableGen/NeonEmitter.cpp @@ -462,9 +462,34 @@ static std::string MangleName(const std::string &name, StringRef typestr, return s; } +/// UseMacro - Examine the prototype string to determine if the intrinsic +/// should be defined as a preprocessor macro instead of an inline function. +static bool UseMacro(const std::string &proto) { + // If this builtin takes an immediate argument, we need to #define it rather + // than use a standard declaration, so that SemaChecking can range check + // the immediate passed by the user. + if (proto.find('i') != std::string::npos) + return true; + + // Pointer arguments need to use macros to avoid hiding aligned attributes + // from the pointer type. + if (proto.find('p') != std::string::npos || + proto.find('c') != std::string::npos) + return true; + + return false; +} + +/// MacroArgUsedDirectly - Return true if argument i for an intrinsic that is +/// defined as a macro should be accessed directly instead of being first +/// assigned to a local temporary. +static bool MacroArgUsedDirectly(const std::string &proto, unsigned i) { + return (proto[i] == 'i' || proto[i] == 'p' || proto[i] == 'c'); +} + // Generate the string "(argtype a, argtype b, ...)" static std::string GenArgs(const std::string &proto, StringRef typestr) { - bool define = proto.find('i') != std::string::npos; + bool define = UseMacro(proto); char arg = 'a'; std::string s; @@ -472,10 +497,10 @@ static std::string GenArgs(const std::string &proto, StringRef typestr) { for (unsigned i = 1, e = proto.size(); i != e; ++i, ++arg) { if (define) { - // Immediate macro arguments are used directly instead of being assigned + // Some macro arguments are used directly instead of being assigned // to local temporaries; prepend an underscore prefix to make their // names consistent with the local temporaries. - if (proto[i] == 'i') + if (MacroArgUsedDirectly(proto, i)) s += "__"; } else { s += TypeString(proto[i], typestr) + " __"; @@ -494,11 +519,28 @@ static std::string GenArgs(const std::string &proto, StringRef typestr) { static std::string GenMacroLocals(const std::string &proto, StringRef typestr) { char arg = 'a'; std::string s; + bool generatedLocal = false; for (unsigned i = 1, e = proto.size(); i != e; ++i, ++arg) { // Do not create a temporary for an immediate argument. // That would defeat the whole point of using a macro! - if (proto[i] == 'i') continue; + if (proto[i] == 'i') + continue; + generatedLocal = true; + + // For other (non-immediate) arguments that are used directly, a local + // temporary is still needed to get the correct type checking, even though + // that temporary is not used for anything. + if (MacroArgUsedDirectly(proto, i)) { + s += TypeString(proto[i], typestr) + " __"; + s.push_back(arg); + s += "_ = (__"; + s.push_back(arg); + s += "); (void)__"; + s.push_back(arg); + s += "_; "; + continue; + } s += TypeString(proto[i], typestr) + " __"; s.push_back(arg); @@ -507,7 +549,8 @@ static std::string GenMacroLocals(const std::string &proto, StringRef typestr) { s += "); "; } - s += "\\\n "; + if (generatedLocal) + s += "\\\n "; return s; } @@ -568,11 +611,7 @@ static std::string GenOpString(OpKind op, const std::string &proto, StringRef typestr) { bool quad; unsigned nElts = GetNumElements(typestr, quad); - - // If this builtin takes an immediate argument, we need to #define it rather - // than use a standard declaration, so that SemaChecking can range check - // the immediate passed by the user. - bool define = proto.find('i') != std::string::npos; + bool define = UseMacro(proto); std::string ts = TypeString(proto[0], typestr); std::string s; @@ -608,16 +647,9 @@ static std::string GenOpString(OpKind op, const std::string &proto, case OpMul: s += "__a * __b;"; break; - case OpMullN: - s += Extend(typestr, "__a") + " * " + - Extend(typestr, Duplicate(nElts << (int)quad, typestr, "__b")) + ";"; - break; case OpMullLane: - s += Extend(typestr, "__a") + " * " + - Extend(typestr, SplatLane(nElts, "__b", "__c")) + ";"; - break; - case OpMull: - s += Extend(typestr, "__a") + " * " + Extend(typestr, "__b") + ";"; + s += MangleName("vmull", typestr, ClassS) + "(__a, " + + SplatLane(nElts, "__b", "__c") + ");"; break; case OpMlaN: s += "__a + (__b * " + Duplicate(nElts, typestr, "__c") + ");"; @@ -629,16 +661,15 @@ static std::string GenOpString(OpKind op, const std::string &proto, s += "__a + (__b * __c);"; break; case OpMlalN: - s += "__a + (" + Extend(typestr, "__b") + " * " + - Extend(typestr, Duplicate(nElts, typestr, "__c")) + ");"; + s += "__a + " + MangleName("vmull", typestr, ClassS) + "(__b, " + + Duplicate(nElts, typestr, "__c") + ");"; break; case OpMlalLane: - s += "__a + (" + Extend(typestr, "__b") + " * " + - Extend(typestr, SplatLane(nElts, "__c", "__d")) + ");"; + s += "__a + " + MangleName("vmull", typestr, ClassS) + "(__b, " + + SplatLane(nElts, "__c", "__d") + ");"; break; case OpMlal: - s += "__a + (" + Extend(typestr, "__b") + " * " + - Extend(typestr, "__c") + ");"; + s += "__a + " + MangleName("vmull", typestr, ClassS) + "(__b, __c);"; break; case OpMlsN: s += "__a - (__b * " + Duplicate(nElts, typestr, "__c") + ");"; @@ -650,16 +681,15 @@ static std::string GenOpString(OpKind op, const std::string &proto, s += "__a - (__b * __c);"; break; case OpMlslN: - s += "__a - (" + Extend(typestr, "__b") + " * " + - Extend(typestr, Duplicate(nElts, typestr, "__c")) + ");"; + s += "__a - " + MangleName("vmull", typestr, ClassS) + "(__b, " + + Duplicate(nElts, typestr, "__c") + ");"; break; case OpMlslLane: - s += "__a - (" + Extend(typestr, "__b") + " * " + - Extend(typestr, SplatLane(nElts, "__c", "__d")) + ");"; + s += "__a - " + MangleName("vmull", typestr, ClassS) + "(__b, " + + SplatLane(nElts, "__c", "__d") + ");"; break; case OpMlsl: - s += "__a - (" + Extend(typestr, "__b") + " * " + - Extend(typestr, "__c") + ");"; + s += "__a - " + MangleName("vmull", typestr, ClassS) + "(__b, __c);"; break; case OpQDMullLane: s += MangleName("vqdmull", typestr, ClassS) + "(__a, " + @@ -867,10 +897,7 @@ static std::string GenBuiltin(const std::string &name, const std::string &proto, // sret-like argument. bool sret = (proto[0] >= '2' && proto[0] <= '4'); - // If this builtin takes an immediate argument, we need to #define it rather - // than use a standard declaration, so that SemaChecking can range check - // the immediate passed by the user. - bool define = proto.find('i') != std::string::npos; + bool define = UseMacro(proto); // Check if the prototype has a scalar operand with the type of the vector // elements. If not, bitcasting the args will take care of arg checking. @@ -1008,7 +1035,7 @@ static std::string GenIntrinsic(const std::string &name, StringRef outTypeStr, StringRef inTypeStr, OpKind kind, ClassKind classKind) { assert(!proto.empty() && ""); - bool define = proto.find('i') != std::string::npos; + bool define = UseMacro(proto); std::string s; // static always inline + return type @@ -1148,17 +1175,20 @@ void NeonEmitter::run(raw_ostream &OS) { std::vector<Record*> RV = Records.getAllDerivedDefinitions("Inst"); - // Emit vmovl and vabd intrinsics first so they can be used by other + // Emit vmovl, vmull and vabd intrinsics first so they can be used by other // intrinsics. (Some of the saturating multiply instructions are also // used to implement the corresponding "_lane" variants, but tablegen // sorts the records into alphabetical order so that the "_lane" variants // come after the intrinsics they use.) emitIntrinsic(OS, Records.getDef("VMOVL")); + emitIntrinsic(OS, Records.getDef("VMULL")); emitIntrinsic(OS, Records.getDef("VABD")); for (unsigned i = 0, e = RV.size(); i != e; ++i) { Record *R = RV[i]; - if (R->getName() != "VMOVL" && R->getName() != "VABD") + if (R->getName() != "VMOVL" && + R->getName() != "VMULL" && + R->getName() != "VABD") emitIntrinsic(OS, R); } diff --git a/utils/TableGen/NeonEmitter.h b/utils/TableGen/NeonEmitter.h index 1e6fcbf..12e4e86 100644 --- a/utils/TableGen/NeonEmitter.h +++ b/utils/TableGen/NeonEmitter.h @@ -30,13 +30,11 @@ enum OpKind { OpSubl, OpSubw, OpMul, - OpMull, OpMla, OpMlal, OpMls, OpMlsl, OpMulN, - OpMullN, OpMlaN, OpMlsN, OpMlalN, @@ -105,13 +103,11 @@ namespace llvm { OpMap["OP_SUBL"] = OpSubl; OpMap["OP_SUBW"] = OpSubw; OpMap["OP_MUL"] = OpMul; - OpMap["OP_MULL"] = OpMull; OpMap["OP_MLA"] = OpMla; OpMap["OP_MLAL"] = OpMlal; OpMap["OP_MLS"] = OpMls; OpMap["OP_MLSL"] = OpMlsl; OpMap["OP_MUL_N"] = OpMulN; - OpMap["OP_MULL_N"]= OpMullN; OpMap["OP_MLA_N"] = OpMlaN; OpMap["OP_MLS_N"] = OpMlsN; OpMap["OP_MLAL_N"] = OpMlalN; diff --git a/utils/TableGen/OptParserEmitter.cpp b/utils/TableGen/OptParserEmitter.cpp index 6892912..431026c 100644 --- a/utils/TableGen/OptParserEmitter.cpp +++ b/utils/TableGen/OptParserEmitter.cpp @@ -35,7 +35,7 @@ static int CompareOptionRecords(const void *Av, const void *Bv) { const Record *A = *(Record**) Av; const Record *B = *(Record**) Bv; - // Sentinel options preceed all others and are only ordered by precedence. + // Sentinel options precede all others and are only ordered by precedence. bool ASent = A->getValueAsDef("Kind")->getValueAsBit("Sentinel"); bool BSent = B->getValueAsDef("Kind")->getValueAsBit("Sentinel"); if (ASent != BSent) diff --git a/utils/TableGen/Record.h b/utils/TableGen/Record.h index f3a5df2..522b719 100644 --- a/utils/TableGen/Record.h +++ b/utils/TableGen/Record.h @@ -707,7 +707,7 @@ class CodeInit : public Init { public: explicit CodeInit(const std::string &V) : Value(V) {} - const std::string getValue() const { return Value; } + const std::string &getValue() const { return Value; } virtual Init *convertInitializerTo(RecTy *Ty) { return Ty->convertValue(this); diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp index 96399a4..4ddc47d 100644 --- a/utils/TableGen/RegisterInfoEmitter.cpp +++ b/utils/TableGen/RegisterInfoEmitter.cpp @@ -38,7 +38,10 @@ void RegisterInfoEmitter::runEnums(raw_ostream &OS) { OS << "enum {\n NoRegister,\n"; for (unsigned i = 0, e = Registers.size(); i != e; ++i) - OS << " " << Registers[i].getName() << ", \t// " << i+1 << "\n"; + OS << " " << Registers[i].getName() << " = " << + Registers[i].EnumValue << ",\n"; + assert(Registers.size() == Registers[Registers.size()-1].EnumValue && + "Register enum value mismatch!"); OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n"; OS << "};\n"; if (!Namespace.empty()) @@ -91,7 +94,7 @@ void RegisterInfoEmitter::runHeader(raw_ostream &OS) { if (!RegisterClasses.empty()) { OS << "namespace " << RegisterClasses[0].Namespace << " { // Register classes\n"; - + OS << " enum {\n"; for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { if (i) OS << ",\n"; @@ -358,7 +361,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { // Give the register class a legal C name if it's anonymous. std::string Name = RC.TheDef->getName(); - + // Emit the register list now. OS << " // " << Name << " Register Class...\n" << " static const unsigned " << Name @@ -376,12 +379,12 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { // Emit the ValueType arrays for each RegisterClass for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { const CodeGenRegisterClass &RC = RegisterClasses[rc]; - + // Give the register class a legal C name if it's anonymous. std::string Name = RC.TheDef->getName() + "VTs"; - + // Emit the register list now. - OS << " // " << Name + OS << " // " << Name << " Register Class Value Types...\n" << " static const EVT " << Name << "[] = {\n "; @@ -390,7 +393,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { OS << "MVT::Other\n };\n\n"; } OS << "} // end anonymous namespace\n\n"; - + // Now that all of the structs have been emitted, emit the instances. if (!RegisterClasses.empty()) { OS << "namespace " << RegisterClasses[0].Namespace @@ -398,7 +401,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) OS << " " << RegisterClasses[i].getName() << "Class\t" << RegisterClasses[i].getName() << "RegClass;\n"; - + std::map<unsigned, std::set<unsigned> > SuperClassMap; std::map<unsigned, std::set<unsigned> > SuperRegClassMap; OS << "\n"; @@ -488,7 +491,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { // Give the register class a legal C name if it's anonymous. std::string Name = RC.TheDef->getName(); - OS << " // " << Name + OS << " // " << Name << " Register Class sub-classes...\n" << " static const TargetRegisterClass* const " << Name << "Subclasses[] = {\n "; @@ -500,7 +503,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { // Sub-classes are used to determine if a virtual register can be used // as an instruction operand, or if it must be copied first. if (rc == rc2 || !RC.hasSubClass(&RC2)) continue; - + if (!Empty) OS << ", "; OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass"; Empty = false; @@ -524,7 +527,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { // Give the register class a legal C name if it's anonymous. std::string Name = RC.TheDef->getName(); - OS << " // " << Name + OS << " // " << Name << " Register Class super-classes...\n" << " static const TargetRegisterClass* const " << Name << "Superclasses[] = {\n "; @@ -538,7 +541,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { const CodeGenRegisterClass &RC2 = RegisterClasses[*II]; if (!Empty) OS << ", "; OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass"; - Empty = false; + Empty = false; } } @@ -550,7 +553,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { const CodeGenRegisterClass &RC = RegisterClasses[i]; OS << RC.MethodBodies << "\n"; - OS << RC.getName() << "Class::" << RC.getName() + OS << RC.getName() << "Class::" << RC.getName() << "Class() : TargetRegisterClass(" << RC.getName() + "RegClassID" << ", " << '\"' << RC.getName() << "\", " @@ -567,7 +570,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { << RC.getName() << ", " << RC.getName() << " + " << RC.Elements.size() << ") {}\n"; } - + OS << "}\n"; } @@ -584,7 +587,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { std::map<Record*, std::set<Record*>, LessRecord> RegisterAliases; typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy; DwarfRegNumsMapTy DwarfRegNums; - + const std::vector<CodeGenRegister> &Regs = Target.getRegisters(); for (unsigned i = 0, e = Regs.size(); i != e; ++i) { @@ -623,7 +626,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { RegisterAliases); } } - + // Print the SubregHashTable, a simple quadratically probed // hash table for determining if a register is a subregister // of another register. @@ -633,13 +636,13 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { RegNo[Regs[i].TheDef] = i; NumSubRegs += RegisterSubRegs[Regs[i].TheDef].size(); } - + unsigned SubregHashTableSize = 2 * NextPowerOf2(2 * NumSubRegs); unsigned* SubregHashTable = new unsigned[2 * SubregHashTableSize]; std::fill(SubregHashTable, SubregHashTable + 2 * SubregHashTableSize, ~0U); - + unsigned hashMisses = 0; - + for (unsigned i = 0, e = Regs.size(); i != e; ++i) { Record* R = Regs[i].TheDef; for (std::set<Record*>::iterator I = RegisterSubRegs[R].begin(), @@ -654,26 +657,26 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { SubregHashTable[index*2+1] != ~0U) { index = (index + ProbeAmt) & (SubregHashTableSize-1); ProbeAmt += 2; - + hashMisses++; } - + SubregHashTable[index*2] = i; SubregHashTable[index*2+1] = RegNo[RJ]; } } - + OS << "\n\n // Number of hash collisions: " << hashMisses << "\n"; - + if (SubregHashTableSize) { std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace"); - + OS << " const unsigned SubregHashTable[] = { "; for (unsigned i = 0; i < SubregHashTableSize - 1; ++i) { if (i != 0) // Insert spaces for nice formatting. OS << " "; - + if (SubregHashTable[2*i] != ~0U) { OS << getQualifiedName(Regs[SubregHashTable[2*i]].TheDef) << ", " << getQualifiedName(Regs[SubregHashTable[2*i+1]].TheDef) << ", \n"; @@ -681,7 +684,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n"; } } - + unsigned Idx = SubregHashTableSize*2-2; if (SubregHashTable[Idx] != ~0U) { OS << " " @@ -690,14 +693,14 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { } else { OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n"; } - + OS << " const unsigned SubregHashTableSize = " << SubregHashTableSize << ";\n"; } else { OS << " const unsigned SubregHashTable[] = { ~0U, ~0U };\n" << " const unsigned SubregHashTableSize = 1;\n"; } - + delete [] SubregHashTable; @@ -709,13 +712,13 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { RegNo[Regs[i].TheDef] = i; NumAliases += RegisterAliases[Regs[i].TheDef].size(); } - + unsigned AliasesHashTableSize = 2 * NextPowerOf2(2 * NumAliases); unsigned* AliasesHashTable = new unsigned[2 * AliasesHashTableSize]; std::fill(AliasesHashTable, AliasesHashTable + 2 * AliasesHashTableSize, ~0U); - + hashMisses = 0; - + for (unsigned i = 0, e = Regs.size(); i != e; ++i) { Record* R = Regs[i].TheDef; for (std::set<Record*>::iterator I = RegisterAliases[R].begin(), @@ -730,26 +733,26 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { AliasesHashTable[index*2+1] != ~0U) { index = (index + ProbeAmt) & (AliasesHashTableSize-1); ProbeAmt += 2; - + hashMisses++; } - + AliasesHashTable[index*2] = i; AliasesHashTable[index*2+1] = RegNo[RJ]; } } - + OS << "\n\n // Number of hash collisions: " << hashMisses << "\n"; - + if (AliasesHashTableSize) { std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace"); - + OS << " const unsigned AliasesHashTable[] = { "; for (unsigned i = 0; i < AliasesHashTableSize - 1; ++i) { if (i != 0) // Insert spaces for nice formatting. OS << " "; - + if (AliasesHashTable[2*i] != ~0U) { OS << getQualifiedName(Regs[AliasesHashTable[2*i]].TheDef) << ", " << getQualifiedName(Regs[AliasesHashTable[2*i+1]].TheDef) << ", \n"; @@ -757,7 +760,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n"; } } - + unsigned Idx = AliasesHashTableSize*2-2; if (AliasesHashTable[Idx] != ~0U) { OS << " " @@ -766,14 +769,14 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { } else { OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n"; } - + OS << " const unsigned AliasesHashTableSize = " << AliasesHashTableSize << ";\n"; } else { OS << " const unsigned AliasesHashTable[] = { ~0U, ~0U };\n" << " const unsigned AliasesHashTableSize = 1;\n"; } - + delete [] AliasesHashTable; if (!RegisterAliases.empty()) @@ -838,7 +841,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { } OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors\n"; - OS << " { \"NOREG\",\t0,\t0,\t0 },\n"; + OS << " { \"NOREG\",\t0,\t0,\t0,\t0 },\n"; // Now that register alias and sub-registers sets have been emitted, emit the // register descriptors now. @@ -851,9 +854,10 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { else OS << "Empty_SubRegsSet,\t"; if (!RegisterSuperRegs[Reg.TheDef].empty()) - OS << Reg.getName() << "_SuperRegsSet },\n"; + OS << Reg.getName() << "_SuperRegsSet,\t"; else - OS << "Empty_SuperRegsSet },\n"; + OS << "Empty_SuperRegsSet,\t"; + OS << Reg.CostPerUse << " },\n"; } OS << " };\n"; // End of register descriptors... @@ -966,7 +970,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { } // Now we know maximal length of number list. Append -1's, where needed - for (DwarfRegNumsMapTy::iterator + for (DwarfRegNumsMapTy::iterator I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) for (unsigned i = I->second.size(), e = maxLength; i != e; ++i) I->second.push_back(-1); @@ -978,18 +982,18 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { << " default:\n" << " assert(0 && \"Unknown DWARF flavour\");\n" << " return -1;\n"; - + for (unsigned i = 0, e = maxLength; i != e; ++i) { OS << " case " << i << ":\n" << " switch (RegNum) {\n" << " default:\n" << " assert(0 && \"Invalid RegNum\");\n" << " return -1;\n"; - + // Sort by name to get a stable order. - - for (DwarfRegNumsMapTy::iterator + + for (DwarfRegNumsMapTy::iterator I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) { int RegNo = I->second[i]; if (RegNo != -2) @@ -1002,7 +1006,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { } OS << " };\n"; } - + OS << " };\n}\n\n"; OS << "} // End llvm namespace \n"; diff --git a/utils/TableGen/SubtargetEmitter.cpp b/utils/TableGen/SubtargetEmitter.cpp index e35bdca..928fa4b 100644 --- a/utils/TableGen/SubtargetEmitter.cpp +++ b/utils/TableGen/SubtargetEmitter.cpp @@ -31,24 +31,30 @@ void SubtargetEmitter::Enumeration(raw_ostream &OS, // Open enumeration OS << "enum {\n"; - + // For each record - for (unsigned i = 0, N = DefList.size(); i < N;) { + unsigned N = DefList.size(); + if (N > 64) { + errs() << "Too many (> 64) subtarget features!\n"; + exit(1); + } + + for (unsigned i = 0; i < N;) { // Next record Record *Def = DefList[i]; - + // Get and emit name OS << " " << Def->getName(); - + // If bit flags then emit expression (1 << i) - if (isBits) OS << " = " << " 1 << " << i; + if (isBits) OS << " = " << " 1ULL << " << i; // Depending on 'if more in the list' emit comma if (++i < N) OS << ","; - + OS << "\n"; } - + // Close enumeration OS << "};\n"; } @@ -66,7 +72,7 @@ void SubtargetEmitter::FeatureKeyValues(raw_ostream &OS) { // Begin feature table OS << "// Sorted (by key) array of values for CPU features.\n" << "static const llvm::SubtargetFeatureKV FeatureKV[] = {\n"; - + // For each feature for (unsigned i = 0, N = FeatureList.size(); i < N; ++i) { // Next feature @@ -75,20 +81,20 @@ void SubtargetEmitter::FeatureKeyValues(raw_ostream &OS) { const std::string &Name = Feature->getName(); const std::string &CommandLineName = Feature->getValueAsString("Name"); const std::string &Desc = Feature->getValueAsString("Desc"); - + if (CommandLineName.empty()) continue; - + // Emit as { "feature", "description", featureEnum, i1 | i2 | ... | in } OS << " { " << "\"" << CommandLineName << "\", " << "\"" << Desc << "\", " << Name << ", "; - const std::vector<Record*> &ImpliesList = + const std::vector<Record*> &ImpliesList = Feature->getValueAsListOfDefs("Implies"); - + if (ImpliesList.empty()) { - OS << "0"; + OS << "0ULL"; } else { for (unsigned j = 0, M = ImpliesList.size(); j < M;) { OS << ImpliesList[j]->getName(); @@ -97,13 +103,13 @@ void SubtargetEmitter::FeatureKeyValues(raw_ostream &OS) { } OS << " }"; - + // Depending on 'if more in the list' emit comma if ((i + 1) < N) OS << ","; - + OS << "\n"; } - + // End feature table OS << "};\n"; @@ -126,39 +132,39 @@ void SubtargetEmitter::CPUKeyValues(raw_ostream &OS) { // Begin processor table OS << "// Sorted (by key) array of values for CPU subtype.\n" << "static const llvm::SubtargetFeatureKV SubTypeKV[] = {\n"; - + // For each processor for (unsigned i = 0, N = ProcessorList.size(); i < N;) { // Next processor Record *Processor = ProcessorList[i]; const std::string &Name = Processor->getValueAsString("Name"); - const std::vector<Record*> &FeatureList = + const std::vector<Record*> &FeatureList = Processor->getValueAsListOfDefs("Features"); - + // Emit as { "cpu", "description", f1 | f2 | ... fn }, OS << " { " << "\"" << Name << "\", " << "\"Select the " << Name << " processor\", "; - + if (FeatureList.empty()) { - OS << "0"; + OS << "0ULL"; } else { for (unsigned j = 0, M = FeatureList.size(); j < M;) { OS << FeatureList[j]->getName(); if (++j < M) OS << " | "; } } - + // The "0" is for the "implies" section of this data structure. - OS << ", 0 }"; - + OS << ", 0ULL }"; + // Depending on 'if more in the list' emit comma if (++i < N) OS << ","; - + OS << "\n"; } - + // End processor table OS << "};\n"; @@ -185,7 +191,7 @@ CollectAllItinClasses(raw_ostream &OS, // Assign itinerary class a unique number ItinClassesMap[ItinClass->getName()] = i; } - + // Emit size of table OS<<"\nenum {\n"; OS<<" ItinClassesSize = " << N << "\n"; @@ -213,21 +219,21 @@ void SubtargetEmitter::FormItineraryStageString(const std::string &Name, for (unsigned i = 0; i < N;) { // Next stage const Record *Stage = StageList[i]; - + // Form string as ,{ cycles, u1 | u2 | ... | un, timeinc, kind } int Cycles = Stage->getValueAsInt("Cycles"); ItinString += " { " + itostr(Cycles) + ", "; - + // Get unit list const std::vector<Record*> &UnitList = Stage->getValueAsListOfDefs("Units"); - + // For each unit for (unsigned j = 0, M = UnitList.size(); j < M;) { // Add name and bitwise or ItinString += Name + "FU::" + UnitList[j]->getName(); if (++j < M) ItinString += " | "; } - + int TimeInc = Stage->getValueAsInt("TimeInc"); ItinString += ", " + itostr(TimeInc); @@ -256,7 +262,7 @@ void SubtargetEmitter::FormItineraryOperandCycleString(Record *ItinData, for (unsigned i = 0; i < N;) { // Next operand cycle const int OCycle = OperandCycleList[i]; - + ItinString += " " + itostr(OCycle); if (++i < N) ItinString += ", "; } @@ -292,7 +298,7 @@ void SubtargetEmitter::EmitStageAndOperandCycleData(raw_ostream &OS, // Gather processor iteraries std::vector<Record*> ProcItinList = Records.getAllDerivedDefinitions("ProcessorItineraries"); - + // If just no itinerary then don't bother if (ProcItinList.size() < 2) return; @@ -332,7 +338,7 @@ void SubtargetEmitter::EmitStageAndOperandCycleData(raw_ostream &OS, // Begin stages table std::string StageTable = "\nstatic const llvm::InstrStage Stages[] = {\n"; StageTable += " { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary\n"; - + // Begin operand cycle table std::string OperandCycleTable = "static const unsigned OperandCycles[] = {\n"; OperandCycleTable += " 0, // No itinerary\n"; @@ -340,32 +346,31 @@ void SubtargetEmitter::EmitStageAndOperandCycleData(raw_ostream &OS, // Begin pipeline bypass table std::string BypassTable = "static const unsigned ForwardingPathes[] = {\n"; BypassTable += " 0, // No itinerary\n"; - + unsigned StageCount = 1, OperandCycleCount = 1; - unsigned ItinStageEnum = 1, ItinOperandCycleEnum = 1; std::map<std::string, unsigned> ItinStageMap, ItinOperandMap; for (unsigned i = 0, N = ProcItinList.size(); i < N; i++) { // Next record Record *Proc = ProcItinList[i]; - + // Get processor itinerary name const std::string &Name = Proc->getName(); - + // Skip default if (Name == "NoItineraries") continue; - + // Create and expand processor itinerary to cover all itinerary classes std::vector<InstrItinerary> ItinList; ItinList.resize(NItinClasses); - + // Get itinerary data list std::vector<Record*> ItinDataList = Proc->getValueAsListOfDefs("IID"); - + // For each itinerary data for (unsigned j = 0, M = ItinDataList.size(); j < M; j++) { // Next itinerary data Record *ItinData = ItinDataList[j]; - + // Get string and stage count std::string ItinStageString; unsigned NStages; @@ -386,15 +391,17 @@ void SubtargetEmitter::EmitStageAndOperandCycleData(raw_ostream &OS, if (NStages > 0) { FindStage = ItinStageMap[ItinStageString]; if (FindStage == 0) { - // Emit as { cycles, u1 | u2 | ... | un, timeinc }, // index - StageTable += ItinStageString + ", // " + itostr(ItinStageEnum) + "\n"; + // Emit as { cycles, u1 | u2 | ... | un, timeinc }, // indices + StageTable += ItinStageString + ", // " + itostr(StageCount); + if (NStages > 1) + StageTable += "-" + itostr(StageCount + NStages - 1); + StageTable += "\n"; // Record Itin class number. ItinStageMap[ItinStageString] = FindStage = StageCount; StageCount += NStages; - ItinStageEnum++; } } - + // Check to see if operand cycle already exists and create if it doesn't unsigned FindOperandCycle = 0; if (NOperandCycles > 0) { @@ -402,25 +409,25 @@ void SubtargetEmitter::EmitStageAndOperandCycleData(raw_ostream &OS, FindOperandCycle = ItinOperandMap[ItinOperandString]; if (FindOperandCycle == 0) { // Emit as cycle, // index - OperandCycleTable += ItinOperandCycleString + ", // " + - itostr(ItinOperandCycleEnum) + "\n"; + OperandCycleTable += ItinOperandCycleString + ", // "; + std::string OperandIdxComment = itostr(OperandCycleCount); + if (NOperandCycles > 1) + OperandIdxComment += "-" + + itostr(OperandCycleCount + NOperandCycles - 1); + OperandCycleTable += OperandIdxComment + "\n"; // Record Itin class number. - ItinOperandMap[ItinOperandCycleString] = + ItinOperandMap[ItinOperandCycleString] = FindOperandCycle = OperandCycleCount; - // Emit as bypass, // index - BypassTable += ItinBypassString + ", // " + - itostr(ItinOperandCycleEnum) + "\n"; - + BypassTable += ItinBypassString + ", // " + OperandIdxComment + "\n"; OperandCycleCount += NOperandCycles; - ItinOperandCycleEnum++; } } - + // Locate where to inject into processor itinerary table const std::string &Name = ItinData->getValueAsDef("TheClass")->getName(); unsigned Find = ItinClassesMap[Name]; - + // Set up itinerary as location and location + stage count unsigned NumUOps = ItinClassList[Find]->getValueAsInt("NumMicroOps"); InstrItinerary Intinerary = { NumUOps, FindStage, FindStage + NStages, @@ -430,7 +437,7 @@ void SubtargetEmitter::EmitStageAndOperandCycleData(raw_ostream &OS, // Inject - empty slots will be 0, 0 ItinList[Find] = Intinerary; } - + // Add process itinerary to list ProcList.push_back(ItinList); } @@ -450,7 +457,7 @@ void SubtargetEmitter::EmitStageAndOperandCycleData(raw_ostream &OS, OS << StageTable; OS << OperandCycleTable; OS << BypassTable; - + // Emit size of tables OS<<"\nenum {\n"; OS<<" StagesSize = sizeof(Stages)/sizeof(llvm::InstrStage),\n"; @@ -461,12 +468,14 @@ void SubtargetEmitter::EmitStageAndOperandCycleData(raw_ostream &OS, // // EmitProcessorData - Generate data for processor itineraries. // -void SubtargetEmitter::EmitProcessorData(raw_ostream &OS, - std::vector<std::vector<InstrItinerary> > &ProcList) { +void SubtargetEmitter:: +EmitProcessorData(raw_ostream &OS, + std::vector<Record*> &ItinClassList, + std::vector<std::vector<InstrItinerary> > &ProcList) { // Get an iterator for processor itinerary stages std::vector<std::vector<InstrItinerary> >::iterator ProcListIter = ProcList.begin(); - + // For each processor itinerary std::vector<Record*> Itins = Records.getAllDerivedDefinitions("ProcessorItineraries"); @@ -476,35 +485,36 @@ void SubtargetEmitter::EmitProcessorData(raw_ostream &OS, // Get processor itinerary name const std::string &Name = Itin->getName(); - + // Skip default if (Name == "NoItineraries") continue; // Begin processor itinerary table OS << "\n"; OS << "static const llvm::InstrItinerary " << Name << "[] = {\n"; - + // For each itinerary class std::vector<InstrItinerary> &ItinList = *ProcListIter++; + assert(ItinList.size() == ItinClassList.size() && "bad itinerary"); for (unsigned j = 0, M = ItinList.size(); j < M; ++j) { InstrItinerary &Intinerary = ItinList[j]; - - // Emit in the form of + + // Emit in the form of // { firstStage, lastStage, firstCycle, lastCycle } // index if (Intinerary.FirstStage == 0) { OS << " { 1, 0, 0, 0, 0 }"; } else { OS << " { " << Intinerary.NumMicroOps << ", " << - Intinerary.FirstStage << ", " << - Intinerary.LastStage << ", " << - Intinerary.FirstOperandCycle << ", " << + Intinerary.FirstStage << ", " << + Intinerary.LastStage << ", " << + Intinerary.FirstOperandCycle << ", " << Intinerary.LastOperandCycle << " }"; } - - OS << ", // " << j << "\n"; + + OS << ", // " << j << " " << ItinClassList[j]->getName() << "\n"; } - + // End processor itinerary table OS << " { 1, ~0U, ~0U, ~0U, ~0U } // end marker\n"; OS << "};\n"; @@ -524,7 +534,7 @@ void SubtargetEmitter::EmitProcessorLookup(raw_ostream &OS) { OS << "\n"; OS << "// Sorted (by key) array of itineraries for CPU subtype.\n" << "static const llvm::SubtargetInfoKV ProcItinKV[] = {\n"; - + // For each processor for (unsigned i = 0, N = ProcessorList.size(); i < N;) { // Next processor @@ -533,20 +543,20 @@ void SubtargetEmitter::EmitProcessorLookup(raw_ostream &OS) { const std::string &Name = Processor->getValueAsString("Name"); const std::string &ProcItin = Processor->getValueAsDef("ProcItin")->getName(); - + // Emit as { "cpu", procinit }, OS << " { " << "\"" << Name << "\", " << "(void *)&" << ProcItin; - + OS << " }"; - + // Depending on ''if more in the list'' emit comma if (++i < N) OS << ","; - + OS << "\n"; } - + // End processor table OS << "};\n"; @@ -566,20 +576,20 @@ void SubtargetEmitter::EmitData(raw_ostream &OS) { std::vector<Record*> ItinClassList = Records.getAllDerivedDefinitions("InstrItinClass"); std::sort(ItinClassList.begin(), ItinClassList.end(), LessRecord()); - + // Enumerate all the itinerary classes unsigned NItinClasses = CollectAllItinClasses(OS, ItinClassesMap, ItinClassList); // Make sure the rest is worth the effort HasItineraries = NItinClasses != 1; // Ignore NoItinerary. - + if (HasItineraries) { std::vector<std::vector<InstrItinerary> > ProcList; // Emit the stage data EmitStageAndOperandCycleData(OS, NItinClasses, ItinClassesMap, ItinClassList, ProcList); // Emit the processor itinerary data - EmitProcessorData(OS, ProcList); + EmitProcessorData(OS, ItinClassList, ProcList); // Emit the processor lookup data EmitProcessorLookup(OS); } @@ -594,8 +604,8 @@ void SubtargetEmitter::ParseFeaturesFunction(raw_ostream &OS) { Records.getAllDerivedDefinitions("SubtargetFeature"); std::sort(Features.begin(), Features.end(), LessRecord()); - OS << "// ParseSubtargetFeatures - Parses features string setting specified\n" - << "// subtarget options.\n" + OS << "// ParseSubtargetFeatures - Parses features string setting specified\n" + << "// subtarget options.\n" << "std::string llvm::"; OS << Target; OS << "Subtarget::ParseSubtargetFeatures(const std::string &FS,\n" @@ -604,7 +614,7 @@ void SubtargetEmitter::ParseFeaturesFunction(raw_ostream &OS) { << " DEBUG(dbgs() << \"\\nCPU:\" << CPU);\n" << " SubtargetFeatures Features(FS);\n" << " Features.setCPUIfNone(CPU);\n" - << " uint32_t Bits = Features.getBits(SubTypeKV, SubTypeKVSize,\n" + << " uint64_t Bits = Features.getBits(SubTypeKV, SubTypeKVSize,\n" << " FeatureKV, FeatureKVSize);\n"; for (unsigned i = 0; i < Features.size(); i++) { @@ -618,7 +628,7 @@ void SubtargetEmitter::ParseFeaturesFunction(raw_ostream &OS) { OS << " if ((Bits & " << Instance << ") != 0) " << Attribute << " = " << Value << ";\n"; else - OS << " if ((Bits & " << Instance << ") != 0 && " << Attribute << + OS << " if ((Bits & " << Instance << ") != 0 && " << Attribute << " < " << Value << ") " << Attribute << " = " << Value << ";\n"; } diff --git a/utils/TableGen/SubtargetEmitter.h b/utils/TableGen/SubtargetEmitter.h index 3abec3b..93055b7 100644 --- a/utils/TableGen/SubtargetEmitter.h +++ b/utils/TableGen/SubtargetEmitter.h @@ -24,11 +24,11 @@ namespace llvm { class SubtargetEmitter : public TableGenBackend { - + RecordKeeper &Records; std::string Target; bool HasItineraries; - + void Enumeration(raw_ostream &OS, const char *ClassName, bool isBits); void FeatureKeyValues(raw_ostream &OS); void CPUKeyValues(raw_ostream &OS); @@ -48,11 +48,12 @@ class SubtargetEmitter : public TableGenBackend { std::vector<Record*> &ItinClassList, std::vector<std::vector<InstrItinerary> > &ProcList); void EmitProcessorData(raw_ostream &OS, - std::vector<std::vector<InstrItinerary> > &ProcList); + std::vector<Record*> &ItinClassList, + std::vector<std::vector<InstrItinerary> > &ProcList); void EmitProcessorLookup(raw_ostream &OS); void EmitData(raw_ostream &OS); void ParseFeaturesFunction(raw_ostream &OS); - + public: SubtargetEmitter(RecordKeeper &R) : Records(R), HasItineraries(false) {} diff --git a/utils/TableGen/TGLexer.h b/utils/TableGen/TGLexer.h index 55a6c5d..e1aa5a7 100644 --- a/utils/TableGen/TGLexer.h +++ b/utils/TableGen/TGLexer.h @@ -15,7 +15,6 @@ #define TGLEXER_H #include "llvm/Support/DataTypes.h" -#include <vector> #include <string> #include <cassert> @@ -36,7 +35,7 @@ namespace tgtok { l_brace, r_brace, // { } l_paren, r_paren, // ( ) less, greater, // < > - colon, semi, // ; : + colon, semi, // : ; comma, period, // , . equal, question, // = ? diff --git a/utils/TableGen/TGParser.cpp b/utils/TableGen/TGParser.cpp index f6041be..59097f9 100644 --- a/utils/TableGen/TGParser.cpp +++ b/utils/TableGen/TGParser.cpp @@ -1153,6 +1153,7 @@ Init *TGParser::ParseSimpleValue(Record *CurRec, RecTy *ItemType) { s << "Type mismatch for list, expected list type, got " << ItemType->getAsString(); TokError(s.str()); + return 0; } GivenListTy = ListType; } diff --git a/utils/TableGen/TGValueTypes.cpp b/utils/TableGen/TGValueTypes.cpp index 122d085..af0d9f4 100644 --- a/utils/TableGen/TGValueTypes.cpp +++ b/utils/TableGen/TGValueTypes.cpp @@ -16,7 +16,6 @@ #include "llvm/CodeGen/ValueTypes.h" #include <map> -#include <vector> using namespace llvm; namespace llvm { diff --git a/utils/TableGen/TableGen.cpp b/utils/TableGen/TableGen.cpp index 3b7dc01..aa92302 100644 --- a/utils/TableGen/TableGen.cpp +++ b/utils/TableGen/TableGen.cpp @@ -65,6 +65,7 @@ enum ActionType { GenClangAttrSpellingList, GenClangDiagsDefs, GenClangDiagGroups, + GenClangDiagsIndexName, GenClangDeclNodes, GenClangStmtNodes, GenClangSACheckers, @@ -133,12 +134,16 @@ namespace { "Generate clang PCH attribute reader"), clEnumValN(GenClangAttrPCHWrite, "gen-clang-attr-pch-write", "Generate clang PCH attribute writer"), - clEnumValN(GenClangAttrSpellingList, "gen-clang-attr-spelling-list", + clEnumValN(GenClangAttrSpellingList, + "gen-clang-attr-spelling-list", "Generate a clang attribute spelling list"), clEnumValN(GenClangDiagsDefs, "gen-clang-diags-defs", "Generate Clang diagnostics definitions"), clEnumValN(GenClangDiagGroups, "gen-clang-diag-groups", "Generate Clang diagnostic groups"), + clEnumValN(GenClangDiagsIndexName, + "gen-clang-diags-index-name", + "Generate Clang diagnostic name index"), clEnumValN(GenClangDeclNodes, "gen-clang-decl-nodes", "Generate Clang AST declaration nodes"), clEnumValN(GenClangStmtNodes, "gen-clang-stmt-nodes", @@ -295,6 +300,9 @@ int main(int argc, char **argv) { case GenClangDiagGroups: ClangDiagGroupsEmitter(Records).run(Out.os()); break; + case GenClangDiagsIndexName: + ClangDiagsIndexNameEmitter(Records).run(Out.os()); + break; case GenClangDeclNodes: ClangASTNodesEmitter(Records, "Decl", "Decl").run(Out.os()); ClangDeclContextEmitter(Records).run(Out.os()); diff --git a/utils/TableGen/X86DisassemblerTables.cpp b/utils/TableGen/X86DisassemblerTables.cpp index 94797f5..7431059 100644 --- a/utils/TableGen/X86DisassemblerTables.cpp +++ b/utils/TableGen/X86DisassemblerTables.cpp @@ -18,6 +18,7 @@ #include "X86DisassemblerTables.h" #include "TableGenBackend.h" +#include "llvm/ADT/STLExtras.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/Format.h" @@ -46,9 +47,11 @@ static inline bool inheritsFrom(InstructionContext child, case IC_OPSIZE: return(inheritsFrom(child, IC_64BIT_OPSIZE)); case IC_XD: - return(inheritsFrom(child, IC_64BIT_XD)); + return(inheritsFrom(child, IC_64BIT_XD) || + inheritsFrom(child, IC_VEX_XD)); case IC_XS: - return(inheritsFrom(child, IC_64BIT_XS)); + return(inheritsFrom(child, IC_64BIT_XS) || + inheritsFrom(child, IC_VEX_XS)); case IC_64BIT_REXW: return(inheritsFrom(child, IC_64BIT_REXW_XS) || inheritsFrom(child, IC_64BIT_REXW_XD) || @@ -65,6 +68,35 @@ static inline bool inheritsFrom(InstructionContext child, return false; case IC_64BIT_REXW_OPSIZE: return false; + case IC_VEX: + return(inheritsFrom(child, IC_VEX_XS) || + inheritsFrom(child, IC_VEX_XD) || + inheritsFrom(child, IC_VEX_L) || + inheritsFrom(child, IC_VEX_W) || + inheritsFrom(child, IC_VEX_OPSIZE)); + case IC_VEX_XS: + return(inheritsFrom(child, IC_VEX_L_XS) || + inheritsFrom(child, IC_VEX_W_XS)); + case IC_VEX_XD: + return(inheritsFrom(child, IC_VEX_L_XD) || + inheritsFrom(child, IC_VEX_W_XD)); + case IC_VEX_L: + return(inheritsFrom(child, IC_VEX_L_XS) || + inheritsFrom(child, IC_VEX_L_XD)); + case IC_VEX_L_XS: + return false; + case IC_VEX_L_XD: + return false; + case IC_VEX_W: + return(inheritsFrom(child, IC_VEX_W_XS) || + inheritsFrom(child, IC_VEX_W_XD) || + inheritsFrom(child, IC_VEX_W_OPSIZE)); + case IC_VEX_W_XS: + return false; + case IC_VEX_W_XD: + return false; + case IC_VEX_OPSIZE: + return inheritsFrom(child, IC_VEX_W_OPSIZE); default: return false; } @@ -236,7 +268,7 @@ static const char* stringForModifierType(ModifierType mt) DisassemblerTables::DisassemblerTables() { unsigned i; - for (i = 0; i < 4; i++) { + for (i = 0; i < array_lengthof(Tables); i++) { Tables[i] = new ContextDecision; memset(Tables[i], 0, sizeof(ContextDecision)); } @@ -247,7 +279,7 @@ DisassemblerTables::DisassemblerTables() { DisassemblerTables::~DisassemblerTables() { unsigned i; - for (i = 0; i < 4; i++) + for (i = 0; i < array_lengthof(Tables); i++) delete Tables[i]; } @@ -461,7 +493,29 @@ void DisassemblerTables::emitContextTable(raw_ostream &o, uint32_t &i) const { for (index = 0; index < 256; ++index) { o.indent(i * 2); - if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XS)) + if ((index & ATTR_VEXL) && (index & ATTR_OPSIZE)) + o << "IC_VEX_L_OPSIZE"; + else if ((index & ATTR_VEXL) && (index & ATTR_XD)) + o << "IC_VEX_L_XD"; + else if ((index & ATTR_VEXL) && (index & ATTR_XS)) + o << "IC_VEX_L_XS"; + else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_OPSIZE)) + o << "IC_VEX_W_OPSIZE"; + else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XD)) + o << "IC_VEX_W_XD"; + else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XS)) + o << "IC_VEX_W_XS"; + else if (index & ATTR_VEXL) + o << "IC_VEX_L"; + else if ((index & ATTR_VEX) && (index & ATTR_REXW)) + o << "IC_VEX_W"; + else if ((index & ATTR_VEX) && (index & ATTR_OPSIZE)) + o << "IC_VEX_OPSIZE"; + else if ((index & ATTR_VEX) && (index & ATTR_XD)) + o << "IC_VEX_XD"; + else if ((index & ATTR_VEX) && (index & ATTR_XS)) + o << "IC_VEX_XS"; + else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XS)) o << "IC_64BIT_REXW_XS"; else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XD)) o << "IC_64BIT_REXW_XD"; @@ -484,6 +538,8 @@ void DisassemblerTables::emitContextTable(raw_ostream &o, uint32_t &i) const { o << "IC_XD"; else if (index & ATTR_OPSIZE) o << "IC_OPSIZE"; + else if (index & ATTR_VEX) + o << "IC_VEX"; else o << "IC"; @@ -510,6 +566,8 @@ void DisassemblerTables::emitContextDecisions(raw_ostream &o1, emitContextDecision(o1, o2, i1, i2, *Tables[1], TWOBYTE_STR); emitContextDecision(o1, o2, i1, i2, *Tables[2], THREEBYTE38_STR); emitContextDecision(o1, o2, i1, i2, *Tables[3], THREEBYTE3A_STR); + emitContextDecision(o1, o2, i1, i2, *Tables[4], THREEBYTEA6_STR); + emitContextDecision(o1, o2, i1, i2, *Tables[5], THREEBYTEA7_STR); } void DisassemblerTables::emit(raw_ostream &o) const { diff --git a/utils/TableGen/X86DisassemblerTables.h b/utils/TableGen/X86DisassemblerTables.h index 08eba01..d16ebfc 100644 --- a/utils/TableGen/X86DisassemblerTables.h +++ b/utils/TableGen/X86DisassemblerTables.h @@ -39,7 +39,9 @@ private: /// [1] two-byte opcodes of the form 0f __ /// [2] three-byte opcodes of the form 0f 38 __ /// [3] three-byte opcodes of the form 0f 3a __ - ContextDecision* Tables[4]; + /// [4] three-byte opcodes of the form 0f a6 __ + /// [5] three-byte opcodes of the form 0f a7 __ + ContextDecision* Tables[6]; /// The instruction information table std::vector<InstructionSpecifier> InstructionSpecifiers; @@ -77,7 +79,7 @@ private: /// regardless of ModR/M byte, two entries - one for bytes 0x00-0xbf and one /// for bytes 0xc0-0xff -, or 256 entries, one for each possible byte. /// nnnn is the number of a table for looking up these values. The tables - /// are writen separately so that tables consisting entirely of zeros will + /// are written separately so that tables consisting entirely of zeros will /// not be duplicated. (These all have the name modRMEmptyTable.) A table /// is printed as: /// @@ -141,8 +143,9 @@ private: /// } /// } /// - /// NAME is the name of the ContextDecision (typically one of the four names - /// ONEBYTE_SYM, TWOBYTE_SYM, THREEBYTE38_SYM, and THREEBYTE3A_SYM from + /// NAME is the name of the ContextDecision (typically one of the four names + /// ONEBYTE_SYM, TWOBYTE_SYM, THREEBYTE38_SYM, THREEBYTE3A_SYM, + /// THREEBYTEA6_SYM, and THREEBYTEA7_SYM from /// X86DisassemblerDecoderCommon.h). /// IC is one of the contexts in InstructionContext. There is an opcode /// decision for each possible context. diff --git a/utils/TableGen/X86RecognizableInstr.cpp b/utils/TableGen/X86RecognizableInstr.cpp index b0839c3..f7518a9 100644 --- a/utils/TableGen/X86RecognizableInstr.cpp +++ b/utils/TableGen/X86RecognizableInstr.cpp @@ -68,7 +68,7 @@ namespace X86Local { DC = 7, DD = 8, DE = 9, DF = 10, XD = 11, XS = 12, T8 = 13, P_TA = 14, - P_0F_AE = 16, P_0F_01 = 17 + A6 = 15, A7 = 16 }; } @@ -214,7 +214,9 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables, HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix"); HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix"); + HasVEXPrefix = Rec->getValueAsBit("hasVEXPrefix"); HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix"); + HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix"); HasLockPrefix = Rec->getValueAsBit("hasLockPrefix"); IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly"); @@ -224,7 +226,8 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables, Operands = &insn.Operands.OperandList; IsSSE = HasOpSizePrefix && (Name.find("16") == Name.npos); - HasFROperands = false; + HasFROperands = hasFROperands(); + HasVEX_LPrefix = has256BitOperands() || Rec->getValueAsBit("hasVEX_L"); ShouldBeEmitted = true; } @@ -248,7 +251,32 @@ void RecognizableInstr::processInstr(DisassemblerTables &tables, InstructionContext RecognizableInstr::insnContext() const { InstructionContext insnContext; - if (Name.find("64") != Name.npos || HasREX_WPrefix) { + if (HasVEX_4VPrefix || HasVEXPrefix) { + if (HasOpSizePrefix && HasVEX_LPrefix) + insnContext = IC_VEX_L_OPSIZE; + else if (HasOpSizePrefix && HasVEX_WPrefix) + insnContext = IC_VEX_W_OPSIZE; + else if (HasOpSizePrefix) + insnContext = IC_VEX_OPSIZE; + else if (HasVEX_LPrefix && Prefix == X86Local::XS) + insnContext = IC_VEX_L_XS; + else if (HasVEX_LPrefix && Prefix == X86Local::XD) + insnContext = IC_VEX_L_XD; + else if (HasVEX_WPrefix && Prefix == X86Local::XS) + insnContext = IC_VEX_W_XS; + else if (HasVEX_WPrefix && Prefix == X86Local::XD) + insnContext = IC_VEX_W_XD; + else if (HasVEX_WPrefix) + insnContext = IC_VEX_W; + else if (HasVEX_LPrefix) + insnContext = IC_VEX_L; + else if (Prefix == X86Local::XD) + insnContext = IC_VEX_XD; + else if (Prefix == X86Local::XS) + insnContext = IC_VEX_XS; + else + insnContext = IC_VEX; + } else if (Name.find("64") != Name.npos || HasREX_WPrefix) { if (HasREX_WPrefix && HasOpSizePrefix) insnContext = IC_64BIT_REXW_OPSIZE; else if (HasOpSizePrefix) @@ -280,6 +308,10 @@ InstructionContext RecognizableInstr::insnContext() const { } RecognizableInstr::filter_ret RecognizableInstr::filter() const { + /////////////////// + // FILTER_STRONG + // + // Filter out intrinsics if (!Rec->isSubClassOf("X86Inst")) @@ -291,26 +323,71 @@ RecognizableInstr::filter_ret RecognizableInstr::filter() const { if (Form == X86Local::MRMInitReg) return FILTER_STRONG; + + + // TEMPORARY pending bug fixes - + if (Name.find("VMOVDQU") != Name.npos || + Name.find("VMOVDQA") != Name.npos || + Name.find("VROUND") != Name.npos) + return FILTER_STRONG; + + // Filter out artificial instructions + + if (Name.find("TAILJMP") != Name.npos || + Name.find("_Int") != Name.npos || + Name.find("_int") != Name.npos || + Name.find("Int_") != Name.npos || + Name.find("_NOREX") != Name.npos || + Name.find("_TC") != Name.npos || + Name.find("EH_RETURN") != Name.npos || + Name.find("V_SET") != Name.npos || + Name.find("LOCK_") != Name.npos || + Name.find("WIN") != Name.npos || + Name.find("_AVX") != Name.npos || + Name.find("2SDL") != Name.npos) + return FILTER_STRONG; + + // Filter out instructions with segment override prefixes. + // They're too messy to handle now and we'll special case them if needed. + + if (SegOvr) + return FILTER_STRONG; + + // Filter out instructions that can't be printed. + + if (AsmString.size() == 0) + return FILTER_STRONG; + + // Filter out instructions with subreg operands. + + if (AsmString.find("subreg") != AsmString.npos) + return FILTER_STRONG; + + ///////////////// + // FILTER_WEAK + // + + // Filter out instructions with a LOCK prefix; // prefer forms that do not have the prefix if (HasLockPrefix) return FILTER_WEAK; - - // Filter out artificial instructions - if (Name.find("TAILJMP") != Name.npos || - Name.find("_Int") != Name.npos || - Name.find("_int") != Name.npos || - Name.find("Int_") != Name.npos || - Name.find("_NOREX") != Name.npos || - Name.find("_TC") != Name.npos || - Name.find("EH_RETURN") != Name.npos || - Name.find("V_SET") != Name.npos || - Name.find("LOCK_") != Name.npos || - Name.find("WIN") != Name.npos) - return FILTER_STRONG; + // Filter out alternate forms of AVX instructions + if (Name.find("_alt") != Name.npos || + Name.find("XrYr") != Name.npos || + Name.find("r64r") != Name.npos || + Name.find("_64mr") != Name.npos || + Name.find("Xrr") != Name.npos || + Name.find("rr64") != Name.npos) + return FILTER_WEAK; + + if (Name == "VMASKMOVDQU64" || + Name == "VEXTRACTPSrr64" || + Name == "VMOVQd64rr" || + Name == "VMOVQs64rr") + return FILTER_WEAK; // Special cases. @@ -339,6 +416,7 @@ RecognizableInstr::filter_ret RecognizableInstr::filter() const { Name == "PUSH32i16" || Name == "PUSH64i16" || Name == "MOVPQI2QImr" || + Name == "VMOVPQI2QImr" || Name == "MOVSDmr" || Name == "MOVSDrm" || Name == "MOVSSmr" || @@ -349,22 +427,6 @@ RecognizableInstr::filter_ret RecognizableInstr::filter() const { Name == "CRC32r16") return FILTER_WEAK; - // Filter out instructions with segment override prefixes. - // They're too messy to handle now and we'll special case them if needed. - - if (SegOvr) - return FILTER_STRONG; - - // Filter out instructions that can't be printed. - - if (AsmString.size() == 0) - return FILTER_STRONG; - - // Filter out instructions with subreg operands. - - if (AsmString.find("subreg") != AsmString.npos) - return FILTER_STRONG; - if (HasFROperands && Name.find("MOV") != Name.npos && ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) || (Name.find("to") != Name.npos))) @@ -372,6 +434,33 @@ RecognizableInstr::filter_ret RecognizableInstr::filter() const { return FILTER_NORMAL; } + +bool RecognizableInstr::hasFROperands() const { + const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands; + unsigned numOperands = OperandList.size(); + + for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) { + const std::string &recName = OperandList[operandIndex].Rec->getName(); + + if (recName.find("FR") != recName.npos) + return true; + } + return false; +} + +bool RecognizableInstr::has256BitOperands() const { + const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands; + unsigned numOperands = OperandList.size(); + + for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) { + const std::string &recName = OperandList[operandIndex].Rec->getName(); + + if (!recName.compare("VR256") || !recName.compare("f256mem")) { + return true; + } + } + return false; +} void RecognizableInstr::handleOperand( bool optional, @@ -395,13 +484,13 @@ void RecognizableInstr::handleOperand( } const std::string &typeName = (*Operands)[operandIndex].Rec->getName(); - + Spec->operands[operandIndex].encoding = encodingFromString(typeName, HasOpSizePrefix); Spec->operands[operandIndex].type = typeFromString(typeName, - IsSSE, - HasREX_WPrefix, - HasOpSizePrefix); + IsSSE, + HasREX_WPrefix, + HasOpSizePrefix); ++operandIndex; ++physicalOperandIndex; @@ -530,31 +619,45 @@ void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) { case X86Local::MRMSrcReg: // Operand 1 is a register operand in the Reg/Opcode field. // Operand 2 is a register operand in the R/M field. + // - In AVX, there is a register operand in the VEX.vvvv field here - // Operand 3 (optional) is an immediate. - assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && - "Unexpected number of operands for MRMSrcRegFrm"); - HANDLE_OPERAND(roRegister) - HANDLE_OPERAND(rmRegister) if (HasVEX_4VPrefix) + assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 && + "Unexpected number of operands for MRMSrcRegFrm with VEX_4V"); + else + assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && + "Unexpected number of operands for MRMSrcRegFrm"); + + HANDLE_OPERAND(roRegister) + + if (HasVEX_4VPrefix) // FIXME: In AVX, the register below becomes the one encoded // in ModRMVEX and the one above the one in the VEX.VVVV field - HANDLE_OPTIONAL(rmRegister) - else - HANDLE_OPTIONAL(immediate) + HANDLE_OPERAND(vvvvRegister) + + HANDLE_OPERAND(rmRegister) + HANDLE_OPTIONAL(immediate) break; case X86Local::MRMSrcMem: // Operand 1 is a register operand in the Reg/Opcode field. // Operand 2 is a memory operand (possibly SIB-extended) + // - In AVX, there is a register operand in the VEX.vvvv field here - // Operand 3 (optional) is an immediate. - assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && - "Unexpected number of operands for MRMSrcMemFrm"); + + if (HasVEX_4VPrefix) + assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 && + "Unexpected number of operands for MRMSrcMemFrm with VEX_4V"); + else + assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && + "Unexpected number of operands for MRMSrcMemFrm"); + HANDLE_OPERAND(roRegister) if (HasVEX_4VPrefix) // FIXME: In AVX, the register below becomes the one encoded // in ModRMVEX and the one above the one in the VEX.VVVV field - HANDLE_OPTIONAL(rmRegister) + HANDLE_OPERAND(vvvvRegister) HANDLE_OPERAND(memory) HANDLE_OPTIONAL(immediate) @@ -569,8 +672,14 @@ void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) { case X86Local::MRM7r: // Operand 1 is a register operand in the R/M field. // Operand 2 (optional) is an immediate or relocation. - assert(numPhysicalOperands <= 2 && - "Unexpected number of operands for MRMnRFrm"); + if (HasVEX_4VPrefix) + assert(numPhysicalOperands <= 3 && + "Unexpected number of operands for MRMSrcMemFrm with VEX_4V"); + else + assert(numPhysicalOperands <= 2 && + "Unexpected number of operands for MRMnRFrm"); + if (HasVEX_4VPrefix) + HANDLE_OPERAND(vvvvRegister); HANDLE_OPTIONAL(rmRegister) HANDLE_OPTIONAL(relocation) break; @@ -687,6 +796,22 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { filter = new DumbFilter(); opcodeToSet = Opcode; break; + case X86Local::A6: + opcodeType = THREEBYTE_A6; + if (needsModRMForDecode(Form)) + filter = new ModFilter(isRegFormat(Form)); + else + filter = new DumbFilter(); + opcodeToSet = Opcode; + break; + case X86Local::A7: + opcodeType = THREEBYTE_A7; + if (needsModRMForDecode(Form)) + filter = new ModFilter(isRegFormat(Form)); + else + filter = new DumbFilter(); + opcodeToSet = Opcode; + break; case X86Local::D8: case X86Local::D9: case X86Local::DA: @@ -854,6 +979,7 @@ OperandType RecognizableInstr::typeFromString(const std::string &s, TYPE("ssmem", TYPE_M32FP) TYPE("RST", TYPE_ST) TYPE("i128mem", TYPE_M128) + TYPE("i256mem", TYPE_M256) TYPE("i64i32imm_pcrel", TYPE_REL64) TYPE("i16imm_pcrel", TYPE_REL16) TYPE("i32imm_pcrel", TYPE_REL32) @@ -878,6 +1004,7 @@ OperandType RecognizableInstr::typeFromString(const std::string &s, TYPE("offset16", TYPE_MOFFS16) TYPE("offset32", TYPE_MOFFS32) TYPE("offset64", TYPE_MOFFS64) + TYPE("VR256", TYPE_XMM256) errs() << "Unhandled type string " << s << "\n"; llvm_unreachable("Unhandled type string"); } @@ -900,6 +1027,10 @@ OperandEncoding RecognizableInstr::immediateEncodingFromString ENCODING("i64i32imm", ENCODING_ID) ENCODING("i64i8imm", ENCODING_IB) ENCODING("i8imm", ENCODING_IB) + // This is not a typo. Instructions like BLENDVPD put + // register IDs in 8-bit immediates nowadays. + ENCODING("VR256", ENCODING_IB) + ENCODING("VR128", ENCODING_IB) errs() << "Unhandled immediate encoding " << s << "\n"; llvm_unreachable("Unhandled immediate encoding"); } @@ -915,6 +1046,7 @@ OperandEncoding RecognizableInstr::rmRegisterEncodingFromString ENCODING("FR64", ENCODING_RM) ENCODING("FR32", ENCODING_RM) ENCODING("VR64", ENCODING_RM) + ENCODING("VR256", ENCODING_RM) errs() << "Unhandled R/M register encoding " << s << "\n"; llvm_unreachable("Unhandled R/M register encoding"); } @@ -933,10 +1065,22 @@ OperandEncoding RecognizableInstr::roRegisterEncodingFromString ENCODING("SEGMENT_REG", ENCODING_REG) ENCODING("DEBUG_REG", ENCODING_REG) ENCODING("CONTROL_REG", ENCODING_REG) + ENCODING("VR256", ENCODING_REG) errs() << "Unhandled reg/opcode register encoding " << s << "\n"; llvm_unreachable("Unhandled reg/opcode register encoding"); } +OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString + (const std::string &s, + bool hasOpSizePrefix) { + ENCODING("FR32", ENCODING_VVVV) + ENCODING("FR64", ENCODING_VVVV) + ENCODING("VR128", ENCODING_VVVV) + ENCODING("VR256", ENCODING_VVVV) + errs() << "Unhandled VEX.vvvv register encoding " << s << "\n"; + llvm_unreachable("Unhandled VEX.vvvv register encoding"); +} + OperandEncoding RecognizableInstr::memoryEncodingFromString (const std::string &s, bool hasOpSizePrefix) { @@ -951,6 +1095,7 @@ OperandEncoding RecognizableInstr::memoryEncodingFromString ENCODING("f64mem", ENCODING_RM) ENCODING("f32mem", ENCODING_RM) ENCODING("i128mem", ENCODING_RM) + ENCODING("i256mem", ENCODING_RM) ENCODING("f80mem", ENCODING_RM) ENCODING("lea32mem", ENCODING_RM) ENCODING("lea64_32mem", ENCODING_RM) diff --git a/utils/TableGen/X86RecognizableInstr.h b/utils/TableGen/X86RecognizableInstr.h index c043b90..c7ec18c 100644 --- a/utils/TableGen/X86RecognizableInstr.h +++ b/utils/TableGen/X86RecognizableInstr.h @@ -52,8 +52,14 @@ private: bool HasOpSizePrefix; /// The hasREX_WPrefix field from the record bool HasREX_WPrefix; + /// The hasVEXPrefix field from the record + bool HasVEXPrefix; /// The hasVEX_4VPrefix field from the record bool HasVEX_4VPrefix; + /// The hasVEX_WPrefix field from the record + bool HasVEX_WPrefix; + /// Inferred from the operands; indicates whether the L bit in the VEX prefix is set + bool HasVEX_LPrefix; /// The hasLockPrefix field from the record bool HasLockPrefix; /// The isCodeGenOnly filed from the record @@ -96,7 +102,7 @@ private: // error if it conflcits with any other FILTER_NORMAL // instruction }; - + /// filter - Determines whether the instruction should be decodable. Some /// instructions are pure intrinsics and use unencodable operands; many /// synthetic instructions are duplicates of other instructions; other @@ -106,6 +112,12 @@ private: /// /// @return - The degree of filtering to be applied (see filter_ret). filter_ret filter() const; + + /// hasFROperands - Returns true if any operand is a FR operand. + bool hasFROperands() const; + + /// has256BitOperands - Returns true if any operand is a 256-bit SSE operand. + bool has256BitOperands() const; /// typeFromString - Translates an operand type from the string provided in /// the LLVM tables to an OperandType for use in the operand specifier. @@ -155,6 +167,8 @@ private: bool hasOpSizePrefix); static OperandEncoding opcodeModifierEncodingFromString(const std::string &s, bool hasOpSizePrefix); + static OperandEncoding vvvvRegisterEncodingFromString(const std::string &s, + bool HasOpSizePrefix); /// handleOperand - Converts a single operand from the LLVM table format to /// the emitted table format, handling any duplicate operands it encounters |
