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Diffstat (limited to 'usr.bin/clang/lli/lli.1')
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diff --git a/usr.bin/clang/lli/lli.1 b/usr.bin/clang/lli/lli.1 new file mode 100644 index 0000000..f90a652 --- /dev/null +++ b/usr.bin/clang/lli/lli.1 @@ -0,0 +1,310 @@ +.\" $FreeBSD$ +.\" Automatically generated by Pod::Man 2.23 (Pod::Simple 3.14) +.\" +.\" Standard preamble: +.\" ======================================================================== +.de Sp \" Vertical space (when we can't use .PP) +.if t .sp .5v +.if n .sp +.. +.de Vb \" Begin verbatim text +.ft CW +.nf +.ne \\$1 +.. +.de Ve \" End verbatim text +.ft R +.fi +.. +.\" Set up some character translations and predefined strings. \*(-- will +.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left +.\" double quote, and \*(R" will give a right double quote. \*(C+ will +.\" give a nicer C++. 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Always turn off hyphenation; it makes +.\" way too many mistakes in technical documents. +.if n .ad l +.nh +.SH "NAME" +lli \- directly execute programs from LLVM bitcode +.SH "SYNOPSIS" +.IX Header "SYNOPSIS" +\&\fBlli\fR [\fIoptions\fR] [\fIfilename\fR] [\fIprogram args\fR] +.SH "DESCRIPTION" +.IX Header "DESCRIPTION" +\&\fBlli\fR directly executes programs in \s-1LLVM\s0 bitcode format. It takes a program +in \s-1LLVM\s0 bitcode format and executes it using a just-in-time compiler, if one is +available for the current architecture, or an interpreter. \fBlli\fR takes all of +the same code generator options as llc, but they are only effective when +\&\fBlli\fR is using the just-in-time compiler. +.PP +If \fIfilename\fR is not specified, then \fBlli\fR reads the \s-1LLVM\s0 bitcode for the +program from standard input. +.PP +The optional \fIargs\fR specified on the command line are passed to the program as +arguments. +.SH "GENERAL OPTIONS" +.IX Header "GENERAL OPTIONS" +.IP "\fB\-fake\-argv0\fR=\fIexecutable\fR" 4 +.IX Item "-fake-argv0=executable" +Override the \f(CW\*(C`argv[0]\*(C'\fR value passed into the executing program. +.IP "\fB\-force\-interpreter\fR=\fI{false,true}\fR" 4 +.IX Item "-force-interpreter={false,true}" +If set to true, use the interpreter even if a just-in-time compiler is available +for this architecture. Defaults to false. +.IP "\fB\-help\fR" 4 +.IX Item "-help" +Print a summary of command line options. +.IP "\fB\-load\fR=\fIpuginfilename\fR" 4 +.IX Item "-load=puginfilename" +Causes \fBlli\fR to load the plugin (shared object) named \fIpluginfilename\fR and use +it for optimization. +.IP "\fB\-stats\fR" 4 +.IX Item "-stats" +Print statistics from the code-generation passes. This is only meaningful for +the just-in-time compiler, at present. +.IP "\fB\-time\-passes\fR" 4 +.IX Item "-time-passes" +Record the amount of time needed for each code-generation pass and print it to +standard error. +.IP "\fB\-version\fR" 4 +.IX Item "-version" +Print out the version of \fBlli\fR and exit without doing anything else. +.SH "TARGET OPTIONS" +.IX Header "TARGET OPTIONS" +.IP "\fB\-mtriple\fR=\fItarget triple\fR" 4 +.IX Item "-mtriple=target triple" +Override the target triple specified in the input bitcode file with the +specified string. This may result in a crash if you pick an +architecture which is not compatible with the current system. +.IP "\fB\-march\fR=\fIarch\fR" 4 +.IX Item "-march=arch" +Specify the architecture for which to generate assembly, overriding the target +encoded in the bitcode file. See the output of \fBllc \-help\fR for a list of +valid architectures. By default this is inferred from the target triple or +autodetected to the current architecture. +.IP "\fB\-mcpu\fR=\fIcpuname\fR" 4 +.IX Item "-mcpu=cpuname" +Specify a specific chip in the current architecture to generate code for. +By default this is inferred from the target triple and autodetected to +the current architecture. For a list of available CPUs, use: +\&\fBllvm-as < /dev/null | llc \-march=xyz \-mcpu=help\fR +.IP "\fB\-mattr\fR=\fIa1,+a2,\-a3,...\fR" 4 +.IX Item "-mattr=a1,+a2,-a3,..." +Override or control specific attributes of the target, such as whether \s-1SIMD\s0 +operations are enabled or not. The default set of attributes is set by the +current \s-1CPU\s0. For a list of available attributes, use: +\&\fBllvm-as < /dev/null | llc \-march=xyz \-mattr=help\fR +.SH "FLOATING POINT OPTIONS" +.IX Header "FLOATING POINT OPTIONS" +.IP "\fB\-disable\-excess\-fp\-precision\fR" 4 +.IX Item "-disable-excess-fp-precision" +Disable optimizations that may increase floating point precision. +.IP "\fB\-enable\-no\-infs\-fp\-math\fR" 4 +.IX Item "-enable-no-infs-fp-math" +Enable optimizations that assume no Inf values. +.IP "\fB\-enable\-no\-nans\-fp\-math\fR" 4 +.IX Item "-enable-no-nans-fp-math" +Enable optimizations that assume no \s-1NAN\s0 values. +.IP "\fB\-enable\-unsafe\-fp\-math\fR" 4 +.IX Item "-enable-unsafe-fp-math" +Causes \fBlli\fR to enable optimizations that may decrease floating point +precision. +.IP "\fB\-soft\-float\fR" 4 +.IX Item "-soft-float" +Causes \fBlli\fR to generate software floating point library calls instead of +equivalent hardware instructions. +.SH "CODE GENERATION OPTIONS" +.IX Header "CODE GENERATION OPTIONS" +.IP "\fB\-code\-model\fR=\fImodel\fR" 4 +.IX Item "-code-model=model" +Choose the code model from: +.Sp +.Vb 5 +\& default: Target default code model +\& small: Small code model +\& kernel: Kernel code model +\& medium: Medium code model +\& large: Large code model +.Ve +.IP "\fB\-disable\-post\-RA\-scheduler\fR" 4 +.IX Item "-disable-post-RA-scheduler" +Disable scheduling after register allocation. +.IP "\fB\-disable\-spill\-fusing\fR" 4 +.IX Item "-disable-spill-fusing" +Disable fusing of spill code into instructions. +.IP "\fB\-enable\-correct\-eh\-support\fR" 4 +.IX Item "-enable-correct-eh-support" +Make the \-lowerinvoke pass insert expensive, but correct, \s-1EH\s0 code. +.IP "\fB\-jit\-enable\-eh\fR" 4 +.IX Item "-jit-enable-eh" +Exception handling should be enabled in the just-in-time compiler. +.IP "\fB\-join\-liveintervals\fR" 4 +.IX Item "-join-liveintervals" +Coalesce copies (default=true). +.IP "\fB\-nozero\-initialized\-in\-bss\fR Don't place zero-initialized symbols into the \s-1BSS\s0 section." 4 +.IX Item "-nozero-initialized-in-bss Don't place zero-initialized symbols into the BSS section." +.PD 0 +.IP "\fB\-pre\-RA\-sched\fR=\fIscheduler\fR" 4 +.IX Item "-pre-RA-sched=scheduler" +.PD +Instruction schedulers available (before register allocation): +.Sp +.Vb 7 +\& =default: Best scheduler for the target +\& =none: No scheduling: breadth first sequencing +\& =simple: Simple two pass scheduling: minimize critical path and maximize processor utilization +\& =simple\-noitin: Simple two pass scheduling: Same as simple except using generic latency +\& =list\-burr: Bottom\-up register reduction list scheduling +\& =list\-tdrr: Top\-down register reduction list scheduling +\& =list\-td: Top\-down list scheduler \-print\-machineinstrs \- Print generated machine code +.Ve +.IP "\fB\-regalloc\fR=\fIallocator\fR" 4 +.IX Item "-regalloc=allocator" +Register allocator to use (default=linearscan) +.Sp +.Vb 3 +\& =bigblock: Big\-block register allocator +\& =linearscan: linear scan register allocator =local \- local register allocator +\& =simple: simple register allocator +.Ve +.IP "\fB\-relocation\-model\fR=\fImodel\fR" 4 +.IX Item "-relocation-model=model" +Choose relocation model from: +.Sp +.Vb 3 +\& =default: Target default relocation model +\& =static: Non\-relocatable code =pic \- Fully relocatable, position independent code +\& =dynamic\-no\-pic: Relocatable external references, non\-relocatable code +.Ve +.IP "\fB\-spiller\fR" 4 +.IX Item "-spiller" +Spiller to use (default=local) +.Sp +.Vb 2 +\& =simple: simple spiller +\& =local: local spiller +.Ve +.IP "\fB\-x86\-asm\-syntax\fR=\fIsyntax\fR" 4 +.IX Item "-x86-asm-syntax=syntax" +Choose style of code to emit from X86 backend: +.Sp +.Vb 2 +\& =att: Emit AT&T\-style assembly +\& =intel: Emit Intel\-style assembly +.Ve +.SH "EXIT STATUS" +.IX Header "EXIT STATUS" +If \fBlli\fR fails to load the program, it will exit with an exit code of 1. +Otherwise, it will return the exit code of the program it executes. +.SH "SEE ALSO" +.IX Header "SEE ALSO" +llc +.SH "AUTHOR" +.IX Header "AUTHOR" +Maintained by the \s-1LLVM\s0 Team (<http://llvm.org/>). |
