diff options
Diffstat (limited to 'test')
368 files changed, 10356 insertions, 1794 deletions
diff --git a/test/Analysis/BasicAA/args-rets-allocas-loads.ll b/test/Analysis/BasicAA/args-rets-allocas-loads.ll new file mode 100644 index 0000000..5d3f67e --- /dev/null +++ b/test/Analysis/BasicAA/args-rets-allocas-loads.ll @@ -0,0 +1,310 @@ +; RUN: opt -aa-eval -print-all-alias-modref-info -disable-output < %s |& FileCheck %s + +declare void @callee(double* %callee_arg) +declare void @nocap_callee(double* nocapture %nocap_callee_arg) + +declare double* @normal_returner() +declare noalias double* @noalias_returner() + +define void @caller_a(double* %arg_a0, + double* %arg_a1, + double* noalias %noalias_arg_a0, + double* noalias %noalias_arg_a1, + double** %indirect_a0, + double** %indirect_a1) { + %loaded_a0 = load double** %indirect_a0 + %loaded_a1 = load double** %indirect_a1 + + %escape_alloca_a0 = alloca double + %escape_alloca_a1 = alloca double + %noescape_alloca_a0 = alloca double + %noescape_alloca_a1 = alloca double + + %normal_ret_a0 = call double* @normal_returner() + %normal_ret_a1 = call double* @normal_returner() + %noalias_ret_a0 = call double* @noalias_returner() + %noalias_ret_a1 = call double* @noalias_returner() + + call void @callee(double* %escape_alloca_a0) + call void @callee(double* %escape_alloca_a1) + call void @nocap_callee(double* %noescape_alloca_a0) + call void @nocap_callee(double* %noescape_alloca_a1) + + store double 0.0, double* %loaded_a0 + store double 0.0, double* %loaded_a1 + store double 0.0, double* %arg_a0 + store double 0.0, double* %arg_a1 + store double 0.0, double* %noalias_arg_a0 + store double 0.0, double* %noalias_arg_a1 + store double 0.0, double* %escape_alloca_a0 + store double 0.0, double* %escape_alloca_a1 + store double 0.0, double* %noescape_alloca_a0 + store double 0.0, double* %noescape_alloca_a1 + store double 0.0, double* %normal_ret_a0 + store double 0.0, double* %normal_ret_a1 + store double 0.0, double* %noalias_ret_a0 + store double 0.0, double* %noalias_ret_a1 + ret void +} + +; CHECK: Function: caller_a: 16 pointers, 8 call sites +; CHECK: MayAlias: double* %arg_a0, double* %arg_a1 +; CHECK: NoAlias: double* %arg_a0, double* %noalias_arg_a0 +; CHECK: NoAlias: double* %arg_a1, double* %noalias_arg_a0 +; CHECK: NoAlias: double* %arg_a0, double* %noalias_arg_a1 +; CHECK: NoAlias: double* %arg_a1, double* %noalias_arg_a1 +; CHECK: NoAlias: double* %noalias_arg_a0, double* %noalias_arg_a1 +; CHECK: MayAlias: double* %arg_a0, double** %indirect_a0 +; CHECK: MayAlias: double* %arg_a1, double** %indirect_a0 +; CHECK: NoAlias: double* %noalias_arg_a0, double** %indirect_a0 +; CHECK: NoAlias: double* %noalias_arg_a1, double** %indirect_a0 +; CHECK: MayAlias: double* %arg_a0, double** %indirect_a1 +; CHECK: MayAlias: double* %arg_a1, double** %indirect_a1 +; CHECK: NoAlias: double* %noalias_arg_a0, double** %indirect_a1 +; CHECK: NoAlias: double* %noalias_arg_a1, double** %indirect_a1 +; CHECK: MayAlias: double** %indirect_a0, double** %indirect_a1 +; CHECK: MayAlias: double* %arg_a0, double* %loaded_a0 +; CHECK: MayAlias: double* %arg_a1, double* %loaded_a0 +; CHECK: NoAlias: double* %loaded_a0, double* %noalias_arg_a0 +; CHECK: NoAlias: double* %loaded_a0, double* %noalias_arg_a1 +; CHECK: MayAlias: double* %loaded_a0, double** %indirect_a0 +; CHECK: MayAlias: double* %loaded_a0, double** %indirect_a1 +; CHECK: MayAlias: double* %arg_a0, double* %loaded_a1 +; CHECK: MayAlias: double* %arg_a1, double* %loaded_a1 +; CHECK: NoAlias: double* %loaded_a1, double* %noalias_arg_a0 +; CHECK: NoAlias: double* %loaded_a1, double* %noalias_arg_a1 +; CHECK: MayAlias: double* %loaded_a1, double** %indirect_a0 +; CHECK: MayAlias: double* %loaded_a1, double** %indirect_a1 +; CHECK: MayAlias: double* %loaded_a0, double* %loaded_a1 +; CHECK: NoAlias: double* %arg_a0, double* %escape_alloca_a0 +; CHECK: NoAlias: double* %arg_a1, double* %escape_alloca_a0 +; CHECK: NoAlias: double* %escape_alloca_a0, double* %noalias_arg_a0 +; CHECK: NoAlias: double* %escape_alloca_a0, double* %noalias_arg_a1 +; CHECK: NoAlias: double* %escape_alloca_a0, double** %indirect_a0 +; CHECK: NoAlias: double* %escape_alloca_a0, double** %indirect_a1 +; CHECK: MayAlias: double* %escape_alloca_a0, double* %loaded_a0 +; CHECK: MayAlias: double* %escape_alloca_a0, double* %loaded_a1 +; CHECK: NoAlias: double* %arg_a0, double* %escape_alloca_a1 +; CHECK: NoAlias: double* %arg_a1, double* %escape_alloca_a1 +; CHECK: NoAlias: double* %escape_alloca_a1, double* %noalias_arg_a0 +; CHECK: NoAlias: double* %escape_alloca_a1, double* %noalias_arg_a1 +; CHECK: NoAlias: double* %escape_alloca_a1, double** %indirect_a0 +; CHECK: NoAlias: double* %escape_alloca_a1, double** %indirect_a1 +; CHECK: MayAlias: double* %escape_alloca_a1, double* %loaded_a0 +; CHECK: MayAlias: double* %escape_alloca_a1, double* %loaded_a1 +; CHECK: NoAlias: double* %escape_alloca_a0, double* %escape_alloca_a1 +; CHECK: NoAlias: double* %arg_a0, double* %noescape_alloca_a0 +; CHECK: NoAlias: double* %arg_a1, double* %noescape_alloca_a0 +; CHECK: NoAlias: double* %noalias_arg_a0, double* %noescape_alloca_a0 +; CHECK: NoAlias: double* %noalias_arg_a1, double* %noescape_alloca_a0 +; CHECK: NoAlias: double* %noescape_alloca_a0, double** %indirect_a0 +; CHECK: NoAlias: double* %noescape_alloca_a0, double** %indirect_a1 +; CHECK: NoAlias: double* %loaded_a0, double* %noescape_alloca_a0 +; CHECK: NoAlias: double* %loaded_a1, double* %noescape_alloca_a0 +; CHECK: NoAlias: double* %escape_alloca_a0, double* %noescape_alloca_a0 +; CHECK: NoAlias: double* %escape_alloca_a1, double* %noescape_alloca_a0 +; CHECK: NoAlias: double* %arg_a0, double* %noescape_alloca_a1 +; CHECK: NoAlias: double* %arg_a1, double* %noescape_alloca_a1 +; CHECK: NoAlias: double* %noalias_arg_a0, double* %noescape_alloca_a1 +; CHECK: NoAlias: double* %noalias_arg_a1, double* %noescape_alloca_a1 +; CHECK: NoAlias: double* %noescape_alloca_a1, double** %indirect_a0 +; CHECK: NoAlias: double* %noescape_alloca_a1, double** %indirect_a1 +; CHECK: NoAlias: double* %loaded_a0, double* %noescape_alloca_a1 +; CHECK: NoAlias: double* %loaded_a1, double* %noescape_alloca_a1 +; CHECK: NoAlias: double* %escape_alloca_a0, double* %noescape_alloca_a1 +; CHECK: NoAlias: double* %escape_alloca_a1, double* %noescape_alloca_a1 +; CHECK: NoAlias: double* %noescape_alloca_a0, double* %noescape_alloca_a1 +; CHECK: MayAlias: double* %arg_a0, double* %normal_ret_a0 +; CHECK: MayAlias: double* %arg_a1, double* %normal_ret_a0 +; CHECK: NoAlias: double* %noalias_arg_a0, double* %normal_ret_a0 +; CHECK: NoAlias: double* %noalias_arg_a1, double* %normal_ret_a0 +; CHECK: MayAlias: double* %normal_ret_a0, double** %indirect_a0 +; CHECK: MayAlias: double* %normal_ret_a0, double** %indirect_a1 +; CHECK: MayAlias: double* %loaded_a0, double* %normal_ret_a0 +; CHECK: MayAlias: double* %loaded_a1, double* %normal_ret_a0 +; CHECK: MayAlias: double* %escape_alloca_a0, double* %normal_ret_a0 +; CHECK: MayAlias: double* %escape_alloca_a1, double* %normal_ret_a0 +; CHECK: NoAlias: double* %noescape_alloca_a0, double* %normal_ret_a0 +; CHECK: NoAlias: double* %noescape_alloca_a1, double* %normal_ret_a0 +; CHECK: MayAlias: double* %arg_a0, double* %normal_ret_a1 +; CHECK: MayAlias: double* %arg_a1, double* %normal_ret_a1 +; CHECK: NoAlias: double* %noalias_arg_a0, double* %normal_ret_a1 +; CHECK: NoAlias: double* %noalias_arg_a1, double* %normal_ret_a1 +; CHECK: MayAlias: double* %normal_ret_a1, double** %indirect_a0 +; CHECK: MayAlias: double* %normal_ret_a1, double** %indirect_a1 +; CHECK: MayAlias: double* %loaded_a0, double* %normal_ret_a1 +; CHECK: MayAlias: double* %loaded_a1, double* %normal_ret_a1 +; CHECK: MayAlias: double* %escape_alloca_a0, double* %normal_ret_a1 +; CHECK: MayAlias: double* %escape_alloca_a1, double* %normal_ret_a1 +; CHECK: NoAlias: double* %noescape_alloca_a0, double* %normal_ret_a1 +; CHECK: NoAlias: double* %noescape_alloca_a1, double* %normal_ret_a1 +; CHECK: MayAlias: double* %normal_ret_a0, double* %normal_ret_a1 +; CHECK: NoAlias: double* %arg_a0, double* %noalias_ret_a0 +; CHECK: NoAlias: double* %arg_a1, double* %noalias_ret_a0 +; CHECK: NoAlias: double* %noalias_arg_a0, double* %noalias_ret_a0 +; CHECK: NoAlias: double* %noalias_arg_a1, double* %noalias_ret_a0 +; CHECK: NoAlias: double* %noalias_ret_a0, double** %indirect_a0 +; CHECK: NoAlias: double* %noalias_ret_a0, double** %indirect_a1 +; CHECK: NoAlias: double* %loaded_a0, double* %noalias_ret_a0 +; CHECK: NoAlias: double* %loaded_a1, double* %noalias_ret_a0 +; CHECK: NoAlias: double* %escape_alloca_a0, double* %noalias_ret_a0 +; CHECK: NoAlias: double* %escape_alloca_a1, double* %noalias_ret_a0 +; CHECK: NoAlias: double* %noalias_ret_a0, double* %noescape_alloca_a0 +; CHECK: NoAlias: double* %noalias_ret_a0, double* %noescape_alloca_a1 +; CHECK: NoAlias: double* %noalias_ret_a0, double* %normal_ret_a0 +; CHECK: NoAlias: double* %noalias_ret_a0, double* %normal_ret_a1 +; CHECK: NoAlias: double* %arg_a0, double* %noalias_ret_a1 +; CHECK: NoAlias: double* %arg_a1, double* %noalias_ret_a1 +; CHECK: NoAlias: double* %noalias_arg_a0, double* %noalias_ret_a1 +; CHECK: NoAlias: double* %noalias_arg_a1, double* %noalias_ret_a1 +; CHECK: NoAlias: double* %noalias_ret_a1, double** %indirect_a0 +; CHECK: NoAlias: double* %noalias_ret_a1, double** %indirect_a1 +; CHECK: NoAlias: double* %loaded_a0, double* %noalias_ret_a1 +; CHECK: NoAlias: double* %loaded_a1, double* %noalias_ret_a1 +; CHECK: NoAlias: double* %escape_alloca_a0, double* %noalias_ret_a1 +; CHECK: NoAlias: double* %escape_alloca_a1, double* %noalias_ret_a1 +; CHECK: NoAlias: double* %noalias_ret_a1, double* %noescape_alloca_a0 +; CHECK: NoAlias: double* %noalias_ret_a1, double* %noescape_alloca_a1 +; CHECK: NoAlias: double* %noalias_ret_a1, double* %normal_ret_a0 +; CHECK: NoAlias: double* %noalias_ret_a1, double* %normal_ret_a1 +; CHECK: NoAlias: double* %noalias_ret_a0, double* %noalias_ret_a1 +; CHECK: ModRef: Ptr: double* %arg_a0 <-> %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1] +; CHECK: ModRef: Ptr: double* %arg_a1 <-> %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1] +; CHECK: NoModRef: Ptr: double* %noalias_arg_a0 <-> %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1] +; CHECK: NoModRef: Ptr: double* %noalias_arg_a1 <-> %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1] +; CHECK: ModRef: Ptr: double** %indirect_a0 <-> %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1] +; CHECK: ModRef: Ptr: double** %indirect_a1 <-> %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1] +; CHECK: ModRef: Ptr: double* %loaded_a0 <-> %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1] +; CHECK: ModRef: Ptr: double* %loaded_a1 <-> %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1] +; CHECK: ModRef: Ptr: double* %escape_alloca_a0 <-> %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1] +; CHECK: ModRef: Ptr: double* %escape_alloca_a1 <-> %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1] +; CHECK: NoModRef: Ptr: double* %noescape_alloca_a0 <-> %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1] +; CHECK: NoModRef: Ptr: double* %noescape_alloca_a1 <-> %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1] +; CHECK: ModRef: Ptr: double* %normal_ret_a0 <-> %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1] +; CHECK: ModRef: Ptr: double* %normal_ret_a1 <-> %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1] +; CHECK: NoModRef: Ptr: double* %noalias_ret_a0 <-> %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1] +; CHECK: NoModRef: Ptr: double* %noalias_ret_a1 <-> %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1] +; CHECK: ModRef: Ptr: double* %arg_a0 <-> %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1] +; CHECK: ModRef: Ptr: double* %arg_a1 <-> %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1] +; CHECK: NoModRef: Ptr: double* %noalias_arg_a0 <-> %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1] +; CHECK: NoModRef: Ptr: double* %noalias_arg_a1 <-> %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1] +; CHECK: ModRef: Ptr: double** %indirect_a0 <-> %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1] +; CHECK: ModRef: Ptr: double** %indirect_a1 <-> %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1] +; CHECK: ModRef: Ptr: double* %loaded_a0 <-> %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1] +; CHECK: ModRef: Ptr: double* %loaded_a1 <-> %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1] +; CHECK: ModRef: Ptr: double* %escape_alloca_a0 <-> %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1] +; CHECK: ModRef: Ptr: double* %escape_alloca_a1 <-> %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1] +; CHECK: NoModRef: Ptr: double* %noescape_alloca_a0 <-> %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1] +; CHECK: NoModRef: Ptr: double* %noescape_alloca_a1 <-> %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1] +; CHECK: ModRef: Ptr: double* %normal_ret_a0 <-> %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1] +; CHECK: ModRef: Ptr: double* %normal_ret_a1 <-> %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1] +; CHECK: NoModRef: Ptr: double* %noalias_ret_a0 <-> %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1] +; CHECK: NoModRef: Ptr: double* %noalias_ret_a1 <-> %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1] +; CHECK: ModRef: Ptr: double* %arg_a0 <-> %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1] +; CHECK: ModRef: Ptr: double* %arg_a1 <-> %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1] +; CHECK: NoModRef: Ptr: double* %noalias_arg_a0 <-> %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1] +; CHECK: NoModRef: Ptr: double* %noalias_arg_a1 <-> %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1] +; CHECK: ModRef: Ptr: double** %indirect_a0 <-> %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1] +; CHECK: ModRef: Ptr: double** %indirect_a1 <-> %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1] +; CHECK: ModRef: Ptr: double* %loaded_a0 <-> %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1] +; CHECK: ModRef: Ptr: double* %loaded_a1 <-> %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1] +; CHECK: ModRef: Ptr: double* %escape_alloca_a0 <-> %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1] +; CHECK: ModRef: Ptr: double* %escape_alloca_a1 <-> %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1] +; CHECK: NoModRef: Ptr: double* %noescape_alloca_a0 <-> %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1] +; CHECK: NoModRef: Ptr: double* %noescape_alloca_a1 <-> %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1] +; CHECK: ModRef: Ptr: double* %normal_ret_a0 <-> %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1] +; CHECK: ModRef: Ptr: double* %normal_ret_a1 <-> %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1] +; CHECK: ModRef: Ptr: double* %noalias_ret_a0 <-> %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1] +; CHECK: NoModRef: Ptr: double* %noalias_ret_a1 <-> %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1] +; CHECK: ModRef: Ptr: double* %arg_a0 <-> %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1] +; CHECK: ModRef: Ptr: double* %arg_a1 <-> %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1] +; CHECK: NoModRef: Ptr: double* %noalias_arg_a0 <-> %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1] +; CHECK: NoModRef: Ptr: double* %noalias_arg_a1 <-> %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1] +; CHECK: ModRef: Ptr: double** %indirect_a0 <-> %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1] +; CHECK: ModRef: Ptr: double** %indirect_a1 <-> %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1] +; CHECK: ModRef: Ptr: double* %loaded_a0 <-> %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1] +; CHECK: ModRef: Ptr: double* %loaded_a1 <-> %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1] +; CHECK: ModRef: Ptr: double* %escape_alloca_a0 <-> %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1] +; CHECK: ModRef: Ptr: double* %escape_alloca_a1 <-> %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1] +; CHECK: NoModRef: Ptr: double* %noescape_alloca_a0 <-> %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1] +; CHECK: NoModRef: Ptr: double* %noescape_alloca_a1 <-> %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1] +; CHECK: ModRef: Ptr: double* %normal_ret_a0 <-> %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1] +; CHECK: ModRef: Ptr: double* %normal_ret_a1 <-> %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1] +; CHECK: NoModRef: Ptr: double* %noalias_ret_a0 <-> %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1] +; CHECK: ModRef: Ptr: double* %noalias_ret_a1 <-> %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1] +; CHECK: ModRef: Ptr: double* %arg_a0 <-> call void @callee(double* %escape_alloca_a0) +; CHECK: ModRef: Ptr: double* %arg_a1 <-> call void @callee(double* %escape_alloca_a0) +; CHECK: NoModRef: Ptr: double* %noalias_arg_a0 <-> call void @callee(double* %escape_alloca_a0) +; CHECK: NoModRef: Ptr: double* %noalias_arg_a1 <-> call void @callee(double* %escape_alloca_a0) +; CHECK: ModRef: Ptr: double** %indirect_a0 <-> call void @callee(double* %escape_alloca_a0) +; CHECK: ModRef: Ptr: double** %indirect_a1 <-> call void @callee(double* %escape_alloca_a0) +; CHECK: ModRef: Ptr: double* %loaded_a0 <-> call void @callee(double* %escape_alloca_a0) +; CHECK: ModRef: Ptr: double* %loaded_a1 <-> call void @callee(double* %escape_alloca_a0) +; CHECK: ModRef: Ptr: double* %escape_alloca_a0 <-> call void @callee(double* %escape_alloca_a0) +; CHECK: ModRef: Ptr: double* %escape_alloca_a1 <-> call void @callee(double* %escape_alloca_a0) +; CHECK: NoModRef: Ptr: double* %noescape_alloca_a0 <-> call void @callee(double* %escape_alloca_a0) +; CHECK: NoModRef: Ptr: double* %noescape_alloca_a1 <-> call void @callee(double* %escape_alloca_a0) +; CHECK: ModRef: Ptr: double* %normal_ret_a0 <-> call void @callee(double* %escape_alloca_a0) +; CHECK: ModRef: Ptr: double* %normal_ret_a1 <-> call void @callee(double* %escape_alloca_a0) +; CHECK: NoModRef: Ptr: double* %noalias_ret_a0 <-> call void @callee(double* %escape_alloca_a0) +; CHECK: NoModRef: Ptr: double* %noalias_ret_a1 <-> call void @callee(double* %escape_alloca_a0) +; CHECK: ModRef: Ptr: double* %arg_a0 <-> call void @callee(double* %escape_alloca_a1) +; CHECK: ModRef: Ptr: double* %arg_a1 <-> call void @callee(double* %escape_alloca_a1) +; CHECK: NoModRef: Ptr: double* %noalias_arg_a0 <-> call void @callee(double* %escape_alloca_a1) +; CHECK: NoModRef: Ptr: double* %noalias_arg_a1 <-> call void @callee(double* %escape_alloca_a1) +; CHECK: ModRef: Ptr: double** %indirect_a0 <-> call void @callee(double* %escape_alloca_a1) +; CHECK: ModRef: Ptr: double** %indirect_a1 <-> call void @callee(double* %escape_alloca_a1) +; CHECK: ModRef: Ptr: double* %loaded_a0 <-> call void @callee(double* %escape_alloca_a1) +; CHECK: ModRef: Ptr: double* %loaded_a1 <-> call void @callee(double* %escape_alloca_a1) +; CHECK: ModRef: Ptr: double* %escape_alloca_a0 <-> call void @callee(double* %escape_alloca_a1) +; CHECK: ModRef: Ptr: double* %escape_alloca_a1 <-> call void @callee(double* %escape_alloca_a1) +; CHECK: NoModRef: Ptr: double* %noescape_alloca_a0 <-> call void @callee(double* %escape_alloca_a1) +; CHECK: NoModRef: Ptr: double* %noescape_alloca_a1 <-> call void @callee(double* %escape_alloca_a1) +; CHECK: ModRef: Ptr: double* %normal_ret_a0 <-> call void @callee(double* %escape_alloca_a1) +; CHECK: ModRef: Ptr: double* %normal_ret_a1 <-> call void @callee(double* %escape_alloca_a1) +; CHECK: NoModRef: Ptr: double* %noalias_ret_a0 <-> call void @callee(double* %escape_alloca_a1) +; CHECK: NoModRef: Ptr: double* %noalias_ret_a1 <-> call void @callee(double* %escape_alloca_a1) +; CHECK: ModRef: Ptr: double* %arg_a0 <-> call void @nocap_callee(double* %noescape_alloca_a0) +; CHECK: ModRef: Ptr: double* %arg_a1 <-> call void @nocap_callee(double* %noescape_alloca_a0) +; CHECK: NoModRef: Ptr: double* %noalias_arg_a0 <-> call void @nocap_callee(double* %noescape_alloca_a0) +; CHECK: NoModRef: Ptr: double* %noalias_arg_a1 <-> call void @nocap_callee(double* %noescape_alloca_a0) +; CHECK: ModRef: Ptr: double** %indirect_a0 <-> call void @nocap_callee(double* %noescape_alloca_a0) +; CHECK: ModRef: Ptr: double** %indirect_a1 <-> call void @nocap_callee(double* %noescape_alloca_a0) +; CHECK: ModRef: Ptr: double* %loaded_a0 <-> call void @nocap_callee(double* %noescape_alloca_a0) +; CHECK: ModRef: Ptr: double* %loaded_a1 <-> call void @nocap_callee(double* %noescape_alloca_a0) +; CHECK: ModRef: Ptr: double* %escape_alloca_a0 <-> call void @nocap_callee(double* %noescape_alloca_a0) +; CHECK: ModRef: Ptr: double* %escape_alloca_a1 <-> call void @nocap_callee(double* %noescape_alloca_a0) +; CHECK: ModRef: Ptr: double* %noescape_alloca_a0 <-> call void @nocap_callee(double* %noescape_alloca_a0) +; CHECK: NoModRef: Ptr: double* %noescape_alloca_a1 <-> call void @nocap_callee(double* %noescape_alloca_a0) +; CHECK: ModRef: Ptr: double* %normal_ret_a0 <-> call void @nocap_callee(double* %noescape_alloca_a0) +; CHECK: ModRef: Ptr: double* %normal_ret_a1 <-> call void @nocap_callee(double* %noescape_alloca_a0) +; CHECK: NoModRef: Ptr: double* %noalias_ret_a0 <-> call void @nocap_callee(double* %noescape_alloca_a0) +; CHECK: NoModRef: Ptr: double* %noalias_ret_a1 <-> call void @nocap_callee(double* %noescape_alloca_a0) +; CHECK: ModRef: Ptr: double* %arg_a0 <-> call void @nocap_callee(double* %noescape_alloca_a1) +; CHECK: ModRef: Ptr: double* %arg_a1 <-> call void @nocap_callee(double* %noescape_alloca_a1) +; CHECK: NoModRef: Ptr: double* %noalias_arg_a0 <-> call void @nocap_callee(double* %noescape_alloca_a1) +; CHECK: NoModRef: Ptr: double* %noalias_arg_a1 <-> call void @nocap_callee(double* %noescape_alloca_a1) +; CHECK: ModRef: Ptr: double** %indirect_a0 <-> call void @nocap_callee(double* %noescape_alloca_a1) +; CHECK: ModRef: Ptr: double** %indirect_a1 <-> call void @nocap_callee(double* %noescape_alloca_a1) +; CHECK: ModRef: Ptr: double* %loaded_a0 <-> call void @nocap_callee(double* %noescape_alloca_a1) +; CHECK: ModRef: Ptr: double* %loaded_a1 <-> call void @nocap_callee(double* %noescape_alloca_a1) +; CHECK: ModRef: Ptr: double* %escape_alloca_a0 <-> call void @nocap_callee(double* %noescape_alloca_a1) +; CHECK: ModRef: Ptr: double* %escape_alloca_a1 <-> call void @nocap_callee(double* %noescape_alloca_a1) +; CHECK: NoModRef: Ptr: double* %noescape_alloca_a0 <-> call void @nocap_callee(double* %noescape_alloca_a1) +; CHECK: ModRef: Ptr: double* %noescape_alloca_a1 <-> call void @nocap_callee(double* %noescape_alloca_a1) +; CHECK: ModRef: Ptr: double* %normal_ret_a0 <-> call void @nocap_callee(double* %noescape_alloca_a1) +; CHECK: ModRef: Ptr: double* %normal_ret_a1 <-> call void @nocap_callee(double* %noescape_alloca_a1) +; CHECK: NoModRef: Ptr: double* %noalias_ret_a0 <-> call void @nocap_callee(double* %noescape_alloca_a1) +; CHECK: NoModRef: Ptr: double* %noalias_ret_a1 <-> call void @nocap_callee(double* %noescape_alloca_a1) +; CHECK: ===== Alias Analysis Evaluator Report ===== +; CHECK: 120 Total Alias Queries Performed +; CHECK: 84 no alias responses (70.0%) +; CHECK: 36 may alias responses (30.0%) +; CHECK: 0 must alias responses (0.0%) +; CHECK: Alias Analysis Evaluator Pointer Alias Summary: 70%/30%/0% +; CHECK: 128 Total ModRef Queries Performed +; CHECK: 44 no mod/ref responses (34.3%) +; CHECK: 0 mod responses (0.0%) +; CHECK: 0 ref responses (0.0%) +; CHECK: 84 mod & ref responses (65.6%) +; CHECK: Alias Analysis Evaluator Mod/Ref Summary: 34%/0%/0%/65% diff --git a/test/Analysis/BasicAA/unreachable-block.ll b/test/Analysis/BasicAA/unreachable-block.ll new file mode 100644 index 0000000..3382188 --- /dev/null +++ b/test/Analysis/BasicAA/unreachable-block.ll @@ -0,0 +1,16 @@ +; RUN: opt -aa-eval -disable-output < %s >& /dev/null + +; BasicAA shouldn't infinitely recurse on the use-def cycles in +; unreachable code. + +define void @func_2() nounwind { +entry: + unreachable + +bb: + %t = select i1 undef, i32* %t, i32* undef + %p = select i1 undef, i32* %p, i32* %p + %q = select i1 undef, i32* undef, i32* %p + %a = getelementptr i8* %a, i32 0 + unreachable +} diff --git a/test/Analysis/ScalarEvolution/2008-07-29-SMinExpr.ll b/test/Analysis/ScalarEvolution/2008-07-29-SMinExpr.ll index 1626c1f..3542ad2 100644 --- a/test/Analysis/ScalarEvolution/2008-07-29-SMinExpr.ll +++ b/test/Analysis/ScalarEvolution/2008-07-29-SMinExpr.ll @@ -22,5 +22,5 @@ afterfor: ; preds = %forinc, %entry ret i32 %j.0.lcssa } -; CHECK: backedge-taken count is (-2147483632 + ((-1 + (-1 * %x)) smax (-1 + (-1 * %y)))) +; CHECK: backedge-taken count is (-2147483632 + ((-1 + (-1 * %{{[xy]}})) smax (-1 + (-1 * %{{[xy]}})))) diff --git a/test/Analysis/ScalarEvolution/scev-aa.ll b/test/Analysis/ScalarEvolution/scev-aa.ll index e07aca2..866664a 100644 --- a/test/Analysis/ScalarEvolution/scev-aa.ll +++ b/test/Analysis/ScalarEvolution/scev-aa.ll @@ -1,8 +1,9 @@ ; RUN: opt < %s -scev-aa -aa-eval -print-all-alias-modref-info \ ; RUN: |& FileCheck %s -; At the time of this writing, -basicaa only misses the example of the form -; A[i+(j+1)] != A[i+j], which can arise from multi-dimensional array references. +; At the time of this writing, -basicaa misses the example of the form +; A[i+(j+1)] != A[i+j], which can arise from multi-dimensional array references, +; and the example of the form A[0] != A[i+1], where i+1 is known to be positive. target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64" @@ -189,6 +190,27 @@ define void @bar() { ret void } +; TODO: This is theoretically provable to be NoAlias. +; CHECK: Function: nonnegative: 2 pointers, 0 call sites +; CHECK: MayAlias: i64* %arrayidx, i64* %p + +define void @nonnegative(i64* %p) nounwind { +entry: + br label %for.body + +for.body: ; preds = %entry, %for.body + %i = phi i64 [ %inc, %for.body ], [ 0, %entry ] ; <i64> [#uses=2] + %inc = add nsw i64 %i, 1 ; <i64> [#uses=2] + %arrayidx = getelementptr inbounds i64* %p, i64 %inc + store i64 0, i64* %arrayidx + %tmp6 = load i64* %p ; <i64> [#uses=1] + %cmp = icmp slt i64 %inc, %tmp6 ; <i1> [#uses=1] + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.body, %entry + ret void +} + ; CHECK: 13 no alias responses -; CHECK: 26 may alias responses +; CHECK: 27 may alias responses ; CHECK: 18 must alias responses diff --git a/test/Analysis/ScalarEvolution/trip-count10.ll b/test/Analysis/ScalarEvolution/trip-count10.ll index 0a992f9..546e1dc 100644 --- a/test/Analysis/ScalarEvolution/trip-count10.ll +++ b/test/Analysis/ScalarEvolution/trip-count10.ll @@ -74,3 +74,53 @@ loop: return: ret void } + +; Trip counts for non-polynomial iterations. It's theoretically possible +; to compute a maximum count for these, but short of that, ScalarEvolution +; should return unknown. + +; PR7416 +; CHECK: Determining loop execution counts for: @nonpolynomial +; CHECK-NEXT: Loop %loophead: Unpredictable backedge-taken count +; CHECK-NEXT: Loop %loophead: Unpredictable max backedge-taken count + +declare i1 @g() nounwind + +define void @nonpolynomial() { +entry: + br label %loophead +loophead: + %x = phi i32 [0, %entry], [%x.1, %bb1], [%x.2, %bb2] + %y = icmp slt i32 %x, 100 + br i1 %y, label %loopbody, label %retbb +loopbody: + %z = call i1 @g() + br i1 %z, label %bb1, label %bb2 +bb1: + %x.1 = add i32 %x, 2 + br label %loophead +bb2: + %x.2 = add i32 %x, 3 + br label %loophead +retbb: + ret void +} + +; PHI nodes with all constant operands. + +; CHECK: Determining loop execution counts for: @constant_phi_operands +; CHECK: Loop %loop: backedge-taken count is 1 +; CHECK: Loop %loop: max backedge-taken count is 1 + +define void @constant_phi_operands() nounwind { +entry: + br label %loop + +loop: + %i = phi i64 [ 1, %loop ], [ 0, %entry ] + %exitcond = icmp eq i64 %i, 1 + br i1 %exitcond, label %return, label %loop + +return: + ret void +} diff --git a/test/BugPoint/remove_arguments_test.ll b/test/BugPoint/remove_arguments_test.ll index fb17c78..439ea54 100644 --- a/test/BugPoint/remove_arguments_test.ll +++ b/test/BugPoint/remove_arguments_test.ll @@ -1,11 +1,17 @@ ; RUN: bugpoint %s -output-prefix %t -bugpoint-crashcalls -silence-passes +; RUN: llvm-dis %t-reduced-simplified.bc -o - | FileCheck %s ; Test to make sure that arguments are removed from the function if they are -; unnecessary. +; unnecessary. And clean up any types that that frees up too. + +; CHECK: target triple +; CHECK-NOT: struct.anon +%struct.anon = type { i32 } declare i32 @test2() -define i32 @test(i32 %A, i32 %B, float %C) { +; CHECK: define void @test() { +define i32 @test(i32 %A, %struct.anon* %B, float %C) { call i32 @test2() ret i32 %1 } diff --git a/test/CMakeLists.txt b/test/CMakeLists.txt index ab060c9..433af90 100644 --- a/test/CMakeLists.txt +++ b/test/CMakeLists.txt @@ -35,6 +35,7 @@ if(PYTHONINTERP_FOUND) -e "s#\@LLVM_BINARY_DIR\@#${LLVM_BINARY_DIR}#" -e "s#\@LLVM_TOOLS_DIR\@#${LLVM_TOOLS_BINARY_DIR}/${CMAKE_CFG_INTDIR}#" -e "s#\@LLVMGCCDIR\@##" + -e "s#\@PYTHON_EXECUTABLE\@#${PYTHON_EXECUTABLE}#" ${CMAKE_CURRENT_SOURCE_DIR}/lit.site.cfg.in > ${CMAKE_CURRENT_BINARY_DIR}/lit.site.cfg COMMAND sed -e "s#\@LLVM_SOURCE_DIR\@#${LLVM_MAIN_SRC_DIR}#" diff --git a/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll b/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll index f775c61..fd2f462 100644 --- a/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll +++ b/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll @@ -1,4 +1,3 @@ -; RUN: llc < %s -mtriple=arm-linux-gnueabi -regalloc=local ; RUN: llc < %s -mtriple=arm-linux-gnueabi -regalloc=fast ; PR1925 diff --git a/test/CodeGen/ARM/2008-02-29-RegAllocLocal.ll b/test/CodeGen/ARM/2008-02-29-RegAllocLocal.ll index 8ef8c7b..44da8e7 100644 --- a/test/CodeGen/ARM/2008-02-29-RegAllocLocal.ll +++ b/test/CodeGen/ARM/2008-02-29-RegAllocLocal.ll @@ -1,4 +1,3 @@ -; RUN: llc < %s -mtriple=arm-apple-darwin -regalloc=local ; RUN: llc < %s -mtriple=arm-apple-darwin -regalloc=fast ; PR1925 diff --git a/test/CodeGen/ARM/2009-05-07-RegAllocLocal.ll b/test/CodeGen/ARM/2009-05-07-RegAllocLocal.ll index 912e6f9..524b5eb 100644 --- a/test/CodeGen/ARM/2009-05-07-RegAllocLocal.ll +++ b/test/CodeGen/ARM/2009-05-07-RegAllocLocal.ll @@ -1,4 +1,3 @@ -; RUN: llc < %s -mtriple=armv5-unknown-linux-gnueabi -O0 -regalloc=local ; RUN: llc < %s -mtriple=armv5-unknown-linux-gnueabi -O0 -regalloc=fast ; PR4100 @.str = external constant [30 x i8] ; <[30 x i8]*> [#uses=1] diff --git a/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll b/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll index e068be7..7e9b066 100644 --- a/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll +++ b/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll @@ -3,7 +3,7 @@ %struct.rtunion = type { i64 } %struct.rtx_def = type { i16, i8, i8, [1 x %struct.rtunion] } -define arm_apcscc void @simplify_unary_real(i8* nocapture %p) nounwind { +define void @simplify_unary_real(i8* nocapture %p) nounwind { entry: %tmp121 = load i64* null, align 4 ; <i64> [#uses=1] %0 = getelementptr %struct.rtx_def* null, i32 0, i32 3, i32 3, i32 0 ; <i64*> [#uses=1] diff --git a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll index 17efe00..812f018 100644 --- a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll +++ b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll @@ -8,11 +8,11 @@ @"\01LC16" = external constant [33 x i8], align 1 ; <[33 x i8]*> [#uses=1] @"\01LC17" = external constant [47 x i8], align 1 ; <[47 x i8]*> [#uses=1] -declare arm_apcscc i32 @printf(i8* nocapture, ...) nounwind +declare i32 @printf(i8* nocapture, ...) nounwind -declare arm_apcscc void @diff(i8*, i8*, i32, i32, i32, i32) nounwind +declare void @diff(i8*, i8*, i32, i32, i32, i32) nounwind -define arm_apcscc void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { +define void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { entry: br i1 undef, label %bb5, label %bb @@ -44,17 +44,17 @@ bb11: ; preds = %bb9 store i32 0, i32* @no_mat, align 4 store i32 0, i32* @no_mis, align 4 %3 = getelementptr i8* %B, i32 %0 ; <i8*> [#uses=1] - tail call arm_apcscc void @diff(i8* undef, i8* %3, i32 undef, i32 undef, i32 undef, i32 undef) nounwind + tail call void @diff(i8* undef, i8* %3, i32 undef, i32 undef, i32 undef, i32 undef) nounwind %4 = sitofp i32 undef to double ; <double> [#uses=1] %5 = fdiv double %4, 1.000000e+01 ; <double> [#uses=1] - %6 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([29 x i8]* @"\01LC12", i32 0, i32 0), double %5) nounwind ; <i32> [#uses=0] + %6 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([29 x i8]* @"\01LC12", i32 0, i32 0), double %5) nounwind ; <i32> [#uses=0] %7 = load i32* @al_len, align 4 ; <i32> [#uses=1] %8 = load i32* @no_mat, align 4 ; <i32> [#uses=1] %9 = load i32* @no_mis, align 4 ; <i32> [#uses=1] %10 = sub i32 %7, %8 ; <i32> [#uses=1] %11 = sub i32 %10, %9 ; <i32> [#uses=1] - %12 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([33 x i8]* @"\01LC16", i32 0, i32 0), i32 %11) nounwind ; <i32> [#uses=0] - %13 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([47 x i8]* @"\01LC17", i32 0, i32 0), i32 undef, i32 %1, i32 undef, i32 undef) nounwind ; <i32> [#uses=0] + %12 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([33 x i8]* @"\01LC16", i32 0, i32 0), i32 %11) nounwind ; <i32> [#uses=0] + %13 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([47 x i8]* @"\01LC17", i32 0, i32 0), i32 undef, i32 %1, i32 undef, i32 undef) nounwind ; <i32> [#uses=0] br i1 undef, label %bb15, label %bb12 bb12: ; preds = %bb11 diff --git a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll index f520be3..f5fb97c 100644 --- a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll +++ b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll @@ -6,11 +6,11 @@ @"\01LC15" = external constant [33 x i8], align 1 ; <[33 x i8]*> [#uses=1] @"\01LC17" = external constant [47 x i8], align 1 ; <[47 x i8]*> [#uses=1] -declare arm_apcscc i32 @printf(i8* nocapture, ...) nounwind +declare i32 @printf(i8* nocapture, ...) nounwind -declare arm_apcscc void @diff(i8*, i8*, i32, i32, i32, i32) nounwind +declare void @diff(i8*, i8*, i32, i32, i32, i32) nounwind -define arm_apcscc void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { +define void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { entry: br i1 undef, label %bb5, label %bb @@ -41,11 +41,11 @@ bb11: ; preds = %bb9 store i32 0, i32* @no_mat, align 4 store i32 0, i32* @no_mis, align 4 %4 = getelementptr i8* %B, i32 %0 ; <i8*> [#uses=1] - tail call arm_apcscc void @diff(i8* undef, i8* %4, i32 undef, i32 %3, i32 undef, i32 undef) nounwind - %5 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([33 x i8]* @"\01LC11", i32 0, i32 0), i32 %tmp13) nounwind ; <i32> [#uses=0] + tail call void @diff(i8* undef, i8* %4, i32 undef, i32 %3, i32 undef, i32 undef) nounwind + %5 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([33 x i8]* @"\01LC11", i32 0, i32 0), i32 %tmp13) nounwind ; <i32> [#uses=0] %6 = load i32* @no_mis, align 4 ; <i32> [#uses=1] - %7 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([33 x i8]* @"\01LC15", i32 0, i32 0), i32 %6) nounwind ; <i32> [#uses=0] - %8 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([47 x i8]* @"\01LC17", i32 0, i32 0), i32 undef, i32 %1, i32 undef, i32 %2) nounwind ; <i32> [#uses=0] + %7 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([33 x i8]* @"\01LC15", i32 0, i32 0), i32 %6) nounwind ; <i32> [#uses=0] + %8 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([47 x i8]* @"\01LC17", i32 0, i32 0), i32 undef, i32 %1, i32 undef, i32 %2) nounwind ; <i32> [#uses=0] br i1 undef, label %bb15, label %bb12 bb12: ; preds = %bb11 diff --git a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll index eee6ff9..d7e4c90 100644 --- a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll +++ b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll @@ -2,7 +2,7 @@ @JJ = external global i32* ; <i32**> [#uses=1] -define arm_apcscc void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { +define void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { entry: br i1 undef, label %bb5, label %bb diff --git a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll index 93c92b1..77c133a 100644 --- a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll +++ b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll @@ -6,9 +6,9 @@ @no_mis = external global i32 ; <i32*> [#uses=1] @name1 = external global i8* ; <i8**> [#uses=1] -declare arm_apcscc void @diff(i8*, i8*, i32, i32, i32, i32) nounwind +declare void @diff(i8*, i8*, i32, i32, i32, i32) nounwind -define arm_apcscc void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { +define void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { entry: br i1 undef, label %bb5, label %bb @@ -35,7 +35,7 @@ bb11: ; preds = %bb9 store i32 0, i32* @no_mis, align 4 %1 = getelementptr i8* %A, i32 0 ; <i8*> [#uses=1] %2 = getelementptr i8* %B, i32 0 ; <i8*> [#uses=1] - tail call arm_apcscc void @diff(i8* %1, i8* %2, i32 undef, i32 undef, i32 undef, i32 undef) nounwind + tail call void @diff(i8* %1, i8* %2, i32 undef, i32 undef, i32 undef, i32 undef) nounwind br i1 undef, label %bb15, label %bb12 bb12: ; preds = %bb11 diff --git a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll index 277283d..16f5d1d 100644 --- a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll +++ b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll @@ -2,7 +2,7 @@ @XX = external global i32* ; <i32**> [#uses=1] -define arm_apcscc void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { +define void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { entry: br i1 undef, label %bb5, label %bb diff --git a/test/CodeGen/ARM/2009-07-01-CommuteBug.ll b/test/CodeGen/ARM/2009-07-01-CommuteBug.ll index 5c0e5fa..f0d79ce 100644 --- a/test/CodeGen/ARM/2009-07-01-CommuteBug.ll +++ b/test/CodeGen/ARM/2009-07-01-CommuteBug.ll @@ -4,7 +4,7 @@ @II = external global i32* ; <i32**> [#uses=1] @JJ = external global i32* ; <i32**> [#uses=1] -define arm_apcscc void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { +define void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { entry: br i1 undef, label %bb5, label %bb diff --git a/test/CodeGen/ARM/2009-07-18-RewriterBug.ll b/test/CodeGen/ARM/2009-07-18-RewriterBug.ll index 2b7ccd8..454fee5 100644 --- a/test/CodeGen/ARM/2009-07-18-RewriterBug.ll +++ b/test/CodeGen/ARM/2009-07-18-RewriterBug.ll @@ -8,7 +8,7 @@ @_2E_str7 = internal constant [21 x i8] c"ERROR: Only 1 point!\00", section "__TEXT,__cstring,cstring_literals", align 1 ; <[21 x i8]*> [#uses=1] @llvm.used = appending global [1 x i8*] [i8* bitcast (void (%struct.EDGE_PAIR*, %struct.VERTEX*, %struct.VERTEX*)* @build_delaunay to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] -define arm_apcscc void @build_delaunay(%struct.EDGE_PAIR* noalias nocapture sret %agg.result, %struct.VERTEX* %tree, %struct.VERTEX* %extra) nounwind { +define void @build_delaunay(%struct.EDGE_PAIR* noalias nocapture sret %agg.result, %struct.VERTEX* %tree, %struct.VERTEX* %extra) nounwind { entry: %delright = alloca %struct.EDGE_PAIR, align 8 ; <%struct.EDGE_PAIR*> [#uses=3] %delleft = alloca %struct.EDGE_PAIR, align 8 ; <%struct.EDGE_PAIR*> [#uses=3] @@ -29,10 +29,10 @@ bb1.i: ; preds = %bb1.i, %bb br i1 %6, label %get_low.exit, label %bb1.i get_low.exit: ; preds = %bb1.i - call arm_apcscc void @build_delaunay(%struct.EDGE_PAIR* noalias sret %delright, %struct.VERTEX* %2, %struct.VERTEX* %extra) nounwind + call void @build_delaunay(%struct.EDGE_PAIR* noalias sret %delright, %struct.VERTEX* %2, %struct.VERTEX* %extra) nounwind %7 = getelementptr %struct.VERTEX* %tree, i32 0, i32 1 ; <%struct.VERTEX**> [#uses=1] %8 = load %struct.VERTEX** %7, align 4 ; <%struct.VERTEX*> [#uses=1] - call arm_apcscc void @build_delaunay(%struct.EDGE_PAIR* noalias sret %delleft, %struct.VERTEX* %8, %struct.VERTEX* %tree) nounwind + call void @build_delaunay(%struct.EDGE_PAIR* noalias sret %delleft, %struct.VERTEX* %8, %struct.VERTEX* %tree) nounwind %9 = getelementptr %struct.EDGE_PAIR* %delleft, i32 0, i32 0 ; <%struct.edge_rec**> [#uses=1] %10 = load %struct.edge_rec** %9, align 8 ; <%struct.edge_rec*> [#uses=2] %11 = getelementptr %struct.EDGE_PAIR* %delleft, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] @@ -141,7 +141,7 @@ bb5.i: ; preds = %bb3.i %85 = inttoptr i32 %84 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %86 = getelementptr %struct.edge_rec* %ldi_addr.0.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] %87 = load %struct.VERTEX** %86, align 4 ; <%struct.VERTEX*> [#uses=1] - %88 = call arm_apcscc %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=6] + %88 = call %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=6] %89 = getelementptr %struct.edge_rec* %88, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=4] store %struct.edge_rec* %88, %struct.edge_rec** %89, align 4 %90 = getelementptr %struct.edge_rec* %88, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=2] @@ -780,7 +780,7 @@ bb24.i: ; preds = %bb23.i, %bb21.i %592 = and i32 %589, -64 ; <i32> [#uses=1] %593 = or i32 %591, %592 ; <i32> [#uses=1] %594 = inttoptr i32 %593 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %595 = call arm_apcscc %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=5] + %595 = call %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=5] %596 = getelementptr %struct.edge_rec* %595, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=4] store %struct.edge_rec* %595, %struct.edge_rec** %596, align 4 %597 = getelementptr %struct.edge_rec* %595, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] @@ -882,7 +882,7 @@ bb25.i: ; preds = %bb23.i, %bb22.i %677 = and i32 %674, -64 ; <i32> [#uses=1] %678 = or i32 %676, %677 ; <i32> [#uses=1] %679 = inttoptr i32 %678 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %680 = call arm_apcscc %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=4] + %680 = call %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=4] %681 = getelementptr %struct.edge_rec* %680, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=5] store %struct.edge_rec* %680, %struct.edge_rec** %681, align 4 %682 = getelementptr %struct.edge_rec* %680, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] @@ -1005,15 +1005,15 @@ bb7: ; preds = %bb %762 = getelementptr %struct.VERTEX* %tree, i32 0, i32 1 ; <%struct.VERTEX**> [#uses=1] %763 = load %struct.VERTEX** %762, align 4 ; <%struct.VERTEX*> [#uses=4] %764 = icmp eq %struct.VERTEX* %763, null ; <i1> [#uses=1] - %765 = call arm_apcscc %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=5] + %765 = call %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=5] %766 = getelementptr %struct.edge_rec* %765, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=4] store %struct.edge_rec* %765, %struct.edge_rec** %766, align 4 %767 = getelementptr %struct.edge_rec* %765, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=3] br i1 %764, label %bb10, label %bb11 bb8: ; preds = %entry - %768 = call arm_apcscc i32 @puts(i8* getelementptr ([21 x i8]* @_2E_str7, i32 0, i32 0)) nounwind ; <i32> [#uses=0] - call arm_apcscc void @exit(i32 -1) noreturn nounwind + %768 = call i32 @puts(i8* getelementptr ([21 x i8]* @_2E_str7, i32 0, i32 0)) nounwind ; <i32> [#uses=0] + call void @exit(i32 -1) noreturn nounwind unreachable bb10: ; preds = %bb7 @@ -1053,7 +1053,7 @@ bb11: ; preds = %bb7 store %struct.VERTEX* %tree, %struct.VERTEX** %790, align 4 %791 = getelementptr %struct.edge_rec* %785, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] store %struct.edge_rec* %783, %struct.edge_rec** %791, align 4 - %792 = call arm_apcscc %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=4] + %792 = call %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=4] %793 = getelementptr %struct.edge_rec* %792, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=4] store %struct.edge_rec* %792, %struct.edge_rec** %793, align 4 %794 = getelementptr %struct.edge_rec* %792, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] @@ -1117,7 +1117,7 @@ bb11: ; preds = %bb7 %843 = or i32 %841, %842 ; <i32> [#uses=1] %844 = inttoptr i32 %843 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %845 = load %struct.VERTEX** %767, align 4 ; <%struct.VERTEX*> [#uses=1] - %846 = call arm_apcscc %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=4] + %846 = call %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=4] %847 = getelementptr %struct.edge_rec* %846, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=7] store %struct.edge_rec* %846, %struct.edge_rec** %847, align 4 %848 = getelementptr %struct.edge_rec* %846, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] @@ -1316,8 +1316,8 @@ bb15: ; preds = %bb14, %bb13, %bb11, %bb10, %bb6 ret void } -declare arm_apcscc i32 @puts(i8* nocapture) nounwind +declare i32 @puts(i8* nocapture) nounwind -declare arm_apcscc void @exit(i32) noreturn nounwind +declare void @exit(i32) noreturn nounwind -declare arm_apcscc %struct.edge_rec* @alloc_edge() nounwind +declare %struct.edge_rec* @alloc_edge() nounwind diff --git a/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll b/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll index b4b989b..d477ba98 100644 --- a/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll +++ b/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll @@ -6,9 +6,9 @@ %struct.cli_bm_patt = type { i8*, i8*, i16, i16, i8*, i8*, i8, %struct.cli_bm_patt*, i16 } %struct.cli_matcher = type { i16, i8, i8*, %struct.cli_bm_patt**, i32*, i32, i8, i8, %struct.cli_ac_node*, %struct.cli_ac_node**, %struct.cli_ac_patt**, i32, i32, i32 } -declare arm_apcscc i32 @strlen(i8* nocapture) nounwind readonly +declare i32 @strlen(i8* nocapture) nounwind readonly -define arm_apcscc i32 @cli_ac_addsig(%struct.cli_matcher* nocapture %root, i8* %virname, i8* %hexsig, i32 %sigid, i16 zeroext %parts, i16 zeroext %partno, i16 zeroext %type, i32 %mindist, i32 %maxdist, i8* %offset, i8 zeroext %target) nounwind { +define i32 @cli_ac_addsig(%struct.cli_matcher* nocapture %root, i8* %virname, i8* %hexsig, i32 %sigid, i16 zeroext %parts, i16 zeroext %partno, i16 zeroext %type, i32 %mindist, i32 %maxdist, i8* %offset, i8 zeroext %target) nounwind { entry: br i1 undef, label %bb126, label %bb1 @@ -86,7 +86,7 @@ bb52: ; preds = %cli_calloc.exit %0 = load i16* undef, align 4 ; <i16> [#uses=1] %1 = icmp eq i16 %0, 0 ; <i1> [#uses=1] %iftmp.20.0 = select i1 %1, i8* %hexsig, i8* null ; <i8*> [#uses=1] - %2 = tail call arm_apcscc i32 @strlen(i8* %iftmp.20.0) nounwind readonly ; <i32> [#uses=0] + %2 = tail call i32 @strlen(i8* %iftmp.20.0) nounwind readonly ; <i32> [#uses=0] unreachable bb126: ; preds = %entry diff --git a/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll b/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll index 24f4990..6761687 100644 --- a/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll +++ b/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll @@ -6,7 +6,7 @@ %struct.cli_bm_patt = type { i8*, i8*, i16, i16, i8*, i8*, i8, %struct.cli_bm_patt*, i16 } %struct.cli_matcher = type { i16, i8, i8*, %struct.cli_bm_patt**, i32*, i32, i8, i8, %struct.cli_ac_node*, %struct.cli_ac_node**, %struct.cli_ac_patt**, i32, i32, i32 } -define arm_apcscc i32 @cli_ac_addsig(%struct.cli_matcher* nocapture %root, i8* %virname, i8* %hexsig, i32 %sigid, i16 zeroext %parts, i16 zeroext %partno, i16 zeroext %type, i32 %mindist, i32 %maxdist, i8* %offset, i8 zeroext %target) nounwind { +define i32 @cli_ac_addsig(%struct.cli_matcher* nocapture %root, i8* %virname, i8* %hexsig, i32 %sigid, i16 zeroext %parts, i16 zeroext %partno, i16 zeroext %type, i32 %mindist, i32 %maxdist, i8* %offset, i8 zeroext %target) nounwind { entry: br i1 undef, label %bb126, label %bb1 diff --git a/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll b/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll index e1d19d1..5003fbd 100644 --- a/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll +++ b/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll @@ -4,7 +4,7 @@ declare double @llvm.exp.f64(double) nounwind readonly -define arm_apcscc void @findratio(double* nocapture %res1, double* nocapture %res2) nounwind { +define void @findratio(double* nocapture %res1, double* nocapture %res2) nounwind { entry: br label %bb diff --git a/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll b/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll index 2d4e58d..a656c49 100644 --- a/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll +++ b/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll @@ -4,7 +4,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64" target triple = "armv7-apple-darwin9" -define arm_apcscc <4 x i32> @scale(<4 x i32> %v, i32 %f) nounwind { +define <4 x i32> @scale(<4 x i32> %v, i32 %f) nounwind { entry: %v_addr = alloca <4 x i32> ; <<4 x i32>*> [#uses=2] %f_addr = alloca i32 ; <i32*> [#uses=2] diff --git a/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll b/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll index 65ffed2..3097522 100644 --- a/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll +++ b/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll @@ -1,10 +1,10 @@ -; RUN: llc < %s -mtriple=armv6-elf +; RUN: llc < %s -mtriple=arm-linux-gnueabi ; PR4528 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64" target triple = "armv6-elf" -define arm_aapcscc i32 @file_read_actor(i32* nocapture %desc, i32* %page, i32 %offset, i32 %size) nounwind optsize { +define i32 @file_read_actor(i32* nocapture %desc, i32* %page, i32 %offset, i32 %size) nounwind optsize { entry: br i1 undef, label %fault_in_pages_writeable.exit, label %bb5.i @@ -26,8 +26,8 @@ bb2: ; preds = %fault_in_pages_writeable.exit unreachable bb3: ; preds = %fault_in_pages_writeable.exit - %1 = tail call arm_aapcscc i32 @__copy_to_user(i8* undef, i8* undef, i32 undef) nounwind ; <i32> [#uses=0] + %1 = tail call i32 @__copy_to_user(i8* undef, i8* undef, i32 undef) nounwind ; <i32> [#uses=0] unreachable } -declare arm_aapcscc i32 @__copy_to_user(i8*, i8*, i32) +declare i32 @__copy_to_user(i8*, i8*, i32) diff --git a/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll b/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll index 9e5372a..d666f12 100644 --- a/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll +++ b/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll @@ -1,7 +1,7 @@ -; RUN: llc < %s -mtriple=armv6-elf +; RUN: llc < %s -mtriple=arm-linux-gnueabi ; PR4528 -define arm_aapcscc i32 @file_read_actor(i32 %desc, i32 %page, i32 %offset, i32 %size) nounwind optsize { +define i32 @file_read_actor(i32 %desc, i32 %page, i32 %offset, i32 %size) nounwind optsize { entry: br i1 undef, label %fault_in_pages_writeable.exit, label %bb5.i @@ -18,8 +18,8 @@ bb2: ; preds = %fault_in_pages_writeable.exit unreachable bb3: ; preds = %fault_in_pages_writeable.exit - %2 = tail call arm_aapcscc i32 @__copy_to_user(i8* undef, i8* undef, i32 undef) nounwind ; <i32> [#uses=0] + %2 = tail call i32 @__copy_to_user(i8* undef, i8* undef, i32 undef) nounwind ; <i32> [#uses=0] unreachable } -declare arm_aapcscc i32 @__copy_to_user(i8*, i8*, i32) +declare i32 @__copy_to_user(i8*, i8*, i32) diff --git a/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll b/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll index 18d68f7..4b41015 100644 --- a/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll +++ b/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm +; RUN: llc < %s -mtriple=arm-linux-gnueabi ; PR4528 ; Inline asm is allowed to contain operands "=&r", "0". @@ -6,7 +6,7 @@ %struct.device_dma_parameters = type { i32, i32 } %struct.iovec = type { i8*, i32 } -define arm_aapcscc i32 @generic_segment_checks(%struct.iovec* nocapture %iov, i32* nocapture %nr_segs, i32* nocapture %count, i32 %access_flags) nounwind optsize { +define i32 @generic_segment_checks(%struct.iovec* nocapture %iov, i32* nocapture %nr_segs, i32* nocapture %count, i32 %access_flags) nounwind optsize { entry: br label %bb8 diff --git a/test/CodeGen/ARM/2009-08-15-RegScavengerAssert.ll b/test/CodeGen/ARM/2009-08-15-RegScavengerAssert.ll index a46482c..2993647 100644 --- a/test/CodeGen/ARM/2009-08-15-RegScavengerAssert.ll +++ b/test/CodeGen/ARM/2009-08-15-RegScavengerAssert.ll @@ -1,10 +1,10 @@ -; RUN: llc < %s -march=arm +; RUN: llc < %s -mtriple=arm-linux-gnueabi ; PR4716 -define arm_aapcscc void @_start() nounwind naked { +define void @_start() nounwind naked { entry: - tail call arm_aapcscc void @exit(i32 undef) noreturn nounwind + tail call void @exit(i32 undef) noreturn nounwind unreachable } -declare arm_aapcscc void @exit(i32) noreturn nounwind +declare void @exit(i32) noreturn nounwind diff --git a/test/CodeGen/ARM/2009-08-21-PostRAKill.ll b/test/CodeGen/ARM/2009-08-21-PostRAKill.ll index 84915c4..c598fe6 100644 --- a/test/CodeGen/ARM/2009-08-21-PostRAKill.ll +++ b/test/CodeGen/ARM/2009-08-21-PostRAKill.ll @@ -7,7 +7,7 @@ target triple = "armv7-apple-darwin9" %struct.tree = type { i32, double, double, %struct.tree*, %struct.tree*, %struct.tree*, %struct.tree* } @g = common global %struct.tree* null -define arm_apcscc %struct.tree* @tsp(%struct.tree* %t, i32 %nproc) nounwind { +define %struct.tree* @tsp(%struct.tree* %t, i32 %nproc) nounwind { entry: %t.idx51.val.i = load double* null ; <double> [#uses=1] br i1 undef, label %bb4.i, label %bb.i diff --git a/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll b/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll index a21ffc3..cc92c26 100644 --- a/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll +++ b/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll @@ -9,7 +9,7 @@ target triple = "armv7-apple-darwin9" %struct.icstruct = type { [3 x i32], i16 } %struct.node = type { i16, double, [3 x double], i32, i32 } -declare arm_apcscc double @floor(double) nounwind readnone +declare double @floor(double) nounwind readnone define void @intcoord(%struct.icstruct* noalias nocapture sret %agg.result, i1 %a, double %b) { entry: @@ -28,7 +28,7 @@ bb7: ; preds = %bb3 br i1 %a, label %bb11, label %bb9 bb9: ; preds = %bb7 - %0 = tail call arm_apcscc double @floor(double %b) nounwind readnone ; <double> [#uses=0] + %0 = tail call double @floor(double %b) nounwind readnone ; <double> [#uses=0] br label %bb11 bb11: ; preds = %bb9, %bb7 diff --git a/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll b/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll index e3d8ea6..90a4a42 100644 --- a/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll +++ b/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll @@ -9,7 +9,7 @@ target triple = "armv7-apple-darwin9" %struct.Patient = type { i32, i32, i32, %struct.Village* } %struct.Village = type { [4 x %struct.Village*], %struct.Village*, %struct.List, %struct.Hosp, i32, i32 } -define arm_apcscc %struct.Village* @alloc_tree(i32 %level, i32 %label, %struct.Village* %back, i1 %p) nounwind { +define %struct.Village* @alloc_tree(i32 %level, i32 %label, %struct.Village* %back, i1 %p) nounwind { entry: br i1 %p, label %bb8, label %bb1 diff --git a/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll b/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll index 9123377..5cfc68d 100644 --- a/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll +++ b/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll @@ -8,19 +8,19 @@ target triple = "armv7-apple-darwin9" @.str1 = external constant [31 x i8], align 1 ; <[31 x i8]*> [#uses=1] @.str2 = external constant [4 x i8], align 1 ; <[4 x i8]*> [#uses=1] -declare arm_apcscc i32 @getUnknown(i32, ...) nounwind +declare i32 @getUnknown(i32, ...) nounwind declare void @llvm.va_start(i8*) nounwind declare void @llvm.va_end(i8*) nounwind -declare arm_apcscc i32 @printf(i8* nocapture, ...) nounwind +declare i32 @printf(i8* nocapture, ...) nounwind -define arm_apcscc i32 @main() nounwind { +define i32 @main() nounwind { entry: - %0 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([31 x i8]* @.str1, i32 0, i32 0), i32 1, i32 1, i32 1, i32 1, i32 1, i32 1) nounwind ; <i32> [#uses=0] - %1 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([31 x i8]* @.str1, i32 0, i32 0), i32 -128, i32 116, i32 116, i32 -3852, i32 -31232, i32 -1708916736) nounwind ; <i32> [#uses=0] - %2 = tail call arm_apcscc i32 (i32, ...)* @getUnknown(i32 undef, i32 116, i32 116, i32 -3852, i32 -31232, i32 30556, i32 -1708916736) nounwind ; <i32> [#uses=1] - %3 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([4 x i8]* @.str2, i32 0, i32 0), i32 %2) nounwind ; <i32> [#uses=0] + %0 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([31 x i8]* @.str1, i32 0, i32 0), i32 1, i32 1, i32 1, i32 1, i32 1, i32 1) nounwind ; <i32> [#uses=0] + %1 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([31 x i8]* @.str1, i32 0, i32 0), i32 -128, i32 116, i32 116, i32 -3852, i32 -31232, i32 -1708916736) nounwind ; <i32> [#uses=0] + %2 = tail call i32 (i32, ...)* @getUnknown(i32 undef, i32 116, i32 116, i32 -3852, i32 -31232, i32 30556, i32 -1708916736) nounwind ; <i32> [#uses=1] + %3 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([4 x i8]* @.str2, i32 0, i32 0), i32 %2) nounwind ; <i32> [#uses=0] ret i32 0 } diff --git a/test/CodeGen/ARM/2009-08-23-linkerprivate.ll b/test/CodeGen/ARM/2009-08-23-linkerprivate.ll index 0fad533..392c70a 100644 --- a/test/CodeGen/ARM/2009-08-23-linkerprivate.ll +++ b/test/CodeGen/ARM/2009-08-23-linkerprivate.ll @@ -2,7 +2,7 @@ ; ModuleID = '/Volumes/MacOS9/tests/WebKit/JavaScriptCore/profiler/ProfilerServer.mm' -@"\01l_objc_msgSend_fixup_alloc" = linker_private hidden global i32 0, section "__DATA, __objc_msgrefs, coalesced", align 16 ; <i32*> [#uses=0] +@"\01l_objc_msgSend_fixup_alloc" = linker_private_weak hidden global i32 0, section "__DATA, __objc_msgrefs, coalesced", align 16 ; CHECK: .globl l_objc_msgSend_fixup_alloc ; CHECK: .weak_definition l_objc_msgSend_fixup_alloc diff --git a/test/CodeGen/ARM/2009-08-26-ScalarToVector.ll b/test/CodeGen/ARM/2009-08-26-ScalarToVector.ll index c6ef256..5407013 100644 --- a/test/CodeGen/ARM/2009-08-26-ScalarToVector.ll +++ b/test/CodeGen/ARM/2009-08-26-ScalarToVector.ll @@ -10,7 +10,7 @@ target triple = "thumbv7-elf" declare <2 x i32> @llvm.arm.neon.vpadd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone -define arm_apcscc void @_ZN6squish10ClusterFit9Compress3EPv(%quuz* %this, i8* %block) { +define void @_ZN6squish10ClusterFit9Compress3EPv(%quuz* %this, i8* %block) { entry: %0 = lshr <4 x i32> zeroinitializer, <i32 31, i32 31, i32 31, i32 31> ; <<4 x i32>> [#uses=1] %1 = shufflevector <4 x i32> %0, <4 x i32> undef, <2 x i32> <i32 2, i32 3> ; <<2 x i32>> [#uses=1] diff --git a/test/CodeGen/ARM/2009-08-27-ScalarToVector.ll b/test/CodeGen/ARM/2009-08-27-ScalarToVector.ll index bc5bfe9..cac8569 100644 --- a/test/CodeGen/ARM/2009-08-27-ScalarToVector.ll +++ b/test/CodeGen/ARM/2009-08-27-ScalarToVector.ll @@ -8,7 +8,7 @@ target triple = "thumbv7-elf" %quux = type { i32 (...)**, %baz*, i32 } %quuz = type { %quux, i32, %bar, [128 x i8], [16 x %foo], %foo, %foo, %foo } -define arm_apcscc void @aaaa(%quuz* %this, i8* %block) { +define void @aaaa(%quuz* %this, i8* %block) { entry: br i1 undef, label %bb.nph269, label %bb201 diff --git a/test/CodeGen/ARM/2009-08-29-ExtractEltf32.ll b/test/CodeGen/ARM/2009-08-29-ExtractEltf32.ll index d5178b4..5bd30ea 100644 --- a/test/CodeGen/ARM/2009-08-29-ExtractEltf32.ll +++ b/test/CodeGen/ARM/2009-08-29-ExtractEltf32.ll @@ -2,7 +2,7 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32" target triple = "thumbv7-elf" -define arm_apcscc void @foo() nounwind { +define void @foo() nounwind { entry: %0 = tail call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> undef, <2 x float> undef) nounwind ; <<2 x float>> [#uses=1] %tmp28 = extractelement <2 x float> %0, i32 0 ; <float> [#uses=1] diff --git a/test/CodeGen/ARM/2009-08-29-TooLongSplat.ll b/test/CodeGen/ARM/2009-08-29-TooLongSplat.ll index 266fce6..4655962 100644 --- a/test/CodeGen/ARM/2009-08-29-TooLongSplat.ll +++ b/test/CodeGen/ARM/2009-08-29-TooLongSplat.ll @@ -2,7 +2,7 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32" target triple = "thumbv7-elf" -define arm_apcscc void @aaa() nounwind { +define void @aaa() nounwind { entry: %0 = fmul <4 x float> undef, <float 1.000000e+00, float 1.000000e+01, float 1.000000e+02, float 0x3EB0C6F7A0000000> ; <<4 x float>> [#uses=1] %tmp31 = extractelement <4 x float> %0, i32 0 ; <float> [#uses=1] diff --git a/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll b/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll index c0ad65f..397eba4 100644 --- a/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll +++ b/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll @@ -2,7 +2,7 @@ %struct.A = type { i32* } -define arm_apcscc void @"\01-[MyFunction Name:]"() { +define void @"\01-[MyFunction Name:]"() { entry: %save_filt.1 = alloca i32 ; <i32*> [#uses=2] %save_eptr.0 = alloca i8* ; <i8**> [#uses=2] @@ -10,12 +10,12 @@ entry: %eh_exception = alloca i8* ; <i8**> [#uses=5] %eh_selector = alloca i32 ; <i32*> [#uses=3] %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] - call arm_apcscc void @_ZN1AC1Ev(%struct.A* %a) - invoke arm_apcscc void @_Z3barv() + call void @_ZN1AC1Ev(%struct.A* %a) + invoke void @_Z3barv() to label %invcont unwind label %lpad invcont: ; preds = %entry - call arm_apcscc void @_ZN1AD1Ev(%struct.A* %a) nounwind + call void @_ZN1AD1Ev(%struct.A* %a) nounwind br label %return bb: ; preds = %ppad @@ -23,7 +23,7 @@ bb: ; preds = %ppad store i32 %eh_select, i32* %save_filt.1, align 4 %eh_value = load i8** %eh_exception ; <i8*> [#uses=1] store i8* %eh_value, i8** %save_eptr.0, align 4 - call arm_apcscc void @_ZN1AD1Ev(%struct.A* %a) nounwind + call void @_ZN1AD1Ev(%struct.A* %a) nounwind %0 = load i8** %save_eptr.0, align 4 ; <i8*> [#uses=1] store i8* %0, i8** %eh_exception, align 4 %1 = load i32* %save_filt.1, align 4 ; <i32> [#uses=1] @@ -46,16 +46,16 @@ ppad: ; preds = %lpad Unwind: ; preds = %bb %eh_ptr3 = load i8** %eh_exception ; <i8*> [#uses=1] - call arm_apcscc void @_Unwind_SjLj_Resume(i8* %eh_ptr3) + call void @_Unwind_SjLj_Resume(i8* %eh_ptr3) unreachable } -define linkonce_odr arm_apcscc void @_ZN1AC1Ev(%struct.A* %this) { +define linkonce_odr void @_ZN1AC1Ev(%struct.A* %this) { entry: %this_addr = alloca %struct.A* ; <%struct.A**> [#uses=2] %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] store %struct.A* %this, %struct.A** %this_addr - %0 = call arm_apcscc i8* @_Znwm(i32 4) ; <i8*> [#uses=1] + %0 = call i8* @_Znwm(i32 4) ; <i8*> [#uses=1] %1 = bitcast i8* %0 to i32* ; <i32*> [#uses=1] %2 = load %struct.A** %this_addr, align 4 ; <%struct.A*> [#uses=1] %3 = getelementptr inbounds %struct.A* %2, i32 0, i32 0 ; <i32**> [#uses=1] @@ -66,9 +66,9 @@ return: ; preds = %entry ret void } -declare arm_apcscc i8* @_Znwm(i32) +declare i8* @_Znwm(i32) -define linkonce_odr arm_apcscc void @_ZN1AD1Ev(%struct.A* %this) nounwind { +define linkonce_odr void @_ZN1AD1Ev(%struct.A* %this) nounwind { entry: %this_addr = alloca %struct.A* ; <%struct.A**> [#uses=2] %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] @@ -77,7 +77,7 @@ entry: %1 = getelementptr inbounds %struct.A* %0, i32 0, i32 0 ; <i32**> [#uses=1] %2 = load i32** %1, align 4 ; <i32*> [#uses=1] %3 = bitcast i32* %2 to i8* ; <i8*> [#uses=1] - call arm_apcscc void @_ZdlPv(i8* %3) nounwind + call void @_ZdlPv(i8* %3) nounwind br label %bb bb: ; preds = %entry @@ -88,9 +88,9 @@ return: ; preds = %bb } ;CHECK: L_LSDA_0: -declare arm_apcscc void @_ZdlPv(i8*) nounwind +declare void @_ZdlPv(i8*) nounwind -declare arm_apcscc void @_Z3barv() +declare void @_Z3barv() declare i8* @llvm.eh.exception() nounwind @@ -98,6 +98,6 @@ declare i32 @llvm.eh.selector.i32(i8*, i8*, ...) nounwind declare i32 @llvm.eh.typeid.for.i32(i8*) nounwind -declare arm_apcscc i32 @__gxx_personality_sj0(...) +declare i32 @__gxx_personality_sj0(...) -declare arm_apcscc void @_Unwind_SjLj_Resume(i8*) +declare void @_Unwind_SjLj_Resume(i8*) diff --git a/test/CodeGen/ARM/2009-09-01-PostRAProlog.ll b/test/CodeGen/ARM/2009-09-01-PostRAProlog.ll index bf91fe0..06a152d 100644 --- a/test/CodeGen/ARM/2009-09-01-PostRAProlog.ll +++ b/test/CodeGen/ARM/2009-09-01-PostRAProlog.ll @@ -30,11 +30,11 @@ target triple = "thumbv7-apple-darwin9" @.str218 = private constant [6 x i8] c"%7d%c\00", align 1 ; <[6 x i8]*> [#uses=1] @.str319 = private constant [30 x i8] c"Failed to allocate %u bytes.\0A\00", align 1 ; <[30 x i8]*> [#uses=1] -declare arm_apcscc i32 @puts(i8* nocapture) nounwind +declare i32 @puts(i8* nocapture) nounwind -declare arm_apcscc i32 @getchar() nounwind +declare i32 @getchar() nounwind -define internal arm_apcscc i32 @transpose() nounwind readonly { +define internal i32 @transpose() nounwind readonly { ; CHECK: push entry: %0 = load i32* getelementptr inbounds ([128 x i32]* @columns, i32 0, i32 1), align 4 ; <i32> [#uses=1] @@ -101,6 +101,6 @@ bb7: ; preds = %bb5 ret i32 -128 } -declare arm_apcscc noalias i8* @calloc(i32, i32) nounwind +declare noalias i8* @calloc(i32, i32) nounwind declare void @llvm.memset.i64(i8* nocapture, i8, i64, i32) nounwind diff --git a/test/CodeGen/ARM/2009-09-09-AllOnes.ll b/test/CodeGen/ARM/2009-09-09-AllOnes.ll index f654a16..8522a77 100644 --- a/test/CodeGen/ARM/2009-09-09-AllOnes.ll +++ b/test/CodeGen/ARM/2009-09-09-AllOnes.ll @@ -2,7 +2,7 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32" target triple = "thumbv7-elf" -define arm_apcscc void @foo() { +define void @foo() { entry: %0 = insertelement <4 x i32> undef, i32 -1, i32 3 store <4 x i32> %0, <4 x i32>* undef, align 16 diff --git a/test/CodeGen/ARM/2009-09-24-spill-align.ll b/test/CodeGen/ARM/2009-09-24-spill-align.ll index 5476d5f..8bfd026 100644 --- a/test/CodeGen/ARM/2009-09-24-spill-align.ll +++ b/test/CodeGen/ARM/2009-09-24-spill-align.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s ; pr4926 -define arm_apcscc void @test_vget_lanep16() nounwind { +define void @test_vget_lanep16() nounwind { entry: %arg0_poly16x4_t = alloca <4 x i16> ; <<4 x i16>*> [#uses=1] %out_poly16_t = alloca i16 ; <i16*> [#uses=1] diff --git a/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll b/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll index 53bd668..4aa879d 100644 --- a/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll +++ b/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll @@ -3,7 +3,7 @@ %0 = type { double, double } -define arm_aapcscc void @foo(%0* noalias nocapture sret %agg.result, double %x.0, double %y.0) nounwind { +define void @foo(%0* noalias nocapture sret %agg.result, double %x.0, double %y.0) nounwind { ; CHECK: foo: ; CHECK: bl __adddf3 ; CHECK-NOT: strd diff --git a/test/CodeGen/ARM/2009-10-27-double-align.ll b/test/CodeGen/ARM/2009-10-27-double-align.ll index f17d059..c31b116 100644 --- a/test/CodeGen/ARM/2009-10-27-double-align.ll +++ b/test/CodeGen/ARM/2009-10-27-double-align.ll @@ -2,13 +2,13 @@ @.str = private constant [1 x i8] zeroinitializer, align 1 -define arm_aapcscc void @g() { +define void @g() { entry: ;CHECK: [sp, #8] ;CHECK: [sp, #12] ;CHECK: [sp] - tail call arm_aapcscc void (i8*, ...)* @f(i8* getelementptr ([1 x i8]* @.str, i32 0, i32 0), i32 1, double 2.000000e+00, i32 3, double 4.000000e+00) + tail call void (i8*, ...)* @f(i8* getelementptr ([1 x i8]* @.str, i32 0, i32 0), i32 1, double 2.000000e+00, i32 3, double 4.000000e+00) ret void } -declare arm_aapcscc void @f(i8*, ...) +declare void @f(i8*, ...) diff --git a/test/CodeGen/ARM/2009-11-01-NeonMoves.ll b/test/CodeGen/ARM/2009-11-01-NeonMoves.ll index 62f3786..34f7519 100644 --- a/test/CodeGen/ARM/2009-11-01-NeonMoves.ll +++ b/test/CodeGen/ARM/2009-11-01-NeonMoves.ll @@ -11,11 +11,11 @@ entry: %0 = getelementptr inbounds %foo* %quat_addr, i32 0, i32 0 ; <<4 x float>*> [#uses=1] store <4 x float> %quat.0, <4 x float>* %0 %1 = call arm_aapcs_vfpcc <4 x float> @quux(%foo* %quat_addr) nounwind ; <<4 x float>> [#uses=3] -;CHECK: vmov.f32 -;CHECK: vmov.f32 %2 = fmul <4 x float> %1, %1 ; <<4 x float>> [#uses=2] %3 = shufflevector <4 x float> %2, <4 x float> undef, <2 x i32> <i32 0, i32 1> ; <<2 x float>> [#uses=1] %4 = shufflevector <4 x float> %2, <4 x float> undef, <2 x i32> <i32 2, i32 3> ; <<2 x float>> [#uses=1] +;CHECK-NOT: vmov +;CHECK: vpadd %5 = call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> %3, <2 x float> %4) nounwind ; <<2 x float>> [#uses=2] %6 = call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> %5, <2 x float> %5) nounwind ; <<2 x float>> [#uses=2] %7 = shufflevector <2 x float> %6, <2 x float> %6, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=2] diff --git a/test/CodeGen/ARM/2009-12-02-vtrn-undef.ll b/test/CodeGen/ARM/2009-12-02-vtrn-undef.ll index a737591..198faeb 100644 --- a/test/CodeGen/ARM/2009-12-02-vtrn-undef.ll +++ b/test/CodeGen/ARM/2009-12-02-vtrn-undef.ll @@ -6,7 +6,7 @@ target triple = "armv7-apple-darwin10" %struct.int16x8_t = type { <8 x i16> } %struct.int16x8x2_t = type { [2 x %struct.int16x8_t] } -define arm_apcscc void @t(%struct.int16x8x2_t* noalias nocapture sret %agg.result, <8 x i16> %tmp.0, %struct.int16x8x2_t* nocapture %dst) nounwind { +define void @t(%struct.int16x8x2_t* noalias nocapture sret %agg.result, <8 x i16> %tmp.0, %struct.int16x8x2_t* nocapture %dst) nounwind { entry: ;CHECK: vtrn.16 %0 = shufflevector <8 x i16> %tmp.0, <8 x i16> undef, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6> diff --git a/test/CodeGen/ARM/2010-04-09-NeonSelect.ll b/test/CodeGen/ARM/2010-04-09-NeonSelect.ll index 71e0b0a..89d6a68 100644 --- a/test/CodeGen/ARM/2010-04-09-NeonSelect.ll +++ b/test/CodeGen/ARM/2010-04-09-NeonSelect.ll @@ -1,7 +1,7 @@ ; RUN: llc -march=arm -mattr=+neon < %s ; Radar 7770501: Don't crash on SELECT and SELECT_CC with NEON vector values. -define arm_apcscc void @vDSP_FFT16_copv(float* nocapture %O, float* nocapture %I, i32 %Direction) nounwind { +define void @vDSP_FFT16_copv(float* nocapture %O, float* nocapture %I, i32 %Direction) nounwind { entry: %.22 = select i1 undef, <4 x float> undef, <4 x float> zeroinitializer ; <<4 x float>> [#uses=1] %0 = fadd <4 x float> undef, %.22 ; <<4 x float>> [#uses=1] diff --git a/test/CodeGen/ARM/2010-04-13-v2f64SplitArg.ll b/test/CodeGen/ARM/2010-04-13-v2f64SplitArg.ll index 4f71b83..1354c79 100644 --- a/test/CodeGen/ARM/2010-04-13-v2f64SplitArg.ll +++ b/test/CodeGen/ARM/2010-04-13-v2f64SplitArg.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -mtriple=arm-apple-darwin -mcpu=cortex-a8 ; Radar 7855014 -define arm_apcscc void @test1(i32 %f0, i32 %f1, i32 %f2, <4 x i32> %f3) nounwind { +define void @test1(i32 %f0, i32 %f1, i32 %f2, <4 x i32> %f3) nounwind { entry: unreachable } diff --git a/test/CodeGen/ARM/2010-04-14-SplitVector.ll b/test/CodeGen/ARM/2010-04-14-SplitVector.ll index 42f9852..5d0c3cf 100644 --- a/test/CodeGen/ARM/2010-04-14-SplitVector.ll +++ b/test/CodeGen/ARM/2010-04-14-SplitVector.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mcpu=arm1136jf-s ; Radar 7854640 -define arm_apcscc void @test() nounwind { +define void @test() nounwind { bb: br i1 undef, label %bb9, label %bb10 diff --git a/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll b/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll index ed7bca8..05581c3 100644 --- a/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll +++ b/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll @@ -3,7 +3,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64-n32" target triple = "armv4t-apple-darwin10" -define hidden arm_apcscc i32 @__addvsi3(i32 %a, i32 %b) nounwind { +define hidden i32 @__addvsi3(i32 %a, i32 %b) nounwind { entry: tail call void @llvm.dbg.value(metadata !{i32 %b}, i64 0, metadata !0) %0 = add nsw i32 %b, %a, !dbg !9 ; <i32> [#uses=1] diff --git a/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll b/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll index b158afd..9461643 100644 --- a/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll +++ b/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll @@ -1,4 +1,3 @@ -; RUN: llc < %s -O0 -verify-machineinstrs -regalloc=local ; RUN: llc < %s -O0 -verify-machineinstrs -regalloc=fast ; rdar://problem/7948106 ;; This test would spill %R4 before the call to zz, but it forgot to move the @@ -11,7 +10,7 @@ target triple = "armv6-apple-darwin" @.str = external constant [1 x i8] ; <[1 x i8]*> [#uses=1] -define arm_apcscc void @yy(%struct.q* %qq) nounwind { +define void @yy(%struct.q* %qq) nounwind { entry: %vla6 = alloca i8, i32 undef, align 1 ; <i8*> [#uses=1] %vla10 = alloca i8, i32 undef, align 1 ; <i8*> [#uses=1] @@ -20,18 +19,18 @@ entry: %tmp21 = load i32* undef ; <i32> [#uses=1] %0 = mul i32 1, %tmp21 ; <i32> [#uses=1] %vla22 = alloca i8, i32 %0, align 1 ; <i8*> [#uses=1] - call arm_apcscc void (...)* @zz(i8* getelementptr inbounds ([1 x i8]* @.str, i32 0, i32 0), i32 2, i32 1) + call void (...)* @zz(i8* getelementptr inbounds ([1 x i8]* @.str, i32 0, i32 0), i32 2, i32 1) br i1 undef, label %if.then, label %if.end36 if.then: ; preds = %entry - %call = call arm_apcscc i32 (...)* @x(%struct.q* undef, i8* undef, i8* %vla6, i8* %vla10, i32 undef) ; <i32> [#uses=0] - %call35 = call arm_apcscc i32 (...)* @x(%struct.q* undef, i8* %vla14, i8* %vla18, i8* %vla22, i32 undef) ; <i32> [#uses=0] + %call = call i32 (...)* @x(%struct.q* undef, i8* undef, i8* %vla6, i8* %vla10, i32 undef) ; <i32> [#uses=0] + %call35 = call i32 (...)* @x(%struct.q* undef, i8* %vla14, i8* %vla18, i8* %vla22, i32 undef) ; <i32> [#uses=0] unreachable if.end36: ; preds = %entry ret void } -declare arm_apcscc void @zz(...) +declare void @zz(...) -declare arm_apcscc i32 @x(...) +declare i32 @x(...) diff --git a/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll b/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll index 9907228..5ad1c09 100644 --- a/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll +++ b/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll @@ -4,7 +4,7 @@ %struct.foo = type { i64, i64 } -define arm_apcscc zeroext i8 @t(%struct.foo* %this) noreturn optsize { +define zeroext i8 @t(%struct.foo* %this) noreturn optsize { entry: ; ARM: t: ; ARM: str r0, [r1], r0 diff --git a/test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll b/test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll index b6fbf9b..ff60fa8 100644 --- a/test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll +++ b/test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon -O0 +; RUN: llc < %s -march=arm -mattr=+neon -O0 -regalloc=linearscan ; This test would crash the rewriter when trying to handle a spill after one of ; the @llvm.arm.neon.vld3.v8i8 defined three parts of a register. diff --git a/test/CodeGen/ARM/2010-05-21-BuildVector.ll b/test/CodeGen/ARM/2010-05-21-BuildVector.ll index 6b19490..ce959d1 100644 --- a/test/CodeGen/ARM/2010-05-21-BuildVector.ll +++ b/test/CodeGen/ARM/2010-05-21-BuildVector.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s ; Radar 7872877 -define arm_apcscc void @test(float* %fltp, i32 %packedValue, float* %table) nounwind { +define void @test(float* %fltp, i32 %packedValue, float* %table) nounwind { entry: %0 = load float* %fltp %1 = insertelement <4 x float> undef, float %0, i32 0 diff --git a/test/CodeGen/ARM/2010-06-11-vmovdrr-bitcast.ll b/test/CodeGen/ARM/2010-06-11-vmovdrr-bitcast.ll new file mode 100644 index 0000000..e4f2099 --- /dev/null +++ b/test/CodeGen/ARM/2010-06-11-vmovdrr-bitcast.ll @@ -0,0 +1,19 @@ +; RUN: llc < %s -march=arm -mattr=+neon +; Radar 8084742 + +%struct.__int8x8x2_t = type { [2 x <8 x i8>] } + +define void @foo(%struct.__int8x8x2_t* nocapture %a, i8* %b) nounwind { +entry: + %0 = bitcast %struct.__int8x8x2_t* %a to i128* ; <i128*> [#uses=1] + %srcval = load i128* %0, align 8 ; <i128> [#uses=2] + %tmp6 = trunc i128 %srcval to i64 ; <i64> [#uses=1] + %tmp8 = lshr i128 %srcval, 64 ; <i128> [#uses=1] + %tmp9 = trunc i128 %tmp8 to i64 ; <i64> [#uses=1] + %tmp16.i = bitcast i64 %tmp6 to <8 x i8> ; <<8 x i8>> [#uses=1] + %tmp20.i = bitcast i64 %tmp9 to <8 x i8> ; <<8 x i8>> [#uses=1] + tail call void @llvm.arm.neon.vst2.v8i8(i8* %b, <8 x i8> %tmp16.i, <8 x i8> %tmp20.i) nounwind + ret void +} + +declare void @llvm.arm.neon.vst2.v8i8(i8*, <8 x i8>, <8 x i8>) nounwind diff --git a/test/CodeGen/ARM/2010-06-21-LdStMultipleBug.ll b/test/CodeGen/ARM/2010-06-21-LdStMultipleBug.ll new file mode 100644 index 0000000..816a6d4 --- /dev/null +++ b/test/CodeGen/ARM/2010-06-21-LdStMultipleBug.ll @@ -0,0 +1,148 @@ +; RUN: llc < %s -mtriple=armv7-apple-darwin -O3 -mcpu=arm1136jf-s +; PR7421 + +%struct.CONTENTBOX = type { i32, i32, i32, i32, i32 } +%struct.FILE = type { i8* } +%struct.tilebox = type { %struct.tilebox*, double, double, double, double, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } +%struct.UNCOMBOX = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } +%struct.cellbox = type { i8*, i32, i32, i32, [9 x i32], i32, i32, i32, i32, i32, i32, i32, double, double, double, double, double, i32, i32, %struct.CONTENTBOX*, %struct.UNCOMBOX*, [8 x %struct.tilebox*] } +%struct.termbox = type { %struct.termbox*, i32, i32, i32, i32, i32 } + +@.str2708 = external constant [14 x i8], align 4 ; <[14 x i8]*> [#uses=1] + +define void @TW_oldinput(%struct.FILE* nocapture %fp) nounwind { +entry: + %xcenter = alloca i32, align 4 ; <i32*> [#uses=2] + %0 = call i32 (%struct.FILE*, i8*, ...)* @fscanf(%struct.FILE* %fp, i8* getelementptr inbounds ([14 x i8]* @.str2708, i32 0, i32 0), i32* undef, i32* undef, i32* %xcenter, i32* null) nounwind ; <i32> [#uses=1] + %1 = icmp eq i32 %0, 4 ; <i1> [#uses=1] + br i1 %1, label %bb, label %return + +bb: ; preds = %bb445, %entry + %2 = load %struct.cellbox** undef, align 4 ; <%struct.cellbox*> [#uses=2] + %3 = getelementptr inbounds %struct.cellbox* %2, i32 0, i32 3 ; <i32*> [#uses=1] + store i32 undef, i32* %3, align 4 + %4 = load i32* undef, align 4 ; <i32> [#uses=3] + %5 = icmp eq i32 undef, 1 ; <i1> [#uses=1] + br i1 %5, label %bb10, label %bb445 + +bb10: ; preds = %bb + br i1 undef, label %bb11, label %bb445 + +bb11: ; preds = %bb10 + %6 = load %struct.tilebox** undef, align 4 ; <%struct.tilebox*> [#uses=3] + %7 = load %struct.termbox** null, align 4 ; <%struct.termbox*> [#uses=1] + %8 = getelementptr inbounds %struct.tilebox* %6, i32 0, i32 13 ; <i32*> [#uses=1] + %9 = load i32* %8, align 4 ; <i32> [#uses=3] + %10 = getelementptr inbounds %struct.tilebox* %6, i32 0, i32 15 ; <i32*> [#uses=1] + %11 = load i32* %10, align 4 ; <i32> [#uses=1] + br i1 false, label %bb12, label %bb13 + +bb12: ; preds = %bb11 + unreachable + +bb13: ; preds = %bb11 + %iftmp.40.0.neg = sdiv i32 0, -2 ; <i32> [#uses=2] + %12 = sub nsw i32 0, %9 ; <i32> [#uses=1] + %13 = sitofp i32 %12 to double ; <double> [#uses=1] + %14 = fdiv double %13, 0.000000e+00 ; <double> [#uses=1] + %15 = fptosi double %14 to i32 ; <i32> [#uses=1] + %iftmp.41.0.in = add i32 0, %15 ; <i32> [#uses=1] + %iftmp.41.0.neg = sdiv i32 %iftmp.41.0.in, -2 ; <i32> [#uses=3] + br i1 undef, label %bb43.loopexit, label %bb21 + +bb21: ; preds = %bb13 + %16 = fptosi double undef to i32 ; <i32> [#uses=1] + %17 = fsub double undef, 0.000000e+00 ; <double> [#uses=1] + %not.460 = fcmp oge double %17, 5.000000e-01 ; <i1> [#uses=1] + %18 = zext i1 %not.460 to i32 ; <i32> [#uses=1] + %iftmp.42.0 = add i32 %16, %iftmp.41.0.neg ; <i32> [#uses=1] + %19 = add i32 %iftmp.42.0, %18 ; <i32> [#uses=1] + store i32 %19, i32* undef, align 4 + %20 = sub nsw i32 0, %9 ; <i32> [#uses=1] + %21 = sitofp i32 %20 to double ; <double> [#uses=1] + %22 = fdiv double %21, 0.000000e+00 ; <double> [#uses=2] + %23 = fptosi double %22 to i32 ; <i32> [#uses=1] + %24 = fsub double %22, undef ; <double> [#uses=1] + %not.461 = fcmp oge double %24, 5.000000e-01 ; <i1> [#uses=1] + %25 = zext i1 %not.461 to i32 ; <i32> [#uses=1] + %iftmp.43.0 = add i32 %23, %iftmp.41.0.neg ; <i32> [#uses=1] + %26 = add i32 %iftmp.43.0, %25 ; <i32> [#uses=1] + %27 = getelementptr inbounds %struct.tilebox* %6, i32 0, i32 10 ; <i32*> [#uses=1] + store i32 %26, i32* %27, align 4 + %28 = fptosi double undef to i32 ; <i32> [#uses=1] + %iftmp.45.0 = add i32 %28, %iftmp.40.0.neg ; <i32> [#uses=1] + %29 = add i32 %iftmp.45.0, 0 ; <i32> [#uses=1] + store i32 %29, i32* undef, align 4 + br label %bb43.loopexit + +bb36: ; preds = %bb43.loopexit, %bb36 + %termptr.0478 = phi %struct.termbox* [ %42, %bb36 ], [ %7, %bb43.loopexit ] ; <%struct.termbox*> [#uses=1] + %30 = load i32* undef, align 4 ; <i32> [#uses=1] + %31 = sub nsw i32 %30, %9 ; <i32> [#uses=1] + %32 = sitofp i32 %31 to double ; <double> [#uses=1] + %33 = fdiv double %32, 0.000000e+00 ; <double> [#uses=1] + %34 = fptosi double %33 to i32 ; <i32> [#uses=1] + %iftmp.46.0 = add i32 %34, %iftmp.41.0.neg ; <i32> [#uses=1] + %35 = add i32 %iftmp.46.0, 0 ; <i32> [#uses=1] + store i32 %35, i32* undef, align 4 + %36 = sub nsw i32 0, %11 ; <i32> [#uses=1] + %37 = sitofp i32 %36 to double ; <double> [#uses=1] + %38 = fmul double %37, 0.000000e+00 ; <double> [#uses=1] + %39 = fptosi double %38 to i32 ; <i32> [#uses=1] + %iftmp.47.0 = add i32 %39, %iftmp.40.0.neg ; <i32> [#uses=1] + %40 = add i32 %iftmp.47.0, 0 ; <i32> [#uses=1] + store i32 %40, i32* undef, align 4 + %41 = getelementptr inbounds %struct.termbox* %termptr.0478, i32 0, i32 0 ; <%struct.termbox**> [#uses=1] + %42 = load %struct.termbox** %41, align 4 ; <%struct.termbox*> [#uses=2] + %43 = icmp eq %struct.termbox* %42, null ; <i1> [#uses=1] + br i1 %43, label %bb52.loopexit, label %bb36 + +bb43.loopexit: ; preds = %bb21, %bb13 + br i1 undef, label %bb52.loopexit, label %bb36 + +bb52.loopexit: ; preds = %bb43.loopexit, %bb36 + %44 = icmp eq i32 %4, 0 ; <i1> [#uses=1] + br i1 %44, label %bb.nph485, label %bb54 + +bb54: ; preds = %bb52.loopexit + switch i32 %4, label %bb62 [ + i32 2, label %bb56 + i32 3, label %bb57 + ] + +bb56: ; preds = %bb54 + br label %bb62 + +bb57: ; preds = %bb54 + br label %bb62 + +bb62: ; preds = %bb57, %bb56, %bb54 + unreachable + +bb.nph485: ; preds = %bb52.loopexit + br label %bb248 + +bb248: ; preds = %bb322, %bb.nph485 + %45 = icmp eq i32 undef, %4 ; <i1> [#uses=1] + br i1 %45, label %bb322, label %bb249 + +bb249: ; preds = %bb248 + %46 = getelementptr inbounds %struct.cellbox* %2, i32 0, i32 21, i32 undef ; <%struct.tilebox**> [#uses=1] + %47 = load %struct.tilebox** %46, align 4 ; <%struct.tilebox*> [#uses=1] + %48 = getelementptr inbounds %struct.tilebox* %47, i32 0, i32 11 ; <i32*> [#uses=1] + store i32 undef, i32* %48, align 4 + unreachable + +bb322: ; preds = %bb248 + br i1 undef, label %bb248, label %bb445 + +bb445: ; preds = %bb322, %bb10, %bb + %49 = call i32 (%struct.FILE*, i8*, ...)* @fscanf(%struct.FILE* %fp, i8* getelementptr inbounds ([14 x i8]* @.str2708, i32 0, i32 0), i32* undef, i32* undef, i32* %xcenter, i32* null) nounwind ; <i32> [#uses=1] + %50 = icmp eq i32 %49, 4 ; <i1> [#uses=1] + br i1 %50, label %bb, label %return + +return: ; preds = %bb445, %entry + ret void +} + +declare i32 @fscanf(%struct.FILE* nocapture, i8* nocapture, ...) nounwind diff --git a/test/CodeGen/ARM/2010-06-21-nondarwin-tc.ll b/test/CodeGen/ARM/2010-06-21-nondarwin-tc.ll new file mode 100755 index 0000000..7650d88 --- /dev/null +++ b/test/CodeGen/ARM/2010-06-21-nondarwin-tc.ll @@ -0,0 +1,145 @@ +; RUN: llc < %s -march=arm -mtriple=armv4t-unknown-linux-gnueabi | FileCheck %s +; PR 7433 + +%0 = type { i8*, i8* } +%1 = type { i8*, i8*, i8* } +%"class.llvm::Record" = type { i32, %"class.std::basic_string", %"class.llvm::SMLoc", %"class.std::vector", %"class.std::vector", %"class.std::vector" } +%"class.llvm::RecordVal" = type { %"class.std::basic_string", %"struct.llvm::Init"*, i32, %"struct.llvm::Init"* } +%"class.llvm::SMLoc" = type { i8* } +%"class.llvm::StringInit" = type { [8 x i8], %"class.std::basic_string" } +%"class.std::basic_string" = type { %"class.llvm::SMLoc" } +%"class.std::vector" = type { [12 x i8] } +%"struct.llvm::Init" = type { i32 (...)** } + +@_ZTIN4llvm5RecTyE = external constant %0 ; <%0*> [#uses=1] +@_ZTIN4llvm4InitE = external constant %0 ; <%0*> [#uses=1] +@_ZTIN4llvm11RecordRecTyE = external constant %1 ; <%1*> [#uses=1] +@.str8 = external constant [47 x i8] ; <[47 x i8]*> [#uses=1] +@_ZTIN4llvm9UnsetInitE = external constant %1 ; <%1*> [#uses=1] +@.str51 = external constant [45 x i8] ; <[45 x i8]*> [#uses=1] +@__PRETTY_FUNCTION__._ZNK4llvm7VarInit12getFieldInitERNS_6RecordEPKNS_9RecordValERKSs = external constant [116 x i8] ; <[116 x i8]*> [#uses=1] + +@_ZN4llvm9RecordValC1ERKSsPNS_5RecTyEj = alias void (%"class.llvm::RecordVal"*, %"class.std::basic_string"*, %"struct.llvm::Init"*, i32)* @_ZN4llvm9RecordValC2ERKSsPNS_5RecTyEj ; <void (%"class.llvm::RecordVal"*, %"class.std::basic_string"*, %"struct.llvm::Init"*, i32)*> [#uses=0] + +declare i8* @__dynamic_cast(i8*, i8*, i8*, i32) + +declare void @__assert_fail(i8*, i8*, i32, i8*) noreturn + +declare void @_ZN4llvm9RecordValC2ERKSsPNS_5RecTyEj(%"class.llvm::RecordVal"*, %"class.std::basic_string"*, %"struct.llvm::Init"*, i32) align 2 + +define %"struct.llvm::Init"* @_ZNK4llvm7VarInit12getFieldInitERNS_6RecordEPKNS_9RecordValERKSs(%"class.llvm::StringInit"* %this, %"class.llvm::Record"* %R, %"class.llvm::RecordVal"* %RV, %"class.std::basic_string"* %FieldName) align 2 { +;CHECK: ldmia sp!, {r4, r5, r6, r7, r8, lr} +;CHECK: bx r12 @ TAILCALL +entry: + %.loc = alloca i32 ; <i32*> [#uses=2] + %tmp.i = getelementptr inbounds %"class.llvm::StringInit"* %this, i32 0, i32 0, i32 4 ; <i8*> [#uses=1] + %0 = bitcast i8* %tmp.i to %"struct.llvm::Init"** ; <%"struct.llvm::Init"**> [#uses=1] + %tmp2.i = load %"struct.llvm::Init"** %0 ; <%"struct.llvm::Init"*> [#uses=2] + %1 = icmp eq %"struct.llvm::Init"* %tmp2.i, null ; <i1> [#uses=1] + br i1 %1, label %entry.return_crit_edge, label %tmpbb + +entry.return_crit_edge: ; preds = %entry + br label %return + +tmpbb: ; preds = %entry + %2 = bitcast %"struct.llvm::Init"* %tmp2.i to i8* ; <i8*> [#uses=1] + %3 = tail call i8* @__dynamic_cast(i8* %2, i8* bitcast (%0* @_ZTIN4llvm5RecTyE to i8*), i8* bitcast (%1* @_ZTIN4llvm11RecordRecTyE to i8*), i32 -1) ; <i8*> [#uses=1] + %phitmp = icmp eq i8* %3, null ; <i1> [#uses=1] + br i1 %phitmp, label %.return_crit_edge, label %if.then + +.return_crit_edge: ; preds = %tmpbb + br label %return + +if.then: ; preds = %tmpbb + %tmp2.i.i.i.i = getelementptr inbounds %"class.llvm::StringInit"* %this, i32 0, i32 1, i32 0, i32 0 ; <i8**> [#uses=1] + %tmp3.i.i.i.i = load i8** %tmp2.i.i.i.i ; <i8*> [#uses=2] + %arrayidx.i.i.i.i = getelementptr inbounds i8* %tmp3.i.i.i.i, i32 -12 ; <i8*> [#uses=1] + %tmp.i.i.i = bitcast i8* %arrayidx.i.i.i.i to i32* ; <i32*> [#uses=1] + %tmp2.i.i.i = load i32* %tmp.i.i.i ; <i32> [#uses=1] + %tmp.i5 = getelementptr inbounds %"class.llvm::Record"* %R, i32 0, i32 4 ; <%"class.std::vector"*> [#uses=1] + %tmp2.i.i = getelementptr inbounds %"class.llvm::Record"* %R, i32 0, i32 4, i32 0, i32 4 ; <i8*> [#uses=1] + %4 = bitcast i8* %tmp2.i.i to %"class.llvm::RecordVal"** ; <%"class.llvm::RecordVal"**> [#uses=1] + %tmp3.i.i6 = load %"class.llvm::RecordVal"** %4 ; <%"class.llvm::RecordVal"*> [#uses=1] + %tmp5.i.i = bitcast %"class.std::vector"* %tmp.i5 to %"class.llvm::RecordVal"** ; <%"class.llvm::RecordVal"**> [#uses=1] + %tmp6.i.i = load %"class.llvm::RecordVal"** %tmp5.i.i ; <%"class.llvm::RecordVal"*> [#uses=5] + %sub.ptr.lhs.cast.i.i = ptrtoint %"class.llvm::RecordVal"* %tmp3.i.i6 to i32 ; <i32> [#uses=1] + %sub.ptr.rhs.cast.i.i = ptrtoint %"class.llvm::RecordVal"* %tmp6.i.i to i32 ; <i32> [#uses=1] + %sub.ptr.sub.i.i = sub i32 %sub.ptr.lhs.cast.i.i, %sub.ptr.rhs.cast.i.i ; <i32> [#uses=1] + %sub.ptr.div.i.i = ashr i32 %sub.ptr.sub.i.i, 4 ; <i32> [#uses=1] + br label %codeRepl + +codeRepl: ; preds = %if.then + %targetBlock = call i1 @_ZNK4llvm7VarInit12getFieldInitERNS_6RecordEPKNS_9RecordValERKSs_for.cond.i(i32 %sub.ptr.div.i.i, %"class.llvm::RecordVal"* %tmp6.i.i, i32 %tmp2.i.i.i, i8* %tmp3.i.i.i.i, i32* %.loc) ; <i1> [#uses=1] + %.reload = load i32* %.loc ; <i32> [#uses=3] + br i1 %targetBlock, label %for.cond.i.return_crit_edge, label %_ZN4llvm6Record8getValueENS_9StringRefE.exit + +for.cond.i.return_crit_edge: ; preds = %codeRepl + br label %return + +_ZN4llvm6Record8getValueENS_9StringRefE.exit: ; preds = %codeRepl + %add.ptr.i.i = getelementptr inbounds %"class.llvm::RecordVal"* %tmp6.i.i, i32 %.reload ; <%"class.llvm::RecordVal"*> [#uses=2] + %tobool5 = icmp eq %"class.llvm::RecordVal"* %add.ptr.i.i, null ; <i1> [#uses=1] + br i1 %tobool5, label %_ZN4llvm6Record8getValueENS_9StringRefE.exit.return_crit_edge, label %if.then6 + +_ZN4llvm6Record8getValueENS_9StringRefE.exit.return_crit_edge: ; preds = %_ZN4llvm6Record8getValueENS_9StringRefE.exit + br label %return + +if.then6: ; preds = %_ZN4llvm6Record8getValueENS_9StringRefE.exit + %cmp = icmp eq %"class.llvm::RecordVal"* %add.ptr.i.i, %RV ; <i1> [#uses=1] + br i1 %cmp, label %if.then6.if.end_crit_edge, label %land.lhs.true + +if.then6.if.end_crit_edge: ; preds = %if.then6 + br label %if.end + +land.lhs.true: ; preds = %if.then6 + %tobool10 = icmp eq %"class.llvm::RecordVal"* %RV, null ; <i1> [#uses=1] + br i1 %tobool10, label %lor.lhs.false, label %land.lhs.true.return_crit_edge + +land.lhs.true.return_crit_edge: ; preds = %land.lhs.true + br label %return + +lor.lhs.false: ; preds = %land.lhs.true + %tmp.i3 = getelementptr inbounds %"class.llvm::RecordVal"* %tmp6.i.i, i32 %.reload, i32 3 ; <%"struct.llvm::Init"**> [#uses=1] + %tmp2.i4 = load %"struct.llvm::Init"** %tmp.i3 ; <%"struct.llvm::Init"*> [#uses=2] + %5 = icmp eq %"struct.llvm::Init"* %tmp2.i4, null ; <i1> [#uses=1] + br i1 %5, label %lor.lhs.false.if.end_crit_edge, label %tmpbb1 + +lor.lhs.false.if.end_crit_edge: ; preds = %lor.lhs.false + br label %if.end + +tmpbb1: ; preds = %lor.lhs.false + %6 = bitcast %"struct.llvm::Init"* %tmp2.i4 to i8* ; <i8*> [#uses=1] + %7 = tail call i8* @__dynamic_cast(i8* %6, i8* bitcast (%0* @_ZTIN4llvm4InitE to i8*), i8* bitcast (%1* @_ZTIN4llvm9UnsetInitE to i8*), i32 -1) ; <i8*> [#uses=1] + %phitmp32 = icmp eq i8* %7, null ; <i1> [#uses=1] + br i1 %phitmp32, label %.if.end_crit_edge, label %.return_crit_edge1 + +.return_crit_edge1: ; preds = %tmpbb1 + br label %return + +.if.end_crit_edge: ; preds = %tmpbb1 + br label %if.end + +if.end: ; preds = %.if.end_crit_edge, %lor.lhs.false.if.end_crit_edge, %if.then6.if.end_crit_edge + %tmp.i1 = getelementptr inbounds %"class.llvm::RecordVal"* %tmp6.i.i, i32 %.reload, i32 3 ; <%"struct.llvm::Init"**> [#uses=1] + %tmp2.i2 = load %"struct.llvm::Init"** %tmp.i1 ; <%"struct.llvm::Init"*> [#uses=3] + %8 = bitcast %"class.llvm::StringInit"* %this to %"struct.llvm::Init"* ; <%"struct.llvm::Init"*> [#uses=1] + %cmp19 = icmp eq %"struct.llvm::Init"* %tmp2.i2, %8 ; <i1> [#uses=1] + br i1 %cmp19, label %cond.false, label %cond.end + +cond.false: ; preds = %if.end + tail call void @__assert_fail(i8* getelementptr inbounds ([45 x i8]* @.str51, i32 0, i32 0), i8* getelementptr inbounds ([47 x i8]* @.str8, i32 0, i32 0), i32 1141, i8* getelementptr inbounds ([116 x i8]* @__PRETTY_FUNCTION__._ZNK4llvm7VarInit12getFieldInitERNS_6RecordEPKNS_9RecordValERKSs, i32 0, i32 0)) noreturn + unreachable + +cond.end: ; preds = %if.end + %9 = bitcast %"struct.llvm::Init"* %tmp2.i2 to %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)*** ; <%"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)***> [#uses=1] + %10 = load %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)*** %9 ; <%"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)**> [#uses=1] + %vfn = getelementptr inbounds %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)** %10, i32 8 ; <%"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)**> [#uses=1] + %11 = load %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)** %vfn ; <%"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)*> [#uses=1] + %call25 = tail call %"struct.llvm::Init"* %11(%"struct.llvm::Init"* %tmp2.i2, %"class.llvm::Record"* %R, %"class.llvm::RecordVal"* %RV, %"class.std::basic_string"* %FieldName) ; <%"struct.llvm::Init"*> [#uses=1] + ret %"struct.llvm::Init"* %call25 + +return: ; preds = %.return_crit_edge1, %land.lhs.true.return_crit_edge, %_ZN4llvm6Record8getValueENS_9StringRefE.exit.return_crit_edge, %for.cond.i.return_crit_edge, %.return_crit_edge, %entry.return_crit_edge + ret %"struct.llvm::Init"* null +} + +declare i1 @_ZNK4llvm7VarInit12getFieldInitERNS_6RecordEPKNS_9RecordValERKSs_for.cond.i(i32, %"class.llvm::RecordVal"*, i32, i8*, i32*) diff --git a/test/CodeGen/ARM/2010-06-25-Thumb2ITInvalidIterator.ll b/test/CodeGen/ARM/2010-06-25-Thumb2ITInvalidIterator.ll new file mode 100644 index 0000000..cdb11c7 --- /dev/null +++ b/test/CodeGen/ARM/2010-06-25-Thumb2ITInvalidIterator.ll @@ -0,0 +1,75 @@ +; RUN: llc < %s + +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32" +target triple = "thumbv7-apple-darwin3.0.0-iphoneos" + +@length = common global i32 0, align 4 ; <i32*> [#uses=1] + +define void @x0(i8* nocapture %buf, i32 %nbytes) nounwind optsize { +entry: + tail call void @llvm.dbg.value(metadata !{i8* %buf}, i64 0, metadata !0), !dbg !15 + tail call void @llvm.dbg.value(metadata !{i32 %nbytes}, i64 0, metadata !8), !dbg !16 + %tmp = load i32* @length, !dbg !17 ; <i32> [#uses=3] + %cmp = icmp eq i32 %tmp, -1, !dbg !17 ; <i1> [#uses=1] + %cmp.not = xor i1 %cmp, true ; <i1> [#uses=1] + %cmp3 = icmp ult i32 %tmp, %nbytes, !dbg !17 ; <i1> [#uses=1] + %or.cond = and i1 %cmp.not, %cmp3 ; <i1> [#uses=1] + tail call void @llvm.dbg.value(metadata !{i32 %tmp}, i64 0, metadata !8), !dbg !17 + %nbytes.addr.0 = select i1 %or.cond, i32 %tmp, i32 %nbytes ; <i32> [#uses=1] + tail call void @llvm.dbg.value(metadata !18, i64 0, metadata !10), !dbg !19 + br label %while.cond, !dbg !20 + +while.cond: ; preds = %while.body, %entry + %0 = phi i32 [ 0, %entry ], [ %inc, %while.body ] ; <i32> [#uses=3] + %buf.addr.0 = getelementptr i8* %buf, i32 %0 ; <i8*> [#uses=1] + %cmp7 = icmp ult i32 %0, %nbytes.addr.0, !dbg !20 ; <i1> [#uses=1] + br i1 %cmp7, label %land.rhs, label %while.end, !dbg !20 + +land.rhs: ; preds = %while.cond + %call = tail call i32 @x1() nounwind optsize, !dbg !20 ; <i32> [#uses=2] + %cmp9 = icmp eq i32 %call, -1, !dbg !20 ; <i1> [#uses=1] + br i1 %cmp9, label %while.end, label %while.body, !dbg !20 + +while.body: ; preds = %land.rhs + %conv = trunc i32 %call to i8, !dbg !21 ; <i8> [#uses=1] + store i8 %conv, i8* %buf.addr.0, !dbg !21 + %inc = add i32 %0, 1, !dbg !23 ; <i32> [#uses=1] + br label %while.cond, !dbg !24 + +while.end: ; preds = %land.rhs, %while.cond + ret void, !dbg !25 +} + +declare i32 @x1() optsize + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone + +!llvm.dbg.lv.fn = !{!0, !8, !10, !12} +!llvm.dbg.gv = !{!14} + +!0 = metadata !{i32 524545, metadata !1, metadata !"buf", metadata !2, i32 4, metadata !6} ; [ DW_TAG_arg_variable ] +!1 = metadata !{i32 524334, i32 0, metadata !2, metadata !"x0", metadata !"x0", metadata !"x0", metadata !2, i32 5, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ] +!2 = metadata !{i32 524329, metadata !"t.c", metadata !"/private/tmp", metadata !3} ; [ DW_TAG_file_type ] +!3 = metadata !{i32 524305, i32 0, i32 12, metadata !"t.c", metadata !".", metadata !"clang 2.0", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!4 = metadata !{i32 524309, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ] +!5 = metadata !{null} +!6 = metadata !{i32 524303, metadata !2, metadata !"", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !7} ; [ DW_TAG_pointer_type ] +!7 = metadata !{i32 524324, metadata !2, metadata !"unsigned char", metadata !2, i32 0, i64 8, i64 8, i64 0, i32 0, i32 8} ; [ DW_TAG_base_type ] +!8 = metadata !{i32 524545, metadata !1, metadata !"nbytes", metadata !2, i32 4, metadata !9} ; [ DW_TAG_arg_variable ] +!9 = metadata !{i32 524324, metadata !2, metadata !"unsigned long", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] +!10 = metadata !{i32 524544, metadata !11, metadata !"nread", metadata !2, i32 6, metadata !9} ; [ DW_TAG_auto_variable ] +!11 = metadata !{i32 524299, metadata !1, i32 5, i32 1} ; [ DW_TAG_lexical_block ] +!12 = metadata !{i32 524544, metadata !11, metadata !"c", metadata !2, i32 7, metadata !13} ; [ DW_TAG_auto_variable ] +!13 = metadata !{i32 524324, metadata !2, metadata !"int", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!14 = metadata !{i32 524340, i32 0, metadata !2, metadata !"length", metadata !"length", metadata !"length", metadata !2, i32 1, metadata !13, i1 false, i1 true, i32* @length} ; [ DW_TAG_variable ] +!15 = metadata !{i32 4, i32 24, metadata !1, null} +!16 = metadata !{i32 4, i32 43, metadata !1, null} +!17 = metadata !{i32 9, i32 2, metadata !11, null} +!18 = metadata !{i32 0} +!19 = metadata !{i32 10, i32 2, metadata !11, null} +!20 = metadata !{i32 11, i32 2, metadata !11, null} +!21 = metadata !{i32 12, i32 3, metadata !22, null} +!22 = metadata !{i32 524299, metadata !11, i32 11, i32 45} ; [ DW_TAG_lexical_block ] +!23 = metadata !{i32 13, i32 3, metadata !22, null} +!24 = metadata !{i32 14, i32 2, metadata !22, null} +!25 = metadata !{i32 15, i32 1, metadata !11, null} diff --git a/test/CodeGen/ARM/2010-06-28-DAGCombineUndef.ll b/test/CodeGen/ARM/2010-06-28-DAGCombineUndef.ll new file mode 100644 index 0000000..ad2810b --- /dev/null +++ b/test/CodeGen/ARM/2010-06-28-DAGCombineUndef.ll @@ -0,0 +1,10 @@ +; RUN: llc < %s -march=arm -mattr=+neon + +define void @main() nounwind { +entry: + store <2 x i64> undef, <2 x i64>* undef, align 16 + %0 = load <16 x i8>* undef, align 16 ; <<16 x i8>> [#uses=1] + %1 = or <16 x i8> zeroinitializer, %0 ; <<16 x i8>> [#uses=1] + store <16 x i8> %1, <16 x i8>* undef, align 16 + ret void +} diff --git a/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll b/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll new file mode 100644 index 0000000..0c5b180 --- /dev/null +++ b/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll @@ -0,0 +1,25 @@ +; RUN: llc < %s -O0 -mcpu=cortex-a8 | FileCheck %s +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32" +target triple = "thumbv7-apple-darwin10" + +; This tests the fast register allocator's handling of partial redefines: +; +; %reg1028:dsub_0<def>, %reg1028:dsub_1<def> = VLD1q64 %reg1025... +; %reg1030:dsub_1<def> = COPY %reg1028:dsub_0<kill> +; +; %reg1028 gets allocated %Q0, and if %reg1030 is reloaded for the partial +; redef, it cannot also get %Q0. + +; CHECK: vld1.64 {d0, d1}, [r{{.}}] +; CHECK-NOT: vld1.64 {d0, d1} +; CHECK: vmov.f64 d3, d0 + +define i32 @test(i8* %arg) nounwind { +entry: + %0 = call <2 x i64> @llvm.arm.neon.vld1.v2i64(i8* %arg) + %1 = shufflevector <2 x i64> undef, <2 x i64> %0, <2 x i32> <i32 1, i32 2> + store <2 x i64> %1, <2 x i64>* undef, align 16 + ret i32 undef +} + +declare <2 x i64> @llvm.arm.neon.vld1.v2i64(i8*) nounwind readonly diff --git a/test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll b/test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll new file mode 100644 index 0000000..984583e --- /dev/null +++ b/test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll @@ -0,0 +1,15 @@ +; RUN: llc < %s -march=arm -mattr=+neon + +@.str271 = external constant [21 x i8], align 4 ; <[21 x i8]*> [#uses=1] +@llvm.used = appending global [1 x i8*] [i8* bitcast (i32 (i32, i8**)* @main to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] + +define i32 @main(i32 %argc, i8** %argv) nounwind { +entry: + %0 = shufflevector <2 x i64> undef, <2 x i64> zeroinitializer, <2 x i32> <i32 1, i32 2> ; <<2 x i64>> [#uses=1] + store <2 x i64> %0, <2 x i64>* undef, align 16 + %val4723 = load <8 x i16>* undef ; <<8 x i16>> [#uses=1] + call void @PrintShortX(i8* getelementptr inbounds ([21 x i8]* @.str271, i32 0, i32 0), <8 x i16> %val4723, i32 0) nounwind + ret i32 undef +} + +declare void @PrintShortX(i8*, <8 x i16>, i32) nounwind diff --git a/test/CodeGen/ARM/alloca.ll b/test/CodeGen/ARM/alloca.ll index 82a8c98..4a0835a 100644 --- a/test/CodeGen/ARM/alloca.ll +++ b/test/CodeGen/ARM/alloca.ll @@ -2,11 +2,11 @@ define void @f(i32 %a) { entry: -; CHECK: mov r11, sp +; CHECK: add r11, sp, #4 %tmp = alloca i8, i32 %a ; <i8*> [#uses=1] call void @g( i8* %tmp, i32 %a, i32 1, i32 2, i32 3 ) ret void -; CHECK: mov sp, r11 +; CHECK: sub sp, r11, #4 } declare void @g(i8*, i32, i32, i32, i32) diff --git a/test/CodeGen/ARM/arm-frameaddr.ll b/test/CodeGen/ARM/arm-frameaddr.ll index 1c7ac25..2cf1422 100644 --- a/test/CodeGen/ARM/arm-frameaddr.ll +++ b/test/CodeGen/ARM/arm-frameaddr.ll @@ -3,7 +3,7 @@ ; PR4344 ; PR4416 -define arm_aapcscc i8* @t() nounwind { +define i8* @t() nounwind { entry: ; DARWIN: t: ; DARWIN: mov r0, r7 diff --git a/test/CodeGen/ARM/arm-returnaddr.ll b/test/CodeGen/ARM/arm-returnaddr.ll index 2c8f2ab..382a183 100644 --- a/test/CodeGen/ARM/arm-returnaddr.ll +++ b/test/CodeGen/ARM/arm-returnaddr.ll @@ -1,19 +1,21 @@ ; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s -; RUN: llc < %s -mtriple=thumbv6-apple-darwin +; RUN: llc < %s -mtriple=thumbv6-apple-darwin | FileCheck %s ; rdar://8015977 ; rdar://8020118 -define arm_apcscc i8* @rt0(i32 %x) nounwind readnone { +define i8* @rt0(i32 %x) nounwind readnone { entry: ; CHECK: rt0: +; CHECK: {r7, lr} ; CHECK: mov r0, lr %0 = tail call i8* @llvm.returnaddress(i32 0) ret i8* %0 } -define arm_apcscc i8* @rt2() nounwind readnone { +define i8* @rt2() nounwind readnone { entry: ; CHECK: rt2: +; CHECK: {r7, lr} ; CHECK: ldr r0, [r7] ; CHECK: ldr r0, [r0] ; CHECK: ldr r0, [r0, #4] diff --git a/test/CodeGen/ARM/armv4.ll b/test/CodeGen/ARM/armv4.ll index 49b129da..ef722de 100644 --- a/test/CodeGen/ARM/armv4.ll +++ b/test/CodeGen/ARM/armv4.ll @@ -5,7 +5,7 @@ ; RUN: llc < %s -mtriple=armv4-unknown-eabi | FileCheck %s -check-prefix=ARM ; RUN: llc < %s -mtriple=armv4t-unknown-eabi | FileCheck %s -check-prefix=THUMB -define arm_aapcscc i32 @test(i32 %a) nounwind readnone { +define i32 @test(i32 %a) nounwind readnone { entry: ; ARM: mov pc ; THUMB: bx diff --git a/test/CodeGen/ARM/call-tc.ll b/test/CodeGen/ARM/call-tc.ll new file mode 100644 index 0000000..f1269d5 --- /dev/null +++ b/test/CodeGen/ARM/call-tc.ll @@ -0,0 +1,48 @@ +; RUN: llc < %s -mtriple=arm-apple-darwin -march=arm | FileCheck %s -check-prefix=CHECKV4 +; RUN: llc < %s -march=arm -mtriple=arm-apple-darwin -mattr=+v5t | FileCheck %s -check-prefix=CHECKV5 +; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi\ +; RUN: -relocation-model=pic | FileCheck %s -check-prefix=CHECKELF + +@t = weak global i32 ()* null ; <i32 ()**> [#uses=1] + +declare void @g(i32, i32, i32, i32) + +define void @t1() { +; CHECKELF: t1: +; CHECKELF: PLT + call void @g( i32 1, i32 2, i32 3, i32 4 ) + ret void +} + +define void @t2() { +; CHECKV4: t2: +; CHECKV4: bx r0 @ TAILCALL +; CHECKV5: t2: +; CHECKV5: bx r0 @ TAILCALL + %tmp = load i32 ()** @t ; <i32 ()*> [#uses=1] + %tmp.upgrd.2 = tail call i32 %tmp( ) ; <i32> [#uses=0] + ret void +} + +define i32* @t3(i32, i32, i32*, i32*, i32*) nounwind { +; CHECKV4: t3: +; CHECKV4: bx r{{.*}} +BB0: + %5 = inttoptr i32 %0 to i32* ; <i32*> [#uses=1] + %t35 = volatile load i32* %5 ; <i32> [#uses=1] + %6 = inttoptr i32 %t35 to i32** ; <i32**> [#uses=1] + %7 = getelementptr i32** %6, i32 86 ; <i32**> [#uses=1] + %8 = load i32** %7 ; <i32*> [#uses=1] + %9 = bitcast i32* %8 to i32* (i32, i32*, i32, i32*, i32*, i32*)* ; <i32* (i32, i32*, i32, i32*, i32*, i32*)*> [#uses=1] + %10 = call i32* %9(i32 %0, i32* null, i32 %1, i32* %2, i32* %3, i32* %4) ; <i32*> [#uses=1] + ret i32* %10 +} + +define void @t4() { +; CHECKV4: t4: +; CHECKV4: b _t2 @ TAILCALL +; CHECKV5: t4: +; CHECKV5: b _t2 @ TAILCALL + tail call void @t2( ) ; <i32> [#uses=0] + ret void +} diff --git a/test/CodeGen/ARM/call.ll b/test/CodeGen/ARM/call.ll index c60b75b..c020b6f 100644 --- a/test/CodeGen/ARM/call.ll +++ b/test/CodeGen/ARM/call.ll @@ -8,16 +8,16 @@ declare void @g(i32, i32, i32, i32) define void @f() { -; CHECKV4: mov lr, pc -; CHECKV5: blx ; CHECKELF: PLT call void @g( i32 1, i32 2, i32 3, i32 4 ) ret void } define void @g.upgrd.1() { +; CHECKV4: mov lr, pc +; CHECKV5: blx %tmp = load i32 ()** @t ; <i32 ()*> [#uses=1] - %tmp.upgrd.2 = tail call i32 %tmp( ) ; <i32> [#uses=0] + %tmp.upgrd.2 = call i32 %tmp( ) ; <i32> [#uses=0] ret void } diff --git a/test/CodeGen/ARM/crash-O0.ll b/test/CodeGen/ARM/crash-O0.ll new file mode 100644 index 0000000..8bce4e0 --- /dev/null +++ b/test/CodeGen/ARM/crash-O0.ll @@ -0,0 +1,28 @@ +; RUN: llc < %s -O0 -relocation-model=pic -disable-fp-elim +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64-n32" +target triple = "armv6-apple-darwin10" + +%struct0 = type { i32, i32 } + +; This function would crash RegAllocFast because it tried to spill %CPSR. +define arm_apcscc void @clobber_cc() nounwind noinline ssp { +entry: + %asmtmp = call %struct0 asm sideeffect "...", "=&r,=&r,r,Ir,r,~{cc},~{memory}"(i32* undef, i32 undef, i32 1) nounwind ; <%0> [#uses=0] + unreachable +} + +@.str523 = private constant [256 x i8] c"<Unknown>\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00", align 4 ; <[256 x i8]*> [#uses=1] +declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind + +; This function uses the scavenger for an ADDri instruction. +; ARMBaseRegisterInfo::estimateRSStackSizeLimit must return a 255 limit. +define arm_apcscc void @scavence_ADDri() nounwind { +entry: + %letter = alloca i8 ; <i8*> [#uses=0] + %prodvers = alloca [256 x i8] ; <[256 x i8]*> [#uses=1] + %buildver = alloca [256 x i8] ; <[256 x i8]*> [#uses=0] + call void @llvm.memcpy.p0i8.p0i8.i32(i8* undef, i8* getelementptr inbounds ([256 x i8]* @.str523, i32 0, i32 0), i32 256, i32 1, i1 false) + %prodvers2 = bitcast [256 x i8]* %prodvers to i8* ; <i8*> [#uses=1] + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %prodvers2, i8* getelementptr inbounds ([256 x i8]* @.str523, i32 0, i32 0), i32 256, i32 1, i1 false) + unreachable +} diff --git a/test/CodeGen/ARM/flag-crash.ll b/test/CodeGen/ARM/flag-crash.ll new file mode 100644 index 0000000..9c61944 --- /dev/null +++ b/test/CodeGen/ARM/flag-crash.ll @@ -0,0 +1,27 @@ +; RUN: llc < %s -O3 -mtriple=thumbv7-apple-darwin10 -mcpu=cortex-a8 -relocation-model=pic +; PR7484 + +%struct.gs_matrix = type { float, i32, float, i32, float, i32, float, i32, float, i32, float, i32 } + +define fastcc void @func(%struct.gs_matrix* nocapture %pm1) nounwind { +entry: + %0 = getelementptr inbounds %struct.gs_matrix* %pm1, i32 0, i32 6 + %1 = load float* %0, align 4 + %2 = getelementptr inbounds %struct.gs_matrix* %pm1, i32 0, i32 8 + %3 = load float* %2, align 4 + %4 = getelementptr inbounds %struct.gs_matrix* %pm1, i32 0, i32 2 + %5 = bitcast float* %4 to i32* + %6 = load i32* %5, align 4 + %7 = or i32 0, %6 + %.mask = and i32 %7, 2147483647 + %8 = icmp eq i32 %.mask, 0 + br i1 %8, label %bb, label %bb11 + +bb: + ret void + +bb11: + %9 = fmul float %1, undef + %10 = fmul float %3, undef + ret void +} diff --git a/test/CodeGen/ARM/fpcmp-opt.ll b/test/CodeGen/ARM/fpcmp-opt.ll new file mode 100644 index 0000000..8016033 --- /dev/null +++ b/test/CodeGen/ARM/fpcmp-opt.ll @@ -0,0 +1,29 @@ +; RUN: llc < %s -march=arm -mattr=+vfp2 -enable-unsafe-fp-math -enable-finite-only-fp-math | FileCheck %s +; rdar://7461510 + +define arm_apcscc i32 @t1(float* %a, float* %b) nounwind { +entry: +; CHECK: t1: +; CHECK-NOT: vldr +; CHECK: ldr +; CHECK: ldr +; CHECK: cmp r0, r1 +; CHECK-NOT: vcmpe.f32 +; CHECK-NOT: vmrs +; CHECK: beq + %0 = load float* %a + %1 = load float* %b + %2 = fcmp une float %0, %1 + br i1 %2, label %bb1, label %bb2 + +bb1: + %3 = call i32 @bar() + ret i32 %3 + +bb2: + %4 = call i32 @foo() + ret i32 %4 +} + +declare i32 @bar() +declare i32 @foo() diff --git a/test/CodeGen/ARM/fpconsts.ll b/test/CodeGen/ARM/fpconsts.ll index 710994d..f1d6a16 100644 --- a/test/CodeGen/ARM/fpconsts.ll +++ b/test/CodeGen/ARM/fpconsts.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=arm -mattr=+vfp3 | FileCheck %s -define arm_apcscc float @t1(float %x) nounwind readnone optsize { +define float @t1(float %x) nounwind readnone optsize { entry: ; CHECK: t1: ; CHECK: vmov.f32 s1, #4.000000e+00 @@ -8,7 +8,7 @@ entry: ret float %0 } -define arm_apcscc double @t2(double %x) nounwind readnone optsize { +define double @t2(double %x) nounwind readnone optsize { entry: ; CHECK: t2: ; CHECK: vmov.f64 d1, #3.000000e+00 @@ -16,7 +16,7 @@ entry: ret double %0 } -define arm_apcscc double @t3(double %x) nounwind readnone optsize { +define double @t3(double %x) nounwind readnone optsize { entry: ; CHECK: t3: ; CHECK: vmov.f64 d1, #-1.300000e+01 @@ -24,7 +24,7 @@ entry: ret double %0 } -define arm_apcscc float @t4(float %x) nounwind readnone optsize { +define float @t4(float %x) nounwind readnone optsize { entry: ; CHECK: t4: ; CHECK: vmov.f32 s1, #-2.400000e+01 diff --git a/test/CodeGen/ARM/ifcvt2.ll b/test/CodeGen/ARM/ifcvt2.ll index d9cac80..7b9d0cf 100644 --- a/test/CodeGen/ARM/ifcvt2.ll +++ b/test/CodeGen/ARM/ifcvt2.ll @@ -1,10 +1,8 @@ -; RUN: llc < %s -march=arm > %t -; RUN: grep bxlt %t | count 1 -; RUN: grep bxgt %t | count 1 -; RUN: not grep bxge %t -; RUN: not grep bxle %t +; RUN: llc < %s -march=arm | FileCheck %s define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) { +; CHECK: t1: +; CHECK: bxlt lr %tmp2 = icmp sgt i32 %c, 10 %tmp5 = icmp slt i32 %d, 4 %tmp8 = or i1 %tmp5, %tmp2 @@ -21,6 +19,13 @@ UnifiedReturnBlock: } define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d) { +; CHECK: t2: +; CHECK: bxgt lr +; CHECK: cmp +; CHECK: addge +; CHECK: subge +; CHECK-NOT: bxge lr +; CHECK: bx lr %tmp2 = icmp sgt i32 %c, 10 %tmp5 = icmp slt i32 %d, 4 %tmp8 = and i1 %tmp5, %tmp2 diff --git a/test/CodeGen/ARM/ifcvt6.ll b/test/CodeGen/ARM/ifcvt6.ll index 342208b..e2c0ba3 100644 --- a/test/CodeGen/ARM/ifcvt6.ll +++ b/test/CodeGen/ARM/ifcvt6.ll @@ -11,7 +11,7 @@ entry: br i1 %tmp7, label %cond_true, label %UnifiedReturnBlock cond_true: ; preds = %entry - %tmp10 = tail call i32 (...)* @bar( ) ; <i32> [#uses=0] + %tmp10 = call i32 (...)* @bar( ) ; <i32> [#uses=0] ret void UnifiedReturnBlock: ; preds = %entry diff --git a/test/CodeGen/ARM/indirectbr.ll b/test/CodeGen/ARM/indirectbr.ll index f898060..0aac9d1 100644 --- a/test/CodeGen/ARM/indirectbr.ll +++ b/test/CodeGen/ARM/indirectbr.ll @@ -5,7 +5,7 @@ @nextaddr = global i8* null ; <i8**> [#uses=2] @C.0.2070 = private constant [5 x i8*] [i8* blockaddress(@foo, %L1), i8* blockaddress(@foo, %L2), i8* blockaddress(@foo, %L3), i8* blockaddress(@foo, %L4), i8* blockaddress(@foo, %L5)] ; <[5 x i8*]*> [#uses=1] -define internal arm_apcscc i32 @foo(i32 %i) nounwind { +define internal i32 @foo(i32 %i) nounwind { ; ARM: foo: ; THUMB: foo: ; THUMB2: foo: diff --git a/test/CodeGen/ARM/inlineasm.ll b/test/CodeGen/ARM/inlineasm.ll index d522348..cca3c69 100644 --- a/test/CodeGen/ARM/inlineasm.ll +++ b/test/CodeGen/ARM/inlineasm.ll @@ -6,14 +6,6 @@ define i32 @test1(i32 %tmp54) { } define void @test2() { - %tmp1 = call i64 asm "ldmia $1!, {$0, ${0:H}}", "=r,=*r,1"( i32** null, i32* null ) ; <i64> [#uses=2] - %tmp2 = lshr i64 %tmp1, 32 ; <i64> [#uses=1] - %tmp3 = trunc i64 %tmp2 to i32 ; <i32> [#uses=1] - %tmp4 = call i32 asm "pkhbt $0, $1, $2, lsl #16", "=r,r,r"( i32 0, i32 %tmp3 ) ; <i32> [#uses=0] - ret void -} - -define void @test3() { tail call void asm sideeffect "/* number: ${0:c} */", "i"( i32 1 ) ret void } diff --git a/test/CodeGen/ARM/inlineasm3.ll b/test/CodeGen/ARM/inlineasm3.ll index f062772..687e138 100644 --- a/test/CodeGen/ARM/inlineasm3.ll +++ b/test/CodeGen/ARM/inlineasm3.ll @@ -3,7 +3,7 @@ ; Radar 7449043 %struct.int32x4_t = type { <4 x i32> } -define arm_apcscc void @t() nounwind { +define void @t() nounwind { entry: ; CHECK: vmov.I64 q15, #0 ; CHECK: vmov.32 d30[0], r0 @@ -16,7 +16,7 @@ entry: ; Radar 7457110 %struct.int32x2_t = type { <4 x i32> } -define arm_apcscc void @t2() nounwind { +define void @t2() nounwind { entry: ; CHECK: vmov d30, d0 ; CHECK: vmov.32 r0, d30[0] diff --git a/test/CodeGen/ARM/insn-sched1.ll b/test/CodeGen/ARM/insn-sched1.ll index 59f0d53..1d32322 100644 --- a/test/CodeGen/ARM/insn-sched1.ll +++ b/test/CodeGen/ARM/insn-sched1.ll @@ -4,7 +4,7 @@ define i32 @test(i32 %x) { %tmp = trunc i32 %x to i16 ; <i16> [#uses=1] - %tmp2 = tail call i32 @f( i32 1, i16 %tmp ) ; <i32> [#uses=1] + %tmp2 = call i32 @f( i32 1, i16 %tmp ) ; <i32> [#uses=1] ret i32 %tmp2 } diff --git a/test/CodeGen/ARM/ldm.ll b/test/CodeGen/ARM/ldm.ll index 9a2dc82..78201a6 100644 --- a/test/CodeGen/ARM/ldm.ll +++ b/test/CodeGen/ARM/ldm.ll @@ -28,7 +28,7 @@ define i32 @t3() { %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 1) ; <i32> [#uses=1] %tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 2) ; <i32> [#uses=1] %tmp5 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 3) ; <i32> [#uses=1] - %tmp6 = tail call i32 @f2( i32 %tmp, i32 %tmp3, i32 %tmp5 ) ; <i32> [#uses=1] + %tmp6 = call i32 @f2( i32 %tmp, i32 %tmp3, i32 %tmp5 ) ; <i32> [#uses=1] ret i32 %tmp6 } diff --git a/test/CodeGen/ARM/long_shift.ll b/test/CodeGen/ARM/long_shift.ll index 76332cc..688b7bc 100644 --- a/test/CodeGen/ARM/long_shift.ll +++ b/test/CodeGen/ARM/long_shift.ll @@ -23,10 +23,10 @@ define i32 @f1(i64 %x, i64 %y) { define i32 @f2(i64 %x, i64 %y) { ; CHECK: f2 ; CHECK: mov r0, r0, lsr r2 -; CHECK-NEXT: rsb r12, r2, #32 +; CHECK-NEXT: rsb r3, r2, #32 ; CHECK-NEXT: sub r2, r2, #32 ; CHECK-NEXT: cmp r2, #0 -; CHECK-NEXT: orr r0, r0, r1, lsl r12 +; CHECK-NEXT: orr r0, r0, r1, lsl r3 ; CHECK-NEXT: movge r0, r1, asr r2 %a = ashr i64 %x, %y %b = trunc i64 %a to i32 @@ -36,10 +36,10 @@ define i32 @f2(i64 %x, i64 %y) { define i32 @f3(i64 %x, i64 %y) { ; CHECK: f3 ; CHECK: mov r0, r0, lsr r2 -; CHECK-NEXT: rsb r12, r2, #32 +; CHECK-NEXT: rsb r3, r2, #32 ; CHECK-NEXT: sub r2, r2, #32 ; CHECK-NEXT: cmp r2, #0 -; CHECK-NEXT: orr r0, r0, r1, lsl r12 +; CHECK-NEXT: orr r0, r0, r1, lsl r3 ; CHECK-NEXT: movge r0, r1, lsr r2 %a = lshr i64 %x, %y %b = trunc i64 %a to i32 diff --git a/test/CodeGen/ARM/lsr-code-insertion.ll b/test/CodeGen/ARM/lsr-code-insertion.ll index 1bbb96d..b8c543b 100644 --- a/test/CodeGen/ARM/lsr-code-insertion.ll +++ b/test/CodeGen/ARM/lsr-code-insertion.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -stats |& grep {39.*Number of machine instrs printed} +; RUN: llc < %s -stats |& grep {38.*Number of machine instrs printed} ; RUN: llc < %s -stats |& not grep {.*Number of re-materialization} ; This test really wants to check that the resultant "cond_true" block only ; has a single store in it, and that cond_true55 only has code to materialize diff --git a/test/CodeGen/ARM/lsr-on-unrolled-loops.ll b/test/CodeGen/ARM/lsr-on-unrolled-loops.ll index 2ac4084..25cf135 100644 --- a/test/CodeGen/ARM/lsr-on-unrolled-loops.ll +++ b/test/CodeGen/ARM/lsr-on-unrolled-loops.ll @@ -4,14 +4,14 @@ ; constant offset addressing, so that each of the following stores ; uses the same register. -; CHECK: vstr.32 s0, [r12, #-128] -; CHECK: vstr.32 s0, [r12, #-96] -; CHECK: vstr.32 s0, [r12, #-64] -; CHECK: vstr.32 s0, [r12, #-32] -; CHECK: vstr.32 s0, [r12] -; CHECK: vstr.32 s0, [r12, #32] -; CHECK: vstr.32 s0, [r12, #64] -; CHECK: vstr.32 s0, [r12, #96] +; CHECK: vstr.32 s0, [r9, #-128] +; CHECK: vstr.32 s0, [r9, #-96] +; CHECK: vstr.32 s0, [r9, #-64] +; CHECK: vstr.32 s0, [r9, #-32] +; CHECK: vstr.32 s0, [r9] +; CHECK: vstr.32 s0, [r9, #32] +; CHECK: vstr.32 s0, [r9, #64] +; CHECK: vstr.32 s0, [r9, #96] target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32" @@ -40,7 +40,7 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32- %22 = type { void (%0*)*, void (%0*, i8***, i32, i8**, i32)* } %23 = type { void (%0*, i32)*, void (%0*, i8**, i8**, i32)*, void (%0*)*, void (%0*)* } -define arm_apcscc void @test(%0* nocapture %a0, %11* nocapture %a1, i16* nocapture %a2, i8** nocapture %a3, i32 %a4) nounwind { +define void @test(%0* nocapture %a0, %11* nocapture %a1, i16* nocapture %a2, i8** nocapture %a3, i32 %a4) nounwind { bb: %t = alloca [64 x float], align 4 %t5 = getelementptr inbounds %0* %a0, i32 0, i32 65 @@ -393,7 +393,7 @@ bb295: %struct.z_stream = type { i8*, i32, i32, i8*, i32, i32, i8*, %struct.internal_state*, i8* (i8*, i32, i32)*, void (i8*, i8*)*, i8*, i32, i32, i32 } %union.anon = type { i16 } -define arm_apcscc i32 @longest_match(%struct.internal_state* %s, i32 %cur_match) nounwind optsize { +define i32 @longest_match(%struct.internal_state* %s, i32 %cur_match) nounwind optsize { entry: %0 = getelementptr inbounds %struct.internal_state* %s, i32 0, i32 31 ; <i32*> [#uses=1] %1 = load i32* %0, align 4 ; <i32> [#uses=2] @@ -626,9 +626,11 @@ bb24: ; preds = %bb23 ; LSR should use count-down iteration to avoid requiring the trip count ; in a register, and it shouldn't require any reloads here. -; CHECK: sub.w r9, r9, #1 -; CHECK-NEXT: cmp.w r9, #0 -; CHECK-NEXT: bne.w +; CHECK: @ %bb24 +; CHECK-NEXT: @ in Loop: Header=BB1_1 Depth=1 +; CHECK-NEXT: sub{{.*}} [[REGISTER:r[0-9]+]], #1 +; CHECK-NEXT: cmp{{.*}} [[REGISTER]], #0 +; CHECK-NEXT: bne.w %92 = icmp eq i32 %tmp81, %indvar78 ; <i1> [#uses=1] %indvar.next79 = add i32 %indvar78, 1 ; <i32> [#uses=1] diff --git a/test/CodeGen/ARM/machine-cse-cmp.ll b/test/CodeGen/ARM/machine-cse-cmp.ll new file mode 100644 index 0000000..c77402f --- /dev/null +++ b/test/CodeGen/ARM/machine-cse-cmp.ll @@ -0,0 +1,18 @@ +; RUN: llc < %s -march=arm | FileCheck %s +;rdar://8003725 + +@G1 = external global i32 +@G2 = external global i32 + +define i32 @f1(i32 %cond1, i32 %x1, i32 %x2, i32 %x3) { +entry: +; CHECK: cmp +; CHECK: moveq +; CHECK-NOT: cmp +; CHECK: moveq + %tmp1 = icmp eq i32 %cond1, 0 + %tmp2 = select i1 %tmp1, i32 %x1, i32 %x2 + %tmp3 = select i1 %tmp1, i32 %x2, i32 %x3 + %tmp4 = add i32 %tmp2, %tmp3 + ret i32 %tmp4 +} diff --git a/test/CodeGen/ARM/reg_sequence.ll b/test/CodeGen/ARM/reg_sequence.ll index 3ba82cc..9e365c9 100644 --- a/test/CodeGen/ARM/reg_sequence.ll +++ b/test/CodeGen/ARM/reg_sequence.ll @@ -8,7 +8,7 @@ %struct.__neon_int16x8x2_t = type { <8 x i16>, <8 x i16> } %struct.__neon_int32x4x2_t = type { <4 x i32>, <4 x i32> } -define arm_apcscc void @t1(i16* %i_ptr, i16* %o_ptr, %struct.int32x4_t* nocapture %vT0ptr, %struct.int32x4_t* nocapture %vT1ptr) nounwind { +define void @t1(i16* %i_ptr, i16* %o_ptr, %struct.int32x4_t* nocapture %vT0ptr, %struct.int32x4_t* nocapture %vT1ptr) nounwind { entry: ; CHECK: t1: ; CHECK: vld1.16 @@ -41,13 +41,13 @@ entry: ret void } -define arm_apcscc void @t2(i16* %i_ptr, i16* %o_ptr, %struct.int16x8_t* nocapture %vT0ptr, %struct.int16x8_t* nocapture %vT1ptr) nounwind { +define void @t2(i16* %i_ptr, i16* %o_ptr, %struct.int16x8_t* nocapture %vT0ptr, %struct.int16x8_t* nocapture %vT1ptr) nounwind { entry: ; CHECK: t2: ; CHECK: vld1.16 -; CHECK: vld1.16 -; CHECK-NOT: vmov ; CHECK: vmul.i16 +; CHECK-NOT: vmov +; CHECK: vld1.16 ; CHECK: vmul.i16 ; CHECK-NOT: vmov ; CHECK: vst1.16 @@ -88,7 +88,7 @@ define <8 x i8> @t3(i8* %A, i8* %B) nounwind { ret <8 x i8> %tmp4 } -define arm_apcscc void @t4(i32* %in, i32* %out) nounwind { +define void @t4(i32* %in, i32* %out) nounwind { entry: ; CHECK: t4: ; CHECK: vld2.32 @@ -163,7 +163,7 @@ define <8 x i8> @t6(i8* %A, <8 x i8>* %B) nounwind { ret <8 x i8> %tmp5 } -define arm_apcscc void @t7(i32* %iptr, i32* %optr) nounwind { +define void @t7(i32* %iptr, i32* %optr) nounwind { entry: ; CHECK: t7: ; CHECK: vld2.32 @@ -238,9 +238,10 @@ bb14: ; preds = %bb6 define arm_aapcs_vfpcc float @t9(%0* nocapture, %3* nocapture) nounwind { ; CHECK: t9: ; CHECK: vldr.64 +; CHECK-NOT: vmov d{{.*}}, d0 ; CHECK: vmov.i8 d1 -; CHECK-NEXT: vstmia r0, {d2,d3} -; CHECK-NEXT: vstmia r0, {d0,d1} +; CHECK-NEXT: vstmia r0, {d0, d1} +; CHECK-NEXT: vstmia r0, {d0, d1} %3 = bitcast double 0.000000e+00 to <2 x float> ; <<2 x float>> [#uses=2] %4 = shufflevector <2 x float> %3, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1] store <4 x float> %4, <4 x float>* undef, align 16 @@ -249,13 +250,13 @@ define arm_aapcs_vfpcc float @t9(%0* nocapture, %3* nocapture) nounwind { br label %8 ; <label>:6 ; preds = %8 - br i1 undef, label %7, label %10 + br label %7 ; <label>:7 ; preds = %6 br label %8 ; <label>:8 ; preds = %7, %2 - br i1 undef, label %6, label %9 + br label %6 ; <label>:9 ; preds = %8 ret float undef @@ -269,7 +270,6 @@ define arm_aapcs_vfpcc i32 @t10() nounwind { entry: ; CHECK: t10: ; CHECK: vmov.i32 q1, #0x3F000000 -; CHECK: vdup.32 q0, d0[0] ; CHECK: vmov d0, d1 ; CHECK: vmla.f32 q0, q0, d0[0] %0 = shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1] diff --git a/test/CodeGen/ARM/remat.ll b/test/CodeGen/ARM/remat.ll index 92c1cf1..1e780e6 100644 --- a/test/CodeGen/ARM/remat.ll +++ b/test/CodeGen/ARM/remat.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 -stats -info-output-file - | grep "Number of re-materialization" -define arm_apcscc i32 @main(i32 %argc, i8** nocapture %argv, double %d1, double %d2) nounwind { +define i32 @main(i32 %argc, i8** nocapture %argv, double %d1, double %d2) nounwind { entry: br i1 undef, label %smvp.exit, label %bb.i3 @@ -25,7 +25,7 @@ bb142: ; preds = %bb.nph218.bb.nph218 br i1 %14, label %phi1.exit, label %bb.i35 bb.i35: ; preds = %bb142 - %5 = call arm_apcscc double @sin(double %15) nounwind readonly ; <double> [#uses=1] + %5 = call double @sin(double %15) nounwind readonly ; <double> [#uses=1] %6 = fmul double %5, 0x4031740AFA84AD8A ; <double> [#uses=1] %7 = fsub double 1.000000e+00, undef ; <double> [#uses=1] %8 = fdiv double %7, 6.000000e-01 ; <double> [#uses=1] @@ -62,4 +62,4 @@ bb166: ; preds = %bb127 unreachable } -declare arm_apcscc double @sin(double) nounwind readonly +declare double @sin(double) nounwind readonly diff --git a/test/CodeGen/ARM/select-imm.ll b/test/CodeGen/ARM/select-imm.ll index 07edc91..6e15fde 100644 --- a/test/CodeGen/ARM/select-imm.ll +++ b/test/CodeGen/ARM/select-imm.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -march=arm -mattr=+thumb2 | FileCheck %s --check-prefix=T2 -define arm_apcscc i32 @t1(i32 %c) nounwind readnone { +define i32 @t1(i32 %c) nounwind readnone { entry: ; ARM: t1: ; ARM: mov r1, #101 @@ -17,7 +17,7 @@ entry: ret i32 %1 } -define arm_apcscc i32 @t2(i32 %c) nounwind readnone { +define i32 @t2(i32 %c) nounwind readnone { entry: ; ARM: t2: ; ARM: mov r1, #101 @@ -33,7 +33,7 @@ entry: ret i32 %1 } -define arm_apcscc i32 @t3(i32 %a) nounwind readnone { +define i32 @t3(i32 %a) nounwind readnone { entry: ; ARM: t3: ; ARM: mov r0, #0 diff --git a/test/CodeGen/ARM/spill-q.ll b/test/CodeGen/ARM/spill-q.ll index 03de0c8..792ef79 100644 --- a/test/CodeGen/ARM/spill-q.ll +++ b/test/CodeGen/ARM/spill-q.ll @@ -9,7 +9,7 @@ declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*) nounwind readonly -define arm_apcscc void @aaa(%quuz* %this, i8* %block) { +define void @aaa(%quuz* %this, i8* %block) { ; CHECK: aaa: ; CHECK: bic sp, sp, #15 ; CHECK: vst1.64 {{.*}}sp, :128 diff --git a/test/CodeGen/ARM/trap.ll b/test/CodeGen/ARM/trap.ll index 763dff3..b2f6b6e 100644 --- a/test/CodeGen/ARM/trap.ll +++ b/test/CodeGen/ARM/trap.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm | FileCheck %s ; rdar://7961298 -define arm_apcscc void @t() nounwind { +define void @t() nounwind { entry: ; CHECK: t: ; CHECK: trap diff --git a/test/CodeGen/ARM/unaligned_load_store.ll b/test/CodeGen/ARM/unaligned_load_store.ll index a4494f3..e279491 100644 --- a/test/CodeGen/ARM/unaligned_load_store.ll +++ b/test/CodeGen/ARM/unaligned_load_store.ll @@ -4,7 +4,7 @@ ; rdar://7113725 -define arm_apcscc void @t(i8* nocapture %a, i8* nocapture %b) nounwind { +define void @t(i8* nocapture %a, i8* nocapture %b) nounwind { entry: ; GENERIC: t: ; GENERIC: ldrb r2 diff --git a/test/CodeGen/ARM/va_arg.ll b/test/CodeGen/ARM/va_arg.ll new file mode 100644 index 0000000..7cb9762 --- /dev/null +++ b/test/CodeGen/ARM/va_arg.ll @@ -0,0 +1,41 @@ +; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi | FileCheck %s +; Test that we correctly align elements when using va_arg + +; CHECK: test1: +; CHECK-NOT: bfc +; CHECK: add r0, r0, #7 +; CHECK: bfc r0, #0, #3 +; CHECK-NOT: bfc + +define i64 @test1(i32 %i, ...) nounwind optsize { +entry: + %g = alloca i8*, align 4 + %g1 = bitcast i8** %g to i8* + call void @llvm.va_start(i8* %g1) + %0 = va_arg i8** %g, i64 + call void @llvm.va_end(i8* %g1) + ret i64 %0 +} + +; CHECK: test2: +; CHECK-NOT: bfc +; CHECK: add r0, r0, #7 +; CHECK: bfc r0, #0, #3 +; CHECK-NOT: bfc +; CHECK: bx lr + +define double @test2(i32 %a, i32 %b, ...) nounwind optsize { +entry: + %ap = alloca i8*, align 4 ; <i8**> [#uses=3] + %ap1 = bitcast i8** %ap to i8* ; <i8*> [#uses=2] + call void @llvm.va_start(i8* %ap1) + %0 = va_arg i8** %ap, i32 ; <i32> [#uses=0] + %1 = va_arg i8** %ap, double ; <double> [#uses=1] + call void @llvm.va_end(i8* %ap1) + ret double %1 +} + + +declare void @llvm.va_start(i8*) nounwind + +declare void @llvm.va_end(i8*) nounwind diff --git a/test/CodeGen/ARM/vdup.ll b/test/CodeGen/ARM/vdup.ll index c9a68ca..50e4df9 100644 --- a/test/CodeGen/ARM/vdup.ll +++ b/test/CodeGen/ARM/vdup.ll @@ -244,25 +244,25 @@ define <4 x float> @vduplaneQfloat(<2 x float>* %A) nounwind { ret <4 x float> %tmp2 } -define arm_apcscc <2 x i64> @foo(<2 x i64> %arg0_int64x1_t) nounwind readnone { +define <2 x i64> @foo(<2 x i64> %arg0_int64x1_t) nounwind readnone { entry: %0 = shufflevector <2 x i64> %arg0_int64x1_t, <2 x i64> undef, <2 x i32> <i32 1, i32 1> ret <2 x i64> %0 } -define arm_apcscc <2 x i64> @bar(<2 x i64> %arg0_int64x1_t) nounwind readnone { +define <2 x i64> @bar(<2 x i64> %arg0_int64x1_t) nounwind readnone { entry: %0 = shufflevector <2 x i64> %arg0_int64x1_t, <2 x i64> undef, <2 x i32> <i32 0, i32 0> ret <2 x i64> %0 } -define arm_apcscc <2 x double> @baz(<2 x double> %arg0_int64x1_t) nounwind readnone { +define <2 x double> @baz(<2 x double> %arg0_int64x1_t) nounwind readnone { entry: %0 = shufflevector <2 x double> %arg0_int64x1_t, <2 x double> undef, <2 x i32> <i32 1, i32 1> ret <2 x double> %0 } -define arm_apcscc <2 x double> @qux(<2 x double> %arg0_int64x1_t) nounwind readnone { +define <2 x double> @qux(<2 x double> %arg0_int64x1_t) nounwind readnone { entry: %0 = shufflevector <2 x double> %arg0_int64x1_t, <2 x double> undef, <2 x i32> <i32 0, i32 0> ret <2 x double> %0 diff --git a/test/CodeGen/ARM/vext.ll b/test/CodeGen/ARM/vext.ll index 20d953b..c11a67c 100644 --- a/test/CodeGen/ARM/vext.ll +++ b/test/CodeGen/ARM/vext.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -define arm_apcscc <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind { +define <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK: test_vextd: ;CHECK: vext %tmp1 = load <8 x i8>* %A @@ -9,7 +9,7 @@ define arm_apcscc <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind { ret <8 x i8> %tmp3 } -define arm_apcscc <8 x i8> @test_vextRd(<8 x i8>* %A, <8 x i8>* %B) nounwind { +define <8 x i8> @test_vextRd(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK: test_vextRd: ;CHECK: vext %tmp1 = load <8 x i8>* %A @@ -18,7 +18,7 @@ define arm_apcscc <8 x i8> @test_vextRd(<8 x i8>* %A, <8 x i8>* %B) nounwind { ret <8 x i8> %tmp3 } -define arm_apcscc <16 x i8> @test_vextq(<16 x i8>* %A, <16 x i8>* %B) nounwind { +define <16 x i8> @test_vextq(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK: test_vextq: ;CHECK: vext %tmp1 = load <16 x i8>* %A @@ -27,7 +27,7 @@ define arm_apcscc <16 x i8> @test_vextq(<16 x i8>* %A, <16 x i8>* %B) nounwind { ret <16 x i8> %tmp3 } -define arm_apcscc <16 x i8> @test_vextRq(<16 x i8>* %A, <16 x i8>* %B) nounwind { +define <16 x i8> @test_vextRq(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK: test_vextRq: ;CHECK: vext %tmp1 = load <16 x i8>* %A @@ -36,7 +36,7 @@ define arm_apcscc <16 x i8> @test_vextRq(<16 x i8>* %A, <16 x i8>* %B) nounwind ret <16 x i8> %tmp3 } -define arm_apcscc <4 x i16> @test_vextd16(<4 x i16>* %A, <4 x i16>* %B) nounwind { +define <4 x i16> @test_vextd16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK: test_vextd16: ;CHECK: vext %tmp1 = load <4 x i16>* %A @@ -45,7 +45,7 @@ define arm_apcscc <4 x i16> @test_vextd16(<4 x i16>* %A, <4 x i16>* %B) nounwind ret <4 x i16> %tmp3 } -define arm_apcscc <4 x i32> @test_vextq32(<4 x i32>* %A, <4 x i32>* %B) nounwind { +define <4 x i32> @test_vextq32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK: test_vextq32: ;CHECK: vext %tmp1 = load <4 x i32>* %A diff --git a/test/CodeGen/ARM/vget_lane.ll b/test/CodeGen/ARM/vget_lane.ll index 5dd87d6..05e7f50 100644 --- a/test/CodeGen/ARM/vget_lane.ll +++ b/test/CodeGen/ARM/vget_lane.ll @@ -204,8 +204,8 @@ define <4 x i32> @vsetQ_lane32(<4 x i32>* %A, i32 %B) nounwind { define arm_aapcs_vfpcc <2 x float> @test_vset_lanef32(float %arg0_float32_t, <2 x float> %arg1_float32x2_t) nounwind { ;CHECK: test_vset_lanef32: -;CHECK: vmov.f32 -;CHECK: vmov.f32 +;CHECK: vmov.f32 s3, s0 +;CHECK: vmov.f64 d0, d1 entry: %0 = insertelement <2 x float> %arg1_float32x2_t, float %arg0_float32_t, i32 1 ; <<2 x float>> [#uses=1] ret <2 x float> %0 diff --git a/test/CodeGen/ARM/vmov.ll b/test/CodeGen/ARM/vmov.ll index e4368d6..f803018 100644 --- a/test/CodeGen/ARM/vmov.ll +++ b/test/CodeGen/ARM/vmov.ll @@ -2,141 +2,127 @@ define <8 x i8> @v_movi8() nounwind { ;CHECK: v_movi8: -;CHECK: vmov.i8 +;CHECK: vmov.i8 d0, #0x8 ret <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 > } define <4 x i16> @v_movi16a() nounwind { ;CHECK: v_movi16a: -;CHECK: vmov.i16 +;CHECK: vmov.i16 d0, #0x10 ret <4 x i16> < i16 16, i16 16, i16 16, i16 16 > } -; 0x1000 = 4096 define <4 x i16> @v_movi16b() nounwind { ;CHECK: v_movi16b: -;CHECK: vmov.i16 +;CHECK: vmov.i16 d0, #0x1000 ret <4 x i16> < i16 4096, i16 4096, i16 4096, i16 4096 > } define <2 x i32> @v_movi32a() nounwind { ;CHECK: v_movi32a: -;CHECK: vmov.i32 +;CHECK: vmov.i32 d0, #0x20 ret <2 x i32> < i32 32, i32 32 > } -; 0x2000 = 8192 define <2 x i32> @v_movi32b() nounwind { ;CHECK: v_movi32b: -;CHECK: vmov.i32 +;CHECK: vmov.i32 d0, #0x2000 ret <2 x i32> < i32 8192, i32 8192 > } -; 0x200000 = 2097152 define <2 x i32> @v_movi32c() nounwind { ;CHECK: v_movi32c: -;CHECK: vmov.i32 +;CHECK: vmov.i32 d0, #0x200000 ret <2 x i32> < i32 2097152, i32 2097152 > } -; 0x20000000 = 536870912 define <2 x i32> @v_movi32d() nounwind { ;CHECK: v_movi32d: -;CHECK: vmov.i32 +;CHECK: vmov.i32 d0, #0x20000000 ret <2 x i32> < i32 536870912, i32 536870912 > } -; 0x20ff = 8447 define <2 x i32> @v_movi32e() nounwind { ;CHECK: v_movi32e: -;CHECK: vmov.i32 +;CHECK: vmov.i32 d0, #0x20FF ret <2 x i32> < i32 8447, i32 8447 > } -; 0x20ffff = 2162687 define <2 x i32> @v_movi32f() nounwind { ;CHECK: v_movi32f: -;CHECK: vmov.i32 +;CHECK: vmov.i32 d0, #0x20FFFF ret <2 x i32> < i32 2162687, i32 2162687 > } -; 0xff0000ff0000ffff = 18374687574888349695 define <1 x i64> @v_movi64() nounwind { ;CHECK: v_movi64: -;CHECK: vmov.i64 +;CHECK: vmov.i64 d0, #0xFF0000FF0000FFFF ret <1 x i64> < i64 18374687574888349695 > } define <16 x i8> @v_movQi8() nounwind { ;CHECK: v_movQi8: -;CHECK: vmov.i8 +;CHECK: vmov.i8 q0, #0x8 ret <16 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 > } define <8 x i16> @v_movQi16a() nounwind { ;CHECK: v_movQi16a: -;CHECK: vmov.i16 +;CHECK: vmov.i16 q0, #0x10 ret <8 x i16> < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 > } -; 0x1000 = 4096 define <8 x i16> @v_movQi16b() nounwind { ;CHECK: v_movQi16b: -;CHECK: vmov.i16 +;CHECK: vmov.i16 q0, #0x1000 ret <8 x i16> < i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096 > } define <4 x i32> @v_movQi32a() nounwind { ;CHECK: v_movQi32a: -;CHECK: vmov.i32 +;CHECK: vmov.i32 q0, #0x20 ret <4 x i32> < i32 32, i32 32, i32 32, i32 32 > } -; 0x2000 = 8192 define <4 x i32> @v_movQi32b() nounwind { ;CHECK: v_movQi32b: -;CHECK: vmov.i32 +;CHECK: vmov.i32 q0, #0x2000 ret <4 x i32> < i32 8192, i32 8192, i32 8192, i32 8192 > } -; 0x200000 = 2097152 define <4 x i32> @v_movQi32c() nounwind { ;CHECK: v_movQi32c: -;CHECK: vmov.i32 +;CHECK: vmov.i32 q0, #0x200000 ret <4 x i32> < i32 2097152, i32 2097152, i32 2097152, i32 2097152 > } -; 0x20000000 = 536870912 define <4 x i32> @v_movQi32d() nounwind { ;CHECK: v_movQi32d: -;CHECK: vmov.i32 +;CHECK: vmov.i32 q0, #0x20000000 ret <4 x i32> < i32 536870912, i32 536870912, i32 536870912, i32 536870912 > } -; 0x20ff = 8447 define <4 x i32> @v_movQi32e() nounwind { ;CHECK: v_movQi32e: -;CHECK: vmov.i32 +;CHECK: vmov.i32 q0, #0x20FF ret <4 x i32> < i32 8447, i32 8447, i32 8447, i32 8447 > } -; 0x20ffff = 2162687 define <4 x i32> @v_movQi32f() nounwind { ;CHECK: v_movQi32f: -;CHECK: vmov.i32 +;CHECK: vmov.i32 q0, #0x20FFFF ret <4 x i32> < i32 2162687, i32 2162687, i32 2162687, i32 2162687 > } -; 0xff0000ff0000ffff = 18374687574888349695 define <2 x i64> @v_movQi64() nounwind { ;CHECK: v_movQi64: -;CHECK: vmov.i64 +;CHECK: vmov.i64 q0, #0xFF0000FF0000FFFF ret <2 x i64> < i64 18374687574888349695, i64 18374687574888349695 > } ; Check for correct assembler printing for immediate values. %struct.int8x8_t = type { <8 x i8> } -define arm_apcscc void @vdupn128(%struct.int8x8_t* noalias nocapture sret %agg.result) nounwind { +define void @vdupn128(%struct.int8x8_t* noalias nocapture sret %agg.result) nounwind { entry: ;CHECK: vdupn128: ;CHECK: vmov.i8 d0, #0x80 @@ -145,7 +131,7 @@ entry: ret void } -define arm_apcscc void @vdupnneg75(%struct.int8x8_t* noalias nocapture sret %agg.result) nounwind { +define void @vdupnneg75(%struct.int8x8_t* noalias nocapture sret %agg.result) nounwind { entry: ;CHECK: vdupnneg75: ;CHECK: vmov.i8 d0, #0xB5 diff --git a/test/CodeGen/ARM/vrev.ll b/test/CodeGen/ARM/vrev.ll index f0a04a4..deed554 100644 --- a/test/CodeGen/ARM/vrev.ll +++ b/test/CodeGen/ARM/vrev.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -define arm_apcscc <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind { +define <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind { ;CHECK: test_vrev64D8: ;CHECK: vrev64.8 %tmp1 = load <8 x i8>* %A @@ -8,7 +8,7 @@ define arm_apcscc <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind { ret <8 x i8> %tmp2 } -define arm_apcscc <4 x i16> @test_vrev64D16(<4 x i16>* %A) nounwind { +define <4 x i16> @test_vrev64D16(<4 x i16>* %A) nounwind { ;CHECK: test_vrev64D16: ;CHECK: vrev64.16 %tmp1 = load <4 x i16>* %A @@ -16,7 +16,7 @@ define arm_apcscc <4 x i16> @test_vrev64D16(<4 x i16>* %A) nounwind { ret <4 x i16> %tmp2 } -define arm_apcscc <2 x i32> @test_vrev64D32(<2 x i32>* %A) nounwind { +define <2 x i32> @test_vrev64D32(<2 x i32>* %A) nounwind { ;CHECK: test_vrev64D32: ;CHECK: vrev64.32 %tmp1 = load <2 x i32>* %A @@ -24,7 +24,7 @@ define arm_apcscc <2 x i32> @test_vrev64D32(<2 x i32>* %A) nounwind { ret <2 x i32> %tmp2 } -define arm_apcscc <2 x float> @test_vrev64Df(<2 x float>* %A) nounwind { +define <2 x float> @test_vrev64Df(<2 x float>* %A) nounwind { ;CHECK: test_vrev64Df: ;CHECK: vrev64.32 %tmp1 = load <2 x float>* %A @@ -32,7 +32,7 @@ define arm_apcscc <2 x float> @test_vrev64Df(<2 x float>* %A) nounwind { ret <2 x float> %tmp2 } -define arm_apcscc <16 x i8> @test_vrev64Q8(<16 x i8>* %A) nounwind { +define <16 x i8> @test_vrev64Q8(<16 x i8>* %A) nounwind { ;CHECK: test_vrev64Q8: ;CHECK: vrev64.8 %tmp1 = load <16 x i8>* %A @@ -40,7 +40,7 @@ define arm_apcscc <16 x i8> @test_vrev64Q8(<16 x i8>* %A) nounwind { ret <16 x i8> %tmp2 } -define arm_apcscc <8 x i16> @test_vrev64Q16(<8 x i16>* %A) nounwind { +define <8 x i16> @test_vrev64Q16(<8 x i16>* %A) nounwind { ;CHECK: test_vrev64Q16: ;CHECK: vrev64.16 %tmp1 = load <8 x i16>* %A @@ -48,7 +48,7 @@ define arm_apcscc <8 x i16> @test_vrev64Q16(<8 x i16>* %A) nounwind { ret <8 x i16> %tmp2 } -define arm_apcscc <4 x i32> @test_vrev64Q32(<4 x i32>* %A) nounwind { +define <4 x i32> @test_vrev64Q32(<4 x i32>* %A) nounwind { ;CHECK: test_vrev64Q32: ;CHECK: vrev64.32 %tmp1 = load <4 x i32>* %A @@ -56,7 +56,7 @@ define arm_apcscc <4 x i32> @test_vrev64Q32(<4 x i32>* %A) nounwind { ret <4 x i32> %tmp2 } -define arm_apcscc <4 x float> @test_vrev64Qf(<4 x float>* %A) nounwind { +define <4 x float> @test_vrev64Qf(<4 x float>* %A) nounwind { ;CHECK: test_vrev64Qf: ;CHECK: vrev64.32 %tmp1 = load <4 x float>* %A @@ -64,7 +64,7 @@ define arm_apcscc <4 x float> @test_vrev64Qf(<4 x float>* %A) nounwind { ret <4 x float> %tmp2 } -define arm_apcscc <8 x i8> @test_vrev32D8(<8 x i8>* %A) nounwind { +define <8 x i8> @test_vrev32D8(<8 x i8>* %A) nounwind { ;CHECK: test_vrev32D8: ;CHECK: vrev32.8 %tmp1 = load <8 x i8>* %A @@ -72,7 +72,7 @@ define arm_apcscc <8 x i8> @test_vrev32D8(<8 x i8>* %A) nounwind { ret <8 x i8> %tmp2 } -define arm_apcscc <4 x i16> @test_vrev32D16(<4 x i16>* %A) nounwind { +define <4 x i16> @test_vrev32D16(<4 x i16>* %A) nounwind { ;CHECK: test_vrev32D16: ;CHECK: vrev32.16 %tmp1 = load <4 x i16>* %A @@ -80,7 +80,7 @@ define arm_apcscc <4 x i16> @test_vrev32D16(<4 x i16>* %A) nounwind { ret <4 x i16> %tmp2 } -define arm_apcscc <16 x i8> @test_vrev32Q8(<16 x i8>* %A) nounwind { +define <16 x i8> @test_vrev32Q8(<16 x i8>* %A) nounwind { ;CHECK: test_vrev32Q8: ;CHECK: vrev32.8 %tmp1 = load <16 x i8>* %A @@ -88,7 +88,7 @@ define arm_apcscc <16 x i8> @test_vrev32Q8(<16 x i8>* %A) nounwind { ret <16 x i8> %tmp2 } -define arm_apcscc <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind { +define <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind { ;CHECK: test_vrev32Q16: ;CHECK: vrev32.16 %tmp1 = load <8 x i16>* %A @@ -96,7 +96,7 @@ define arm_apcscc <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind { ret <8 x i16> %tmp2 } -define arm_apcscc <8 x i8> @test_vrev16D8(<8 x i8>* %A) nounwind { +define <8 x i8> @test_vrev16D8(<8 x i8>* %A) nounwind { ;CHECK: test_vrev16D8: ;CHECK: vrev16.8 %tmp1 = load <8 x i8>* %A @@ -104,7 +104,7 @@ define arm_apcscc <8 x i8> @test_vrev16D8(<8 x i8>* %A) nounwind { ret <8 x i8> %tmp2 } -define arm_apcscc <16 x i8> @test_vrev16Q8(<16 x i8>* %A) nounwind { +define <16 x i8> @test_vrev16Q8(<16 x i8>* %A) nounwind { ;CHECK: test_vrev16Q8: ;CHECK: vrev16.8 %tmp1 = load <16 x i8>* %A diff --git a/test/CodeGen/Blackfin/cmp64.ll b/test/CodeGen/Blackfin/cmp64.ll index ef5bf45..6c4f9c5 100644 --- a/test/CodeGen/Blackfin/cmp64.ll +++ b/test/CodeGen/Blackfin/cmp64.ll @@ -1,8 +1,8 @@ ; RUN: llc < %s -march=bfin ; This test tries to use a JustCC register as a data operand for MOVEcc. It -; calls copyRegToReg(JustCC -> DP), failing because JustCC can only be copied to -; D. The proper solution would be to restrict the virtual register to D only. +; copies (JustCC -> DP), failing because JustCC can only be copied to D. +; The proper solution would be to restrict the virtual register to D only. define i32 @main() { entry: diff --git a/test/CodeGen/CellSPU/call.ll b/test/CodeGen/CellSPU/call.ll index 960d2fe..eb7cf2c 100644 --- a/test/CodeGen/CellSPU/call.ll +++ b/test/CodeGen/CellSPU/call.ll @@ -1,7 +1,8 @@ -; RUN: llc < %s -march=cellspu > %t1.s +; RUN: llc < %s -march=cellspu -regalloc=linearscan > %t1.s ; RUN: grep brsl %t1.s | count 1 ; RUN: grep brasl %t1.s | count 1 ; RUN: grep stqd %t1.s | count 80 +; RUN: llc < %s -march=cellspu | FileCheck %s target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128" target triple = "spu" @@ -16,6 +17,8 @@ entry: declare void @extern_stub_1(i32, i32) define i32 @stub_1(i32 %x, float %y) { + ; CHECK: il $3, 0 + ; CHECK: bi $lr entry: ret i32 0 } diff --git a/test/CodeGen/CellSPU/call_indirect.ll b/test/CodeGen/CellSPU/call_indirect.ll index 08dad74..d94d77c 100644 --- a/test/CodeGen/CellSPU/call_indirect.ll +++ b/test/CodeGen/CellSPU/call_indirect.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=cellspu -asm-verbose=0 > %t1.s -; RUN: llc < %s -march=cellspu -mattr=large_mem -asm-verbose=0 > %t2.s +; RUN: llc < %s -march=cellspu -asm-verbose=0 -regalloc=linearscan > %t1.s +; RUN: llc < %s -march=cellspu -mattr=large_mem -asm-verbose=0 -regalloc=linearscan > %t2.s ; RUN: grep bisl %t1.s | count 7 ; RUN: grep ila %t1.s | count 1 ; RUN: grep rotqby %t1.s | count 5 diff --git a/test/CodeGen/CellSPU/jumptable.ll b/test/CodeGen/CellSPU/jumptable.ll index d7d1ef4..42b41b3 100644 --- a/test/CodeGen/CellSPU/jumptable.ll +++ b/test/CodeGen/CellSPU/jumptable.ll @@ -2,9 +2,9 @@ ; This is to check that emitting jumptables doesn't crash llc define i32 @test(i32 %param) { entry: -;CHECK: ai $4, $3, -1 -;CHECK: clgti $5, $4, 3 -;CHECK: brnz $5,.LBB0_2 +;CHECK: ai {{\$.}}, $3, -1 +;CHECK: clgti {{\$., \$.}}, 3 +;CHECK: brnz {{\$.}},.LBB0_2 switch i32 %param, label %bb1 [ i32 1, label %bb3 i32 2, label %bb2 diff --git a/test/CodeGen/CellSPU/loads.ll b/test/CodeGen/CellSPU/loads.ll index 8e5422c..d40217d 100644 --- a/test/CodeGen/CellSPU/loads.ll +++ b/test/CodeGen/CellSPU/loads.ll @@ -18,3 +18,23 @@ entry: ret <4 x float> %tmp1 ; CHECK: lqd $3, 16($3) } + + +declare <4 x i32>* @getv4f32ptr() +define <4 x i32> @func() { + ;CHECK: brasl + ; we need to have some instruction to move the result to safety. + ; which instruction (lr, stqd...) depends on the regalloc + ;CHECK: {{.*}} + ;CHECK: brasl + %rv1 = call <4 x i32>* @getv4f32ptr() + %rv2 = call <4 x i32>* @getv4f32ptr() + %rv3 = load <4 x i32>* %rv1 + ret <4 x i32> %rv3 +} + +define <4 x float> @load_undef(){ + ; CHECK: lqd $3, 0($3) + %val = load <4 x float>* undef + ret <4 x float> %val +} diff --git a/test/CodeGen/CellSPU/shuffles.ll b/test/CodeGen/CellSPU/shuffles.ll new file mode 100644 index 0000000..04accb9 --- /dev/null +++ b/test/CodeGen/CellSPU/shuffles.ll @@ -0,0 +1,18 @@ +; RUN: llc --march=cellspu < %s | FileCheck %s + +define <4 x float> @shuffle(<4 x float> %param1, <4 x float> %param2) { + ; CHECK: cwd {{\$.}}, 0($sp) + ; CHECK: shufb {{\$., \$4, \$3, \$.}} + %val= shufflevector <4 x float> %param1, <4 x float> %param2, <4 x i32> <i32 4,i32 1,i32 2,i32 3> + ret <4 x float> %val +} + +define <4 x float> @splat(float %param1) { + ; CHECK: lqa + ; CHECK: shufb $3 + ; CHECK: bi + %vec = insertelement <1 x float> undef, float %param1, i32 0 + %val= shufflevector <1 x float> %vec, <1 x float> undef, <4 x i32> <i32 0,i32 0,i32 0,i32 0> + ret <4 x float> %val +} + diff --git a/test/CodeGen/CellSPU/vecinsert.ll b/test/CodeGen/CellSPU/vecinsert.ll index 9a00c1f..8dcab1d 100644 --- a/test/CodeGen/CellSPU/vecinsert.ll +++ b/test/CodeGen/CellSPU/vecinsert.ll @@ -1,17 +1,19 @@ ; RUN: llc < %s -march=cellspu > %t1.s ; RUN: grep cbd %t1.s | count 5 ; RUN: grep chd %t1.s | count 5 -; RUN: grep cwd %t1.s | count 10 +; RUN: grep cwd %t1.s | count 11 ; RUN: grep -w il %t1.s | count 5 ; RUN: grep -w ilh %t1.s | count 6 ; RUN: grep iohl %t1.s | count 1 ; RUN: grep ilhu %t1.s | count 4 -; RUN: grep shufb %t1.s | count 26 +; RUN: grep shufb %t1.s | count 27 ; RUN: grep 17219 %t1.s | count 1 ; RUN: grep 22598 %t1.s | count 1 ; RUN: grep -- -39 %t1.s | count 1 ; RUN: grep 24 %t1.s | count 1 ; RUN: grep 1159 %t1.s | count 1 +; RUN: FileCheck %s < %t1.s + ; ModuleID = 'vecinsert.bc' target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128" target triple = "spu-unknown-elf" @@ -118,3 +120,12 @@ entry: store <2 x double> %tmp3, <2 x double>* %arrayidx ret void } + +define <4 x i32> @undef_v4i32( i32 %param ) { + ;CHECK: cwd + ;CHECK: lqa + ;CHECK: shufb + %val = insertelement <4 x i32> <i32 1, i32 2, i32 3, i32 4>, i32 %param, i32 undef + ret <4 x i32> %val +} + diff --git a/test/CodeGen/Generic/2006-09-02-LocalAllocCrash.ll b/test/CodeGen/Generic/2006-09-02-LocalAllocCrash.ll index d5a4d6a..928edc4 100644 --- a/test/CodeGen/Generic/2006-09-02-LocalAllocCrash.ll +++ b/test/CodeGen/Generic/2006-09-02-LocalAllocCrash.ll @@ -1,4 +1,3 @@ -; RUN: llc < %s -regalloc=local ; RUN: llc < %s -regalloc=fast %struct.CHESS_POSITION = type { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i32, i32, i8, i8, [64 x i8], i8, i8, i8, i8, i8 } diff --git a/test/CodeGen/Generic/2010-ZeroSizedArg.ll b/test/CodeGen/Generic/2010-ZeroSizedArg.ll index ba40bd0..d9d8374 100644 --- a/test/CodeGen/Generic/2010-ZeroSizedArg.ll +++ b/test/CodeGen/Generic/2010-ZeroSizedArg.ll @@ -6,7 +6,7 @@ @.str = private constant [1 x i8] c" " -define arm_apcscc void @t(%0) nounwind { +define void @t(%0) nounwind { entry: %arg0 = alloca %union.T0 %1 = bitcast %union.T0* %arg0 to %0* @@ -14,4 +14,4 @@ entry: ret void } -declare arm_apcscc i32 @printf(i8*, ...) +declare i32 @printf(i8*, ...) diff --git a/test/CodeGen/Generic/add-with-overflow-128.ll b/test/CodeGen/Generic/add-with-overflow-128.ll new file mode 100644 index 0000000..c46c820 --- /dev/null +++ b/test/CodeGen/Generic/add-with-overflow-128.ll @@ -0,0 +1,42 @@ +; RUN: llc < %s + +@ok = internal constant [4 x i8] c"%d\0A\00" +@no = internal constant [4 x i8] c"no\0A\00" + +define i1 @func1(i128 signext %v1, i128 signext %v2) nounwind { +entry: + %t = call {i128, i1} @llvm.sadd.with.overflow.i128(i128 %v1, i128 %v2) + %sum = extractvalue {i128, i1} %t, 0 + %sum32 = trunc i128 %sum to i32 + %obit = extractvalue {i128, i1} %t, 1 + br i1 %obit, label %overflow, label %normal + +normal: + %t1 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @ok, i32 0, i32 0), i32 %sum32 ) nounwind + ret i1 true + +overflow: + %t2 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @no, i32 0, i32 0) ) nounwind + ret i1 false +} + +define i1 @func2(i128 zeroext %v1, i128 zeroext %v2) nounwind { +entry: + %t = call {i128, i1} @llvm.uadd.with.overflow.i128(i128 %v1, i128 %v2) + %sum = extractvalue {i128, i1} %t, 0 + %sum32 = trunc i128 %sum to i32 + %obit = extractvalue {i128, i1} %t, 1 + br i1 %obit, label %carry, label %normal + +normal: + %t1 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @ok, i32 0, i32 0), i32 %sum32 ) nounwind + ret i1 true + +carry: + %t2 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @no, i32 0, i32 0) ) nounwind + ret i1 false +} + +declare i32 @printf(i8*, ...) nounwind +declare {i128, i1} @llvm.sadd.with.overflow.i128(i128, i128) +declare {i128, i1} @llvm.uadd.with.overflow.i128(i128, i128) diff --git a/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll b/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll index 9c28da8..3489477 100644 --- a/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll +++ b/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll @@ -1,5 +1,4 @@ ; RUN: llc < %s | FileCheck %s -; RUN: llc < %s -regalloc=local | FileCheck %s ; RUN: llc < %s -regalloc=fast | FileCheck %s ; The first argument of subfc must not be the same as any other register. diff --git a/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll b/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll index 3cfe603..556a4a1c40 100644 --- a/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll +++ b/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll @@ -1,4 +1,3 @@ -; RUN: llc < %s -mtriple=powerpc64-apple-darwin9 -regalloc=local -relocation-model=pic ; RUN: llc < %s -mtriple=powerpc64-apple-darwin9 -regalloc=fast -relocation-model=pic %struct.NSError = type opaque diff --git a/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll b/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll index 8339a0b..b3b9280 100644 --- a/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll +++ b/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll @@ -1,4 +1,3 @@ -; RUN: llc < %s -mtriple=powerpc64-apple-darwin9 -regalloc=local -relocation-model=pic ; RUN: llc < %s -mtriple=powerpc64-apple-darwin9 -regalloc=fast -relocation-model=pic %struct.NSError = type opaque diff --git a/test/CodeGen/PowerPC/2008-02-09-LocalRegAllocAssert.ll b/test/CodeGen/PowerPC/2008-02-09-LocalRegAllocAssert.ll index 45dfdc8..e03bd9e 100644 --- a/test/CodeGen/PowerPC/2008-02-09-LocalRegAllocAssert.ll +++ b/test/CodeGen/PowerPC/2008-02-09-LocalRegAllocAssert.ll @@ -1,4 +1,3 @@ -; RUN: llc < %s -mtriple=powerpc-apple-darwin -regalloc=local ; RUN: llc < %s -mtriple=powerpc-apple-darwin -regalloc=fast define i32 @bork(i64 %foo, i64 %bar) { diff --git a/test/CodeGen/PowerPC/2008-03-06-KillInfo.ll b/test/CodeGen/PowerPC/2008-03-06-KillInfo.ll deleted file mode 100644 index 222dde4..0000000 --- a/test/CodeGen/PowerPC/2008-03-06-KillInfo.ll +++ /dev/null @@ -1,21 +0,0 @@ -; RUN: llc < %s -march=ppc64 -enable-ppc64-regscavenger -@.str242 = external constant [3 x i8] ; <[3 x i8]*> [#uses=1] - -define fastcc void @ParseContent(i8* %buf, i32 %bufsize) { -entry: - %items = alloca [10000 x i8*], align 16 ; <[10000 x i8*]*> [#uses=0] - %tmp86 = add i32 0, -1 ; <i32> [#uses=1] - br i1 false, label %cond_true94, label %cond_next99 -cond_true94: ; preds = %entry - %tmp98 = call i32 (i8*, ...)* @printf( i8* getelementptr ([3 x i8]* @.str242, i32 0, i32 0), i8* null ) ; <i32> [#uses=0] - %tmp20971 = icmp sgt i32 %tmp86, 0 ; <i1> [#uses=1] - br i1 %tmp20971, label %bb101, label %bb212 -cond_next99: ; preds = %entry - ret void -bb101: ; preds = %cond_true94 - ret void -bb212: ; preds = %cond_true94 - ret void -} - -declare i32 @printf(i8*, ...) diff --git a/test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll b/test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll index 50a0278..6a3c440 100644 --- a/test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll +++ b/test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll @@ -10,8 +10,8 @@ target triple = "powerpc-apple-darwin10.0" define void @foo(i32 %y) nounwind ssp { entry: ; CHECK: foo -; CHECK: add r4 -; CHECK: 0(r4) +; CHECK: add r3 +; CHECK: 0(r3) %y_addr = alloca i32 ; <i32*> [#uses=2] %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] store i32 %y, i32* %y_addr diff --git a/test/CodeGen/PowerPC/2009-08-23-linkerprivate.ll b/test/CodeGen/PowerPC/2009-08-23-linkerprivate.ll index 12c4c99..0bde2d5 100644 --- a/test/CodeGen/PowerPC/2009-08-23-linkerprivate.ll +++ b/test/CodeGen/PowerPC/2009-08-23-linkerprivate.ll @@ -2,7 +2,7 @@ ; ModuleID = '/Volumes/MacOS9/tests/WebKit/JavaScriptCore/profiler/ProfilerServer.mm' -@"\01l_objc_msgSend_fixup_alloc" = linker_private hidden global i32 0, section "__DATA, __objc_msgrefs, coalesced", align 16 ; <i32*> [#uses=0] +@"\01l_objc_msgSend_fixup_alloc" = linker_private_weak hidden global i32 0, section "__DATA, __objc_msgrefs, coalesced", align 16 ; CHECK: .globl l_objc_msgSend_fixup_alloc ; CHECK: .weak_definition l_objc_msgSend_fixup_alloc diff --git a/test/CodeGen/PowerPC/2010-02-26-FoldFloats.ll b/test/CodeGen/PowerPC/2010-02-26-FoldFloats.ll deleted file mode 100644 index f43f5ca..0000000 --- a/test/CodeGen/PowerPC/2010-02-26-FoldFloats.ll +++ /dev/null @@ -1,433 +0,0 @@ -; RUN: llc < %s -O3 | FileCheck %s -target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128-n32" -target triple = "powerpc-apple-darwin9.6" - -; There should be no stfs spills -; CHECK: main: -; CHECK-NOT: stfs -; CHECK: .section - -@.str66 = external constant [3 x i8], align 4 ; <[3 x i8]*> [#uses=1] -@.str31 = external constant [6 x i8], align 4 ; <[6 x i8]*> [#uses=1] -@.str61 = external constant [21 x i8], align 4 ; <[21 x i8]*> [#uses=1] -@.str101 = external constant [61 x i8], align 4 ; <[61 x i8]*> [#uses=1] -@.str104 = external constant [31 x i8], align 4 ; <[31 x i8]*> [#uses=1] -@.str105 = external constant [45 x i8], align 4 ; <[45 x i8]*> [#uses=1] -@.str112 = external constant [38 x i8], align 4 ; <[38 x i8]*> [#uses=1] -@.str121 = external constant [36 x i8], align 4 ; <[36 x i8]*> [#uses=1] -@.str12293 = external constant [67 x i8], align 4 ; <[67 x i8]*> [#uses=1] -@.str123 = external constant [68 x i8], align 4 ; <[68 x i8]*> [#uses=1] -@.str124 = external constant [52 x i8], align 4 ; <[52 x i8]*> [#uses=1] -@.str125 = external constant [51 x i8], align 4 ; <[51 x i8]*> [#uses=1] - -define i32 @main(i32 %argc, i8** %argv) noreturn nounwind { -entry: - br i1 undef, label %bb4.i1, label %my_fopen.exit - -bb4.i1: ; preds = %entry - unreachable - -my_fopen.exit: ; preds = %entry - br i1 undef, label %bb.i, label %bb1.i - -bb.i: ; preds = %my_fopen.exit - unreachable - -bb1.i: ; preds = %my_fopen.exit - br label %bb134.i - -bb2.i: ; preds = %bb134.i - %0 = icmp eq i32 undef, 0 ; <i1> [#uses=1] - br i1 %0, label %bb20.i, label %bb21.i - -bb20.i: ; preds = %bb2.i - br label %bb134.i - -bb21.i: ; preds = %bb2.i - %1 = call i32 @strcmp(i8* undef, i8* getelementptr inbounds ([6 x i8]* @.str31, i32 0, i32 0)) nounwind readonly ; <i32> [#uses=0] - br i1 undef, label %bb30.i, label %bb31.i - -bb30.i: ; preds = %bb21.i - br label %bb134.i - -bb31.i: ; preds = %bb21.i - br i1 undef, label %bb41.i, label %bb44.i - -bb41.i: ; preds = %bb31.i - %2 = icmp slt i32 undef, %argc ; <i1> [#uses=1] - br i1 %2, label %bb1.i77.i, label %bb2.i78.i - -bb1.i77.i: ; preds = %bb41.i - %3 = load float* undef, align 4 ; <float> [#uses=2] - %4 = fcmp ugt float %3, 0.000000e+00 ; <i1> [#uses=1] - br i1 %4, label %bb43.i, label %bb42.i - -bb2.i78.i: ; preds = %bb41.i - unreachable - -bb42.i: ; preds = %bb1.i77.i - unreachable - -bb43.i: ; preds = %bb1.i77.i - br label %bb134.i - -bb44.i: ; preds = %bb31.i - br i1 undef, label %bb45.i, label %bb49.i - -bb45.i: ; preds = %bb44.i - %5 = icmp slt i32 undef, %argc ; <i1> [#uses=1] - br i1 %5, label %bb1.i72.i, label %bb2.i73.i - -bb1.i72.i: ; preds = %bb45.i - %6 = load float* undef, align 4 ; <float> [#uses=3] - %7 = fcmp ult float %6, 1.000000e+00 ; <i1> [#uses=1] - %or.cond.i = and i1 undef, %7 ; <i1> [#uses=1] - br i1 %or.cond.i, label %bb48.i, label %bb47.i - -bb2.i73.i: ; preds = %bb45.i - unreachable - -bb47.i: ; preds = %bb1.i72.i - unreachable - -bb48.i: ; preds = %bb1.i72.i - br label %bb134.i - -bb49.i: ; preds = %bb44.i - br i1 undef, label %bb50.i, label %bb53.i - -bb50.i: ; preds = %bb49.i - br i1 false, label %bb1.i67.i, label %bb2.i68.i - -bb1.i67.i: ; preds = %bb50.i - br i1 false, label %read_float_option.exit69.i, label %bb1.i67.bb2.i68_crit_edge.i - -bb1.i67.bb2.i68_crit_edge.i: ; preds = %bb1.i67.i - br label %bb2.i68.i - -bb2.i68.i: ; preds = %bb1.i67.bb2.i68_crit_edge.i, %bb50.i - unreachable - -read_float_option.exit69.i: ; preds = %bb1.i67.i - br i1 undef, label %bb52.i, label %bb51.i - -bb51.i: ; preds = %read_float_option.exit69.i - unreachable - -bb52.i: ; preds = %read_float_option.exit69.i - br label %bb134.i - -bb53.i: ; preds = %bb49.i - %8 = call i32 @strcmp(i8* undef, i8* getelementptr inbounds ([21 x i8]* @.str61, i32 0, i32 0)) nounwind readonly ; <i32> [#uses=0] - br i1 false, label %bb89.i, label %bb92.i - -bb89.i: ; preds = %bb53.i - br i1 undef, label %bb1.i27.i, label %bb2.i28.i - -bb1.i27.i: ; preds = %bb89.i - unreachable - -bb2.i28.i: ; preds = %bb89.i - unreachable - -bb92.i: ; preds = %bb53.i - br i1 undef, label %bb93.i, label %bb96.i - -bb93.i: ; preds = %bb92.i - br i1 undef, label %bb1.i22.i, label %bb2.i23.i - -bb1.i22.i: ; preds = %bb93.i - br i1 undef, label %bb95.i, label %bb94.i - -bb2.i23.i: ; preds = %bb93.i - unreachable - -bb94.i: ; preds = %bb1.i22.i - unreachable - -bb95.i: ; preds = %bb1.i22.i - br label %bb134.i - -bb96.i: ; preds = %bb92.i - br i1 undef, label %bb97.i, label %bb100.i - -bb97.i: ; preds = %bb96.i - %9 = icmp slt i32 undef, %argc ; <i1> [#uses=1] - br i1 %9, label %bb1.i17.i, label %bb2.i18.i - -bb1.i17.i: ; preds = %bb97.i - %10 = call i32 (i8*, i8*, ...)* @"\01_sscanf$LDBL128"(i8* undef, i8* getelementptr inbounds ([3 x i8]* @.str66, i32 0, i32 0), float* undef) nounwind ; <i32> [#uses=1] - %phitmp.i16.i = icmp eq i32 %10, 1 ; <i1> [#uses=1] - br i1 %phitmp.i16.i, label %read_float_option.exit19.i, label %bb1.i17.bb2.i18_crit_edge.i - -bb1.i17.bb2.i18_crit_edge.i: ; preds = %bb1.i17.i - br label %bb2.i18.i - -bb2.i18.i: ; preds = %bb1.i17.bb2.i18_crit_edge.i, %bb97.i - unreachable - -read_float_option.exit19.i: ; preds = %bb1.i17.i - br i1 false, label %bb99.i, label %bb98.i - -bb98.i: ; preds = %read_float_option.exit19.i - unreachable - -bb99.i: ; preds = %read_float_option.exit19.i - br label %bb134.i - -bb100.i: ; preds = %bb96.i - br i1 false, label %bb101.i, label %bb104.i - -bb101.i: ; preds = %bb100.i - br i1 false, label %bb1.i12.i, label %bb2.i13.i - -bb1.i12.i: ; preds = %bb101.i - br i1 undef, label %bb102.i, label %bb103.i - -bb2.i13.i: ; preds = %bb101.i - unreachable - -bb102.i: ; preds = %bb1.i12.i - unreachable - -bb103.i: ; preds = %bb1.i12.i - br label %bb134.i - -bb104.i: ; preds = %bb100.i - unreachable - -bb134.i: ; preds = %bb103.i, %bb99.i, %bb95.i, %bb52.i, %bb48.i, %bb43.i, %bb30.i, %bb20.i, %bb1.i - %annealing_sched.1.0 = phi float [ 1.000000e+01, %bb1.i ], [ %annealing_sched.1.0, %bb20.i ], [ 1.000000e+00, %bb30.i ], [ %annealing_sched.1.0, %bb43.i ], [ %annealing_sched.1.0, %bb48.i ], [ %annealing_sched.1.0, %bb52.i ], [ %annealing_sched.1.0, %bb95.i ], [ %annealing_sched.1.0, %bb99.i ], [ %annealing_sched.1.0, %bb103.i ] ; <float> [#uses=8] - %annealing_sched.2.0 = phi float [ 1.000000e+02, %bb1.i ], [ %annealing_sched.2.0, %bb20.i ], [ %annealing_sched.2.0, %bb30.i ], [ %3, %bb43.i ], [ %annealing_sched.2.0, %bb48.i ], [ %annealing_sched.2.0, %bb52.i ], [ %annealing_sched.2.0, %bb95.i ], [ %annealing_sched.2.0, %bb99.i ], [ %annealing_sched.2.0, %bb103.i ] ; <float> [#uses=8] - %annealing_sched.3.0 = phi float [ 0x3FE99999A0000000, %bb1.i ], [ %annealing_sched.3.0, %bb20.i ], [ %annealing_sched.3.0, %bb30.i ], [ %annealing_sched.3.0, %bb43.i ], [ %6, %bb48.i ], [ %annealing_sched.3.0, %bb52.i ], [ %annealing_sched.3.0, %bb95.i ], [ %annealing_sched.3.0, %bb99.i ], [ %annealing_sched.3.0, %bb103.i ] ; <float> [#uses=8] - %annealing_sched.4.0 = phi float [ 0x3F847AE140000000, %bb1.i ], [ %annealing_sched.4.0, %bb20.i ], [ %annealing_sched.4.0, %bb30.i ], [ %annealing_sched.4.0, %bb43.i ], [ %annealing_sched.4.0, %bb48.i ], [ 0.000000e+00, %bb52.i ], [ %annealing_sched.4.0, %bb95.i ], [ %annealing_sched.4.0, %bb99.i ], [ %annealing_sched.4.0, %bb103.i ] ; <float> [#uses=8] - %router_opts.0.0 = phi float [ 0.000000e+00, %bb1.i ], [ %router_opts.0.0, %bb20.i ], [ 1.000000e+04, %bb30.i ], [ %router_opts.0.0, %bb43.i ], [ %router_opts.0.0, %bb48.i ], [ %router_opts.0.0, %bb52.i ], [ %router_opts.0.0, %bb95.i ], [ %router_opts.0.0, %bb99.i ], [ %router_opts.0.0, %bb103.i ] ; <float> [#uses=8] - %router_opts.1.0 = phi float [ 5.000000e-01, %bb1.i ], [ %router_opts.1.0, %bb20.i ], [ 1.000000e+04, %bb30.i ], [ %router_opts.1.0, %bb43.i ], [ %router_opts.1.0, %bb48.i ], [ %router_opts.1.0, %bb52.i ], [ undef, %bb95.i ], [ %router_opts.1.0, %bb99.i ], [ %router_opts.1.0, %bb103.i ] ; <float> [#uses=7] - %router_opts.2.0 = phi float [ 1.500000e+00, %bb1.i ], [ %router_opts.2.0, %bb20.i ], [ %router_opts.2.0, %bb30.i ], [ %router_opts.2.0, %bb43.i ], [ %router_opts.2.0, %bb48.i ], [ %router_opts.2.0, %bb52.i ], [ %router_opts.2.0, %bb95.i ], [ undef, %bb99.i ], [ %router_opts.2.0, %bb103.i ] ; <float> [#uses=8] - %router_opts.3.0 = phi float [ 0x3FC99999A0000000, %bb1.i ], [ %router_opts.3.0, %bb20.i ], [ %router_opts.3.0, %bb30.i ], [ %router_opts.3.0, %bb43.i ], [ %router_opts.3.0, %bb48.i ], [ %router_opts.3.0, %bb52.i ], [ %router_opts.3.0, %bb95.i ], [ %router_opts.3.0, %bb99.i ], [ 0.000000e+00, %bb103.i ] ; <float> [#uses=8] - %11 = phi float [ 0x3FC99999A0000000, %bb1.i ], [ %11, %bb20.i ], [ %11, %bb30.i ], [ %11, %bb43.i ], [ %11, %bb48.i ], [ %11, %bb52.i ], [ %11, %bb95.i ], [ %11, %bb99.i ], [ 0.000000e+00, %bb103.i ] ; <float> [#uses=8] - %12 = phi float [ 1.500000e+00, %bb1.i ], [ %12, %bb20.i ], [ %12, %bb30.i ], [ %12, %bb43.i ], [ %12, %bb48.i ], [ %12, %bb52.i ], [ %12, %bb95.i ], [ undef, %bb99.i ], [ %12, %bb103.i ] ; <float> [#uses=8] - %13 = phi float [ 5.000000e-01, %bb1.i ], [ %13, %bb20.i ], [ 1.000000e+04, %bb30.i ], [ %13, %bb43.i ], [ %13, %bb48.i ], [ %13, %bb52.i ], [ undef, %bb95.i ], [ %13, %bb99.i ], [ %13, %bb103.i ] ; <float> [#uses=7] - %14 = phi float [ 0.000000e+00, %bb1.i ], [ %14, %bb20.i ], [ 1.000000e+04, %bb30.i ], [ %14, %bb43.i ], [ %14, %bb48.i ], [ %14, %bb52.i ], [ %14, %bb95.i ], [ %14, %bb99.i ], [ %14, %bb103.i ] ; <float> [#uses=8] - %15 = phi float [ 0x3FE99999A0000000, %bb1.i ], [ %15, %bb20.i ], [ %15, %bb30.i ], [ %15, %bb43.i ], [ %6, %bb48.i ], [ %15, %bb52.i ], [ %15, %bb95.i ], [ %15, %bb99.i ], [ %15, %bb103.i ] ; <float> [#uses=8] - %16 = phi float [ 0x3F847AE140000000, %bb1.i ], [ %16, %bb20.i ], [ %16, %bb30.i ], [ %16, %bb43.i ], [ %16, %bb48.i ], [ 0.000000e+00, %bb52.i ], [ %16, %bb95.i ], [ %16, %bb99.i ], [ %16, %bb103.i ] ; <float> [#uses=8] - %17 = phi float [ 1.000000e+01, %bb1.i ], [ %17, %bb20.i ], [ 1.000000e+00, %bb30.i ], [ %17, %bb43.i ], [ %17, %bb48.i ], [ %17, %bb52.i ], [ %17, %bb95.i ], [ %17, %bb99.i ], [ %17, %bb103.i ] ; <float> [#uses=8] - %18 = icmp slt i32 undef, %argc ; <i1> [#uses=1] - br i1 %18, label %bb2.i, label %bb135.i - -bb135.i: ; preds = %bb134.i - br i1 undef, label %bb141.i, label %bb142.i - -bb141.i: ; preds = %bb135.i - unreachable - -bb142.i: ; preds = %bb135.i - br i1 undef, label %bb145.i, label %bb144.i - -bb144.i: ; preds = %bb142.i - unreachable - -bb145.i: ; preds = %bb142.i - br i1 undef, label %bb146.i, label %bb147.i - -bb146.i: ; preds = %bb145.i - unreachable - -bb147.i: ; preds = %bb145.i - br i1 undef, label %bb148.i, label %bb155.i - -bb148.i: ; preds = %bb147.i - br label %bb155.i - -bb155.i: ; preds = %bb148.i, %bb147.i - br i1 undef, label %bb156.i, label %bb161.i - -bb156.i: ; preds = %bb155.i - unreachable - -bb161.i: ; preds = %bb155.i - br i1 undef, label %bb162.i, label %bb163.i - -bb162.i: ; preds = %bb161.i - %19 = fpext float %17 to double ; <double> [#uses=1] - %20 = call i32 (i8*, ...)* @"\01_printf$LDBL128"(i8* getelementptr inbounds ([61 x i8]* @.str101, i32 0, i32 0), double %19) nounwind ; <i32> [#uses=0] - unreachable - -bb163.i: ; preds = %bb161.i - %21 = fpext float %16 to double ; <double> [#uses=1] - %22 = call i32 (i8*, ...)* @"\01_printf$LDBL128"(i8* getelementptr inbounds ([31 x i8]* @.str104, i32 0, i32 0), double %21) nounwind ; <i32> [#uses=0] - %23 = fpext float %15 to double ; <double> [#uses=1] - %24 = call i32 (i8*, ...)* @"\01_printf$LDBL128"(i8* getelementptr inbounds ([45 x i8]* @.str105, i32 0, i32 0), double %23) nounwind ; <i32> [#uses=0] - %25 = call i32 (i8*, ...)* @"\01_printf$LDBL128"(i8* getelementptr inbounds ([38 x i8]* @.str112, i32 0, i32 0), double undef) nounwind ; <i32> [#uses=0] - br i1 undef, label %parse_command.exit, label %bb176.i - -bb176.i: ; preds = %bb163.i - br i1 undef, label %bb177.i, label %bb178.i - -bb177.i: ; preds = %bb176.i - unreachable - -bb178.i: ; preds = %bb176.i - %26 = call i32 (i8*, ...)* @"\01_printf$LDBL128"(i8* getelementptr inbounds ([36 x i8]* @.str121, i32 0, i32 0), double undef) nounwind ; <i32> [#uses=0] - %27 = fpext float %14 to double ; <double> [#uses=1] - %28 = call i32 (i8*, ...)* @"\01_printf$LDBL128"(i8* getelementptr inbounds ([67 x i8]* @.str12293, i32 0, i32 0), double %27) nounwind ; <i32> [#uses=0] - %29 = fpext float %13 to double ; <double> [#uses=1] - %30 = call i32 (i8*, ...)* @"\01_printf$LDBL128"(i8* getelementptr inbounds ([68 x i8]* @.str123, i32 0, i32 0), double %29) nounwind ; <i32> [#uses=0] - %31 = fpext float %12 to double ; <double> [#uses=1] - %32 = call i32 (i8*, ...)* @"\01_printf$LDBL128"(i8* getelementptr inbounds ([52 x i8]* @.str124, i32 0, i32 0), double %31) nounwind ; <i32> [#uses=0] - %33 = fpext float %11 to double ; <double> [#uses=1] - %34 = call i32 (i8*, ...)* @"\01_printf$LDBL128"(i8* getelementptr inbounds ([51 x i8]* @.str125, i32 0, i32 0), double %33) nounwind ; <i32> [#uses=0] - unreachable - -parse_command.exit: ; preds = %bb163.i - br i1 undef, label %bb4.i152.i, label %my_fopen.exit.i - -bb4.i152.i: ; preds = %parse_command.exit - unreachable - -my_fopen.exit.i: ; preds = %parse_command.exit - br i1 undef, label %bb.i6.i99, label %bb49.preheader.i.i - -bb.i6.i99: ; preds = %my_fopen.exit.i - br i1 undef, label %bb3.i.i100, label %bb1.i8.i - -bb1.i8.i: ; preds = %bb.i6.i99 - unreachable - -bb3.i.i100: ; preds = %bb.i6.i99 - unreachable - -bb49.preheader.i.i: ; preds = %my_fopen.exit.i - br i1 undef, label %bb7.i11.i, label %bb50.i.i - -bb7.i11.i: ; preds = %bb49.preheader.i.i - unreachable - -bb50.i.i: ; preds = %bb49.preheader.i.i - br i1 undef, label %bb.i.i.i20.i, label %my_calloc.exit.i.i.i - -bb.i.i.i20.i: ; preds = %bb50.i.i - unreachable - -my_calloc.exit.i.i.i: ; preds = %bb50.i.i - br i1 undef, label %bb.i.i37.i.i, label %alloc_hash_table.exit.i21.i - -bb.i.i37.i.i: ; preds = %my_calloc.exit.i.i.i - unreachable - -alloc_hash_table.exit.i21.i: ; preds = %my_calloc.exit.i.i.i - br i1 undef, label %bb51.i.i, label %bb3.i23.i.i - -bb51.i.i: ; preds = %alloc_hash_table.exit.i21.i - unreachable - -bb3.i23.i.i: ; preds = %alloc_hash_table.exit.i21.i - br i1 undef, label %bb.i8.i.i, label %bb.nph.i.i - -bb.nph.i.i: ; preds = %bb3.i23.i.i - unreachable - -bb.i8.i.i: ; preds = %bb3.i.i34.i, %bb3.i23.i.i - br i1 undef, label %bb3.i.i34.i, label %bb1.i.i32.i - -bb1.i.i32.i: ; preds = %bb.i8.i.i - unreachable - -bb3.i.i34.i: ; preds = %bb.i8.i.i - br i1 undef, label %free_hash_table.exit.i.i, label %bb.i8.i.i - -free_hash_table.exit.i.i: ; preds = %bb3.i.i34.i - br i1 undef, label %check_netlist.exit.i, label %bb59.i.i - -bb59.i.i: ; preds = %free_hash_table.exit.i.i - unreachable - -check_netlist.exit.i: ; preds = %free_hash_table.exit.i.i - br label %bb.i.i3.i - -bb.i.i3.i: ; preds = %bb3.i.i4.i, %check_netlist.exit.i - br i1 false, label %bb3.i.i4.i, label %bb1.i.i.i122 - -bb1.i.i.i122: ; preds = %bb1.i.i.i122, %bb.i.i3.i - br i1 false, label %bb3.i.i4.i, label %bb1.i.i.i122 - -bb3.i.i4.i: ; preds = %bb1.i.i.i122, %bb.i.i3.i - br i1 undef, label %read_net.exit, label %bb.i.i3.i - -read_net.exit: ; preds = %bb3.i.i4.i - br i1 undef, label %bb.i44, label %bb3.i47 - -bb.i44: ; preds = %read_net.exit - unreachable - -bb3.i47: ; preds = %read_net.exit - br i1 false, label %bb9.i50, label %bb8.i49 - -bb8.i49: ; preds = %bb3.i47 - unreachable - -bb9.i50: ; preds = %bb3.i47 - br i1 undef, label %bb11.i51, label %bb12.i52 - -bb11.i51: ; preds = %bb9.i50 - unreachable - -bb12.i52: ; preds = %bb9.i50 - br i1 undef, label %bb.i.i53, label %my_malloc.exit.i54 - -bb.i.i53: ; preds = %bb12.i52 - unreachable - -my_malloc.exit.i54: ; preds = %bb12.i52 - br i1 undef, label %bb.i2.i55, label %my_malloc.exit3.i56 - -bb.i2.i55: ; preds = %my_malloc.exit.i54 - unreachable - -my_malloc.exit3.i56: ; preds = %my_malloc.exit.i54 - br i1 undef, label %bb.i.i.i57, label %my_malloc.exit.i.i - -bb.i.i.i57: ; preds = %my_malloc.exit3.i56 - unreachable - -my_malloc.exit.i.i: ; preds = %my_malloc.exit3.i56 - br i1 undef, label %bb, label %bb10 - -bb: ; preds = %my_malloc.exit.i.i - unreachable - -bb10: ; preds = %my_malloc.exit.i.i - br i1 false, label %bb12, label %bb11 - -bb11: ; preds = %bb10 - unreachable - -bb12: ; preds = %bb10 - store float %annealing_sched.1.0, float* null, align 4 - store float %annealing_sched.2.0, float* undef, align 8 - store float %annealing_sched.3.0, float* undef, align 4 - store float %annealing_sched.4.0, float* undef, align 8 - store float %router_opts.0.0, float* undef, align 8 - store float %router_opts.1.0, float* undef, align 4 - store float %router_opts.2.0, float* null, align 8 - store float %router_opts.3.0, float* undef, align 4 - br i1 undef, label %place_and_route.exit, label %bb7.i22 - -bb7.i22: ; preds = %bb12 - br i1 false, label %bb8.i23, label %bb9.i26 - -bb8.i23: ; preds = %bb7.i22 - unreachable - -bb9.i26: ; preds = %bb7.i22 - unreachable - -place_and_route.exit: ; preds = %bb12 - unreachable -} - -declare i32 @"\01_printf$LDBL128"(i8*, ...) nounwind - -declare i32 @strcmp(i8* nocapture, i8* nocapture) nounwind readonly - -declare i32 @"\01_sscanf$LDBL128"(i8*, i8*, ...) nounwind diff --git a/test/CodeGen/PowerPC/cr_spilling.ll b/test/CodeGen/PowerPC/cr_spilling.ll index 9ed2614..8bd809f 100644 --- a/test/CodeGen/PowerPC/cr_spilling.ll +++ b/test/CodeGen/PowerPC/cr_spilling.ll @@ -1,4 +1,3 @@ -; RUN: llc < %s -march=ppc32 -regalloc=local -O0 -relocation-model=pic -o - ; RUN: llc < %s -march=ppc32 -regalloc=fast -O0 -relocation-model=pic -o - ; PR1638 diff --git a/test/CodeGen/Generic/stack-protector.ll b/test/CodeGen/PowerPC/stack-protector.ll index a59c649..2020361 100644 --- a/test/CodeGen/Generic/stack-protector.ll +++ b/test/CodeGen/PowerPC/stack-protector.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -o - | grep {__stack_chk_guard} -; RUN: llc < %s -o - | grep {__stack_chk_fail} +; RUN: llc -march=ppc32 < %s -o - | grep {__stack_chk_guard} +; RUN: llc -march=ppc32 < %s -o - | grep {__stack_chk_fail} @"\01LC" = internal constant [11 x i8] c"buf == %s\0A\00" ; <[11 x i8]*> [#uses=1] @@ -7,12 +7,12 @@ define void @test(i8* %a) nounwind ssp { entry: %a_addr = alloca i8* ; <i8**> [#uses=2] %buf = alloca [8 x i8] ; <[8 x i8]*> [#uses=2] - %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] + %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] store i8* %a, i8** %a_addr %buf1 = bitcast [8 x i8]* %buf to i8* ; <i8*> [#uses=1] %0 = load i8** %a_addr, align 4 ; <i8*> [#uses=1] %1 = call i8* @strcpy(i8* %buf1, i8* %0) nounwind ; <i8*> [#uses=0] - %buf2 = bitcast [8 x i8]* %buf to i8* ; <i8*> [#uses=1] + %buf2 = bitcast [8 x i8]* %buf to i8* ; <i8*> [#uses=1] %2 = call i32 (i8*, ...)* @printf(i8* getelementptr ([11 x i8]* @"\01LC", i32 0, i32 0), i8* %buf2) nounwind ; <i32> [#uses=0] br label %return diff --git a/test/CodeGen/Thumb/2009-07-19-SPDecBug.ll b/test/CodeGen/Thumb/2009-07-19-SPDecBug.ll index 471a82f..9cdcd31 100644 --- a/test/CodeGen/Thumb/2009-07-19-SPDecBug.ll +++ b/test/CodeGen/Thumb/2009-07-19-SPDecBug.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -mtriple=thumbv6-elf | not grep "subs sp" ; PR4567 -define arm_apcscc i8* @__gets_chk(i8* %s, i32 %slen) nounwind { +define i8* @__gets_chk(i8* %s, i32 %slen) nounwind { entry: br i1 undef, label %bb, label %bb1 @@ -23,11 +23,11 @@ bb4: ; preds = %bb3, %bb2 br i1 undef, label %bb5, label %bb6 bb5: ; preds = %bb4 - %2 = call arm_apcscc i8* @gets(i8* %s) nounwind ; <i8*> [#uses=1] + %2 = call i8* @gets(i8* %s) nounwind ; <i8*> [#uses=1] ret i8* %2 bb6: ; preds = %bb4 unreachable } -declare arm_apcscc i8* @gets(i8*) nounwind +declare i8* @gets(i8*) nounwind diff --git a/test/CodeGen/Thumb/2009-07-20-TwoAddrBug.ll b/test/CodeGen/Thumb/2009-07-20-TwoAddrBug.ll index 6e035d0..d4651a1 100644 --- a/test/CodeGen/Thumb/2009-07-20-TwoAddrBug.ll +++ b/test/CodeGen/Thumb/2009-07-20-TwoAddrBug.ll @@ -2,7 +2,7 @@ @Time.2535 = external global i64 ; <i64*> [#uses=2] -define arm_apcscc i64 @millisecs() nounwind { +define i64 @millisecs() nounwind { entry: %0 = load i64* @Time.2535, align 4 ; <i64> [#uses=2] %1 = add i64 %0, 1 ; <i64> [#uses=1] diff --git a/test/CodeGen/Thumb/2009-07-27-PEIAssert.ll b/test/CodeGen/Thumb/2009-07-27-PEIAssert.ll index f195348..aaca3a7 100644 --- a/test/CodeGen/Thumb/2009-07-27-PEIAssert.ll +++ b/test/CodeGen/Thumb/2009-07-27-PEIAssert.ll @@ -4,10 +4,10 @@ %struct.List = type { i32, i32* } @llvm.used = appending global [1 x i8*] [i8* bitcast (i32 ()* @main to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] -define arm_apcscc i32 @main() nounwind { +define i32 @main() nounwind { entry: %ll = alloca %struct.LinkList*, align 4 ; <%struct.LinkList**> [#uses=1] - %0 = call arm_apcscc i32 @ReadList(%struct.LinkList** %ll, %struct.List** null) nounwind ; <i32> [#uses=1] + %0 = call i32 @ReadList(%struct.LinkList** %ll, %struct.List** null) nounwind ; <i32> [#uses=1] switch i32 %0, label %bb5 [ i32 7, label %bb4 i32 42, label %bb3 @@ -23,4 +23,4 @@ bb5: ; preds = %entry ret i32 1 } -declare arm_apcscc i32 @ReadList(%struct.LinkList** nocapture, %struct.List** nocapture) nounwind +declare i32 @ReadList(%struct.LinkList** nocapture, %struct.List** nocapture) nounwind diff --git a/test/CodeGen/Thumb/2009-08-12-ConstIslandAssert.ll b/test/CodeGen/Thumb/2009-08-12-ConstIslandAssert.ll index ef4b5ce..5b420fc 100644 --- a/test/CodeGen/Thumb/2009-08-12-ConstIslandAssert.ll +++ b/test/CodeGen/Thumb/2009-08-12-ConstIslandAssert.ll @@ -2,7 +2,7 @@ %struct.BF_KEY = type { [18 x i32], [1024 x i32] } -define arm_apcscc void @BF_encrypt(i32* nocapture %data, %struct.BF_KEY* nocapture %key, i32 %encrypt) nounwind { +define void @BF_encrypt(i32* nocapture %data, %struct.BF_KEY* nocapture %key, i32 %encrypt) nounwind { entry: %0 = getelementptr %struct.BF_KEY* %key, i32 0, i32 0, i32 0; <i32*> [#uses=2] %1 = load i32* %data, align 4 ; <i32> [#uses=2] diff --git a/test/CodeGen/Thumb/2009-08-12-RegInfoAssert.ll b/test/CodeGen/Thumb/2009-08-12-RegInfoAssert.ll index b6e67b1..041306d 100644 --- a/test/CodeGen/Thumb/2009-08-12-RegInfoAssert.ll +++ b/test/CodeGen/Thumb/2009-08-12-RegInfoAssert.ll @@ -3,15 +3,15 @@ %struct.vorbis_comment = type { i8**, i32*, i32, i8* } @.str16 = external constant [2 x i8], align 1 ; <[2 x i8]*> [#uses=1] -declare arm_apcscc i8* @__strcpy_chk(i8*, i8*, i32) nounwind +declare i8* @__strcpy_chk(i8*, i8*, i32) nounwind -declare arm_apcscc i8* @__strcat_chk(i8*, i8*, i32) nounwind +declare i8* @__strcat_chk(i8*, i8*, i32) nounwind -define arm_apcscc i8* @vorbis_comment_query(%struct.vorbis_comment* nocapture %vc, i8* %tag, i32 %count) nounwind { +define i8* @vorbis_comment_query(%struct.vorbis_comment* nocapture %vc, i8* %tag, i32 %count) nounwind { entry: %0 = alloca i8, i32 undef, align 4 ; <i8*> [#uses=2] - %1 = call arm_apcscc i8* @__strcpy_chk(i8* %0, i8* %tag, i32 -1) nounwind; <i8*> [#uses=0] - %2 = call arm_apcscc i8* @__strcat_chk(i8* %0, i8* getelementptr ([2 x i8]* @.str16, i32 0, i32 0), i32 -1) nounwind; <i8*> [#uses=0] + %1 = call i8* @__strcpy_chk(i8* %0, i8* %tag, i32 -1) nounwind; <i8*> [#uses=0] + %2 = call i8* @__strcat_chk(i8* %0, i8* getelementptr ([2 x i8]* @.str16, i32 0, i32 0), i32 -1) nounwind; <i8*> [#uses=0] %3 = getelementptr %struct.vorbis_comment* %vc, i32 0, i32 0; <i8***> [#uses=1] br label %bb11 diff --git a/test/CodeGen/Thumb/2009-08-20-ISelBug.ll b/test/CodeGen/Thumb/2009-08-20-ISelBug.ll index 72c9e62..39612c0 100644 --- a/test/CodeGen/Thumb/2009-08-20-ISelBug.ll +++ b/test/CodeGen/Thumb/2009-08-20-ISelBug.ll @@ -9,7 +9,7 @@ @llvm.used = appending global [1 x i8*] [i8* bitcast (i32 (%struct.asl_file_t*, i64, i64*)* @t to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] -define arm_apcscc i32 @t(%struct.asl_file_t* %s, i64 %off, i64* %out) nounwind optsize { +define i32 @t(%struct.asl_file_t* %s, i64 %off, i64* %out) nounwind optsize { ; CHECK: t: ; CHECK: adds r0, #8 entry: @@ -32,7 +32,7 @@ bb3: ; preds = %bb1 br i1 %8, label %bb13, label %bb5 bb5: ; preds = %bb3 - %9 = call arm_apcscc i32 @fseeko(%struct.FILE* %2, i64 %off, i32 0) nounwind ; <i32> [#uses=1] + %9 = call i32 @fseeko(%struct.FILE* %2, i64 %off, i32 0) nounwind ; <i32> [#uses=1] %10 = icmp eq i32 %9, 0 ; <i1> [#uses=1] br i1 %10, label %bb7, label %bb13 @@ -40,7 +40,7 @@ bb7: ; preds = %bb5 store i64 0, i64* %val, align 4 %11 = load %struct.FILE** %1, align 4 ; <%struct.FILE*> [#uses=1] %val8 = bitcast i64* %val to i8* ; <i8*> [#uses=1] - %12 = call arm_apcscc i32 @fread(i8* noalias %val8, i32 8, i32 1, %struct.FILE* noalias %11) nounwind ; <i32> [#uses=1] + %12 = call i32 @fread(i8* noalias %val8, i32 8, i32 1, %struct.FILE* noalias %11) nounwind ; <i32> [#uses=1] %13 = icmp eq i32 %12, 1 ; <i1> [#uses=1] br i1 %13, label %bb10, label %bb13 @@ -50,7 +50,7 @@ bb10: ; preds = %bb7 bb11: ; preds = %bb10 %15 = load i64* %val, align 4 ; <i64> [#uses=1] - %16 = call arm_apcscc i64 @asl_core_ntohq(i64 %15) nounwind ; <i64> [#uses=1] + %16 = call i64 @asl_core_ntohq(i64 %15) nounwind ; <i64> [#uses=1] store i64 %16, i64* %out, align 4 ret i32 0 @@ -59,8 +59,8 @@ bb13: ; preds = %bb10, %bb7, %bb5, % ret i32 %.0 } -declare arm_apcscc i32 @fseeko(%struct.FILE* nocapture, i64, i32) nounwind +declare i32 @fseeko(%struct.FILE* nocapture, i64, i32) nounwind -declare arm_apcscc i32 @fread(i8* noalias nocapture, i32, i32, %struct.FILE* noalias nocapture) nounwind +declare i32 @fread(i8* noalias nocapture, i32, i32, %struct.FILE* noalias nocapture) nounwind -declare arm_apcscc i64 @asl_core_ntohq(i64) +declare i64 @asl_core_ntohq(i64) diff --git a/test/CodeGen/Thumb/2009-12-17-pre-regalloc-taildup.ll b/test/CodeGen/Thumb/2009-12-17-pre-regalloc-taildup.ll index 2a5d9d6..132d9ac 100644 --- a/test/CodeGen/Thumb/2009-12-17-pre-regalloc-taildup.ll +++ b/test/CodeGen/Thumb/2009-12-17-pre-regalloc-taildup.ll @@ -10,7 +10,7 @@ target triple = "thumbv7-apple-darwin10" @codetable.2928 = internal constant [5 x i8*] [i8* blockaddress(@interpret_threaded, %RETURN), i8* blockaddress(@interpret_threaded, %INCREMENT), i8* blockaddress(@interpret_threaded, %DECREMENT), i8* blockaddress(@interpret_threaded, %DOUBLE), i8* blockaddress(@interpret_threaded, %SWAPWORD)] ; <[5 x i8*]*> [#uses=5] @llvm.used = appending global [1 x i8*] [i8* bitcast (i32 (i8*)* @interpret_threaded to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] -define arm_apcscc i32 @interpret_threaded(i8* nocapture %opcodes) nounwind readonly optsize { +define i32 @interpret_threaded(i8* nocapture %opcodes) nounwind readonly optsize { entry: %0 = load i8* %opcodes, align 1 ; <i8> [#uses=1] %1 = zext i8 %0 to i32 ; <i32> [#uses=1] diff --git a/test/CodeGen/Thumb/2010-01-15-local-alloc-spill-physical.ll b/test/CodeGen/Thumb/2010-01-15-local-alloc-spill-physical.ll index 300e66c..fad2669 100644 --- a/test/CodeGen/Thumb/2010-01-15-local-alloc-spill-physical.ll +++ b/test/CodeGen/Thumb/2010-01-15-local-alloc-spill-physical.ll @@ -1,14 +1,13 @@ -; RUN: llc < %s -regalloc=local -relocation-model=pic | FileCheck %s ; RUN: llc < %s -regalloc=fast -relocation-model=pic | FileCheck %s target triple = "thumbv6-apple-darwin10" @fred = internal global i32 0 ; <i32*> [#uses=1] -define arm_apcscc void @foo() nounwind { +define void @foo() nounwind { entry: ; CHECK: str r0, [sp - %0 = call arm_apcscc i32 (...)* @bar() nounwind ; <i32> [#uses=1] + %0 = call i32 (...)* @bar() nounwind ; <i32> [#uses=1] ; CHECK: blx _bar ; CHECK: ldr r1, [sp store i32 %0, i32* @fred, align 4 @@ -18,4 +17,4 @@ return: ; preds = %entry ret void } -declare arm_apcscc i32 @bar(...) +declare i32 @bar(...) diff --git a/test/CodeGen/Thumb/2010-06-18-SibCallCrash.ll b/test/CodeGen/Thumb/2010-06-18-SibCallCrash.ll new file mode 100644 index 0000000..ad8b064 --- /dev/null +++ b/test/CodeGen/Thumb/2010-06-18-SibCallCrash.ll @@ -0,0 +1,8 @@ +; RUN: llc -march=thumb < %s +; rdar://8104457 + +define arm_apcscc void @t(i32* %m) nounwind { +entry: + tail call arm_apcscc void undef(i32* %m, i16 zeroext undef) nounwind + ret void +} diff --git a/test/CodeGen/Thumb/2010-07-01-FuncAlign.ll b/test/CodeGen/Thumb/2010-07-01-FuncAlign.ll new file mode 100644 index 0000000..8e09441 --- /dev/null +++ b/test/CodeGen/Thumb/2010-07-01-FuncAlign.ll @@ -0,0 +1,6 @@ +; RUN: llc < %s -mtriple=thumb-apple-darwin | FileCheck %s +; Radar 8143571: Function alignments were off by a power of two. +; CHECK: .align 1 +define void @test() { + ret void +} diff --git a/test/CodeGen/Thumb/asmprinter-bug.ll b/test/CodeGen/Thumb/asmprinter-bug.ll index 1e3c070..f73f93d 100644 --- a/test/CodeGen/Thumb/asmprinter-bug.ll +++ b/test/CodeGen/Thumb/asmprinter-bug.ll @@ -13,7 +13,7 @@ @__stderrp = external global %struct.FILE* ; <%struct.FILE**> [#uses=1] @.str1 = private constant [28 x i8] c"Final valprev=%d, index=%d\0A\00", section "__TEXT,__cstring,cstring_literals", align 1 ; <[28 x i8]*> [#uses=1] -define arm_apcscc void @adpcm_coder(i16* nocapture %indata, i8* nocapture %outdata, i32 %len, %struct.adpcm_state* nocapture %state) nounwind { +define void @adpcm_coder(i16* nocapture %indata, i8* nocapture %outdata, i32 %len, %struct.adpcm_state* nocapture %state) nounwind { entry: %0 = getelementptr %struct.adpcm_state* %state, i32 0, i32 0 ; <i16*> [#uses=2] %1 = load i16* %0, align 2 ; <i16> [#uses=1] @@ -138,7 +138,7 @@ bb29: ; preds = %bb28, %bb27 ret void } -define arm_apcscc void @adpcm_decoder(i8* nocapture %indata, i16* nocapture %outdata, i32 %len, %struct.adpcm_state* nocapture %state) nounwind { +define void @adpcm_decoder(i8* nocapture %indata, i16* nocapture %outdata, i32 %len, %struct.adpcm_state* nocapture %state) nounwind { entry: %0 = getelementptr %struct.adpcm_state* %state, i32 0, i32 0 ; <i16*> [#uses=2] %1 = load i16* %0, align 2 ; <i16> [#uses=1] @@ -245,17 +245,17 @@ bb22: ; preds = %bb20, %entry ret void } -define arm_apcscc i32 @main() nounwind { +define i32 @main() nounwind { entry: br label %bb bb: ; preds = %bb3, %entry - %0 = tail call arm_apcscc i32 (...)* @read(i32 0, i8* getelementptr ([500 x i8]* @abuf, i32 0, i32 0), i32 500) nounwind ; <i32> [#uses=4] + %0 = tail call i32 (...)* @read(i32 0, i8* getelementptr ([500 x i8]* @abuf, i32 0, i32 0), i32 500) nounwind ; <i32> [#uses=4] %1 = icmp slt i32 %0, 0 ; <i1> [#uses=1] br i1 %1, label %bb1, label %bb2 bb1: ; preds = %bb - tail call arm_apcscc void @perror(i8* getelementptr ([11 x i8]* @.str, i32 0, i32 0)) nounwind + tail call void @perror(i8* getelementptr ([11 x i8]* @.str, i32 0, i32 0)) nounwind ret i32 1 bb2: ; preds = %bb @@ -264,9 +264,9 @@ bb2: ; preds = %bb bb3: ; preds = %bb2 %3 = shl i32 %0, 1 ; <i32> [#uses=1] - tail call arm_apcscc void @adpcm_decoder(i8* getelementptr ([500 x i8]* @abuf, i32 0, i32 0), i16* getelementptr ([1000 x i16]* @sbuf, i32 0, i32 0), i32 %3, %struct.adpcm_state* @state) nounwind + tail call void @adpcm_decoder(i8* getelementptr ([500 x i8]* @abuf, i32 0, i32 0), i16* getelementptr ([1000 x i16]* @sbuf, i32 0, i32 0), i32 %3, %struct.adpcm_state* @state) nounwind %4 = shl i32 %0, 2 ; <i32> [#uses=1] - %5 = tail call arm_apcscc i32 (...)* @write(i32 1, i16* getelementptr ([1000 x i16]* @sbuf, i32 0, i32 0), i32 %4) nounwind ; <i32> [#uses=0] + %5 = tail call i32 (...)* @write(i32 1, i16* getelementptr ([1000 x i16]* @sbuf, i32 0, i32 0), i32 %4) nounwind ; <i32> [#uses=0] br label %bb bb4: ; preds = %bb2 @@ -275,14 +275,14 @@ bb4: ; preds = %bb2 %8 = sext i16 %7 to i32 ; <i32> [#uses=1] %9 = load i8* getelementptr (%struct.adpcm_state* @state, i32 0, i32 1), align 2 ; <i8> [#uses=1] %10 = sext i8 %9 to i32 ; <i32> [#uses=1] - %11 = tail call arm_apcscc i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* %6, i8* getelementptr ([28 x i8]* @.str1, i32 0, i32 0), i32 %8, i32 %10) nounwind ; <i32> [#uses=0] + %11 = tail call i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* %6, i8* getelementptr ([28 x i8]* @.str1, i32 0, i32 0), i32 %8, i32 %10) nounwind ; <i32> [#uses=0] ret i32 0 } -declare arm_apcscc i32 @read(...) +declare i32 @read(...) -declare arm_apcscc void @perror(i8* nocapture) nounwind +declare void @perror(i8* nocapture) nounwind -declare arm_apcscc i32 @write(...) +declare i32 @write(...) -declare arm_apcscc i32 @fprintf(%struct.FILE* nocapture, i8* nocapture, ...) nounwind +declare i32 @fprintf(%struct.FILE* nocapture, i8* nocapture, ...) nounwind diff --git a/test/CodeGen/Thumb/machine-licm.ll b/test/CodeGen/Thumb/machine-licm.ll index a69a64f..a87e82c 100644 --- a/test/CodeGen/Thumb/machine-licm.ll +++ b/test/CodeGen/Thumb/machine-licm.ll @@ -7,7 +7,7 @@ @GV = external global i32 ; <i32*> [#uses=2] -define arm_apcscc void @t(i32* nocapture %vals, i32 %c) nounwind { +define void @t(i32* nocapture %vals, i32 %c) nounwind { entry: ; CHECK: t: %0 = icmp eq i32 %c, 0 ; <i1> [#uses=1] diff --git a/test/CodeGen/Thumb/pop.ll b/test/CodeGen/Thumb/pop.ll index 0e1b2e5..63f2feb 100644 --- a/test/CodeGen/Thumb/pop.ll +++ b/test/CodeGen/Thumb/pop.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -mtriple=thumb-apple-darwin | FileCheck %s ; rdar://7268481 -define arm_apcscc void @t(i8* %a, ...) nounwind { +define void @t(i8* %a, ...) nounwind { ; CHECK: t: ; CHECK: pop {r3} ; CHECK-NEXT: add sp, #12 diff --git a/test/CodeGen/Thumb/push.ll b/test/CodeGen/Thumb/push.ll index 63773c4..94ef8e9 100644 --- a/test/CodeGen/Thumb/push.ll +++ b/test/CodeGen/Thumb/push.ll @@ -1,10 +1,10 @@ ; RUN: llc < %s -mtriple=thumb-apple-darwin -disable-fp-elim | FileCheck %s ; rdar://7268481 -define arm_apcscc void @t() nounwind { -; CHECK: t: -; CHECK-NEXT : push {r7} +define void @t() nounwind { +; CHECK: t: +; CHECK: push {r7} entry: - call void asm sideeffect ".long 0xe7ffdefe", ""() nounwind + call void asm sideeffect alignstack ".long 0xe7ffdefe", ""() nounwind ret void } diff --git a/test/CodeGen/Thumb/trap.ll b/test/CodeGen/Thumb/trap.ll index 76a0589..04cd3ee 100644 --- a/test/CodeGen/Thumb/trap.ll +++ b/test/CodeGen/Thumb/trap.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=thumb | FileCheck %s ; rdar://7961298 -define arm_apcscc void @t() nounwind { +define void @t() nounwind { entry: ; CHECK: t: ; CHECK: trap diff --git a/test/CodeGen/Thumb2/2009-07-17-CrossRegClassCopy.ll b/test/CodeGen/Thumb2/2009-07-17-CrossRegClassCopy.ll index 8f2283f..76ffe2a 100644 --- a/test/CodeGen/Thumb2/2009-07-17-CrossRegClassCopy.ll +++ b/test/CodeGen/Thumb2/2009-07-17-CrossRegClassCopy.ll @@ -4,9 +4,9 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32- target triple = "thumbv6t2-elf" %struct.dwarf_cie = type <{ i32, i32, i8, [0 x i8], [3 x i8] }> -declare arm_apcscc i8* @read_sleb128(i8*, i32* nocapture) nounwind +declare i8* @read_sleb128(i8*, i32* nocapture) nounwind -define arm_apcscc i32 @get_cie_encoding(%struct.dwarf_cie* %cie) nounwind { +define i32 @get_cie_encoding(%struct.dwarf_cie* %cie) nounwind { entry: br i1 undef, label %bb1, label %bb13 @@ -27,7 +27,7 @@ read_uleb128.exit: ; preds = %bb.i %.sum40 = add i32 %indvar.i, undef ; <i32> [#uses=1] %.sum31 = add i32 %.sum40, 2 ; <i32> [#uses=1] %scevgep.i = getelementptr %struct.dwarf_cie* %cie, i32 0, i32 3, i32 %.sum31 ; <i8*> [#uses=1] - %3 = call arm_apcscc i8* @read_sleb128(i8* %scevgep.i, i32* undef) ; <i8*> [#uses=0] + %3 = call i8* @read_sleb128(i8* %scevgep.i, i32* undef) ; <i8*> [#uses=0] unreachable bb13: ; preds = %entry diff --git a/test/CodeGen/Thumb2/2009-07-21-ISelBug.ll b/test/CodeGen/Thumb2/2009-07-21-ISelBug.ll index ef076a4..4e1394f 100644 --- a/test/CodeGen/Thumb2/2009-07-21-ISelBug.ll +++ b/test/CodeGen/Thumb2/2009-07-21-ISelBug.ll @@ -3,7 +3,7 @@ @"\01LC" = external constant [36 x i8], align 1 ; <[36 x i8]*> [#uses=1] -define arm_apcscc i32 @t(i32, ...) nounwind { +define i32 @t(i32, ...) nounwind { entry: ; CHECK: t: ; CHECK: add r7, sp, #12 @@ -24,7 +24,7 @@ entry: %15 = sext i8 %6 to i32 ; <i32> [#uses=2] %16 = sext i16 %10 to i32 ; <i32> [#uses=2] %17 = sext i16 %13 to i32 ; <i32> [#uses=2] - %18 = call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([36 x i8]* @"\01LC", i32 0, i32 0), i32 -128, i32 0, i32 %15, i32 %16, i32 %17, i32 0, i32 %14) nounwind ; <i32> [#uses=0] + %18 = call i32 (i8*, ...)* @printf(i8* getelementptr ([36 x i8]* @"\01LC", i32 0, i32 0), i32 -128, i32 0, i32 %15, i32 %16, i32 %17, i32 0, i32 %14) nounwind ; <i32> [#uses=0] %19 = add i32 0, %15 ; <i32> [#uses=1] %20 = add i32 %19, %16 ; <i32> [#uses=1] %21 = add i32 %20, %14 ; <i32> [#uses=1] @@ -33,4 +33,4 @@ entry: ret i32 %23 } -declare arm_apcscc i32 @printf(i8* nocapture, ...) nounwind +declare i32 @printf(i8* nocapture, ...) nounwind diff --git a/test/CodeGen/Thumb2/2009-07-23-CPIslandBug.ll b/test/CodeGen/Thumb2/2009-07-23-CPIslandBug.ll index 4d21f9b..4357366 100644 --- a/test/CodeGen/Thumb2/2009-07-23-CPIslandBug.ll +++ b/test/CodeGen/Thumb2/2009-07-23-CPIslandBug.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mattr=+vfp2,+thumb2 ; rdar://7083961 -define arm_apcscc i32 @value(i64 %b1, i64 %b2) nounwind readonly { +define i32 @value(i64 %b1, i64 %b2) nounwind readonly { entry: %0 = icmp eq i32 undef, 0 ; <i1> [#uses=1] %mod.0.ph.ph = select i1 %0, float -1.000000e+00, float 1.000000e+00 ; <float> [#uses=1] diff --git a/test/CodeGen/Thumb2/2009-07-30-PEICrash.ll b/test/CodeGen/Thumb2/2009-07-30-PEICrash.ll index f74d12e..3e07618 100644 --- a/test/CodeGen/Thumb2/2009-07-30-PEICrash.ll +++ b/test/CodeGen/Thumb2/2009-07-30-PEICrash.ll @@ -28,7 +28,7 @@ %struct.jvirt_barray_control = type { [64 x i16]**, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.jvirt_barray_control*, %struct.backing_store_info } %struct.jvirt_sarray_control = type { i8**, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.jvirt_sarray_control*, %struct.backing_store_info } -define arm_apcscc void @jpeg_idct_float(%struct.jpeg_decompress_struct* nocapture %cinfo, %struct.jpeg_component_info* nocapture %compptr, i16* nocapture %coef_block, i8** nocapture %output_buf, i32 %output_col) nounwind { +define void @jpeg_idct_float(%struct.jpeg_decompress_struct* nocapture %cinfo, %struct.jpeg_component_info* nocapture %compptr, i16* nocapture %coef_block, i8** nocapture %output_buf, i32 %output_col) nounwind { entry: %workspace = alloca [64 x float], align 4 ; <[64 x float]*> [#uses=11] %0 = load i8** undef, align 4 ; <i8*> [#uses=5] diff --git a/test/CodeGen/Thumb2/2009-08-01-WrongLDRBOpc.ll b/test/CodeGen/Thumb2/2009-08-01-WrongLDRBOpc.ll index a8e86d5..095aecc 100644 --- a/test/CodeGen/Thumb2/2009-08-01-WrongLDRBOpc.ll +++ b/test/CodeGen/Thumb2/2009-08-01-WrongLDRBOpc.ll @@ -6,7 +6,7 @@ @lefline = external global [100 x [20 x i32]] ; <[100 x [20 x i32]]*> [#uses=1] @sep = external global [20 x i32] ; <[20 x i32]*> [#uses=1] -define arm_apcscc void @main(i32 %argc, i8** %argv) noreturn nounwind { +define void @main(i32 %argc, i8** %argv) noreturn nounwind { ; CHECK: main: ; CHECK: ldrb entry: diff --git a/test/CodeGen/Thumb2/2009-08-02-CoalescerBug.ll b/test/CodeGen/Thumb2/2009-08-02-CoalescerBug.ll index 6cbfd0d..41b3029 100644 --- a/test/CodeGen/Thumb2/2009-08-02-CoalescerBug.ll +++ b/test/CodeGen/Thumb2/2009-08-02-CoalescerBug.ll @@ -22,9 +22,9 @@ %"struct.xalanc_1_8::XalanDOMString" = type { %"struct.std::vector<short unsigned int,std::allocator<short unsigned int> >", i32 } %"struct.xalanc_1_8::XalanOutputStream" = type { i32 (...)**, i32, %"struct.std::basic_ostream<char,std::char_traits<char> >.base"*, i32, %"struct.std::vector<short unsigned int,std::allocator<short unsigned int> >", %"struct.xalanc_1_8::XalanDOMString", i8, i8, %"struct.std::CharVectorType" } -declare arm_apcscc void @_ZN10xalanc_1_814FormatterToXML17writeParentTagEndEv(%"struct.xalanc_1_8::FormatterToXML"*) +declare void @_ZN10xalanc_1_814FormatterToXML17writeParentTagEndEv(%"struct.xalanc_1_8::FormatterToXML"*) -define arm_apcscc void @_ZN10xalanc_1_814FormatterToXML5cdataEPKtj(%"struct.xalanc_1_8::FormatterToXML"* %this, i16* %ch, i32 %length) { +define void @_ZN10xalanc_1_814FormatterToXML5cdataEPKtj(%"struct.xalanc_1_8::FormatterToXML"* %this, i16* %ch, i32 %length) { entry: %0 = getelementptr %"struct.xalanc_1_8::FormatterToXML"* %this, i32 0, i32 13 ; <i8*> [#uses=1] br i1 undef, label %bb4, label %bb @@ -36,11 +36,11 @@ bb: ; preds = %entry %3 = getelementptr i32 (...)** %2, i32 11 ; <i32 (...)**> [#uses=1] %4 = load i32 (...)** %3, align 4 ; <i32 (...)*> [#uses=1] %5 = bitcast i32 (...)* %4 to void (%"struct.xalanc_1_8::FormatterToXML"*, i16*, i32)* ; <void (%"struct.xalanc_1_8::FormatterToXML"*, i16*, i32)*> [#uses=1] - tail call arm_apcscc void %5(%"struct.xalanc_1_8::FormatterToXML"* %this, i16* %ch, i32 %length) + tail call void %5(%"struct.xalanc_1_8::FormatterToXML"* %this, i16* %ch, i32 %length) ret void bb4: ; preds = %entry - tail call arm_apcscc void @_ZN10xalanc_1_814FormatterToXML17writeParentTagEndEv(%"struct.xalanc_1_8::FormatterToXML"* %this) - tail call arm_apcscc void undef(%"struct.xalanc_1_8::FormatterToXML"* %this, i16* %ch, i32 0, i32 %length, i8 zeroext undef) + tail call void @_ZN10xalanc_1_814FormatterToXML17writeParentTagEndEv(%"struct.xalanc_1_8::FormatterToXML"* %this) + tail call void undef(%"struct.xalanc_1_8::FormatterToXML"* %this, i16* %ch, i32 0, i32 %length, i8 zeroext undef) ret void } diff --git a/test/CodeGen/Thumb2/2009-08-04-CoalescerAssert.ll b/test/CodeGen/Thumb2/2009-08-04-CoalescerAssert.ll index ebe9d46..acff261 100644 --- a/test/CodeGen/Thumb2/2009-08-04-CoalescerAssert.ll +++ b/test/CodeGen/Thumb2/2009-08-04-CoalescerAssert.ll @@ -5,7 +5,7 @@ %struct._IO_marker = type { %struct._IO_marker*, %struct.FILE*, i32 } @.str2 = external constant [30 x i8], align 1 ; <[30 x i8]*> [#uses=1] -define arm_aapcscc i32 @__mf_heuristic_check(i32 %ptr, i32 %ptr_high) nounwind { +define i32 @__mf_heuristic_check(i32 %ptr, i32 %ptr_high) nounwind { entry: br i1 undef, label %bb1, label %bb @@ -17,7 +17,7 @@ bb1: ; preds = %entry bb2: ; preds = %bb1 %0 = call i8* @llvm.frameaddress(i32 0) ; <i8*> [#uses=1] - %1 = call arm_aapcscc i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* noalias undef, i8* noalias getelementptr ([30 x i8]* @.str2, i32 0, i32 0), i8* %0, i8* null) nounwind ; <i32> [#uses=0] + %1 = call i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* noalias undef, i8* noalias getelementptr ([30 x i8]* @.str2, i32 0, i32 0), i8* %0, i8* null) nounwind ; <i32> [#uses=0] unreachable bb9: ; preds = %bb1 @@ -26,4 +26,4 @@ bb9: ; preds = %bb1 declare i8* @llvm.frameaddress(i32) nounwind readnone -declare arm_aapcscc i32 @fprintf(%struct.FILE* noalias nocapture, i8* noalias nocapture, ...) nounwind +declare i32 @fprintf(%struct.FILE* noalias nocapture, i8* noalias nocapture, ...) nounwind diff --git a/test/CodeGen/Thumb2/2009-08-04-CoalescerBug.ll b/test/CodeGen/Thumb2/2009-08-04-CoalescerBug.ll index 9c1fdb3..b832637 100644 --- a/test/CodeGen/Thumb2/2009-08-04-CoalescerBug.ll +++ b/test/CodeGen/Thumb2/2009-08-04-CoalescerBug.ll @@ -28,17 +28,17 @@ @.str1822946 = external constant [8 x i8], align 1 ; <[8 x i8]*> [#uses=1] @.str1842948 = external constant [11 x i8], align 1 ; <[11 x i8]*> [#uses=1] -declare arm_apcscc i32 @fprintf(%struct.FILE* nocapture, i8* nocapture, ...) nounwind +declare i32 @fprintf(%struct.FILE* nocapture, i8* nocapture, ...) nounwind -declare arm_apcscc i32 @"\01_fwrite"(i8*, i32, i32, i8*) +declare i32 @"\01_fwrite"(i8*, i32, i32, i8*) -declare arm_apcscc %struct.FILE* @OpenIncGraphicFile(i8*, i8 zeroext, %struct.rec** nocapture, %struct.FILE_POS*, i32* nocapture) nounwind +declare %struct.FILE* @OpenIncGraphicFile(i8*, i8 zeroext, %struct.rec** nocapture, %struct.FILE_POS*, i32* nocapture) nounwind -declare arm_apcscc void @Error(i32, i32, i8*, i32, %struct.FILE_POS*, ...) nounwind +declare void @Error(i32, i32, i8*, i32, %struct.FILE_POS*, ...) nounwind -declare arm_apcscc i8* @fgets(i8*, i32, %struct.FILE* nocapture) nounwind +declare i8* @fgets(i8*, i32, %struct.FILE* nocapture) nounwind -define arm_apcscc void @PS_PrintGraphicInclude(%struct.rec* %x, i32 %colmark, i32 %rowmark) nounwind { +define void @PS_PrintGraphicInclude(%struct.rec* %x, i32 %colmark, i32 %rowmark) nounwind { entry: br label %bb5 @@ -49,7 +49,7 @@ bb5: ; preds = %bb5, %entry br i1 undef, label %bb5, label %bb6 bb6: ; preds = %bb5 - %0 = call arm_apcscc %struct.FILE* @OpenIncGraphicFile(i8* undef, i8 zeroext 0, %struct.rec** undef, %struct.FILE_POS* null, i32* undef) nounwind ; <%struct.FILE*> [#uses=1] + %0 = call %struct.FILE* @OpenIncGraphicFile(i8* undef, i8 zeroext 0, %struct.rec** undef, %struct.FILE_POS* null, i32* undef) nounwind ; <%struct.FILE*> [#uses=1] br i1 false, label %bb.i, label %FontHalfXHeight.exit bb.i: ; preds = %bb6 @@ -67,22 +67,22 @@ FontSize.exit: ; preds = %bb.i1, %FontHalfXHeight.exit br i1 %2, label %bb.i5, label %FontName.exit bb.i5: ; preds = %FontSize.exit - call arm_apcscc void (i32, i32, i8*, i32, %struct.FILE_POS*, ...)* @Error(i32 1, i32 2, i8* getelementptr ([20 x i8]* @.str24239, i32 0, i32 0), i32 0, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*), i8* getelementptr ([10 x i8]* @.str81872, i32 0, i32 0)) nounwind + call void (i32, i32, i8*, i32, %struct.FILE_POS*, ...)* @Error(i32 1, i32 2, i8* getelementptr ([20 x i8]* @.str24239, i32 0, i32 0), i32 0, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*), i8* getelementptr ([10 x i8]* @.str81872, i32 0, i32 0)) nounwind br label %FontName.exit FontName.exit: ; preds = %bb.i5, %FontSize.exit - %3 = call arm_apcscc i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* undef, i8* getelementptr ([8 x i8]* @.str1822946, i32 0, i32 0), i32 %1, i8* undef) nounwind ; <i32> [#uses=0] - %4 = call arm_apcscc i32 @"\01_fwrite"(i8* getelementptr ([11 x i8]* @.str1842948, i32 0, i32 0), i32 1, i32 10, i8* undef) nounwind ; <i32> [#uses=0] + %3 = call i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* undef, i8* getelementptr ([8 x i8]* @.str1822946, i32 0, i32 0), i32 %1, i8* undef) nounwind ; <i32> [#uses=0] + %4 = call i32 @"\01_fwrite"(i8* getelementptr ([11 x i8]* @.str1842948, i32 0, i32 0), i32 1, i32 10, i8* undef) nounwind ; <i32> [#uses=0] %5 = sub i32 %colmark, undef ; <i32> [#uses=1] %6 = sub i32 %rowmark, undef ; <i32> [#uses=1] %7 = load %struct.FILE** @out_fp, align 4 ; <%struct.FILE*> [#uses=1] - %8 = call arm_apcscc i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* %7, i8* getelementptr ([17 x i8]* @.str212784, i32 0, i32 0), i32 %5, i32 %6) nounwind ; <i32> [#uses=0] + %8 = call i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* %7, i8* getelementptr ([17 x i8]* @.str212784, i32 0, i32 0), i32 %5, i32 %6) nounwind ; <i32> [#uses=0] store i32 0, i32* @cpexists, align 4 %9 = getelementptr %struct.rec* %y.0, i32 0, i32 0, i32 3, i32 0, i32 0, i32 1 ; <i32*> [#uses=1] %10 = load i32* %9, align 4 ; <i32> [#uses=1] %11 = sub i32 0, %10 ; <i32> [#uses=1] %12 = load %struct.FILE** @out_fp, align 4 ; <%struct.FILE*> [#uses=1] - %13 = call arm_apcscc i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* %12, i8* getelementptr ([17 x i8]* @.str212784, i32 0, i32 0), i32 undef, i32 %11) nounwind ; <i32> [#uses=0] + %13 = call i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* %12, i8* getelementptr ([17 x i8]* @.str212784, i32 0, i32 0), i32 undef, i32 %11) nounwind ; <i32> [#uses=0] store i32 0, i32* @cpexists, align 4 br label %bb100.outer.outer @@ -132,7 +132,7 @@ bb2.i41: ; preds = %bb2.i41, %StringBeginsWith.exit55 br label %bb2.i41 bb2.i.i15.critedge: ; preds = %bb.i47 - %16 = call arm_apcscc i8* @fgets(i8* undef, i32 512, %struct.FILE* %0) nounwind ; <i8*> [#uses=0] + %16 = call i8* @fgets(i8* undef, i32 512, %struct.FILE* %0) nounwind ; <i8*> [#uses=0] %iftmp.560.0 = select i1 undef, i32 2, i32 0 ; <i32> [#uses=1] br label %bb100.outer diff --git a/test/CodeGen/Thumb2/2009-08-04-ScavengerAssert.ll b/test/CodeGen/Thumb2/2009-08-04-ScavengerAssert.ll index 317db64..02fad4b 100644 --- a/test/CodeGen/Thumb2/2009-08-04-ScavengerAssert.ll +++ b/test/CodeGen/Thumb2/2009-08-04-ScavengerAssert.ll @@ -55,25 +55,25 @@ @.str1872951 = external constant [17 x i8], align 1 ; <[17 x i8]*> [#uses=1] @.str1932957 = external constant [26 x i8], align 1 ; <[26 x i8]*> [#uses=1] -declare arm_apcscc i32 @fprintf(%struct.FILE* nocapture, i8* nocapture, ...) nounwind +declare i32 @fprintf(%struct.FILE* nocapture, i8* nocapture, ...) nounwind -declare arm_apcscc i32 @"\01_fwrite"(i8*, i32, i32, i8*) +declare i32 @"\01_fwrite"(i8*, i32, i32, i8*) -declare arm_apcscc i32 @remove(i8* nocapture) nounwind +declare i32 @remove(i8* nocapture) nounwind -declare arm_apcscc %struct.FILE* @OpenIncGraphicFile(i8*, i8 zeroext, %struct.rec** nocapture, %struct.FILE_POS*, i32* nocapture) nounwind +declare %struct.FILE* @OpenIncGraphicFile(i8*, i8 zeroext, %struct.rec** nocapture, %struct.FILE_POS*, i32* nocapture) nounwind -declare arm_apcscc %struct.rec* @MakeWord(i32, i8* nocapture, %struct.FILE_POS*) nounwind +declare %struct.rec* @MakeWord(i32, i8* nocapture, %struct.FILE_POS*) nounwind -declare arm_apcscc void @Error(i32, i32, i8*, i32, %struct.FILE_POS*, ...) nounwind +declare void @Error(i32, i32, i8*, i32, %struct.FILE_POS*, ...) nounwind -declare arm_apcscc i32 @"\01_fputs"(i8*, %struct.FILE*) +declare i32 @"\01_fputs"(i8*, %struct.FILE*) -declare arm_apcscc noalias i8* @calloc(i32, i32) nounwind +declare noalias i8* @calloc(i32, i32) nounwind -declare arm_apcscc i8* @fgets(i8*, i32, %struct.FILE* nocapture) nounwind +declare i8* @fgets(i8*, i32, %struct.FILE* nocapture) nounwind -define arm_apcscc void @PS_PrintGraphicInclude(%struct.rec* %x, i32 %colmark, i32 %rowmark) nounwind { +define void @PS_PrintGraphicInclude(%struct.rec* %x, i32 %colmark, i32 %rowmark) nounwind { entry: %buff = alloca [512 x i8], align 4 ; <[512 x i8]*> [#uses=5] %0 = getelementptr %struct.rec* %x, i32 0, i32 0, i32 1, i32 0, i32 0 ; <i8*> [#uses=2] @@ -94,7 +94,7 @@ bb1: ; preds = %bb, %entry br i1 %8, label %bb2, label %bb3 bb2: ; preds = %bb1 - call arm_apcscc void (i32, i32, i8*, i32, %struct.FILE_POS*, ...)* @Error(i32 1, i32 2, i8* getelementptr ([20 x i8]* @.str24239, i32 0, i32 0), i32 0, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*), i8* getelementptr ([40 x i8]* @.str1802944, i32 0, i32 0)) nounwind + call void (i32, i32, i8*, i32, %struct.FILE_POS*, ...)* @Error(i32 1, i32 2, i8* getelementptr ([20 x i8]* @.str24239, i32 0, i32 0), i32 0, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*), i8* getelementptr ([40 x i8]* @.str1802944, i32 0, i32 0)) nounwind br label %bb3 bb3: ; preds = %bb2, %bb1 @@ -108,7 +108,7 @@ bb5: ; preds = %bb5, %bb3 bb6: ; preds = %bb5 %10 = load i8* %0, align 4 ; <i8> [#uses=1] %11 = getelementptr %struct.rec* %y.0, i32 0, i32 0, i32 1, i32 0 ; <%struct.FILE_POS*> [#uses=1] - %12 = call arm_apcscc %struct.FILE* @OpenIncGraphicFile(i8* undef, i8 zeroext %10, %struct.rec** null, %struct.FILE_POS* %11, i32* undef) nounwind ; <%struct.FILE*> [#uses=4] + %12 = call %struct.FILE* @OpenIncGraphicFile(i8* undef, i8 zeroext %10, %struct.rec** null, %struct.FILE_POS* %11, i32* undef) nounwind ; <%struct.FILE*> [#uses=4] br i1 false, label %bb7, label %bb8 bb7: ; preds = %bb6 @@ -124,7 +124,7 @@ bb9: ; preds = %bb8 br i1 %15, label %bb.i, label %FontHalfXHeight.exit bb.i: ; preds = %bb9 - call arm_apcscc void (i32, i32, i8*, i32, %struct.FILE_POS*, ...)* @Error(i32 1, i32 2, i8* getelementptr ([20 x i8]* @.str24239, i32 0, i32 0), i32 0, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*), i8* getelementptr ([17 x i8]* @.str111875, i32 0, i32 0)) nounwind + call void (i32, i32, i8*, i32, %struct.FILE_POS*, ...)* @Error(i32 1, i32 2, i8* getelementptr ([20 x i8]* @.str24239, i32 0, i32 0), i32 0, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*), i8* getelementptr ([17 x i8]* @.str111875, i32 0, i32 0)) nounwind %.pre186 = load i32* @currentfont, align 4 ; <i32> [#uses=1] br label %FontHalfXHeight.exit @@ -139,7 +139,7 @@ bb1.i: ; preds = %bb.i1, %FontHalfXHeight.exit br i1 undef, label %bb2.i, label %FontSize.exit bb2.i: ; preds = %bb1.i - call arm_apcscc void (i32, i32, i8*, i32, %struct.FILE_POS*, ...)* @Error(i32 37, i32 61, i8* getelementptr ([30 x i8]* @.str101874, i32 0, i32 0), i32 1, %struct.FILE_POS* null) nounwind + call void (i32, i32, i8*, i32, %struct.FILE_POS*, ...)* @Error(i32 37, i32 61, i8* getelementptr ([30 x i8]* @.str101874, i32 0, i32 0), i32 1, %struct.FILE_POS* null) nounwind unreachable FontSize.exit: ; preds = %bb1.i @@ -151,35 +151,35 @@ FontSize.exit: ; preds = %bb1.i br i1 %21, label %bb.i5, label %FontName.exit bb.i5: ; preds = %FontSize.exit - call arm_apcscc void (i32, i32, i8*, i32, %struct.FILE_POS*, ...)* @Error(i32 1, i32 2, i8* getelementptr ([20 x i8]* @.str24239, i32 0, i32 0), i32 0, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*), i8* getelementptr ([10 x i8]* @.str81872, i32 0, i32 0)) nounwind + call void (i32, i32, i8*, i32, %struct.FILE_POS*, ...)* @Error(i32 1, i32 2, i8* getelementptr ([20 x i8]* @.str24239, i32 0, i32 0), i32 0, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*), i8* getelementptr ([10 x i8]* @.str81872, i32 0, i32 0)) nounwind br label %FontName.exit FontName.exit: ; preds = %bb.i5, %FontSize.exit %22 = phi %struct.FONT_INFO* [ undef, %bb.i5 ], [ undef, %FontSize.exit ] ; <%struct.FONT_INFO*> [#uses=1] %23 = getelementptr %struct.FONT_INFO* %22, i32 %19, i32 5 ; <%struct.rec**> [#uses=0] - %24 = call arm_apcscc i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* undef, i8* getelementptr ([8 x i8]* @.str1822946, i32 0, i32 0), i32 %18, i8* null) nounwind ; <i32> [#uses=0] + %24 = call i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* undef, i8* getelementptr ([8 x i8]* @.str1822946, i32 0, i32 0), i32 %18, i8* null) nounwind ; <i32> [#uses=0] br label %bb10 bb10: ; preds = %FontName.exit, %bb8 - %25 = call arm_apcscc i32 @"\01_fwrite"(i8* getelementptr ([11 x i8]* @.str1842948, i32 0, i32 0), i32 1, i32 10, i8* undef) nounwind ; <i32> [#uses=0] + %25 = call i32 @"\01_fwrite"(i8* getelementptr ([11 x i8]* @.str1842948, i32 0, i32 0), i32 1, i32 10, i8* undef) nounwind ; <i32> [#uses=0] %26 = sub i32 %rowmark, undef ; <i32> [#uses=1] %27 = load %struct.FILE** @out_fp, align 4 ; <%struct.FILE*> [#uses=1] - %28 = call arm_apcscc i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* %27, i8* getelementptr ([17 x i8]* @.str212784, i32 0, i32 0), i32 undef, i32 %26) nounwind ; <i32> [#uses=0] + %28 = call i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* %27, i8* getelementptr ([17 x i8]* @.str212784, i32 0, i32 0), i32 undef, i32 %26) nounwind ; <i32> [#uses=0] store i32 0, i32* @cpexists, align 4 - %29 = call arm_apcscc i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* undef, i8* getelementptr ([17 x i8]* @.str192782, i32 0, i32 0), double 2.000000e+01, double 2.000000e+01) nounwind ; <i32> [#uses=0] + %29 = call i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* undef, i8* getelementptr ([17 x i8]* @.str192782, i32 0, i32 0), double 2.000000e+01, double 2.000000e+01) nounwind ; <i32> [#uses=0] %30 = getelementptr %struct.rec* %y.0, i32 0, i32 0, i32 3, i32 0, i32 0, i32 0 ; <i32*> [#uses=1] %31 = load i32* %30, align 4 ; <i32> [#uses=1] %32 = sub i32 0, %31 ; <i32> [#uses=1] %33 = load i32* undef, align 4 ; <i32> [#uses=1] %34 = sub i32 0, %33 ; <i32> [#uses=1] %35 = load %struct.FILE** @out_fp, align 4 ; <%struct.FILE*> [#uses=1] - %36 = call arm_apcscc i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* %35, i8* getelementptr ([17 x i8]* @.str212784, i32 0, i32 0), i32 %32, i32 %34) nounwind ; <i32> [#uses=0] + %36 = call i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* %35, i8* getelementptr ([17 x i8]* @.str212784, i32 0, i32 0), i32 %32, i32 %34) nounwind ; <i32> [#uses=0] store i32 0, i32* @cpexists, align 4 %37 = load %struct.rec** null, align 4 ; <%struct.rec*> [#uses=1] %38 = getelementptr %struct.rec* %37, i32 0, i32 0, i32 4 ; <%struct.FOURTH_UNION*> [#uses=1] - %39 = call arm_apcscc i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* undef, i8* getelementptr ([23 x i8]* @.str1852949, i32 0, i32 0), %struct.FOURTH_UNION* %38) nounwind ; <i32> [#uses=0] + %39 = call i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* undef, i8* getelementptr ([23 x i8]* @.str1852949, i32 0, i32 0), %struct.FOURTH_UNION* %38) nounwind ; <i32> [#uses=0] %buff14 = getelementptr [512 x i8]* %buff, i32 0, i32 0 ; <i8*> [#uses=5] - %40 = call arm_apcscc i8* @fgets(i8* %buff14, i32 512, %struct.FILE* %12) nounwind ; <i8*> [#uses=0] + %40 = call i8* @fgets(i8* %buff14, i32 512, %struct.FILE* %12) nounwind ; <i8*> [#uses=0] %iftmp.506.0 = select i1 undef, i32 2, i32 0 ; <i32> [#uses=1] %41 = getelementptr [512 x i8]* %buff, i32 0, i32 26 ; <i8*> [#uses=1] br label %bb100.outer.outer @@ -230,7 +230,7 @@ bb3.i77: ; preds = %bb2.i75, %StringBeginsWith.exit88 br i1 %50, label %bb24, label %bb2.i.i68 bb24: ; preds = %bb3.i77 - %51 = call arm_apcscc %struct.rec* @MakeWord(i32 11, i8* %41, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*)) nounwind ; <%struct.rec*> [#uses=0] + %51 = call %struct.rec* @MakeWord(i32 11, i8* %41, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*)) nounwind ; <%struct.rec*> [#uses=0] %52 = load i8* getelementptr ([150 x i8]* @zz_lengths, i32 0, i32 0), align 4 ; <i8> [#uses=1] %53 = zext i8 %52 to i32 ; <i32> [#uses=2] %54 = getelementptr [524 x %struct.rec*]* @zz_free, i32 0, i32 %53 ; <%struct.rec**> [#uses=2] @@ -245,7 +245,7 @@ bb.i56: ; preds = %bb27 br i1 undef, label %bb1.i58, label %bb2.i60 bb1.i58: ; preds = %bb.i56 - call arm_apcscc void (i32, i32, i8*, i32, %struct.FILE_POS*, ...)* @Error(i32 31, i32 1, i8* getelementptr ([32 x i8]* @.str1575, i32 0, i32 0), i32 1, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*)) nounwind + call void (i32, i32, i8*, i32, %struct.FILE_POS*, ...)* @Error(i32 31, i32 1, i8* getelementptr ([32 x i8]* @.str1575, i32 0, i32 0), i32 1, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*)) nounwind br label %bb2.i60 bb2.i60: ; preds = %bb1.i58, %bb.i56 @@ -287,7 +287,7 @@ bb37: ; preds = %bb35 br label %bb41 bb41: ; preds = %bb37, %bb35 - %61 = call arm_apcscc i8* @fgets(i8* %buff14, i32 512, %struct.FILE* %12) nounwind ; <i8*> [#uses=1] + %61 = call i8* @fgets(i8* %buff14, i32 512, %struct.FILE* %12) nounwind ; <i8*> [#uses=1] %62 = icmp eq i8* %61, null ; <i1> [#uses=1] %iftmp.554.0 = select i1 %62, i32 2, i32 1 ; <i32> [#uses=1] br label %bb100.outer @@ -342,11 +342,11 @@ bb2.i6.i26: ; preds = %bb2.i6.i26, %StringBeginsWith.exit.i20 br i1 undef, label %bb2.i6.i26, label %bb55 bb55: ; preds = %bb2.i6.i26 - %69 = call arm_apcscc i32 @"\01_fputs"(i8* %buff14, %struct.FILE* undef) nounwind ; <i32> [#uses=0] + %69 = call i32 @"\01_fputs"(i8* %buff14, %struct.FILE* undef) nounwind ; <i32> [#uses=0] unreachable bb58: ; preds = %StringBeginsWith.exit.i20 - %70 = call arm_apcscc i8* @fgets(i8* %buff14, i32 512, %struct.FILE* %12) nounwind ; <i8*> [#uses=0] + %70 = call i8* @fgets(i8* %buff14, i32 512, %struct.FILE* %12) nounwind ; <i8*> [#uses=0] %iftmp.560.0 = select i1 undef, i32 2, i32 0 ; <i32> [#uses=1] br label %bb100.outer @@ -367,7 +367,7 @@ StringBeginsWith.exit: ; preds = %StringBeginsWith.exitthread-split, %bb3.i br i1 %phitmp93, label %bb66, label %bb2.i.i bb66: ; preds = %StringBeginsWith.exit - %71 = call arm_apcscc %struct.rec* @MakeWord(i32 11, i8* undef, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*)) nounwind ; <%struct.rec*> [#uses=4] + %71 = call %struct.rec* @MakeWord(i32 11, i8* undef, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*)) nounwind ; <%struct.rec*> [#uses=4] %72 = load i8* getelementptr ([150 x i8]* @zz_lengths, i32 0, i32 0), align 4 ; <i8> [#uses=1] %73 = zext i8 %72 to i32 ; <i32> [#uses=2] %74 = getelementptr [524 x %struct.rec*]* @zz_free, i32 0, i32 %73 ; <%struct.rec**> [#uses=2] @@ -379,13 +379,13 @@ bb69: ; preds = %bb66 br i1 undef, label %bb.i2, label %GetMemory.exit bb.i2: ; preds = %bb69 - %77 = call arm_apcscc noalias i8* @calloc(i32 1020, i32 4) nounwind ; <i8*> [#uses=1] + %77 = call noalias i8* @calloc(i32 1020, i32 4) nounwind ; <i8*> [#uses=1] %78 = bitcast i8* %77 to i8** ; <i8**> [#uses=3] store i8** %78, i8*** @next_free.4772, align 4 br i1 undef, label %bb1.i3, label %bb2.i4 bb1.i3: ; preds = %bb.i2 - call arm_apcscc void (i32, i32, i8*, i32, %struct.FILE_POS*, ...)* @Error(i32 31, i32 1, i8* getelementptr ([32 x i8]* @.str1575, i32 0, i32 0), i32 1, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*)) nounwind + call void (i32, i32, i8*, i32, %struct.FILE_POS*, ...)* @Error(i32 31, i32 1, i8* getelementptr ([32 x i8]* @.str1575, i32 0, i32 0), i32 1, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*)) nounwind br label %bb2.i4 bb2.i4: ; preds = %bb1.i3, %bb.i2 @@ -482,7 +482,7 @@ bb91: ; preds = %strip_out.exit, %bb.i2.i unreachable bb94: ; preds = %strip_out.exit, %StringBeginsWith.exit.i - %96 = call arm_apcscc i8* @fgets(i8* %buff14, i32 512, %struct.FILE* %12) nounwind ; <i8*> [#uses=0] + %96 = call i8* @fgets(i8* %buff14, i32 512, %struct.FILE* %12) nounwind ; <i8*> [#uses=0] unreachable bb100.outer: ; preds = %bb58, %bb41, %bb100.outer.outer @@ -497,12 +497,12 @@ bb101.split: ; preds = %bb100.outer br i1 %97, label %bb103, label %bb102 bb102: ; preds = %bb101.split - %98 = call arm_apcscc i32 @remove(i8* getelementptr ([9 x i8]* @.str19294, i32 0, i32 0)) nounwind ; <i32> [#uses=0] + %98 = call i32 @remove(i8* getelementptr ([9 x i8]* @.str19294, i32 0, i32 0)) nounwind ; <i32> [#uses=0] unreachable bb103: ; preds = %bb101.split %99 = load %struct.FILE** @out_fp, align 4 ; <%struct.FILE*> [#uses=1] - %100 = call arm_apcscc i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* %99, i8* getelementptr ([26 x i8]* @.str1932957, i32 0, i32 0)) nounwind ; <i32> [#uses=0] + %100 = call i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* %99, i8* getelementptr ([26 x i8]* @.str1932957, i32 0, i32 0)) nounwind ; <i32> [#uses=0] store i32 0, i32* @wordcount, align 4 ret void } diff --git a/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll b/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll index 2bbc231..bfea003 100644 --- a/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll +++ b/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll @@ -8,7 +8,7 @@ %struct.Results = type { float, float, float } %struct.Village = type { [4 x %struct.Village*], %struct.Village*, %struct.List, %struct.Hosp, i32, i32 } -define arm_apcscc void @get_results(%struct.Results* noalias nocapture sret %agg.result, %struct.Village* %village) nounwind { +define void @get_results(%struct.Results* noalias nocapture sret %agg.result, %struct.Village* %village) nounwind { entry: br i1 undef, label %bb, label %bb6.preheader diff --git a/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug2.ll b/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug2.ll index 8294484..9d4fc31 100644 --- a/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug2.ll +++ b/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug2.ll @@ -6,7 +6,7 @@ %struct.Patient = type { i32, i32, i32, %struct.Village* } %struct.Village = type { [4 x %struct.Village*], %struct.Village*, %struct.List, %struct.Hosp, i32, i32 } -define arm_apcscc %struct.List* @sim(%struct.Village* %village) nounwind { +define %struct.List* @sim(%struct.Village* %village) nounwind { entry: br i1 undef, label %bb14, label %bb3.preheader diff --git a/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug3.ll b/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug3.ll index b18c972..ad32dc9 100644 --- a/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug3.ll +++ b/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug3.ll @@ -6,7 +6,7 @@ %struct.Patient = type { i32, i32, i32, %struct.Village* } %struct.Village = type { [4 x %struct.Village*], %struct.Village*, %struct.List, %struct.Hosp, i32, i32 } -define arm_apcscc %struct.List* @sim(%struct.Village* %village) nounwind { +define %struct.List* @sim(%struct.Village* %village) nounwind { entry: br i1 undef, label %bb14, label %bb3.preheader diff --git a/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll b/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll index 4077535..f26c6d1 100644 --- a/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll +++ b/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll @@ -2,12 +2,12 @@ ; PR4659 ; PR4682 -define hidden arm_aapcscc i32 @__gcov_execlp(i8* %path, i8* %arg, ...) nounwind { +define hidden i32 @__gcov_execlp(i8* %path, i8* %arg, ...) nounwind { entry: ; CHECK: __gcov_execlp: ; CHECK: mov sp, r7 ; CHECK: sub sp, #4 - call arm_aapcscc void @__gcov_flush() nounwind + call void @__gcov_flush() nounwind br i1 undef, label %bb5, label %bb bb: ; preds = %bb, %entry @@ -15,10 +15,10 @@ bb: ; preds = %bb, %entry bb5: ; preds = %bb, %entry %0 = alloca i8*, i32 undef, align 4 ; <i8**> [#uses=1] - %1 = call arm_aapcscc i32 @execvp(i8* %path, i8** %0) nounwind ; <i32> [#uses=1] + %1 = call i32 @execvp(i8* %path, i8** %0) nounwind ; <i32> [#uses=1] ret i32 %1 } -declare hidden arm_aapcscc void @__gcov_flush() +declare hidden void @__gcov_flush() -declare arm_aapcscc i32 @execvp(i8*, i8**) nounwind +declare i32 @execvp(i8*, i8**) nounwind diff --git a/test/CodeGen/Thumb2/2009-08-07-NeonFPBug.ll b/test/CodeGen/Thumb2/2009-08-07-NeonFPBug.ll index 96bcbad..f3baeb7 100644 --- a/test/CodeGen/Thumb2/2009-08-07-NeonFPBug.ll +++ b/test/CodeGen/Thumb2/2009-08-07-NeonFPBug.ll @@ -28,7 +28,7 @@ %struct.jvirt_barray_control = type { [64 x i16]**, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.jvirt_barray_control*, %struct.backing_store_info } %struct.jvirt_sarray_control = type { i8**, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.jvirt_sarray_control*, %struct.backing_store_info } -define arm_apcscc void @jpeg_idct_float(%struct.jpeg_decompress_struct* nocapture %cinfo, %struct.jpeg_component_info* nocapture %compptr, i16* nocapture %coef_block, i8** nocapture %output_buf, i32 %output_col) nounwind { +define void @jpeg_idct_float(%struct.jpeg_decompress_struct* nocapture %cinfo, %struct.jpeg_component_info* nocapture %compptr, i16* nocapture %coef_block, i8** nocapture %output_buf, i32 %output_col) nounwind { entry: br label %bb diff --git a/test/CodeGen/Thumb2/2009-08-08-ScavengerAssert.ll b/test/CodeGen/Thumb2/2009-08-08-ScavengerAssert.ll index a0f9918..e3c23ac 100644 --- a/test/CodeGen/Thumb2/2009-08-08-ScavengerAssert.ll +++ b/test/CodeGen/Thumb2/2009-08-08-ScavengerAssert.ll @@ -3,7 +3,7 @@ @g_d = external global double ; <double*> [#uses=1] -define arm_aapcscc void @foo(float %yIncr) { +define void @foo(float %yIncr) { entry: br i1 undef, label %bb, label %bb4 diff --git a/test/CodeGen/Thumb2/2009-08-10-ISelBug.ll b/test/CodeGen/Thumb2/2009-08-10-ISelBug.ll index cbe250b..974ce50 100644 --- a/test/CodeGen/Thumb2/2009-08-10-ISelBug.ll +++ b/test/CodeGen/Thumb2/2009-08-10-ISelBug.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+vfp2 -define arm_apcscc float @t1(i32 %v0) nounwind { +define float @t1(i32 %v0) nounwind { entry: store i32 undef, i32* undef, align 4 %0 = load [4 x i8]** undef, align 4 ; <[4 x i8]*> [#uses=1] diff --git a/test/CodeGen/Thumb2/2009-09-28-ITBlockBug.ll b/test/CodeGen/Thumb2/2009-09-28-ITBlockBug.ll index 8d03b52..b2ed8fc 100644 --- a/test/CodeGen/Thumb2/2009-09-28-ITBlockBug.ll +++ b/test/CodeGen/Thumb2/2009-09-28-ITBlockBug.ll @@ -4,7 +4,7 @@ @getNeighbour = external global void (i32, i32, i32, i32, %struct.pix_pos*)*, align 4 ; <void (i32, i32, i32, i32, %struct.pix_pos*)**> [#uses=2] -define arm_apcscc void @t() nounwind { +define void @t() nounwind { ; CHECK: t: ; CHECK: it eq ; CHECK-NEXT: cmpeq @@ -47,12 +47,12 @@ if.then1992: ; preds = %for.body1940 %tmp14.i302 = load i32* undef ; <i32> [#uses=4] %add.i307452 = or i32 %shl1959, 1 ; <i32> [#uses=1] %sub.i308 = add i32 %shl, -1 ; <i32> [#uses=4] - call arm_apcscc void undef(i32 %tmp14.i302, i32 %sub.i308, i32 %shl1959, i32 0, %struct.pix_pos* undef) nounwind + call void undef(i32 %tmp14.i302, i32 %sub.i308, i32 %shl1959, i32 0, %struct.pix_pos* undef) nounwind %tmp49.i309 = load void (i32, i32, i32, i32, %struct.pix_pos*)** @getNeighbour ; <void (i32, i32, i32, i32, %struct.pix_pos*)*> [#uses=1] - call arm_apcscc void %tmp49.i309(i32 %tmp14.i302, i32 %sub.i308, i32 %add.i307452, i32 0, %struct.pix_pos* null) nounwind + call void %tmp49.i309(i32 %tmp14.i302, i32 %sub.i308, i32 %add.i307452, i32 0, %struct.pix_pos* null) nounwind %tmp49.1.i = load void (i32, i32, i32, i32, %struct.pix_pos*)** @getNeighbour ; <void (i32, i32, i32, i32, %struct.pix_pos*)*> [#uses=1] - call arm_apcscc void %tmp49.1.i(i32 %tmp14.i302, i32 %sub.i308, i32 undef, i32 0, %struct.pix_pos* %arrayidx56.2.i) nounwind - call arm_apcscc void undef(i32 %tmp14.i302, i32 %sub.i308, i32 undef, i32 0, %struct.pix_pos* %arrayidx56.3.i) nounwind + call void %tmp49.1.i(i32 %tmp14.i302, i32 %sub.i308, i32 undef, i32 0, %struct.pix_pos* %arrayidx56.2.i) nounwind + call void undef(i32 %tmp14.i302, i32 %sub.i308, i32 undef, i32 0, %struct.pix_pos* %arrayidx56.3.i) nounwind unreachable if.else2003: ; preds = %for.body1940 diff --git a/test/CodeGen/Thumb2/2009-11-01-CopyReg2RegBug.ll b/test/CodeGen/Thumb2/2009-11-01-CopyReg2RegBug.ll index 216f3e3..4588018 100644 --- a/test/CodeGen/Thumb2/2009-11-01-CopyReg2RegBug.ll +++ b/test/CodeGen/Thumb2/2009-11-01-CopyReg2RegBug.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -relocation-model=pic -disable-fp-elim -mcpu=cortex-a8 -define arm_apcscc void @get_initial_mb16x16_cost() nounwind { +define void @get_initial_mb16x16_cost() nounwind { entry: br i1 undef, label %bb4, label %bb1 diff --git a/test/CodeGen/Thumb2/2009-11-11-ScavengerAssert.ll b/test/CodeGen/Thumb2/2009-11-11-ScavengerAssert.ll index 9f2e399..956263b 100644 --- a/test/CodeGen/Thumb2/2009-11-11-ScavengerAssert.ll +++ b/test/CodeGen/Thumb2/2009-11-11-ScavengerAssert.ll @@ -3,9 +3,9 @@ %struct.OP = type { %struct.OP*, %struct.OP*, %struct.OP* ()*, i32, i16, i16, i8, i8 } %struct.SV = type { i8*, i32, i32 } -declare arm_apcscc void @Perl_mg_set(%struct.SV*) nounwind +declare void @Perl_mg_set(%struct.SV*) nounwind -define arm_apcscc %struct.OP* @Perl_pp_complement() nounwind { +define %struct.OP* @Perl_pp_complement() nounwind { entry: %0 = load %struct.SV** null, align 4 ; <%struct.SV*> [#uses=2] br i1 undef, label %bb21, label %bb5 @@ -23,7 +23,7 @@ bb7: ; preds = %bb6 %4 = bitcast i8* %3 to i32* ; <i32*> [#uses=1] %5 = load i32* %4, align 4 ; <i32> [#uses=1] %storemerge5 = xor i32 %5, -1 ; <i32> [#uses=1] - call arm_apcscc void @Perl_sv_setiv(%struct.SV* undef, i32 %storemerge5) nounwind + call void @Perl_sv_setiv(%struct.SV* undef, i32 %storemerge5) nounwind %6 = getelementptr inbounds %struct.SV* undef, i32 0, i32 2 ; <i32*> [#uses=1] %7 = load i32* %6, align 4 ; <i32> [#uses=1] %8 = and i32 %7, 16384 ; <i32> [#uses=1] @@ -34,7 +34,7 @@ bb8: ; preds = %bb6 unreachable bb11: ; preds = %bb7 - call arm_apcscc void @Perl_mg_set(%struct.SV* undef) nounwind + call void @Perl_mg_set(%struct.SV* undef) nounwind br label %bb12 bb12: ; preds = %bb11, %bb7 @@ -42,11 +42,11 @@ bb12: ; preds = %bb11, %bb7 br label %bb44 bb13: ; preds = %bb5 - %10 = call arm_apcscc i32 @Perl_sv_2uv(%struct.SV* %0) nounwind ; <i32> [#uses=0] + %10 = call i32 @Perl_sv_2uv(%struct.SV* %0) nounwind ; <i32> [#uses=0] br i1 undef, label %bb.i, label %bb1.i bb.i: ; preds = %bb13 - call arm_apcscc void @Perl_sv_setiv(%struct.SV* undef, i32 undef) nounwind + call void @Perl_sv_setiv(%struct.SV* undef, i32 undef) nounwind br label %Perl_sv_setuv.exit bb1.i: ; preds = %bb13 @@ -60,7 +60,7 @@ Perl_sv_setuv.exit: ; preds = %bb1.i, %bb.i br i1 %14, label %bb20, label %bb19 bb19: ; preds = %Perl_sv_setuv.exit - call arm_apcscc void @Perl_mg_set(%struct.SV* undef) nounwind + call void @Perl_mg_set(%struct.SV* undef) nounwind br label %bb20 bb20: ; preds = %bb19, %Perl_sv_setuv.exit @@ -80,6 +80,6 @@ bb44: ; preds = %bb20, %bb12 ret %struct.OP* undef } -declare arm_apcscc void @Perl_sv_setiv(%struct.SV*, i32) nounwind +declare void @Perl_sv_setiv(%struct.SV*, i32) nounwind -declare arm_apcscc i32 @Perl_sv_2uv(%struct.SV*) nounwind +declare i32 @Perl_sv_2uv(%struct.SV*) nounwind diff --git a/test/CodeGen/Thumb2/2009-11-13-STRDBug.ll b/test/CodeGen/Thumb2/2009-11-13-STRDBug.ll index 8a67bb1..0c9fa5e 100644 --- a/test/CodeGen/Thumb2/2009-11-13-STRDBug.ll +++ b/test/CodeGen/Thumb2/2009-11-13-STRDBug.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 ; rdar://7394794 -define arm_apcscc void @lshift_double(i64 %l1, i64 %h1, i64 %count, i32 %prec, i64* nocapture %lv, i64* nocapture %hv, i32 %arith) nounwind { +define void @lshift_double(i64 %l1, i64 %h1, i64 %count, i32 %prec, i64* nocapture %lv, i64* nocapture %hv, i32 %arith) nounwind { entry: %..i = select i1 false, i64 0, i64 0 ; <i64> [#uses=1] br i1 undef, label %bb11.i, label %bb6.i diff --git a/test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll b/test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll index 79ad0a9..8ca001c 100644 --- a/test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll +++ b/test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll @@ -1,7 +1,7 @@ ; RUN: opt < %s -std-compile-opts | \ ; RUN: llc -mtriple=thumbv7-apple-darwin10 -mattr=+neon | FileCheck %s -define arm_apcscc void @fred(i32 %three_by_three, i8* %in, double %dt1, i32 %x_size, i32 %y_size, i8* %bp) nounwind { +define void @fred(i32 %three_by_three, i8* %in, double %dt1, i32 %x_size, i32 %y_size, i8* %bp) nounwind { entry: ; -- The loop following the load should only use a single add-literation ; instruction. @@ -45,7 +45,7 @@ entry: store i8* %bp, i8** %bp_addr %0 = load i8** %in_addr, align 4 ; <i8*> [#uses=1] store i8* %0, i8** %out, align 4 - %1 = call arm_apcscc i32 (...)* @foo() nounwind ; <i32> [#uses=1] + %1 = call i32 (...)* @foo() nounwind ; <i32> [#uses=1] store i32 %1, i32* %i, align 4 %2 = load i32* %three_by_three_addr, align 4 ; <i32> [#uses=1] %3 = icmp eq i32 %2, 0 ; <i1> [#uses=1] @@ -76,7 +76,7 @@ bb3: ; preds = %bb2, %bb %15 = load i32* %n_max, align 4 ; <i32> [#uses=1] %16 = load i32* %n_max, align 4 ; <i32> [#uses=1] %17 = mul i32 %15, %16 ; <i32> [#uses=1] - %18 = call arm_apcscc noalias i8* @malloc(i32 %17) nounwind ; <i8*> [#uses=1] + %18 = call noalias i8* @malloc(i32 %17) nounwind ; <i8*> [#uses=1] store i8* %18, i8** %dp, align 4 %19 = load i8** %dp, align 4 ; <i8*> [#uses=1] store i8* %19, i8** %dpt, align 4 @@ -123,6 +123,6 @@ return: ; preds = %bb6 ret void } -declare arm_apcscc i32 @foo(...) +declare i32 @foo(...) -declare arm_apcscc noalias i8* @malloc(i32) nounwind +declare noalias i8* @malloc(i32) nounwind diff --git a/test/CodeGen/Thumb2/2010-01-06-TailDuplicateLabels.ll b/test/CodeGen/Thumb2/2010-01-06-TailDuplicateLabels.ll index 07a3527..af7d716 100644 --- a/test/CodeGen/Thumb2/2010-01-06-TailDuplicateLabels.ll +++ b/test/CodeGen/Thumb2/2010-01-06-TailDuplicateLabels.ll @@ -17,14 +17,14 @@ target triple = "thumbv7-apple-darwin10" @_ZN3WTFL12thread_heapsE = internal global %"struct.WTF::TCMalloc_ThreadCache"* null ; <%"struct.WTF::TCMalloc_ThreadCache"**> [#uses=1] @llvm.used = appending global [1 x i8*] [i8* bitcast (%"struct.WTF::TCMalloc_ThreadCache"* ()* @_ZN3WTF20TCMalloc_ThreadCache22CreateCacheIfNecessaryEv to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] -define arm_apcscc %"struct.WTF::TCMalloc_ThreadCache"* @_ZN3WTF20TCMalloc_ThreadCache22CreateCacheIfNecessaryEv() nounwind { +define %"struct.WTF::TCMalloc_ThreadCache"* @_ZN3WTF20TCMalloc_ThreadCache22CreateCacheIfNecessaryEv() nounwind { entry: - %0 = tail call arm_apcscc i32 @pthread_mutex_lock(%struct.PlatformMutex* getelementptr inbounds (%struct.SpinLock* @_ZN3WTFL13pageheap_lockE, i32 0, i32 0)) nounwind + %0 = tail call i32 @pthread_mutex_lock(%struct.PlatformMutex* getelementptr inbounds (%struct.SpinLock* @_ZN3WTFL13pageheap_lockE, i32 0, i32 0)) nounwind %.b24 = load i1* @_ZN3WTFL10tsd_initedE.b, align 4 ; <i1> [#uses=1] br i1 %.b24, label %bb5, label %bb6 bb5: ; preds = %entry - %1 = tail call arm_apcscc %struct._opaque_pthread_t* @pthread_self() nounwind + %1 = tail call %struct._opaque_pthread_t* @pthread_self() nounwind br label %bb6 bb6: ; preds = %bb5, %entry @@ -34,7 +34,7 @@ bb6: ; preds = %bb5, %entry bb7: ; preds = %bb11 %2 = getelementptr inbounds %"struct.WTF::TCMalloc_ThreadCache"* %h.0, i32 0, i32 1 %3 = load %struct._opaque_pthread_t** %2, align 4 - %4 = tail call arm_apcscc i32 @pthread_equal(%struct._opaque_pthread_t* %3, %struct._opaque_pthread_t* %me.0) nounwind + %4 = tail call i32 @pthread_equal(%struct._opaque_pthread_t* %3, %struct._opaque_pthread_t* %me.0) nounwind %5 = icmp eq i32 %4, 0 br i1 %5, label %bb10, label %bb14 @@ -49,12 +49,12 @@ bb11: ; preds = %bb10, %bb6 br i1 %7, label %bb13, label %bb7 bb13: ; preds = %bb11 - %8 = tail call arm_apcscc %"struct.WTF::TCMalloc_ThreadCache"* @_ZN3WTF20TCMalloc_ThreadCache7NewHeapEP17_opaque_pthread_t(%struct._opaque_pthread_t* %me.0) nounwind + %8 = tail call %"struct.WTF::TCMalloc_ThreadCache"* @_ZN3WTF20TCMalloc_ThreadCache7NewHeapEP17_opaque_pthread_t(%struct._opaque_pthread_t* %me.0) nounwind br label %bb14 bb14: ; preds = %bb13, %bb7 %heap.1 = phi %"struct.WTF::TCMalloc_ThreadCache"* [ %8, %bb13 ], [ %h.0, %bb7 ] ; <%"struct.WTF::TCMalloc_ThreadCache"*> [#uses=4] - %9 = tail call arm_apcscc i32 @pthread_mutex_unlock(%struct.PlatformMutex* getelementptr inbounds (%struct.SpinLock* @_ZN3WTFL13pageheap_lockE, i32 0, i32 0)) nounwind + %9 = tail call i32 @pthread_mutex_unlock(%struct.PlatformMutex* getelementptr inbounds (%struct.SpinLock* @_ZN3WTFL13pageheap_lockE, i32 0, i32 0)) nounwind %10 = getelementptr inbounds %"struct.WTF::TCMalloc_ThreadCache"* %heap.1, i32 0, i32 2 %11 = load i8* %10, align 4 %toBool15not = icmp eq i8 %11, 0 ; <i1> [#uses=1] @@ -68,22 +68,22 @@ bb21: ; preds = %bb19 store i8 1, i8* %10, align 4 %12 = load i32* @_ZN3WTFL8heap_keyE, align 4 %13 = bitcast %"struct.WTF::TCMalloc_ThreadCache"* %heap.1 to i8* - %14 = tail call arm_apcscc i32 @pthread_setspecific(i32 %12, i8* %13) nounwind + %14 = tail call i32 @pthread_setspecific(i32 %12, i8* %13) nounwind ret %"struct.WTF::TCMalloc_ThreadCache"* %heap.1 bb22: ; preds = %bb19, %bb14 ret %"struct.WTF::TCMalloc_ThreadCache"* %heap.1 } -declare arm_apcscc i32 @pthread_mutex_lock(%struct.PlatformMutex*) +declare i32 @pthread_mutex_lock(%struct.PlatformMutex*) -declare arm_apcscc i32 @pthread_mutex_unlock(%struct.PlatformMutex*) +declare i32 @pthread_mutex_unlock(%struct.PlatformMutex*) -declare hidden arm_apcscc %"struct.WTF::TCMalloc_ThreadCache"* @_ZN3WTF20TCMalloc_ThreadCache7NewHeapEP17_opaque_pthread_t(%struct._opaque_pthread_t*) nounwind +declare hidden %"struct.WTF::TCMalloc_ThreadCache"* @_ZN3WTF20TCMalloc_ThreadCache7NewHeapEP17_opaque_pthread_t(%struct._opaque_pthread_t*) nounwind -declare arm_apcscc i32 @pthread_setspecific(i32, i8*) +declare i32 @pthread_setspecific(i32, i8*) -declare arm_apcscc %struct._opaque_pthread_t* @pthread_self() +declare %struct._opaque_pthread_t* @pthread_self() -declare arm_apcscc i32 @pthread_equal(%struct._opaque_pthread_t*, %struct._opaque_pthread_t*) +declare i32 @pthread_equal(%struct._opaque_pthread_t*, %struct._opaque_pthread_t*) diff --git a/test/CodeGen/Thumb2/2010-01-19-RemovePredicates.ll b/test/CodeGen/Thumb2/2010-01-19-RemovePredicates.ll index 41682c1..771a4f8 100644 --- a/test/CodeGen/Thumb2/2010-01-19-RemovePredicates.ll +++ b/test/CodeGen/Thumb2/2010-01-19-RemovePredicates.ll @@ -6,16 +6,16 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32" target triple = "thumbv7-apple-darwin10" -declare arm_apcscc void @etoe53(i16* nocapture, i16* nocapture) nounwind +declare void @etoe53(i16* nocapture, i16* nocapture) nounwind -define arm_apcscc void @earith(double* nocapture %value, i32 %icode, double* nocapture %r1, double* nocapture %r2) nounwind { +define void @earith(double* nocapture %value, i32 %icode, double* nocapture %r1, double* nocapture %r2) nounwind { entry: %v = alloca [6 x i16], align 4 ; <[6 x i16]*> [#uses=1] br i1 undef, label %bb2.i, label %bb5 bb2.i: ; preds = %entry %0 = bitcast double* %value to i16* ; <i16*> [#uses=1] - call arm_apcscc void @etoe53(i16* null, i16* %0) nounwind + call void @etoe53(i16* null, i16* %0) nounwind ret void bb5: ; preds = %entry @@ -48,6 +48,6 @@ bb35: ; preds = %bb5 bb46: ; preds = %bb26, %bb10 %1 = bitcast double* %value to i16* ; <i16*> [#uses=1] %v47 = getelementptr inbounds [6 x i16]* %v, i32 0, i32 0 ; <i16*> [#uses=1] - call arm_apcscc void @etoe53(i16* %v47, i16* %1) nounwind + call void @etoe53(i16* %v47, i16* %1) nounwind ret void } diff --git a/test/CodeGen/Thumb2/2010-02-11-phi-cycle.ll b/test/CodeGen/Thumb2/2010-02-11-phi-cycle.ll index 363f571..c153092 100644 --- a/test/CodeGen/Thumb2/2010-02-11-phi-cycle.ll +++ b/test/CodeGen/Thumb2/2010-02-11-phi-cycle.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32" -define arm_apcscc i32 @test(i32 %n) nounwind { +define i32 @test(i32 %n) nounwind { ; CHECK: test: ; CHECK-NOT: mov ; CHECK: return @@ -16,11 +16,11 @@ bb.nph: ; preds = %entry bb: ; preds = %bb.nph, %bb %indvar = phi i32 [ 0, %bb.nph ], [ %indvar.next, %bb ] ; <i32> [#uses=1] %u.05 = phi i64 [ undef, %bb.nph ], [ %ins, %bb ] ; <i64> [#uses=1] - %1 = tail call arm_apcscc i32 @f() nounwind ; <i32> [#uses=1] + %1 = tail call i32 @f() nounwind ; <i32> [#uses=1] %tmp4 = zext i32 %1 to i64 ; <i64> [#uses=1] %mask = and i64 %u.05, -4294967296 ; <i64> [#uses=1] %ins = or i64 %tmp4, %mask ; <i64> [#uses=2] - tail call arm_apcscc void @g(i64 %ins) nounwind + tail call void @g(i64 %ins) nounwind %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=2] %exitcond = icmp eq i32 %indvar.next, %tmp ; <i1> [#uses=1] br i1 %exitcond, label %return, label %bb @@ -29,7 +29,7 @@ return: ; preds = %bb, %entry ret i32 undef } -define arm_apcscc i32 @test_dead_cycle(i32 %n) nounwind { +define i32 @test_dead_cycle(i32 %n) nounwind { ; CHECK: test_dead_cycle: ; CHECK: blx ; CHECK-NOT: mov @@ -50,11 +50,11 @@ bb: ; preds = %bb.nph, %bb2 br i1 %1, label %bb1, label %bb2 bb1: ; preds = %bb - %2 = tail call arm_apcscc i32 @f() nounwind ; <i32> [#uses=1] + %2 = tail call i32 @f() nounwind ; <i32> [#uses=1] %tmp6 = zext i32 %2 to i64 ; <i64> [#uses=1] %mask = and i64 %u.17, -4294967296 ; <i64> [#uses=1] %ins = or i64 %tmp6, %mask ; <i64> [#uses=1] - tail call arm_apcscc void @g(i64 %ins) nounwind + tail call void @g(i64 %ins) nounwind br label %bb2 bb2: ; preds = %bb1, %bb @@ -71,6 +71,6 @@ return: ; preds = %bb2, %entry ret i32 undef } -declare arm_apcscc i32 @f() +declare i32 @f() -declare arm_apcscc void @g(i64) +declare void @g(i64) diff --git a/test/CodeGen/Thumb2/2010-02-24-BigStack.ll b/test/CodeGen/Thumb2/2010-02-24-BigStack.ll index 533546b..2b53747 100644 --- a/test/CodeGen/Thumb2/2010-02-24-BigStack.ll +++ b/test/CodeGen/Thumb2/2010-02-24-BigStack.ll @@ -4,7 +4,7 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32" target triple = "thumbv7-apple-darwin3.0.0-iphoneos" -define arm_apcscc void @FindMin(double* %panelTDEL, i8* %dclOfRow, i32 %numRows, i32 %numCols, double* %retMin_RES_TDEL) { +define void @FindMin(double* %panelTDEL, i8* %dclOfRow, i32 %numRows, i32 %numCols, double* %retMin_RES_TDEL) { entry: %panelTDEL.addr = alloca double*, align 4 ; <double**> [#uses=1] %panelResTDEL = alloca [2560 x double], align 4 ; <[2560 x double]*> [#uses=0] diff --git a/test/CodeGen/Thumb2/2010-03-08-addi12-ccout.ll b/test/CodeGen/Thumb2/2010-03-08-addi12-ccout.ll index 54f4122..7ce3c25 100644 --- a/test/CodeGen/Thumb2/2010-03-08-addi12-ccout.ll +++ b/test/CodeGen/Thumb2/2010-03-08-addi12-ccout.ll @@ -2,13 +2,13 @@ @.str41196 = external constant [2 x i8], align 4 ; <[2 x i8]*> [#uses=1] -declare arm_apcscc void @syStopraw(i32) nounwind +declare void @syStopraw(i32) nounwind -declare arm_apcscc i32 @SyFopen(i8*, i8*) nounwind +declare i32 @SyFopen(i8*, i8*) nounwind -declare arm_apcscc i8* @SyFgets(i8*, i32) nounwind +declare i8* @SyFgets(i8*, i32) nounwind -define arm_apcscc void @SyHelp(i8* nocapture %topic, i32 %fin) nounwind { +define void @SyHelp(i8* nocapture %topic, i32 %fin) nounwind { entry: %line = alloca [256 x i8], align 4 ; <[256 x i8]*> [#uses=1] %secname = alloca [1024 x i8], align 4 ; <[1024 x i8]*> [#uses=0] @@ -70,7 +70,7 @@ bb163: ; preds = %bb162, %bb161 unreachable bb224: ; preds = %bb162 - %0 = call arm_apcscc i32 @SyFopen(i8* undef, i8* getelementptr inbounds ([2 x i8]* @.str41196, i32 0, i32 0)) nounwind ; <i32> [#uses=2] + %0 = call i32 @SyFopen(i8* undef, i8* getelementptr inbounds ([2 x i8]* @.str41196, i32 0, i32 0)) nounwind ; <i32> [#uses=2] br i1 false, label %bb297, label %bb300 bb297: ; preds = %bb224 @@ -177,7 +177,7 @@ bb369: ; preds = %bb368, %bb356 br i1 undef, label %bb373, label %bb388 bb373: ; preds = %bb383, %bb369 - %7 = call arm_apcscc i8* @SyFgets(i8* undef, i32 %0) nounwind ; <i8*> [#uses=1] + %7 = call i8* @SyFgets(i8* undef, i32 %0) nounwind ; <i8*> [#uses=1] %8 = icmp eq i8* %7, null ; <i1> [#uses=1] br i1 %8, label %bb375, label %bb383 @@ -241,7 +241,7 @@ bb405: ; preds = %bb404, %bb403 br i1 undef, label %return, label %bb406 bb406: ; preds = %bb405 - call arm_apcscc void @syStopraw(i32 %fin) nounwind + call void @syStopraw(i32 %fin) nounwind ret void bb407: ; preds = %bb404 @@ -255,7 +255,7 @@ bb428: ; preds = %bb407 br label %bb440 bb440: ; preds = %bb428, %bb300 - %13 = call arm_apcscc i8* @SyFgets(i8* undef, i32 %0) nounwind ; <i8*> [#uses=0] + %13 = call i8* @SyFgets(i8* undef, i32 %0) nounwind ; <i8*> [#uses=0] br i1 false, label %bb442, label %bb308 bb442: ; preds = %bb440 diff --git a/test/CodeGen/Thumb2/2010-03-15-AsmCCClobber.ll b/test/CodeGen/Thumb2/2010-03-15-AsmCCClobber.ll index 71ff68a..7ee1986 100644 --- a/test/CodeGen/Thumb2/2010-03-15-AsmCCClobber.ll +++ b/test/CodeGen/Thumb2/2010-03-15-AsmCCClobber.ll @@ -13,7 +13,7 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32- ; CHECK: InlineAsm End ; CHECK: cmp ; CHECK: beq -define arm_apcscc void @test(%s1* %this, i32 %format, i32 %w, i32 %h, i32 %levels, i32* %s, i8* %data, i32* nocapture %rowbytes, void (i8*, i8*)* %release, i8* %info) nounwind { +define void @test(%s1* %this, i32 %format, i32 %w, i32 %h, i32 %levels, i32* %s, i8* %data, i32* nocapture %rowbytes, void (i8*, i8*)* %release, i8* %info) nounwind { entry: %tmp1 = getelementptr inbounds %s1* %this, i32 0, i32 0, i32 0, i32 1, i32 0, i32 0 volatile store i32 1, i32* %tmp1, align 4 @@ -32,9 +32,9 @@ entry: %tmp19 = getelementptr inbounds %s1* %this, i32 0, i32 10 store i64 0, i64* %tmp19, align 4 %tmp20 = getelementptr inbounds %s1* %this, i32 0, i32 0 - tail call arm_apcscc void @f1(%s3* %tmp20, i32* %s) nounwind + tail call void @f1(%s3* %tmp20, i32* %s) nounwind %tmp21 = shl i32 %format, 6 - %tmp22 = tail call arm_apcscc zeroext i8 @f2(i32 %format) nounwind + %tmp22 = tail call zeroext i8 @f2(i32 %format) nounwind %toBoolnot = icmp eq i8 %tmp22, 0 %tmp23 = zext i1 %toBoolnot to i32 %flags.0 = or i32 %tmp23, %tmp21 @@ -59,5 +59,5 @@ return: ret void } -declare arm_apcscc void @f1(%s3*, i32*) -declare arm_apcscc zeroext i8 @f2(i32) +declare void @f1(%s3*, i32*) +declare zeroext i8 @f2(i32) diff --git a/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll b/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll index fea2dca..3f1b9eb 100644 --- a/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll +++ b/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll @@ -4,7 +4,7 @@ ; Make sure the result of the first dynamic_alloc isn't copied back to sp more ; than once. We'll deal with poor codegen later. -define arm_apcscc void @t() nounwind ssp { +define void @t() nounwind ssp { entry: ; CHECK: t: ; CHECK: mov r0, sp diff --git a/test/CodeGen/Thumb2/2010-04-26-CopyRegCrash.ll b/test/CodeGen/Thumb2/2010-04-26-CopyRegCrash.ll index 950b67e..3be016f 100644 --- a/test/CodeGen/Thumb2/2010-04-26-CopyRegCrash.ll +++ b/test/CodeGen/Thumb2/2010-04-26-CopyRegCrash.ll @@ -4,7 +4,7 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32" target triple = "thumbv7-apple-darwin10" -define arm_apcscc void @test(i32 %mode) nounwind optsize noinline { +define void @test(i32 %mode) nounwind optsize noinline { entry: br i1 undef, label %return, label %bb3 diff --git a/test/CodeGen/Thumb2/2010-05-24-rsbs.ll b/test/CodeGen/Thumb2/2010-05-24-rsbs.ll index 7a40aa9..e72d542 100644 --- a/test/CodeGen/Thumb2/2010-05-24-rsbs.ll +++ b/test/CodeGen/Thumb2/2010-05-24-rsbs.ll @@ -2,7 +2,7 @@ ; Radar 8017376: Missing 's' suffix for t2RSBS instructions. ; CHECK: rsbs -define arm_apcscc i64 @test(i64 %x) nounwind readnone { +define i64 @test(i64 %x) nounwind readnone { entry: %0 = sub nsw i64 1, %x ; <i64> [#uses=1] ret i64 %0 diff --git a/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll b/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll new file mode 100644 index 0000000..2675006 --- /dev/null +++ b/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll @@ -0,0 +1,41 @@ +; RUN: llc < %s -O3 -relocation-model=pic -mattr=+thumb2 -mcpu=cortex-a8 | FileCheck %s +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32" +target triple = "thumbv7-apple-darwin10" + +; This is a case where the coalescer was too eager. These two copies were +; considered equivalent and coalescable: +; +; 140 %reg1038:dsub_0<def> = VMOVD %reg1047:dsub_0, pred:14, pred:%reg0 +; 148 %reg1038:dsub_1<def> = VMOVD %reg1047:dsub_0, pred:14, pred:%reg0 +; +; Only one can be coalesced. + +@.str = private constant [7 x i8] c"%g %g\0A\00", align 4 ; <[7 x i8]*> [#uses=1] + +define i32 @main(i32 %argc, i8** nocapture %Argv) nounwind { +entry: + %0 = icmp eq i32 %argc, 2123 ; <i1> [#uses=1] + %U.0 = select i1 %0, double 3.282190e+01, double 8.731834e+02 ; <double> [#uses=2] + %1 = icmp eq i32 %argc, 5123 ; <i1> [#uses=1] + %V.0.ph = select i1 %1, double 7.779980e+01, double 0x409CCB9C779A6B51 ; <double> [#uses=1] + %2 = insertelement <2 x double> undef, double %U.0, i32 0 ; <<2 x double>> [#uses=2] + %3 = insertelement <2 x double> %2, double %U.0, i32 1 ; <<2 x double>> [#uses=2] + %4 = insertelement <2 x double> %2, double %V.0.ph, i32 1 ; <<2 x double>> [#uses=2] +; Constant pool load followed by add. +; Then clobber the loaded register, not the sum. +; CHECK: vldr.64 [[LDR:d.]] +; CHECK: vadd.f64 [[ADD:d.]], [[LDR]], [[LDR]] +; CHECK: vmov.f64 [[LDR]] + %5 = fadd <2 x double> %3, %3 ; <<2 x double>> [#uses=2] + %6 = fadd <2 x double> %4, %4 ; <<2 x double>> [#uses=2] + %tmp7 = extractelement <2 x double> %5, i32 0 ; <double> [#uses=1] + %tmp5 = extractelement <2 x double> %5, i32 1 ; <double> [#uses=1] +; CHECK: printf + %7 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([7 x i8]* @.str, i32 0, i32 0), double %tmp7, double %tmp5) nounwind ; <i32> [#uses=0] + %tmp3 = extractelement <2 x double> %6, i32 0 ; <double> [#uses=1] + %tmp1 = extractelement <2 x double> %6, i32 1 ; <double> [#uses=1] + %8 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([7 x i8]* @.str, i32 0, i32 0), double %tmp3, double %tmp1) nounwind ; <i32> [#uses=0] + ret i32 0 +} + +declare i32 @printf(i8* nocapture, ...) nounwind diff --git a/test/CodeGen/Thumb2/2010-06-19-ITBlockCrash.ll b/test/CodeGen/Thumb2/2010-06-19-ITBlockCrash.ll new file mode 100644 index 0000000..501f763 --- /dev/null +++ b/test/CodeGen/Thumb2/2010-06-19-ITBlockCrash.ll @@ -0,0 +1,35 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -O3 -relocation-model=pic -disable-fp-elim -mcpu=cortex-a8 +; rdar://8110842 + +declare arm_apcscc i32 @__maskrune(i32, i32) + +define arm_apcscc i32 @strncmpic(i8* nocapture %s1, i8* nocapture %s2, i32 %n) nounwind { +entry: + br i1 undef, label %bb11, label %bb19 + +bb11: ; preds = %entry + %0 = sext i8 0 to i32 ; <i32> [#uses=1] + br i1 undef, label %bb.i.i10, label %bb1.i.i11 + +bb.i.i10: ; preds = %bb11 + br label %isupper144.exit12 + +bb1.i.i11: ; preds = %bb11 + %1 = tail call arm_apcscc i32 @__maskrune(i32 %0, i32 32768) nounwind ; <i32> [#uses=1] + %2 = icmp ne i32 %1, 0 ; <i1> [#uses=1] + %3 = zext i1 %2 to i32 ; <i32> [#uses=1] + %.pre = load i8* undef, align 1 ; <i8> [#uses=1] + br label %isupper144.exit12 + +isupper144.exit12: ; preds = %bb1.i.i11, %bb.i.i10 + %4 = phi i8 [ %.pre, %bb1.i.i11 ], [ 0, %bb.i.i10 ] ; <i8> [#uses=1] + %5 = phi i32 [ %3, %bb1.i.i11 ], [ undef, %bb.i.i10 ] ; <i32> [#uses=1] + %6 = icmp eq i32 %5, 0 ; <i1> [#uses=1] + %7 = sext i8 %4 to i32 ; <i32> [#uses=1] + %storemerge1 = select i1 %6, i32 %7, i32 undef ; <i32> [#uses=1] + %8 = sub nsw i32 %storemerge1, 0 ; <i32> [#uses=1] + ret i32 %8 + +bb19: ; preds = %entry + ret i32 0 +} diff --git a/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll b/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll new file mode 100644 index 0000000..c5fc509 --- /dev/null +++ b/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll @@ -0,0 +1,127 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -O3 -relocation-model=pic -mcpu=cortex-a8 | FileCheck %s +; rdar://8115404 +; Tail merging must not split an IT block. + +%struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 } +%struct._RuneCharClass = type { [14 x i8], i32 } +%struct._RuneEntry = type { i32, i32, i32, i32* } +%struct._RuneLocale = type { [8 x i8], [32 x i8], i32 (i8*, i32, i8**)*, i32 (i32, i8*, i32, i8**)*, i32, [256 x i32], [256 x i32], [256 x i32], %struct._RuneRange, %struct._RuneRange, %struct._RuneRange, i8*, i32, i32, %struct._RuneCharClass* } +%struct._RuneRange = type { i32, %struct._RuneEntry* } +%struct.__sFILEX = type opaque +%struct.__sbuf = type { i8*, i32 } + +@finput = external global %struct.FILE* ; <%struct.FILE**> [#uses=1] +@_DefaultRuneLocale = external global %struct._RuneLocale ; <%struct._RuneLocale*> [#uses=0] +@token_buffer = external global [1025 x i8], align 4 ; <[1025 x i8]*> [#uses=1] +@.str73 = external constant [6 x i8], align 4 ; <[6 x i8]*> [#uses=0] +@.str174 = external constant [5 x i8], align 4 ; <[5 x i8]*> [#uses=0] +@.str275 = external constant [6 x i8], align 4 ; <[6 x i8]*> [#uses=0] +@.str376 = external constant [5 x i8], align 4 ; <[5 x i8]*> [#uses=0] +@.str477 = external constant [6 x i8], align 4 ; <[6 x i8]*> [#uses=0] +@.str578 = external constant [6 x i8], align 4 ; <[6 x i8]*> [#uses=0] +@.str679 = external constant [7 x i8], align 4 ; <[7 x i8]*> [#uses=0] +@.str780 = external constant [6 x i8], align 4 ; <[6 x i8]*> [#uses=0] +@.str881 = external constant [5 x i8], align 4 ; <[5 x i8]*> [#uses=0] +@.str982 = external constant [6 x i8], align 4 ; <[6 x i8]*> [#uses=0] +@.str1083 = external constant [9 x i8], align 4 ; <[9 x i8]*> [#uses=0] +@.str1184 = external constant [7 x i8], align 4 ; <[7 x i8]*> [#uses=0] +@.str1285 = external constant [16 x i8], align 4 ; <[16 x i8]*> [#uses=0] +@.str1386 = external constant [12 x i8], align 4 ; <[12 x i8]*> [#uses=0] +@.str1487 = external constant [5 x i8], align 4 ; <[5 x i8]*> [#uses=0] +@llvm.used = external global [1 x i8*] ; <[1 x i8*]*> [#uses=0] + +define fastcc i32 @parse_percent_token() nounwind { +entry: +; CHECK: ittt eq +; CHECK: ittt eq +; CHECK: ittt eq +; CHECK: ittt eq +; CHECK: ittt eq +; CHECK: moveq r0 +; CHECK-NOT: LBB0_ +; CHECK: ldreq +; CHECK: popeq + switch i32 undef, label %bb7 [ + i32 37, label %bb43 + i32 48, label %bb5 + i32 50, label %bb4 + i32 60, label %bb2 + i32 61, label %bb6 + i32 62, label %bb3 + i32 123, label %bb1 + ] + +bb1: ; preds = %entry + ret i32 8 + +bb2: ; preds = %entry + ret i32 15 + +bb3: ; preds = %entry + ret i32 16 + +bb4: ; preds = %entry + ret i32 17 + +bb5: ; preds = %entry + ret i32 9 + +bb6: ; preds = %entry + ret i32 18 + +bb7: ; preds = %entry + br i1 undef, label %bb.i.i, label %bb1.i.i + +bb.i.i: ; preds = %bb7 + br i1 undef, label %bb43, label %bb12 + +bb1.i.i: ; preds = %bb7 + unreachable + +bb9: ; preds = %bb.i.i2 + br i1 undef, label %bb10, label %bb11 + +bb10: ; preds = %bb9 + br label %bb11 + +bb11: ; preds = %bb10, %bb9 + %p.0 = phi i8* [ undef, %bb10 ], [ %p.1, %bb9 ] ; <i8*> [#uses=1] + %0 = load %struct.FILE** @finput, align 4 ; <%struct.FILE*> [#uses=1] + %1 = tail call i32 @getc(%struct.FILE* %0) nounwind ; <i32> [#uses=0] + br label %bb12 + +bb12: ; preds = %bb11, %bb.i.i + %p.1 = phi i8* [ %p.0, %bb11 ], [ getelementptr inbounds ([1025 x i8]* @token_buffer, i32 0, i32 0), %bb.i.i ] ; <i8*> [#uses=2] + %2 = icmp ult i32 undef, 128 ; <i1> [#uses=1] + br i1 %2, label %bb.i.i2, label %bb1.i.i3 + +bb.i.i2: ; preds = %bb12 + %3 = load i32* null, align 4 ; <i32> [#uses=1] + %4 = lshr i32 %3, 8 ; <i32> [#uses=1] + %.lobit.i1 = and i32 %4, 1 ; <i32> [#uses=1] + %.not = icmp ne i32 %.lobit.i1, 0 ; <i1> [#uses=1] + %or.cond = or i1 %.not, undef ; <i1> [#uses=1] + br i1 %or.cond, label %bb9, label %bb14 + +bb1.i.i3: ; preds = %bb12 + unreachable + +bb14: ; preds = %bb.i.i2 + store i8 0, i8* %p.1, align 1 + br i1 undef, label %bb43, label %bb15 + +bb15: ; preds = %bb14 + unreachable + +bb43: ; preds = %bb14, %bb.i.i, %entry + %.0 = phi i32 [ 7, %entry ], [ 24, %bb.i.i ], [ 9, %bb14 ] ; <i32> [#uses=1] + ret i32 %.0 +} + +declare i32 @getc(%struct.FILE* nocapture) nounwind + +declare i32 @strcmp(i8* nocapture, i8* nocapture) nounwind readonly + +declare i32 @__maskrune(i32, i32) + +declare i32 @ungetc(i32, %struct.FILE* nocapture) nounwind diff --git a/test/CodeGen/Thumb2/crash.ll b/test/CodeGen/Thumb2/crash.ll new file mode 100644 index 0000000..87af9d1 --- /dev/null +++ b/test/CodeGen/Thumb2/crash.ll @@ -0,0 +1,49 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32" +target triple = "thumbv7-apple-darwin10" + +; This function would crash LiveIntervalAnalysis by creating a chain of 4 INSERT_SUBREGs of the same register. +define arm_apcscc void @NEON_vst4q_u32(i32* nocapture %sp0, i32* nocapture %sp1, i32* nocapture %sp2, i32* nocapture %sp3, i32* %dp) nounwind { +entry: + %0 = bitcast i32* %sp0 to <4 x i32>* ; <<4 x i32>*> [#uses=1] + %1 = load <4 x i32>* %0, align 16 ; <<4 x i32>> [#uses=1] + %2 = bitcast i32* %sp1 to <4 x i32>* ; <<4 x i32>*> [#uses=1] + %3 = load <4 x i32>* %2, align 16 ; <<4 x i32>> [#uses=1] + %4 = bitcast i32* %sp2 to <4 x i32>* ; <<4 x i32>*> [#uses=1] + %5 = load <4 x i32>* %4, align 16 ; <<4 x i32>> [#uses=1] + %6 = bitcast i32* %sp3 to <4 x i32>* ; <<4 x i32>*> [#uses=1] + %7 = load <4 x i32>* %6, align 16 ; <<4 x i32>> [#uses=1] + %8 = bitcast i32* %dp to i8* ; <i8*> [#uses=1] + tail call void @llvm.arm.neon.vst4.v4i32(i8* %8, <4 x i32> %1, <4 x i32> %3, <4 x i32> %5, <4 x i32> %7) + ret void +} + +declare void @llvm.arm.neon.vst4.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>) nounwind + +@sbuf = common global [16 x i32] zeroinitializer, align 16 ; <[16 x i32]*> [#uses=5] +@dbuf = common global [16 x i32] zeroinitializer ; <[16 x i32]*> [#uses=2] + +; This function creates 4 chained INSERT_SUBREGS and then invokes the register scavenger. +; The first INSERT_SUBREG needs an <undef> use operand for that to work. +define arm_apcscc i32 @main() nounwind { +bb.nph: + br label %bb + +bb: ; preds = %bb, %bb.nph + %0 = phi i32 [ 0, %bb.nph ], [ %1, %bb ] ; <i32> [#uses=4] + %scevgep = getelementptr [16 x i32]* @sbuf, i32 0, i32 %0 ; <i32*> [#uses=1] + %scevgep5 = getelementptr [16 x i32]* @dbuf, i32 0, i32 %0 ; <i32*> [#uses=1] + store i32 %0, i32* %scevgep, align 4 + store i32 -1, i32* %scevgep5, align 4 + %1 = add nsw i32 %0, 1 ; <i32> [#uses=2] + %exitcond = icmp eq i32 %1, 16 ; <i1> [#uses=1] + br i1 %exitcond, label %bb2, label %bb + +bb2: ; preds = %bb + %2 = load <4 x i32>* bitcast ([16 x i32]* @sbuf to <4 x i32>*), align 16 ; <<4 x i32>> [#uses=1] + %3 = load <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32]* @sbuf, i32 0, i32 4) to <4 x i32>*), align 16 ; <<4 x i32>> [#uses=1] + %4 = load <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32]* @sbuf, i32 0, i32 8) to <4 x i32>*), align 16 ; <<4 x i32>> [#uses=1] + %5 = load <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32]* @sbuf, i32 0, i32 12) to <4 x i32>*), align 16 ; <<4 x i32>> [#uses=1] + tail call void @llvm.arm.neon.vst4.v4i32(i8* bitcast ([16 x i32]* @dbuf to i8*), <4 x i32> %2, <4 x i32> %3, <4 x i32> %4, <4 x i32> %5) nounwind + ret i32 0 +} diff --git a/test/CodeGen/Thumb2/cross-rc-coalescing-1.ll b/test/CodeGen/Thumb2/cross-rc-coalescing-1.ll index 572f1e8..c71c3ca 100644 --- a/test/CodeGen/Thumb2/cross-rc-coalescing-1.ll +++ b/test/CodeGen/Thumb2/cross-rc-coalescing-1.ll @@ -4,9 +4,9 @@ %struct.__sFILEX = type opaque %struct.__sbuf = type { i8*, i32 } -declare arm_apcscc i32 @fgetc(%struct.FILE* nocapture) nounwind +declare i32 @fgetc(%struct.FILE* nocapture) nounwind -define arm_apcscc i32 @main(i32 %argc, i8** nocapture %argv) nounwind { +define i32 @main(i32 %argc, i8** nocapture %argv) nounwind { entry: br i1 undef, label %bb, label %bb1 @@ -20,7 +20,7 @@ bb.i1: ; preds = %bb1 unreachable bb1.i2: ; preds = %bb1 - %0 = call arm_apcscc i32 @fgetc(%struct.FILE* undef) nounwind ; <i32> [#uses=0] + %0 = call i32 @fgetc(%struct.FILE* undef) nounwind ; <i32> [#uses=0] br i1 undef, label %bb2.i3, label %bb3.i4 bb2.i3: ; preds = %bb1.i2 diff --git a/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll b/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll index 6c45349..583f405 100644 --- a/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll +++ b/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 | grep vmov.f32 | count 1 -define arm_apcscc void @fht(float* nocapture %fz, i16 signext %n) nounwind { +define void @fht(float* nocapture %fz, i16 signext %n) nounwind { entry: br label %bb5 diff --git a/test/CodeGen/Thumb2/frameless.ll b/test/CodeGen/Thumb2/frameless.ll index c3c8cf1..fa8d5d8 100644 --- a/test/CodeGen/Thumb2/frameless.ll +++ b/test/CodeGen/Thumb2/frameless.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -disable-fp-elim | not grep mov ; RUN: llc < %s -mtriple=thumbv7-linux -disable-fp-elim | not grep mov -define arm_apcscc void @t() nounwind readnone { +define void @t() nounwind readnone { ret void } diff --git a/test/CodeGen/Thumb2/frameless2.ll b/test/CodeGen/Thumb2/frameless2.ll index 7cc7b19..c5d3239 100644 --- a/test/CodeGen/Thumb2/frameless2.ll +++ b/test/CodeGen/Thumb2/frameless2.ll @@ -3,7 +3,7 @@ %struct.noise3 = type { [3 x [17 x i32]] } %struct.noiseguard = type { i32, i32, i32 } -define arm_apcscc void @vorbis_encode_noisebias_setup(i8* nocapture %vi.0.7.val, double %s, i32 %block, i32* nocapture %suppress, %struct.noise3* nocapture %in, %struct.noiseguard* nocapture %guard, double %userbias) nounwind { +define void @vorbis_encode_noisebias_setup(i8* nocapture %vi.0.7.val, double %s, i32 %block, i32* nocapture %suppress, %struct.noise3* nocapture %in, %struct.noiseguard* nocapture %guard, double %userbias) nounwind { entry: %0 = getelementptr %struct.noiseguard* %guard, i32 %block, i32 2; <i32*> [#uses=1] %1 = load i32* %0, align 4 ; <i32> [#uses=1] diff --git a/test/CodeGen/Thumb2/ifcvt-neon.ll b/test/CodeGen/Thumb2/ifcvt-neon.ll index c667909..6832053 100644 --- a/test/CodeGen/Thumb2/ifcvt-neon.ll +++ b/test/CodeGen/Thumb2/ifcvt-neon.ll @@ -4,7 +4,7 @@ @a = common global float 0.000000e+00 ; <float*> [#uses=2] @b = common global float 0.000000e+00 ; <float*> [#uses=1] -define arm_apcscc float @t(i32 %c) nounwind { +define float @t(i32 %c) nounwind { entry: %0 = icmp sgt i32 %c, 1 ; <i1> [#uses=1] %1 = load float* @a, align 4 ; <float> [#uses=2] diff --git a/test/CodeGen/Thumb2/ldr-str-imm12.ll b/test/CodeGen/Thumb2/ldr-str-imm12.ll index 55cdac9..29b8e75 100644 --- a/test/CodeGen/Thumb2/ldr-str-imm12.ll +++ b/test/CodeGen/Thumb2/ldr-str-imm12.ll @@ -20,15 +20,12 @@ @zz_hold = external global %union.rec* ; <%union.rec**> [#uses=2] @zz_res = external global %union.rec* ; <%union.rec**> [#uses=1] -define arm_apcscc %union.rec* @Manifest(%union.rec* %x, %union.rec* %env, %struct.STYLE* %style, %union.rec** %bthr, %union.rec** %fthr, %union.rec** %target, %union.rec** %crs, i32 %ok, i32 %need_expand, %union.rec** %enclose, i32 %fcr) nounwind { +define %union.rec* @Manifest(%union.rec* %x, %union.rec* %env, %struct.STYLE* %style, %union.rec** %bthr, %union.rec** %fthr, %union.rec** %target, %union.rec** %crs, i32 %ok, i32 %need_expand, %union.rec** %enclose, i32 %fcr) nounwind { entry: ; CHECK: ldr.w r9, [r7, #28] %xgaps.i = alloca [32 x %union.rec*], align 4 ; <[32 x %union.rec*]*> [#uses=0] %ycomp.i = alloca [32 x %union.rec*], align 4 ; <[32 x %union.rec*]*> [#uses=0] - br i1 false, label %bb, label %bb20 - -bb: ; preds = %entry - unreachable + br label %bb20 bb20: ; preds = %entry switch i32 undef, label %bb1287 [ @@ -56,7 +53,7 @@ bb420: ; preds = %bb20, %bb20 store %union.rec* null, %union.rec** @zz_hold, align 4 store %union.rec* null, %union.rec** @zz_res, align 4 store %union.rec* %x, %union.rec** @zz_hold, align 4 - %0 = call arm_apcscc %union.rec* @Manifest(%union.rec* undef, %union.rec* %env, %struct.STYLE* %style, %union.rec** %bthr, %union.rec** %fthr, %union.rec** %target, %union.rec** %crs, i32 %ok, i32 %need_expand, %union.rec** %enclose, i32 %fcr) nounwind ; <%union.rec*> [#uses=0] + %0 = call %union.rec* @Manifest(%union.rec* undef, %union.rec* %env, %struct.STYLE* %style, %union.rec** %bthr, %union.rec** %fthr, %union.rec** %target, %union.rec** %crs, i32 %ok, i32 %need_expand, %union.rec** %enclose, i32 %fcr) nounwind ; <%union.rec*> [#uses=0] unreachable bb438: ; preds = %bb20, %bb20 diff --git a/test/CodeGen/Thumb2/lsr-deficiency.ll b/test/CodeGen/Thumb2/lsr-deficiency.ll index 2038606..7fa782f 100644 --- a/test/CodeGen/Thumb2/lsr-deficiency.ll +++ b/test/CodeGen/Thumb2/lsr-deficiency.ll @@ -11,7 +11,7 @@ @G = external global i32 ; <i32*> [#uses=2] @array = external global i32* ; <i32**> [#uses=1] -define arm_apcscc void @t() nounwind optsize { +define void @t() nounwind optsize { ; CHECK: t: ; CHECK: mov.w r2, #1000 entry: diff --git a/test/CodeGen/Thumb2/machine-licm.ll b/test/CodeGen/Thumb2/machine-licm.ll index 98acc28..cdb3041 100644 --- a/test/CodeGen/Thumb2/machine-licm.ll +++ b/test/CodeGen/Thumb2/machine-licm.ll @@ -8,7 +8,7 @@ @GV = external global i32 ; <i32*> [#uses=2] -define arm_apcscc void @t1(i32* nocapture %vals, i32 %c) nounwind { +define void @t1(i32* nocapture %vals, i32 %c) nounwind { entry: ; CHECK: t1: ; CHECK: cbz @@ -52,11 +52,11 @@ return: ; preds = %bb, %entry } ; rdar://8001136 -define arm_apcscc void @t2(i8* %ptr1, i8* %ptr2) nounwind { +define void @t2(i8* %ptr1, i8* %ptr2) nounwind { entry: ; CHECK: t2: ; CHECK: adr r{{.}}, #LCPI1_0 -; CHECK: vldmia r3, {d0,d1} +; CHECK: vldmia r3, {d0, d1} br i1 undef, label %bb1, label %bb2 bb1: diff --git a/test/CodeGen/Thumb2/pic-load.ll b/test/CodeGen/Thumb2/pic-load.ll index 1f8aea9..35a03e7 100644 --- a/test/CodeGen/Thumb2/pic-load.ll +++ b/test/CodeGen/Thumb2/pic-load.ll @@ -5,7 +5,7 @@ @__dso_handle = external global { } ; <{ }*> [#uses=1] @llvm.used = appending global [1 x i8*] [i8* bitcast (i32 (void ()*)* @atexit to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] -define hidden arm_apcscc i32 @atexit(void ()* %func) nounwind { +define hidden i32 @atexit(void ()* %func) nounwind { entry: ; CHECK: atexit: ; CHECK: add r0, pc @@ -14,8 +14,8 @@ entry: store void ()* %func, void ()** %0, align 4 %1 = getelementptr %struct.one_atexit_routine* %r, i32 0, i32 1 ; <i32*> [#uses=1] store i32 0, i32* %1, align 4 - %2 = call arm_apcscc i32 @atexit_common(%struct.one_atexit_routine* %r, i8* bitcast ({ }* @__dso_handle to i8*)) nounwind ; <i32> [#uses=1] + %2 = call i32 @atexit_common(%struct.one_atexit_routine* %r, i8* bitcast ({ }* @__dso_handle to i8*)) nounwind ; <i32> [#uses=1] ret i32 %2 } -declare arm_apcscc i32 @atexit_common(%struct.one_atexit_routine*, i8*) nounwind +declare i32 @atexit_common(%struct.one_atexit_routine*, i8*) nounwind diff --git a/test/CodeGen/Thumb2/sign_extend_inreg.ll b/test/CodeGen/Thumb2/sign_extend_inreg.ll deleted file mode 100644 index 9a02c1c..0000000 --- a/test/CodeGen/Thumb2/sign_extend_inreg.ll +++ /dev/null @@ -1,22 +0,0 @@ -; RUN: llc < %s -mcpu=cortex-a8 | FileCheck %s -check-prefix=CHECK-A8 -; RUN: llc < %s -mcpu=cortex-m3 | FileCheck %s -check-prefix=CHECK-M3 - -target triple = "thumbv7-apple-darwin10" - -define arm_apcscc i32 @f1(i16* %ptr) nounwind { -; CHECK-A8: f1 -; CHECK-A8: sxth -; CHECK-M3: f1 -; CHECK-M3-NOT: sxth -; CHECK-M3: bx lr - %1 = load i16* %ptr - %2 = icmp eq i16 %1, 1 - %3 = sext i16 %1 to i32 - br i1 %2, label %.next, label %.exit - -.next: - br label %.exit - -.exit: - ret i32 %3 -} diff --git a/test/CodeGen/Thumb2/thumb2-call-tc.ll b/test/CodeGen/Thumb2/thumb2-call-tc.ll new file mode 100644 index 0000000..24502b0 --- /dev/null +++ b/test/CodeGen/Thumb2/thumb2-call-tc.ll @@ -0,0 +1,37 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+thumb2 | FileCheck %s -check-prefix=DARWIN +; RUN: llc < %s -mtriple=thumbv7-linux -mattr=+thumb2 | FileCheck %s -check-prefix=LINUX + +@t = weak global i32 ()* null ; <i32 ()**> [#uses=1] + +declare void @g(i32, i32, i32, i32) + +define void @f() { +; DARWIN: f: +; DARWIN: blx _g + +; LINUX: f: +; LINUX: bl g + tail call void @g( i32 1, i32 2, i32 3, i32 4 ) + ret void +} + +define void @h() { +; DARWIN: h: +; DARWIN: bx r0 @ TAILCALL + +; LINUX: h: +; LINUX: bx r0 @ TAILCALL + %tmp = load i32 ()** @t ; <i32 ()*> [#uses=1] + %tmp.upgrd.2 = tail call i32 %tmp( ) ; <i32> [#uses=0] + ret void +} + +define void @j() { +; DARWIN: j: +; DARWIN: b.w _f @ TAILCALL + +; LINUX: j: +; LINUX: b.w f @ TAILCALL + tail call void @f() + ret void +} diff --git a/test/CodeGen/Thumb2/thumb2-call.ll b/test/CodeGen/Thumb2/thumb2-call.ll index 7dc6b26..8513cfb 100644 --- a/test/CodeGen/Thumb2/thumb2-call.ll +++ b/test/CodeGen/Thumb2/thumb2-call.ll @@ -22,6 +22,6 @@ define void @h() { ; LINUX: h: ; LINUX: blx r0 %tmp = load i32 ()** @t ; <i32 ()*> [#uses=1] - %tmp.upgrd.2 = tail call i32 %tmp( ) ; <i32> [#uses=0] + %tmp.upgrd.2 = call i32 %tmp( ) ; <i32> [#uses=0] ret void } diff --git a/test/CodeGen/Thumb2/thumb2-cbnz.ll b/test/CodeGen/Thumb2/thumb2-cbnz.ll index 0fc6899..10a4985 100644 --- a/test/CodeGen/Thumb2/thumb2-cbnz.ll +++ b/test/CodeGen/Thumb2/thumb2-cbnz.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 | FileCheck %s ; rdar://7354379 -declare arm_apcscc double @floor(double) nounwind readnone +declare double @floor(double) nounwind readnone define void @t(i1 %a, double %b) { entry: @@ -21,9 +21,9 @@ bb7: ; preds = %bb3 bb9: ; preds = %bb7 ; CHECK: cmp r0, #0 -; CHECK-NEXT: cmp r0, #0 +; CHECK: cmp r0, #0 ; CHECK-NEXT: cbnz - %0 = tail call arm_apcscc double @floor(double %b) nounwind readnone ; <double> [#uses=0] + %0 = tail call double @floor(double %b) nounwind readnone ; <double> [#uses=0] br label %bb11 bb11: ; preds = %bb9, %bb7 diff --git a/test/CodeGen/Thumb2/thumb2-eor.ll b/test/CodeGen/Thumb2/thumb2-eor.ll index b7e2766..116a1a3 100644 --- a/test/CodeGen/Thumb2/thumb2-eor.ll +++ b/test/CodeGen/Thumb2/thumb2-eor.ll @@ -9,11 +9,18 @@ define i32 @f1(i32 %a, i32 %b) { define i32 @f2(i32 %a, i32 %b) { ; CHECK: f2: -; CHECK: eor.w r0, r1, r0 +; CHECK: eors r0, r1 %tmp = xor i32 %b, %a ret i32 %tmp } +define i32 @f2b(i32 %a, i32 %b, i32 %c) { +; CHECK: f2b: +; CHECK: eor.w r0, r1, r2 + %tmp = xor i32 %b, %c + ret i32 %tmp +} + define i32 @f3(i32 %a, i32 %b) { ; CHECK: f3: ; CHECK: eor.w r0, r0, r1, lsl #5 diff --git a/test/CodeGen/Thumb2/thumb2-ifcvt1-tc.ll b/test/CodeGen/Thumb2/thumb2-ifcvt1-tc.ll new file mode 100644 index 0000000..c024415 --- /dev/null +++ b/test/CodeGen/Thumb2/thumb2-ifcvt1-tc.ll @@ -0,0 +1,86 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s + +define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { +; CHECK: t1: +; CHECK: it ne +; CHECK: cmpne + switch i32 %c, label %cond_next [ + i32 1, label %cond_true + i32 7, label %cond_true + ] + +cond_true: + %tmp12 = add i32 %a, 1 + %tmp1518 = add i32 %tmp12, %b + ret i32 %tmp1518 + +cond_next: + %tmp15 = add i32 %b, %a + ret i32 %tmp15 +} + +; FIXME: Check for # of unconditional branch after adding branch folding post ifcvt. +define i32 @t2(i32 %a, i32 %b) nounwind { +entry: +; CHECK: t2: +; CHECK: ite gt +; CHECK: subgt +; CHECK: suble + %tmp1434 = icmp eq i32 %a, %b ; <i1> [#uses=1] + br i1 %tmp1434, label %bb17, label %bb.outer + +bb.outer: ; preds = %cond_false, %entry + %b_addr.021.0.ph = phi i32 [ %b, %entry ], [ %tmp10, %cond_false ] ; <i32> [#uses=5] + %a_addr.026.0.ph = phi i32 [ %a, %entry ], [ %a_addr.026.0, %cond_false ] ; <i32> [#uses=1] + br label %bb + +bb: ; preds = %cond_true, %bb.outer + %indvar = phi i32 [ 0, %bb.outer ], [ %indvar.next, %cond_true ] ; <i32> [#uses=2] + %tmp. = sub i32 0, %b_addr.021.0.ph ; <i32> [#uses=1] + %tmp.40 = mul i32 %indvar, %tmp. ; <i32> [#uses=1] + %a_addr.026.0 = add i32 %tmp.40, %a_addr.026.0.ph ; <i32> [#uses=6] + %tmp3 = icmp sgt i32 %a_addr.026.0, %b_addr.021.0.ph ; <i1> [#uses=1] + br i1 %tmp3, label %cond_true, label %cond_false + +cond_true: ; preds = %bb + %tmp7 = sub i32 %a_addr.026.0, %b_addr.021.0.ph ; <i32> [#uses=2] + %tmp1437 = icmp eq i32 %tmp7, %b_addr.021.0.ph ; <i1> [#uses=1] + %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=1] + br i1 %tmp1437, label %bb17, label %bb + +cond_false: ; preds = %bb + %tmp10 = sub i32 %b_addr.021.0.ph, %a_addr.026.0 ; <i32> [#uses=2] + %tmp14 = icmp eq i32 %a_addr.026.0, %tmp10 ; <i1> [#uses=1] + br i1 %tmp14, label %bb17, label %bb.outer + +bb17: ; preds = %cond_false, %cond_true, %entry + %a_addr.026.1 = phi i32 [ %a, %entry ], [ %tmp7, %cond_true ], [ %a_addr.026.0, %cond_false ] ; <i32> [#uses=1] + ret i32 %a_addr.026.1 +} + +@x = external global i32* ; <i32**> [#uses=1] + +define void @foo(i32 %a) nounwind { +entry: + %tmp = load i32** @x ; <i32*> [#uses=1] + store i32 %a, i32* %tmp + ret void +} + +; Tail call prevents use of ifcvt in this one. Seems like a win though. +define void @t3(i32 %a, i32 %b) nounwind { +entry: +; CHECK: t3: +; CHECK-NOT: it lt +; CHECK-NOT: poplt +; CHECK: b.w _foo @ TAILCALL + %tmp1 = icmp sgt i32 %a, 10 ; <i1> [#uses=1] + br i1 %tmp1, label %cond_true, label %UnifiedReturnBlock + +cond_true: ; preds = %entry + tail call void @foo( i32 %b ) + ret void + +UnifiedReturnBlock: ; preds = %entry + ret void +} diff --git a/test/CodeGen/Thumb2/thumb2-ifcvt1.ll b/test/CodeGen/Thumb2/thumb2-ifcvt1.ll index 1d26756..d842d4d 100644 --- a/test/CodeGen/Thumb2/thumb2-ifcvt1.ll +++ b/test/CodeGen/Thumb2/thumb2-ifcvt1.ll @@ -76,7 +76,7 @@ entry: br i1 %tmp1, label %cond_true, label %UnifiedReturnBlock cond_true: ; preds = %entry - tail call void @foo( i32 %b ) + call void @foo( i32 %b ) ret void UnifiedReturnBlock: ; preds = %entry diff --git a/test/CodeGen/Thumb2/thumb2-ifcvt2.ll b/test/CodeGen/Thumb2/thumb2-ifcvt2.ll index d917ffe..2c57348 100644 --- a/test/CodeGen/Thumb2/thumb2-ifcvt2.ll +++ b/test/CodeGen/Thumb2/thumb2-ifcvt2.ll @@ -13,7 +13,7 @@ entry: br i1 %tmp7, label %cond_true, label %UnifiedReturnBlock cond_true: ; preds = %entry - %tmp10 = tail call i32 (...)* @bar( ) ; <i32> [#uses=0] + %tmp10 = call i32 (...)* @bar( ) ; <i32> [#uses=0] ret void UnifiedReturnBlock: ; preds = %entry @@ -32,6 +32,7 @@ entry: ; CHECK: it eq ; CHECK: cmpeq ; CHECK: bne +; CHECK: cmp ; CHECK: itt eq ; CHECK: moveq ; CHECK: popeq diff --git a/test/CodeGen/Thumb2/thumb2-ifcvt3.ll b/test/CodeGen/Thumb2/thumb2-ifcvt3.ll index e465c00..cc2ef14 100644 --- a/test/CodeGen/Thumb2/thumb2-ifcvt3.ll +++ b/test/CodeGen/Thumb2/thumb2-ifcvt3.ll @@ -23,7 +23,7 @@ bb52: ; preds = %newFuncRoot ; CHECK: movne ; CHECK: moveq ; CHECK: pop -; CHECK-NEXT: LBB0_1: +; CHECK-NEXT: @ BB#1: %0 = load i64* @posed, align 4 ; <i64> [#uses=3] %1 = sub i64 %0, %.reload78 ; <i64> [#uses=1] %2 = ashr i64 %1, 1 ; <i64> [#uses=3] diff --git a/test/CodeGen/Thumb2/thumb2-ldm.ll b/test/CodeGen/Thumb2/thumb2-ldm.ll index da2874d..c5f7e84 100644 --- a/test/CodeGen/Thumb2/thumb2-ldm.ll +++ b/test/CodeGen/Thumb2/thumb2-ldm.ll @@ -8,7 +8,7 @@ define i32 @t1() { ; CHECK: pop {r7, pc} %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 0) ; <i32> [#uses=1] %tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 1) ; <i32> [#uses=1] - %tmp4 = tail call i32 @f1( i32 %tmp, i32 %tmp3 ) ; <i32> [#uses=1] + %tmp4 = call i32 @f1( i32 %tmp, i32 %tmp3 ) ; <i32> [#uses=1] ret i32 %tmp4 } @@ -20,7 +20,7 @@ define i32 @t2() { %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 2) ; <i32> [#uses=1] %tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 3) ; <i32> [#uses=1] %tmp5 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 4) ; <i32> [#uses=1] - %tmp6 = tail call i32 @f2( i32 %tmp, i32 %tmp3, i32 %tmp5 ) ; <i32> [#uses=1] + %tmp6 = call i32 @f2( i32 %tmp, i32 %tmp3, i32 %tmp5 ) ; <i32> [#uses=1] ret i32 %tmp6 } @@ -31,7 +31,7 @@ define i32 @t3() { %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 1) ; <i32> [#uses=1] %tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 2) ; <i32> [#uses=1] %tmp5 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 3) ; <i32> [#uses=1] - %tmp6 = tail call i32 @f2( i32 %tmp, i32 %tmp3, i32 %tmp5 ) ; <i32> [#uses=1] + %tmp6 = call i32 @f2( i32 %tmp, i32 %tmp3, i32 %tmp5 ) ; <i32> [#uses=1] ret i32 %tmp6 } diff --git a/test/CodeGen/Thumb2/thumb2-select_xform.ll b/test/CodeGen/Thumb2/thumb2-select_xform.ll index 7fc2e2a..56cb1f6 100644 --- a/test/CodeGen/Thumb2/thumb2-select_xform.ll +++ b/test/CodeGen/Thumb2/thumb2-select_xform.ll @@ -3,8 +3,8 @@ define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind { ; CHECK: t1 ; CHECK: sub.w r0, r1, #-2147483648 +; CHECK: subs r0, #1 ; CHECK: cmp r2, #10 -; CHECK: sub.w r0, r0, #1 ; CHECK: it gt ; CHECK: movgt r0, r1 %tmp1 = icmp sgt i32 %c, 10 diff --git a/test/CodeGen/Thumb2/thumb2-spill-q.ll b/test/CodeGen/Thumb2/thumb2-spill-q.ll index bf9c052..3946371 100644 --- a/test/CodeGen/Thumb2/thumb2-spill-q.ll +++ b/test/CodeGen/Thumb2/thumb2-spill-q.ll @@ -9,7 +9,7 @@ declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*) nounwind readonly -define arm_apcscc void @aaa(%quuz* %this, i8* %block) { +define void @aaa(%quuz* %this, i8* %block) { ; CHECK: aaa: ; CHECK: bic r4, r4, #15 ; CHECK: vst1.64 {{.*}}[{{.*}}, :128] diff --git a/test/CodeGen/Thumb2/thumb2-tbh.ll b/test/CodeGen/Thumb2/thumb2-tbh.ll index 2cf1d6a..cd9c8e1 100644 --- a/test/CodeGen/Thumb2/thumb2-tbh.ll +++ b/test/CodeGen/Thumb2/thumb2-tbh.ll @@ -8,13 +8,13 @@ @.str31 = external constant [28 x i8], align 1 ; <[28 x i8]*> [#uses=1] @_T_gtol = external global %struct._T_tstr* ; <%struct._T_tstr**> [#uses=2] -declare arm_apcscc i32 @strlen(i8* nocapture) nounwind readonly +declare i32 @strlen(i8* nocapture) nounwind readonly -declare arm_apcscc void @Z_fatal(i8*) noreturn nounwind +declare void @Z_fatal(i8*) noreturn nounwind -declare arm_apcscc noalias i8* @calloc(i32, i32) nounwind +declare noalias i8* @calloc(i32, i32) nounwind -define arm_apcscc i32 @main(i32 %argc, i8** nocapture %argv) nounwind { +define i32 @main(i32 %argc, i8** nocapture %argv) nounwind { ; CHECK: main: ; CHECK: tbb entry: @@ -28,39 +28,39 @@ bb5.i: ; preds = %bb42.i br label %bb40.i bb7.i: ; preds = %bb42.i - call arm_apcscc void @_T_addtol(%struct._T_tstr** @_T_gtol, i32 0, i8* null) nounwind + call void @_T_addtol(%struct._T_tstr** @_T_gtol, i32 0, i8* null) nounwind unreachable bb15.i: ; preds = %bb42.i - call arm_apcscc void @_T_addtol(%struct._T_tstr** @_T_gtol, i32 2, i8* null) nounwind + call void @_T_addtol(%struct._T_tstr** @_T_gtol, i32 2, i8* null) nounwind unreachable bb23.i: ; preds = %bb42.i - %1 = call arm_apcscc i32 @strlen(i8* null) nounwind readonly ; <i32> [#uses=0] + %1 = call i32 @strlen(i8* null) nounwind readonly ; <i32> [#uses=0] unreachable bb33.i: ; preds = %bb42.i store i32 0, i32* @_C_nextcmd, align 4 - %2 = call arm_apcscc noalias i8* @calloc(i32 21, i32 1) nounwind ; <i8*> [#uses=0] + %2 = call noalias i8* @calloc(i32 21, i32 1) nounwind ; <i8*> [#uses=0] unreachable bb34.i: ; preds = %bb42.i %3 = load i32* @_C_nextcmd, align 4 ; <i32> [#uses=1] %4 = add i32 %3, 1 ; <i32> [#uses=1] store i32 %4, i32* @_C_nextcmd, align 4 - %5 = call arm_apcscc noalias i8* @calloc(i32 22, i32 1) nounwind ; <i8*> [#uses=0] + %5 = call noalias i8* @calloc(i32 22, i32 1) nounwind ; <i8*> [#uses=0] unreachable bb35.i: ; preds = %bb42.i - %6 = call arm_apcscc noalias i8* @calloc(i32 20, i32 1) nounwind ; <i8*> [#uses=0] + %6 = call noalias i8* @calloc(i32 20, i32 1) nounwind ; <i8*> [#uses=0] unreachable bb37.i: ; preds = %bb42.i - %7 = call arm_apcscc noalias i8* @calloc(i32 14, i32 1) nounwind ; <i8*> [#uses=0] + %7 = call noalias i8* @calloc(i32 14, i32 1) nounwind ; <i8*> [#uses=0] unreachable bb39.i: ; preds = %bb42.i - call arm_apcscc void @Z_fatal(i8* getelementptr ([28 x i8]* @.str31, i32 0, i32 0)) nounwind + call void @Z_fatal(i8* getelementptr ([28 x i8]* @.str31, i32 0, i32 0)) nounwind unreachable bb40.i: ; preds = %bb42.i, %bb5.i, %bb1.i2 @@ -81,4 +81,4 @@ bb42.i: ; preds = %bb40.i, %entry ] } -declare arm_apcscc void @_T_addtol(%struct._T_tstr** nocapture, i32, i8*) nounwind +declare void @_T_addtol(%struct._T_tstr** nocapture, i32, i8*) nounwind diff --git a/test/CodeGen/Thumb2/thumb2-uxtb.ll b/test/CodeGen/Thumb2/thumb2-uxtb.ll index 5411914..1fa4e5c 100644 --- a/test/CodeGen/Thumb2/thumb2-uxtb.ll +++ b/test/CodeGen/Thumb2/thumb2-uxtb.ll @@ -1,47 +1,72 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2,+t2xtpk | FileCheck %s +; RUN: llc < %s -march=thumb -mcpu=cortex-a8 | FileCheck %s -check-prefix=ARMv7A +; RUN: llc < %s -march=thumb -mcpu=cortex-m3 | FileCheck %s -check-prefix=ARMv7M define i32 @test1(i32 %x) { -; CHECK: test1 -; CHECK: uxtb16 r0, r0 +; ARMv7A: test1 +; ARMv7A: uxtb16 r0, r0 + +; ARMv7M: test1 +; ARMv7M: and r0, r0, #16711935 %tmp1 = and i32 %x, 16711935 ; <i32> [#uses=1] ret i32 %tmp1 } +; PR7503 define i32 @test2(i32 %x) { -; CHECK: test2 -; CHECK: uxtb16 r0, r0, ror #8 +; ARMv7A: test2 +; ARMv7A: uxtb16 r0, r0, ror #8 + +; ARMv7M: test2 +; ARMv7M: mov.w r1, #16711935 +; ARMv7M: and.w r0, r1, r0, lsr #8 %tmp1 = lshr i32 %x, 8 ; <i32> [#uses=1] %tmp2 = and i32 %tmp1, 16711935 ; <i32> [#uses=1] ret i32 %tmp2 } define i32 @test3(i32 %x) { -; CHECK: test3 -; CHECK: uxtb16 r0, r0, ror #8 +; ARMv7A: test3 +; ARMv7A: uxtb16 r0, r0, ror #8 + +; ARMv7M: test3 +; ARMv7M: mov.w r1, #16711935 +; ARMv7M: and.w r0, r1, r0, lsr #8 %tmp1 = lshr i32 %x, 8 ; <i32> [#uses=1] %tmp2 = and i32 %tmp1, 16711935 ; <i32> [#uses=1] ret i32 %tmp2 } define i32 @test4(i32 %x) { -; CHECK: test4 -; CHECK: uxtb16 r0, r0, ror #8 +; ARMv7A: test4 +; ARMv7A: uxtb16 r0, r0, ror #8 + +; ARMv7M: test4 +; ARMv7M: mov.w r1, #16711935 +; ARMv7M: and.w r0, r1, r0, lsr #8 %tmp1 = lshr i32 %x, 8 ; <i32> [#uses=1] %tmp6 = and i32 %tmp1, 16711935 ; <i32> [#uses=1] ret i32 %tmp6 } define i32 @test5(i32 %x) { -; CHECK: test5 -; CHECK: uxtb16 r0, r0, ror #8 +; ARMv7A: test5 +; ARMv7A: uxtb16 r0, r0, ror #8 + +; ARMv7M: test5 +; ARMv7M: mov.w r1, #16711935 +; ARMv7M: and.w r0, r1, r0, lsr #8 %tmp1 = lshr i32 %x, 8 ; <i32> [#uses=1] %tmp2 = and i32 %tmp1, 16711935 ; <i32> [#uses=1] ret i32 %tmp2 } define i32 @test6(i32 %x) { -; CHECK: test6 -; CHECK: uxtb16 r0, r0, ror #16 +; ARMv7A: test6 +; ARMv7A: uxtb16 r0, r0, ror #16 + +; ARMv7M: test6 +; ARMv7M: mov.w r1, #16711935 +; ARMv7M: and.w r0, r1, r0, ror #16 %tmp1 = lshr i32 %x, 16 ; <i32> [#uses=1] %tmp2 = and i32 %tmp1, 255 ; <i32> [#uses=1] %tmp4 = shl i32 %x, 16 ; <i32> [#uses=1] @@ -51,8 +76,12 @@ define i32 @test6(i32 %x) { } define i32 @test7(i32 %x) { -; CHECK: test7 -; CHECK: uxtb16 r0, r0, ror #16 +; ARMv7A: test7 +; ARMv7A: uxtb16 r0, r0, ror #16 + +; ARMv7M: test7 +; ARMv7M: mov.w r1, #16711935 +; ARMv7M: and.w r0, r1, r0, ror #16 %tmp1 = lshr i32 %x, 16 ; <i32> [#uses=1] %tmp2 = and i32 %tmp1, 255 ; <i32> [#uses=1] %tmp4 = shl i32 %x, 16 ; <i32> [#uses=1] @@ -62,8 +91,12 @@ define i32 @test7(i32 %x) { } define i32 @test8(i32 %x) { -; CHECK: test8 -; CHECK: uxtb16 r0, r0, ror #24 +; ARMv7A: test8 +; ARMv7A: uxtb16 r0, r0, ror #24 + +; ARMv7M: test8 +; ARMv7M: mov.w r1, #16711935 +; ARMv7M: and.w r0, r1, r0, ror #24 %tmp1 = shl i32 %x, 8 ; <i32> [#uses=1] %tmp2 = and i32 %tmp1, 16711680 ; <i32> [#uses=1] %tmp5 = lshr i32 %x, 24 ; <i32> [#uses=1] @@ -72,8 +105,12 @@ define i32 @test8(i32 %x) { } define i32 @test9(i32 %x) { -; CHECK: test9 -; CHECK: uxtb16 r0, r0, ror #24 +; ARMv7A: test9 +; ARMv7A: uxtb16 r0, r0, ror #24 + +; ARMv7M: test9 +; ARMv7M: mov.w r1, #16711935 +; ARMv7M: and.w r0, r1, r0, ror #24 %tmp1 = lshr i32 %x, 24 ; <i32> [#uses=1] %tmp4 = shl i32 %x, 8 ; <i32> [#uses=1] %tmp5 = and i32 %tmp4, 16711680 ; <i32> [#uses=1] @@ -82,13 +119,19 @@ define i32 @test9(i32 %x) { } define i32 @test10(i32 %p0) { -; CHECK: test10 -; CHECK: mov.w r1, #16253176 -; CHECK: and.w r0, r1, r0, lsr #7 -; CHECK: lsrs r1, r0, #5 -; CHECK: uxtb16 r1, r1 -; CHECK: orr.w r0, r1, r0 +; ARMv7A: test10 +; ARMv7A: mov.w r1, #16253176 +; ARMv7A: and.w r0, r1, r0, lsr #7 +; ARMv7A: lsrs r1, r0, #5 +; ARMv7A: uxtb16 r1, r1 +; ARMv7A: orrs r0, r1 +; ARMv7M: test10 +; ARMv7M: mov.w r1, #16253176 +; ARMv7M: and.w r0, r1, r0, lsr #7 +; ARMv7M: mov.w r1, #458759 +; ARMv7M: and.w r1, r1, r0, lsr #5 +; ARMv7M: orrs r0, r1 %tmp1 = lshr i32 %p0, 7 ; <i32> [#uses=1] %tmp2 = and i32 %tmp1, 16253176 ; <i32> [#uses=2] %tmp4 = lshr i32 %tmp2, 5 ; <i32> [#uses=1] diff --git a/test/CodeGen/X86/2006-11-17-IllegalMove.ll b/test/CodeGen/X86/2006-11-17-IllegalMove.ll index e839d72..affb7af 100644 --- a/test/CodeGen/X86/2006-11-17-IllegalMove.ll +++ b/test/CodeGen/X86/2006-11-17-IllegalMove.ll @@ -15,14 +15,14 @@ bb77: ; preds = %entry, %entry %tmp99 = udiv i64 0, 0 ; <i64> [#uses=1] %tmp = load i8* null ; <i8> [#uses=1] %tmp114 = icmp eq i64 0, 0 ; <i1> [#uses=1] - br i1 %tmp114, label %cond_true115, label %cond_next136 + br label %cond_true115 bb84: ; preds = %entry ret void cond_true115: ; preds = %bb77 %tmp118 = load i8* null ; <i8> [#uses=1] - br i1 false, label %cond_next129, label %cond_true120 + br label %cond_true120 cond_true120: ; preds = %cond_true115 %tmp127 = udiv i8 %tmp, %tmp118 ; <i8> [#uses=1] @@ -30,7 +30,7 @@ cond_true120: ; preds = %cond_true115 br label %cond_next129 cond_next129: ; preds = %cond_true120, %cond_true115 - %iftmp.30.0 = phi i64 [ %tmp127.upgrd.1, %cond_true120 ], [ 0, %cond_true115 ] ; <i64> [#uses=1] + %iftmp.30.0 = phi i64 [ %tmp127.upgrd.1, %cond_true120 ] ; <i64> [#uses=1] %tmp132 = icmp eq i64 %iftmp.30.0, %tmp99 ; <i1> [#uses=1] br i1 %tmp132, label %cond_false148, label %cond_next136 diff --git a/test/CodeGen/X86/2007-01-08-InstrSched.ll b/test/CodeGen/X86/2007-01-08-InstrSched.ll index ef19d72..6f8b89c 100644 --- a/test/CodeGen/X86/2007-01-08-InstrSched.ll +++ b/test/CodeGen/X86/2007-01-08-InstrSched.ll @@ -11,12 +11,12 @@ define float @foo(float %x) nounwind { %tmp14 = fadd float %tmp12, %tmp7 ret float %tmp14 -; CHECK: mulss LCPI0_0(%rip) -; CHECK: mulss LCPI0_1(%rip) +; CHECK: mulss +; CHECK: mulss ; CHECK: addss -; CHECK: mulss LCPI0_2(%rip) +; CHECK: mulss ; CHECK: addss -; CHECK: mulss LCPI0_3(%rip) +; CHECK: mulss ; CHECK: addss ; CHECK: ret } diff --git a/test/CodeGen/X86/2007-10-12-CoalesceExtSubReg.ll b/test/CodeGen/X86/2007-10-12-CoalesceExtSubReg.ll index fc11347..db13fde 100644 --- a/test/CodeGen/X86/2007-10-12-CoalesceExtSubReg.ll +++ b/test/CodeGen/X86/2007-10-12-CoalesceExtSubReg.ll @@ -9,10 +9,7 @@ cond_next127: ; preds = %cond_next391, %entry %tmp149 = mul i32 0, %v.1 ; <i32> [#uses=0] %tmp254 = and i32 0, 15 ; <i32> [#uses=1] %tmp256 = and i32 0, 15 ; <i32> [#uses=2] - br i1 false, label %cond_true267, label %cond_next391 - -cond_true267: ; preds = %cond_next127 - ret i16 0 + br label %cond_next391 cond_next391: ; preds = %cond_next127 %tmp393 = load i32* %ss, align 4 ; <i32> [#uses=1] diff --git a/test/CodeGen/X86/2007-11-04-rip-immediate-constant.ll b/test/CodeGen/X86/2007-11-04-rip-immediate-constant.ll index 8e586a7..228a915 100644 --- a/test/CodeGen/X86/2007-11-04-rip-immediate-constant.ll +++ b/test/CodeGen/X86/2007-11-04-rip-immediate-constant.ll @@ -1,7 +1,7 @@ -; RUN: llc < %s -relocation-model=static | grep {foo _str$} +; RUN: llc < %s -relocation-model=static | grep {foo str$} ; PR1761 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" -target triple = "x86_64-apple-darwin8" +target triple = "x86_64-pc-linux" @str = internal constant [12 x i8] c"init/main.c\00" ; <[12 x i8]*> [#uses=1] define i32 @unknown_bootoption() { diff --git a/test/CodeGen/X86/2007-11-14-Coalescer-Bug.ll b/test/CodeGen/X86/2007-11-14-Coalescer-Bug.ll deleted file mode 100644 index 9c004f9..0000000 --- a/test/CodeGen/X86/2007-11-14-Coalescer-Bug.ll +++ /dev/null @@ -1,68 +0,0 @@ -; RUN: llc < %s -march=x86 -x86-asm-syntax=att | grep movl | count 2 -; RUN: llc < %s -march=x86 -x86-asm-syntax=att | not grep movb - - %struct.double_int = type { i64, i64 } - %struct.tree_common = type <{ i8, [3 x i8] }> - %struct.tree_int_cst = type { %struct.tree_common, %struct.double_int } - %struct.tree_node = type { %struct.tree_int_cst } -@tree_code_type = external constant [0 x i32] ; <[0 x i32]*> [#uses=1] - -define i32 @simple_cst_equal(%struct.tree_node* %t1, %struct.tree_node* %t2) nounwind { -entry: - %tmp2526 = bitcast %struct.tree_node* %t1 to i32* ; <i32*> [#uses=1] - br i1 false, label %UnifiedReturnBlock, label %bb21 - -bb21: ; preds = %entry - %tmp27 = load i32* %tmp2526, align 4 ; <i32> [#uses=1] - %tmp29 = and i32 %tmp27, 255 ; <i32> [#uses=3] - %tmp2930 = trunc i32 %tmp29 to i8 ; <i8> [#uses=1] - %tmp37 = load i32* null, align 4 ; <i32> [#uses=1] - %tmp39 = and i32 %tmp37, 255 ; <i32> [#uses=2] - %tmp3940 = trunc i32 %tmp39 to i8 ; <i8> [#uses=1] - %tmp43 = add i32 %tmp29, -3 ; <i32> [#uses=1] - %tmp44 = icmp ult i32 %tmp43, 3 ; <i1> [#uses=1] - br i1 %tmp44, label %bb47.split, label %bb76 - -bb47.split: ; preds = %bb21 - ret i32 0 - -bb76: ; preds = %bb21 - br i1 false, label %bb82, label %bb146.split - -bb82: ; preds = %bb76 - %tmp94 = getelementptr [0 x i32]* @tree_code_type, i32 0, i32 %tmp39 ; <i32*> [#uses=1] - %tmp95 = load i32* %tmp94, align 4 ; <i32> [#uses=1] - %tmp9596 = trunc i32 %tmp95 to i8 ; <i8> [#uses=1] - %tmp98 = add i8 %tmp9596, -4 ; <i8> [#uses=1] - %tmp99 = icmp ugt i8 %tmp98, 5 ; <i1> [#uses=1] - br i1 %tmp99, label %bb102, label %bb106 - -bb102: ; preds = %bb82 - ret i32 0 - -bb106: ; preds = %bb82 - ret i32 0 - -bb146.split: ; preds = %bb76 - %tmp149 = icmp eq i8 %tmp2930, %tmp3940 ; <i1> [#uses=1] - br i1 %tmp149, label %bb153, label %UnifiedReturnBlock - -bb153: ; preds = %bb146.split - switch i32 %tmp29, label %UnifiedReturnBlock [ - i32 0, label %bb155 - i32 1, label %bb187 - ] - -bb155: ; preds = %bb153 - ret i32 0 - -bb187: ; preds = %bb153 - %tmp198 = icmp eq %struct.tree_node* %t1, %t2 ; <i1> [#uses=1] - br i1 %tmp198, label %bb201, label %UnifiedReturnBlock - -bb201: ; preds = %bb187 - ret i32 0 - -UnifiedReturnBlock: ; preds = %bb187, %bb153, %bb146.split, %entry - ret i32 0 -} diff --git a/test/CodeGen/X86/2008-01-16-FPStackifierAssert.ll b/test/CodeGen/X86/2008-01-16-FPStackifierAssert.ll index 8aabb52..0091397 100644 --- a/test/CodeGen/X86/2008-01-16-FPStackifierAssert.ll +++ b/test/CodeGen/X86/2008-01-16-FPStackifierAssert.ll @@ -1,4 +1,3 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 -regalloc=local ; RUN: llc < %s -march=x86 -mattr=+sse2 -regalloc=fast define void @SolveCubic(double %a, double %b, double %c, double %d, i32* %solutions, double* %x) { diff --git a/test/CodeGen/X86/2008-02-22-LocalRegAllocBug.ll b/test/CodeGen/X86/2008-02-22-LocalRegAllocBug.ll index d294885..da02907 100644 --- a/test/CodeGen/X86/2008-02-22-LocalRegAllocBug.ll +++ b/test/CodeGen/X86/2008-02-22-LocalRegAllocBug.ll @@ -1,4 +1,3 @@ -; RUN: llc < %s -regalloc=local -march=x86 -mattr=+mmx | grep esi ; RUN: llc < %s -regalloc=fast -march=x86 -mattr=+mmx | grep esi ; PR2082 ; Local register allocator was refusing to use ESI, EDI, and EBP so it ran out of diff --git a/test/CodeGen/X86/2008-03-10-RegAllocInfLoop.ll b/test/CodeGen/X86/2008-03-10-RegAllocInfLoop.ll index cd2d609..40aafb4 100644 --- a/test/CodeGen/X86/2008-03-10-RegAllocInfLoop.ll +++ b/test/CodeGen/X86/2008-03-10-RegAllocInfLoop.ll @@ -1,5 +1,4 @@ ; RUN: llc < %s -mtriple=i386-pc-linux-gnu -relocation-model=pic -disable-fp-elim -; RUN: llc < %s -mtriple=i386-pc-linux-gnu -relocation-model=pic -disable-fp-elim -schedule-livein-copies | not grep {Number of register spills} ; PR2134 declare fastcc i8* @w_addchar(i8*, i32*, i32*, i8 signext ) nounwind diff --git a/test/CodeGen/X86/2008-03-18-CoalescerBug.ll b/test/CodeGen/X86/2008-03-18-CoalescerBug.ll index ccc4d75..3ae5026 100644 --- a/test/CodeGen/X86/2008-03-18-CoalescerBug.ll +++ b/test/CodeGen/X86/2008-03-18-CoalescerBug.ll @@ -19,7 +19,7 @@ bb33: ; preds = %entry br i1 %tmp35, label %bb38, label %bb87.preheader bb38: ; preds = %bb33 %tmp53 = add i32 %tmp19, %delta ; <i32> [#uses=2] - br i1 false, label %bb50, label %bb43 + br label %bb43 bb43: ; preds = %bb38 store i32 %tmp53, i32* null, align 4 ret void diff --git a/test/CodeGen/X86/2008-04-09-BranchFolding.ll b/test/CodeGen/X86/2008-04-09-BranchFolding.ll index 41fbdd1..f4b2d71 100644 --- a/test/CodeGen/X86/2008-04-09-BranchFolding.ll +++ b/test/CodeGen/X86/2008-04-09-BranchFolding.ll @@ -10,7 +10,7 @@ define fastcc %struct.tree_node* @pushdecl(%struct.tree_node* %x) nounwind { entry: %tmp3.i40 = icmp eq %struct.binding_level* null, null ; <i1> [#uses=2] - br i1 false, label %bb143, label %bb140 + br label %bb140 bb140: ; preds = %entry br i1 %tmp3.i40, label %bb160, label %bb17.i bb17.i: ; preds = %bb140 diff --git a/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll b/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll index 716563b..0742371 100644 --- a/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll +++ b/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll @@ -1,5 +1,4 @@ ; RUN: llc < %s -mtriple=x86_64-apple-darwin -; RUN: llc < %s -mtriple=x86_64-apple-darwin -relocation-model=pic -disable-fp-elim -O0 -regalloc=local ; RUN: llc < %s -mtriple=x86_64-apple-darwin -relocation-model=pic -disable-fp-elim -O0 -regalloc=fast ; PR5534 diff --git a/test/CodeGen/X86/2008-05-21-CoalescerBug.ll b/test/CodeGen/X86/2008-05-21-CoalescerBug.ll index 9cf50f4..e5dda4a 100644 --- a/test/CodeGen/X86/2008-05-21-CoalescerBug.ll +++ b/test/CodeGen/X86/2008-05-21-CoalescerBug.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -O0 -fast-isel=false | grep mov | count 5 +; RUN: llc < %s -march=x86 -O0 -fast-isel=false -regalloc=linearscan | grep mov | count 5 ; PR2343 %llvm.dbg.anchor.type = type { i32, i32 } diff --git a/test/CodeGen/X86/2008-05-28-LocalRegAllocBug.ll b/test/CodeGen/X86/2008-05-28-LocalRegAllocBug.ll index 5929aff..94c95d4 100644 --- a/test/CodeGen/X86/2008-05-28-LocalRegAllocBug.ll +++ b/test/CodeGen/X86/2008-05-28-LocalRegAllocBug.ll @@ -1,4 +1,3 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin -regalloc=local ; RUN: llc < %s -mtriple=i386-apple-darwin -regalloc=fast @_ZTVN10Evaluation10GridOutputILi3EEE = external constant [5 x i32 (...)*] ; <[5 x i32 (...)*]*> [#uses=1] diff --git a/test/CodeGen/X86/2008-08-23-X86-64AsmBug.ll b/test/CodeGen/X86/2008-08-23-X86-64AsmBug.ll index eacb4a5..ce9e389 100644 --- a/test/CodeGen/X86/2008-08-23-X86-64AsmBug.ll +++ b/test/CodeGen/X86/2008-08-23-X86-64AsmBug.ll @@ -7,7 +7,7 @@ define double @_Z7qstrtodPKcPS0_Pb(i8* %s00, i8** %se, i8* %ok) nounwind { entry: - br i1 false, label %bb151, label %bb163 + br label %bb163 bb151: ; preds = %entry br label %bb163 @@ -19,13 +19,13 @@ bb163: ; preds = %bb151, %entry br label %bb5.i bb5.i: ; preds = %bb5.i57.i, %bb163 - %b.0.i = phi %struct.Bigint* [ null, %bb163 ], [ %tmp9.i.i41.i, %bb5.i57.i ] ; <%struct.Bigint*> [#uses=1] + %b.0.i = phi %struct.Bigint* [ null, %bb163 ] ; <%struct.Bigint*> [#uses=1] %tmp3.i7.i728 = load i32* null, align 4 ; <i32> [#uses=1] br label %bb.i27.i bb.i27.i: ; preds = %bb.i27.i, %bb5.i %tmp23.i20.i = lshr i32 0, 16 ; <i32> [#uses=1] - br i1 false, label %bb.i27.i, label %bb5.i57.i + br label %bb5.i57.i bb5.i57.i: ; preds = %bb.i27.i %tmp50.i35.i = load i32* null, align 4 ; <i32> [#uses=1] @@ -41,7 +41,7 @@ bb5.i57.i: ; preds = %bb.i27.i store i32 %tmp23.i20.i, i32* null, align 4 %tmp74.i61.i = add i32 %tmp3.i7.i728, 1 ; <i32> [#uses=1] store i32 %tmp74.i61.i, i32* null, align 4 - br i1 false, label %bb5.i, label %bb7.i + br label %bb7.i bb7.i: ; preds = %bb5.i57.i %tmp514 = load i32* null, align 4 ; <i32> [#uses=1] diff --git a/test/CodeGen/X86/2008-09-17-inline-asm-1.ll b/test/CodeGen/X86/2008-09-17-inline-asm-1.ll index dd83336..3c64fe4 100644 --- a/test/CodeGen/X86/2008-09-17-inline-asm-1.ll +++ b/test/CodeGen/X86/2008-09-17-inline-asm-1.ll @@ -1,5 +1,4 @@ ; RUN: llc < %s -march=x86 | FileCheck %s -; RUN: llc < %s -march=x86 -regalloc=local | FileCheck %s ; RUN: llc < %s -march=x86 -regalloc=fast | FileCheck %s ; %0 must not be put in EAX or EDX. diff --git a/test/CodeGen/X86/2008-09-18-inline-asm-2.ll b/test/CodeGen/X86/2008-09-18-inline-asm-2.ll index 4400940..eadfda0 100644 --- a/test/CodeGen/X86/2008-09-18-inline-asm-2.ll +++ b/test/CodeGen/X86/2008-09-18-inline-asm-2.ll @@ -1,6 +1,5 @@ -; RUN: llc < %s -march=x86 | grep "#%ebp %esi %edi 8(%edx) %eax (%ebx)" -; RUN: llc < %s -march=x86 -regalloc=local | grep "#%edi %ebp %edx 8(%ebx) %eax (%esi)" -; RUN: llc < %s -march=x86 -regalloc=fast | grep "#%edi %ebp %edx 8(%ebx) %eax (%esi)" +; RUN: llc < %s -march=x86 | grep "#%ebp %edi %ebx 8(%esi) %eax %dl" +; RUN: llc < %s -march=x86 -regalloc=fast | grep "#%ebx %esi %edi 8(%ebp) %eax %dl" ; The 1st, 2nd, 3rd and 5th registers above must all be different. The registers ; referenced in the 4th and 6th operands must not be the same as the 1st or 5th diff --git a/test/CodeGen/X86/2008-10-16-SpillerBug.ll b/test/CodeGen/X86/2008-10-16-SpillerBug.ll deleted file mode 100644 index 87305a0..0000000 --- a/test/CodeGen/X86/2008-10-16-SpillerBug.ll +++ /dev/null @@ -1,160 +0,0 @@ -; RUN: llc < %s -relocation-model=pic -disable-fp-elim -mtriple=i386-apple-darwin -stats |& grep asm-printer | grep 41 -; RUN: llc < %s -relocation-model=pic -disable-fp-elim -mtriple=i386-apple-darwin | FileCheck %s - - %struct.XXDActiveTextureTargets = type { i64, i64, i64, i64, i64, i64 } - %struct.XXDAlphaTest = type { float, i16, i8, i8 } - %struct.XXDArrayRange = type { i8, i8, i8, i8 } - %struct.XXDBlendMode = type { i16, i16, i16, i16, %struct.XXTColor4, i16, i16, i8, i8, i8, i8 } - %struct.XXDClearColor = type { double, %struct.XXTColor4, %struct.XXTColor4, float, i32 } - %struct.XXDClipPlane = type { i32, [6 x %struct.XXTColor4] } - %struct.XXDColorBuffer = type { i16, i8, i8, [8 x i16], i8, i8, i8, i8 } - %struct.XXDColorMatrix = type { [16 x float]*, %struct.XXDImagingCC } - %struct.XXDConvolution = type { %struct.XXTColor4, %struct.XXDImagingCC, i16, i16, [0 x i32], float*, i32, i32 } - %struct.XXDDepthTest = type { i16, i16, i8, i8, i8, i8, double, double } - %struct.XXDFixedFunction = type { %struct.YYToken* } - %struct.XXDFogMode = type { %struct.XXTColor4, float, float, float, float, float, i16, i16, i16, i8, i8 } - %struct.XXDHintMode = type { i16, i16, i16, i16, i16, i16, i16, i16, i16, i16 } - %struct.XXDHistogram = type { %struct.XXTFixedColor4*, i32, i16, i8, i8 } - %struct.XXDImagingCC = type { { float, float }, { float, float }, { float, float }, { float, float } } - %struct.XXDImagingSubset = type { %struct.XXDConvolution, %struct.XXDConvolution, %struct.XXDConvolution, %struct.XXDColorMatrix, %struct.XXDMinmax, %struct.XXDHistogram, %struct.XXDImagingCC, %struct.XXDImagingCC, %struct.XXDImagingCC, %struct.XXDImagingCC, i32, [0 x i32] } - %struct.XXDLight = type { %struct.XXTColor4, %struct.XXTColor4, %struct.XXTColor4, %struct.XXTColor4, %struct.XXTCoord3, float, float, float, float, float, %struct.XXTCoord3, float, %struct.XXTCoord3, float, %struct.XXTCoord3, float, float, float, float, float } - %struct.XXDLightModel = type { %struct.XXTColor4, [8 x %struct.XXDLight], [2 x %struct.XXDMaterial], i32, i16, i16, i16, i8, i8, i8, i8, i8, i8 } - %struct.XXDLightProduct = type { %struct.XXTColor4, %struct.XXTColor4, %struct.XXTColor4 } - %struct.XXDLineMode = type { float, i32, i16, i16, i8, i8, i8, i8 } - %struct.XXDLogicOp = type { i16, i8, i8 } - %struct.XXDMaskMode = type { i32, [3 x i32], i8, i8, i8, i8, i8, i8, i8, i8 } - %struct.XXDMaterial = type { %struct.XXTColor4, %struct.XXTColor4, %struct.XXTColor4, %struct.XXTColor4, float, float, float, float, [8 x %struct.XXDLightProduct], %struct.XXTColor4, [8 x i32] } - %struct.XXDMinmax = type { %struct.XXDMinmaxTable*, i16, i8, i8, [0 x i32] } - %struct.XXDMinmaxTable = type { %struct.XXTColor4, %struct.XXTColor4 } - %struct.XXDMultisample = type { float, i8, i8, i8, i8, i8, i8, i8, i8 } - %struct.XXDPipelineProgramState = type { i8, i8, i8, i8, [0 x i32], %struct.XXTColor4* } - %struct.XXDPixelMap = type { i32*, float*, float*, float*, float*, float*, float*, float*, float*, i32*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } - %struct.XXDPixelMode = type { float, float, %struct.XXDPixelStore, %struct.XXDPixelTransfer, %struct.XXDPixelMap, %struct.XXDImagingSubset, i32, i32 } - %struct.XXDPixelPack = type { i32, i32, i32, i32, i32, i32, i32, i32, i8, i8, i8, i8 } - %struct.XXDPixelStore = type { %struct.XXDPixelPack, %struct.XXDPixelPack } - %struct.XXDPixelTransfer = type { float, float, float, float, float, float, float, float, float, float, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float } - %struct.XXDPointMode = type { float, float, float, float, %struct.XXTCoord3, float, i8, i8, i8, i8, i16, i16, i32, i16, i16 } - %struct.XXDPolygonMode = type { [128 x i8], float, float, i16, i16, i16, i16, i8, i8, i8, i8, i8, i8, i8, i8 } - %struct.XXDRegisterCombiners = type { i8, i8, i8, i8, i32, [2 x %struct.XXTColor4], [8 x %struct.XXDRegisterCombinersPerStageState], %struct.XXDRegisterCombinersFinalStageState } - %struct.XXDRegisterCombinersFinalStageState = type { i8, i8, i8, i8, [7 x %struct.XXDRegisterCombinersPerVariableState] } - %struct.XXDRegisterCombinersPerPortionState = type { [4 x %struct.XXDRegisterCombinersPerVariableState], i8, i8, i8, i8, i16, i16, i16, i16, i16, i16 } - %struct.XXDRegisterCombinersPerStageState = type { [2 x %struct.XXDRegisterCombinersPerPortionState], [2 x %struct.XXTColor4] } - %struct.XXDRegisterCombinersPerVariableState = type { i16, i16, i16, i16 } - %struct.XXDScissorTest = type { %struct.XXTFixedColor4, i8, i8, i8, i8 } - %struct.XXDState = type <{ i16, i16, i16, i16, i32, i32, [256 x %struct.XXTColor4], [128 x %struct.XXTColor4], %struct.XXDViewport, %struct.XXDTransform, %struct.XXDLightModel, %struct.XXDActiveTextureTargets, %struct.XXDAlphaTest, %struct.XXDBlendMode, %struct.XXDClearColor, %struct.XXDColorBuffer, %struct.XXDDepthTest, %struct.XXDArrayRange, %struct.XXDFogMode, %struct.XXDHintMode, %struct.XXDLineMode, %struct.XXDLogicOp, %struct.XXDMaskMode, %struct.XXDPixelMode, %struct.XXDPointMode, %struct.XXDPolygonMode, %struct.XXDScissorTest, i32, %struct.XXDStencilTest, [8 x %struct.XXDTextureMode], [16 x %struct.XXDTextureImageMode], %struct.XXDArrayRange, [8 x %struct.XXDTextureCoordGen], %struct.XXDClipPlane, %struct.XXDMultisample, %struct.XXDRegisterCombiners, %struct.XXDArrayRange, %struct.XXDArrayRange, [3 x %struct.XXDPipelineProgramState], %struct.XXDArrayRange, %struct.XXDTransformFeedback, i32*, %struct.XXDFixedFunction, [3 x i32], [2 x i32] }> - %struct.XXDStencilTest = type { [3 x { i32, i32, i16, i16, i16, i16 }], i32, [4 x i8] } - %struct.XXDTextureCoordGen = type { { i16, i16, %struct.XXTColor4, %struct.XXTColor4 }, { i16, i16, %struct.XXTColor4, %struct.XXTColor4 }, { i16, i16, %struct.XXTColor4, %struct.XXTColor4 }, { i16, i16, %struct.XXTColor4, %struct.XXTColor4 }, i8, i8, i8, i8 } - %struct.XXDTextureImageMode = type { float } - %struct.XXDTextureMode = type { %struct.XXTColor4, i32, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, float, float, i16, i16, i16, i16, i16, i16, [4 x i16], i8, i8, i8, i8, [3 x float], [4 x float], float, float } - %struct.XXDTextureRec = type opaque - %struct.XXDTransform = type <{ [24 x [16 x float]], [24 x [16 x float]], [16 x float], float, float, float, float, float, i8, i8, i8, i8, i32, i32, i32, i16, i16, i8, i8, i8, i8, i32 }> - %struct.XXDTransformFeedback = type { i8, i8, i8, i8, [0 x i32], [16 x i32], [16 x i32] } - %struct.XXDViewport = type { float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, double, double, i32, i32, i32, i32, float, float, float, float } - %struct.XXTColor4 = type { float, float, float, float } - %struct.XXTCoord3 = type { float, float, float } - %struct.XXTFixedColor4 = type { i32, i32, i32, i32 } - %struct.XXVMTextures = type { [16 x %struct.XXDTextureRec*] } - %struct.XXVMVPContext = type { i32 } - %struct.XXVMVPStack = type { i32, i32 } - %struct.YYToken = type { { i16, i16, i32 } } - %struct._XXVMConstants = type { <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, float, float, float, float, float, float, float, float, float, float, float, float, [256 x float], [4096 x i8], [8 x float], [48 x float], [128 x float], [528 x i8], { void (i8*, i8*, i32, i8*)*, float (float)*, float (float)*, float (float)*, i32 (float)* } } -@llvm.used = appending global [1 x i8*] [ i8* bitcast (void (%struct.XXDState*, <4 x float>*, <4 x float>**, %struct._XXVMConstants*, %struct.YYToken*, %struct.XXVMVPContext*, %struct.XXVMTextures*, %struct.XXVMVPStack*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, [4 x <4 x float>]*, i32*, <4 x i32>*, i64)* @t to i8*) ], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] - -define void @t(%struct.XXDState* %gldst, <4 x float>* %prgrm, <4 x float>** %buffs, %struct._XXVMConstants* %cnstn, %struct.YYToken* %pstrm, %struct.XXVMVPContext* %vmctx, %struct.XXVMTextures* %txtrs, %struct.XXVMVPStack* %vpstk, <4 x float>* %atr0, <4 x float>* %atr1, <4 x float>* %atr2, <4 x float>* %atr3, <4 x float>* %vtx0, <4 x float>* %vtx1, <4 x float>* %vtx2, <4 x float>* %vtx3, [4 x <4 x float>]* %tmpGbl, i32* %oldMsk, <4 x i32>* %adrGbl, i64 %key_token) nounwind { -entry: -; CHECK: t: - %0 = trunc i64 %key_token to i32 ; <i32> [#uses=1] - %1 = getelementptr %struct.YYToken* %pstrm, i32 %0 ; <%struct.YYToken*> [#uses=5] - br label %bb1132 - -bb51: ; preds = %bb1132 -; CHECK: .align 4 -; CHECK: xorl %ecx, %ecx -; CHECK: andl $7 - %2 = getelementptr %struct.YYToken* %1, i32 %operation.0.rec, i32 0, i32 0 ; <i16*> [#uses=1] - %3 = load i16* %2, align 1 ; <i16> [#uses=3] - %4 = lshr i16 %3, 6 ; <i16> [#uses=1] - %5 = trunc i16 %4 to i8 ; <i8> [#uses=1] - %6 = zext i8 %5 to i32 ; <i32> [#uses=1] - %7 = trunc i16 %3 to i8 ; <i8> [#uses=1] - %8 = and i8 %7, 7 ; <i8> [#uses=1] - %mask5556 = zext i8 %8 to i32 ; <i32> [#uses=3] - %.sum1324 = add i32 %mask5556, 2 ; <i32> [#uses=1] - %.rec = add i32 %operation.0.rec, %.sum1324 ; <i32> [#uses=1] - %9 = bitcast %struct.YYToken* %operation.0 to i32* ; <i32*> [#uses=1] - %10 = load i32* %9, align 1 ; <i32> [#uses=1] - %11 = lshr i32 %10, 16 ; <i32> [#uses=2] - %12 = trunc i32 %11 to i8 ; <i8> [#uses=1] - %13 = and i8 %12, 1 ; <i8> [#uses=1] - %14 = lshr i16 %3, 15 ; <i16> [#uses=1] - %15 = trunc i16 %14 to i8 ; <i8> [#uses=1] - %16 = or i8 %13, %15 ; <i8> [#uses=1] - %17 = icmp eq i8 %16, 0 ; <i1> [#uses=1] - br i1 %17, label %bb94, label %bb75 - -bb75: ; preds = %bb51 - %18 = getelementptr %struct.YYToken* %1, i32 0, i32 0, i32 0 ; <i16*> [#uses=1] - %19 = load i16* %18, align 4 ; <i16> [#uses=1] - %20 = load i16* null, align 2 ; <i16> [#uses=1] - %21 = zext i16 %19 to i64 ; <i64> [#uses=1] - %22 = zext i16 %20 to i64 ; <i64> [#uses=1] - %23 = shl i64 %22, 16 ; <i64> [#uses=1] - %.ins1177 = or i64 %23, %21 ; <i64> [#uses=1] - %.ins1175 = or i64 %.ins1177, 0 ; <i64> [#uses=1] - %24 = and i32 %11, 1 ; <i32> [#uses=1] - %.neg1333 = sub i32 %mask5556, %24 ; <i32> [#uses=1] - %.neg1335 = sub i32 %.neg1333, 0 ; <i32> [#uses=1] - %25 = sub i32 %.neg1335, 0 ; <i32> [#uses=1] - br label %bb94 - -bb94: ; preds = %bb75, %bb51 - %extraToken.0 = phi i64 [ %.ins1175, %bb75 ], [ %extraToken.1, %bb51 ] ; <i64> [#uses=1] - %argCount.0 = phi i32 [ %25, %bb75 ], [ %mask5556, %bb51 ] ; <i32> [#uses=1] - %operation.0.sum1392 = add i32 %operation.0.rec, 1 ; <i32> [#uses=2] - %26 = getelementptr %struct.YYToken* %1, i32 %operation.0.sum1392, i32 0, i32 0 ; <i16*> [#uses=1] - %27 = load i16* %26, align 4 ; <i16> [#uses=1] - %28 = getelementptr %struct.YYToken* %1, i32 %operation.0.sum1392, i32 0, i32 1 ; <i16*> [#uses=1] - %29 = load i16* %28, align 2 ; <i16> [#uses=1] - store i16 %27, i16* null, align 8 - store i16 %29, i16* null, align 2 - br i1 false, label %bb1132, label %bb110 - -bb110: ; preds = %bb94 - switch i32 %6, label %bb1078 [ - i32 30, label %bb960 - i32 32, label %bb801 - i32 38, label %bb809 - i32 78, label %bb1066 - ] - -bb801: ; preds = %bb110 - unreachable - -bb809: ; preds = %bb110 - unreachable - -bb960: ; preds = %bb110 - %30 = icmp eq i32 %argCount.0, 1 ; <i1> [#uses=1] - br i1 %30, label %bb962, label %bb965 - -bb962: ; preds = %bb960 - unreachable - -bb965: ; preds = %bb960 - unreachable - -bb1066: ; preds = %bb110 - unreachable - -bb1078: ; preds = %bb110 - unreachable - -bb1132: ; preds = %bb94, %entry - %extraToken.1 = phi i64 [ undef, %entry ], [ %extraToken.0, %bb94 ] ; <i64> [#uses=1] - %operation.0.rec = phi i32 [ 0, %entry ], [ %.rec, %bb94 ] ; <i32> [#uses=4] - %operation.0 = getelementptr %struct.YYToken* %1, i32 %operation.0.rec ; <%struct.YYToken*> [#uses=1] - br i1 false, label %bb1134, label %bb51 - -bb1134: ; preds = %bb1132 - ret void -} diff --git a/test/CodeGen/X86/2009-01-12-CoalescerBug.ll b/test/CodeGen/X86/2009-01-12-CoalescerBug.ll deleted file mode 100644 index 27a7113..0000000 --- a/test/CodeGen/X86/2009-01-12-CoalescerBug.ll +++ /dev/null @@ -1,84 +0,0 @@ -; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | grep movq | count 2 -; PR3311 - - %struct.CUMULATIVE_ARGS = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } - %struct.VEC_basic_block_base = type { i32, i32, [1 x %struct.basic_block_def*] } - %struct.VEC_basic_block_gc = type { %struct.VEC_basic_block_base } - %struct.VEC_edge_base = type { i32, i32, [1 x %struct.edge_def*] } - %struct.VEC_edge_gc = type { %struct.VEC_edge_base } - %struct.VEC_rtx_base = type { i32, i32, [1 x %struct.rtx_def*] } - %struct.VEC_rtx_gc = type { %struct.VEC_rtx_base } - %struct.VEC_temp_slot_p_base = type { i32, i32, [1 x %struct.temp_slot*] } - %struct.VEC_temp_slot_p_gc = type { %struct.VEC_temp_slot_p_base } - %struct.VEC_tree_base = type { i32, i32, [1 x %struct.tree_node*] } - %struct.VEC_tree_gc = type { %struct.VEC_tree_base } - %struct._obstack_chunk = type { i8*, %struct._obstack_chunk*, [4 x i8] } - %struct.basic_block_def = type { %struct.tree_node*, %struct.VEC_edge_gc*, %struct.VEC_edge_gc*, i8*, %struct.loop*, [2 x %struct.et_node*], %struct.basic_block_def*, %struct.basic_block_def*, %struct.basic_block_il_dependent, %struct.tree_node*, %struct.edge_prediction*, i64, i32, i32, i32, i32 } - %struct.basic_block_il_dependent = type { %struct.rtl_bb_info* } - %struct.bitmap_element_def = type { %struct.bitmap_element_def*, %struct.bitmap_element_def*, i32, [2 x i64] } - %struct.bitmap_head_def = type { %struct.bitmap_element_def*, %struct.bitmap_element_def*, i32, %struct.bitmap_obstack* } - %struct.bitmap_obstack = type { %struct.bitmap_element_def*, %struct.bitmap_head_def*, %struct.obstack } - %struct.block_symbol = type { [3 x %struct.rtunion], %struct.object_block*, i64 } - %struct.c_arg_info = type { %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, i8 } - %struct.c_language_function = type { %struct.stmt_tree_s } - %struct.c_switch = type opaque - %struct.control_flow_graph = type { %struct.basic_block_def*, %struct.basic_block_def*, %struct.VEC_basic_block_gc*, i32, i32, i32, %struct.VEC_basic_block_gc*, i32 } - %struct.edge_def = type { %struct.basic_block_def*, %struct.basic_block_def*, %struct.edge_def_insns, i8*, %struct.location_t*, i32, i32, i64, i32 } - %struct.edge_def_insns = type { %struct.rtx_def* } - %struct.edge_prediction = type opaque - %struct.eh_status = type opaque - %struct.emit_status = type { i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.sequence_stack*, i32, %struct.location_t, i32, i8*, %struct.rtx_def** } - %struct.et_node = type opaque - %struct.expr_status = type { i32, i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def* } - %struct.function = type { %struct.eh_status*, %struct.expr_status*, %struct.emit_status*, %struct.varasm_status*, %struct.control_flow_graph*, %struct.tree_node*, %struct.function*, i32, i32, i32, i32, %struct.rtx_def*, %struct.CUMULATIVE_ARGS, %struct.rtx_def*, %struct.rtx_def*, %struct.initial_value_struct*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, i8, i32, i64, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, %struct.VEC_temp_slot_p_gc*, %struct.temp_slot*, %struct.var_refs_queue*, i32, i32, i32, i32, %struct.machine_function*, i32, i32, %struct.language_function*, %struct.htab*, %struct.rtx_def*, i32, i32, i32, %struct.location_t, %struct.VEC_tree_gc*, %struct.tree_node*, i8*, i8*, i8*, i8*, i8*, %struct.tree_node*, i8, i8, i8, i8, i8, i8 } - %struct.htab = type { i32 (i8*)*, i32 (i8*, i8*)*, void (i8*)*, i8**, i64, i64, i64, i32, i32, i8* (i64, i64)*, void (i8*)*, i8*, i8* (i8*, i64, i64)*, void (i8*, i8*)*, i32 } - %struct.initial_value_struct = type opaque - %struct.lang_decl = type { i8 } - %struct.language_function = type { %struct.c_language_function, %struct.tree_node*, %struct.tree_node*, %struct.c_switch*, %struct.c_arg_info*, i32, i32, i32, i32 } - %struct.location_t = type { i8*, i32 } - %struct.loop = type opaque - %struct.machine_function = type { %struct.stack_local_entry*, i8*, %struct.rtx_def*, i32, i32, [4 x i32], i32, i32, i32 } - %struct.object_block = type { %struct.section*, i32, i64, %struct.VEC_rtx_gc*, %struct.VEC_rtx_gc* } - %struct.obstack = type { i64, %struct._obstack_chunk*, i8*, i8*, i8*, i64, i32, %struct._obstack_chunk* (i8*, i64)*, void (i8*, %struct._obstack_chunk*)*, i8*, i8 } - %struct.omp_clause_subcode = type { i32 } - %struct.rtl_bb_info = type { %struct.rtx_def*, %struct.rtx_def*, %struct.bitmap_head_def*, %struct.bitmap_head_def*, %struct.rtx_def*, %struct.rtx_def*, i32 } - %struct.rtunion = type { i8* } - %struct.rtx_def = type { i16, i8, i8, %struct.u } - %struct.section = type { %struct.unnamed_section } - %struct.sequence_stack = type { %struct.rtx_def*, %struct.rtx_def*, %struct.sequence_stack* } - %struct.stack_local_entry = type opaque - %struct.stmt_tree_s = type { %struct.tree_node*, i32 } - %struct.temp_slot = type opaque - %struct.tree_common = type { %struct.tree_node*, %struct.tree_node*, %union.tree_ann_d*, i8, i8, i8, i8, i8 } - %struct.tree_decl_common = type { %struct.tree_decl_minimal, %struct.tree_node*, i8, i8, i8, i8, i8, i32, i32, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, i64, %struct.lang_decl* } - %struct.tree_decl_minimal = type { %struct.tree_common, %struct.location_t, i32, %struct.tree_node*, %struct.tree_node* } - %struct.tree_decl_non_common = type { %struct.tree_decl_with_vis, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node* } - %struct.tree_decl_with_rtl = type { %struct.tree_decl_common, %struct.rtx_def*, i32 } - %struct.tree_decl_with_vis = type { %struct.tree_decl_with_rtl, %struct.tree_node*, %struct.tree_node*, i8, i8, i8, i8 } - %struct.tree_function_decl = type { %struct.tree_decl_non_common, i32, i8, i8, i64, %struct.function* } - %struct.tree_node = type { %struct.tree_function_decl } - %struct.u = type { %struct.block_symbol } - %struct.unnamed_section = type { %struct.omp_clause_subcode, void (i8*)*, i8*, %struct.section* } - %struct.var_refs_queue = type { %struct.rtx_def*, i32, i32, %struct.var_refs_queue* } - %struct.varasm_status = type opaque - %union.tree_ann_d = type opaque -@.str1 = external constant [31 x i8] ; <[31 x i8]*> [#uses=1] -@integer_types = external global [11 x %struct.tree_node*] ; <[11 x %struct.tree_node*]*> [#uses=1] -@__FUNCTION__.31164 = external constant [23 x i8], align 16 ; <[23 x i8]*> [#uses=1] -@llvm.used = appending global [1 x i8*] [ i8* bitcast (i32 (i32, i32)* @c_common_type_for_size to i8*) ], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] - -define i32 @c_common_type_for_size(i32 %bits, i32 %unsignedp) nounwind { -entry: - %0 = load %struct.tree_node** getelementptr ([11 x %struct.tree_node*]* @integer_types, i32 0, i64 5), align 8 ; <%struct.tree_node*> [#uses=1] - br i1 false, label %bb16, label %bb - -bb: ; preds = %entry - tail call void @tree_class_check_failed(%struct.tree_node* %0, i32 2, i8* getelementptr ([31 x i8]* @.str1, i32 0, i64 0), i32 1785, i8* getelementptr ([23 x i8]* @__FUNCTION__.31164, i32 0, i32 0)) noreturn nounwind - unreachable - -bb16: ; preds = %entry - %tmp = add i32 %bits, %unsignedp ; <i32> [#uses=1] - ret i32 %tmp -} - -declare void @tree_class_check_failed(%struct.tree_node*, i32, i8*, i32, i8*) noreturn diff --git a/test/CodeGen/X86/2009-01-29-LocalRegAllocBug.ll b/test/CodeGen/X86/2009-01-29-LocalRegAllocBug.ll index 21b43fb..35fac0c 100644 --- a/test/CodeGen/X86/2009-01-29-LocalRegAllocBug.ll +++ b/test/CodeGen/X86/2009-01-29-LocalRegAllocBug.ll @@ -1,4 +1,3 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin9.6 -regalloc=local -disable-fp-elim ; RUN: llc < %s -mtriple=i386-apple-darwin9.6 -regalloc=fast -disable-fp-elim ; rdar://6538384 diff --git a/test/CodeGen/X86/2009-04-14-IllegalRegs.ll b/test/CodeGen/X86/2009-04-14-IllegalRegs.ll index e5d46f9..bed863e 100644 --- a/test/CodeGen/X86/2009-04-14-IllegalRegs.ll +++ b/test/CodeGen/X86/2009-04-14-IllegalRegs.ll @@ -1,4 +1,3 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin -O0 -regalloc=local | not grep sil ; RUN: llc < %s -mtriple=i386-apple-darwin -O0 -regalloc=fast | not grep sil ; rdar://6787136 diff --git a/test/CodeGen/X86/2009-04-20-LinearScanOpt.ll b/test/CodeGen/X86/2009-04-20-LinearScanOpt.ll index d7b9463..fcb2ed0 100644 --- a/test/CodeGen/X86/2009-04-20-LinearScanOpt.ll +++ b/test/CodeGen/X86/2009-04-20-LinearScanOpt.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin10.0 -relocation-model=pic -disable-fp-elim -stats |& grep asm-printer | grep 83 +; RUN: llc < %s -mtriple=x86_64-apple-darwin10.0 -relocation-model=pic -disable-fp-elim -stats |& grep asm-printer | grep 82 ; rdar://6802189 ; Test if linearscan is unfavoring registers for allocation to allow more reuse diff --git a/test/CodeGen/X86/2009-04-24.ll b/test/CodeGen/X86/2009-04-24.ll index c1ec45f..757042e 100644 --- a/test/CodeGen/X86/2009-04-24.ll +++ b/test/CodeGen/X86/2009-04-24.ll @@ -1,6 +1,4 @@ -; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu -regalloc=local -relocation-model=pic > %t -; RUN: grep {leal.*TLSGD.*___tls_get_addr} %t -; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu -regalloc=local -relocation-model=pic > %t2 +; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu -regalloc=fast -relocation-model=pic > %t2 ; RUN: grep {leaq.*TLSGD.*__tls_get_addr} %t2 ; PR4004 diff --git a/test/CodeGen/X86/2009-08-23-linkerprivate.ll b/test/CodeGen/X86/2009-08-23-linkerprivate.ll index 3da8f00..90fac15 100644 --- a/test/CodeGen/X86/2009-08-23-linkerprivate.ll +++ b/test/CodeGen/X86/2009-08-23-linkerprivate.ll @@ -2,7 +2,7 @@ ; ModuleID = '/Volumes/MacOS9/tests/WebKit/JavaScriptCore/profiler/ProfilerServer.mm' -@"\01l_objc_msgSend_fixup_alloc" = linker_private hidden global i32 0, section "__DATA, __objc_msgrefs, coalesced", align 16 ; <i32*> [#uses=0] +@"\01l_objc_msgSend_fixup_alloc" = linker_private_weak hidden global i32 0, section "__DATA, __objc_msgrefs, coalesced", align 16 ; CHECK: .globl l_objc_msgSend_fixup_alloc ; CHECK: .weak_definition l_objc_msgSend_fixup_alloc diff --git a/test/CodeGen/X86/2009-09-07-CoalescerBug.ll b/test/CodeGen/X86/2009-09-07-CoalescerBug.ll deleted file mode 100644 index 41b4bc0..0000000 --- a/test/CodeGen/X86/2009-09-07-CoalescerBug.ll +++ /dev/null @@ -1,47 +0,0 @@ -; RUN: llc < %s -mtriple=x86_64-unknown-freebsd7.2 -code-model=kernel | FileCheck %s -; PR4689 - -%struct.__s = type { [8 x i8] } -%struct.pcb = type { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i16, i8* } -%struct.pcpu = type { i32*, i32*, i32*, i32*, %struct.pcb*, i64, i32, i32, i32, i32 } - -define i64 @hammer_time(i64 %modulep, i64 %physfree) nounwind ssp noredzone noimplicitfloat { -; CHECK: hammer_time: -; CHECK: movq $Xrsvd, %rax -; CHECK: movq $Xrsvd, %rcx -entry: - br i1 undef, label %if.then, label %if.end - -if.then: ; preds = %entry - br label %if.end - -if.end: ; preds = %if.then, %entry - br label %for.body - -for.body: ; preds = %for.inc, %if.end - switch i32 undef, label %if.then76 [ - i32 9, label %for.inc - i32 10, label %for.inc - i32 11, label %for.inc - i32 12, label %for.inc - ] - -if.then76: ; preds = %for.body - unreachable - -for.inc: ; preds = %for.body, %for.body, %for.body, %for.body - br i1 undef, label %for.end, label %for.body - -for.end: ; preds = %for.inc - call void asm sideeffect "mov $1,%gs:$0", "=*m,r,~{dirflag},~{fpsr},~{flags}"(%struct.__s* bitcast (%struct.pcb** getelementptr (%struct.pcpu* null, i32 0, i32 4) to %struct.__s*), i64 undef) nounwind - br label %for.body170 - -for.body170: ; preds = %for.body170, %for.end - store i64 or (i64 and (i64 or (i64 ptrtoint (void (i32, i32, i32, i32)* @Xrsvd to i64), i64 2097152), i64 2162687), i64 or (i64 or (i64 and (i64 shl (i64 ptrtoint (void (i32, i32, i32, i32)* @Xrsvd to i64), i64 32), i64 -281474976710656), i64 140737488355328), i64 15393162788864)), i64* undef - br i1 undef, label %for.end175, label %for.body170 - -for.end175: ; preds = %for.body170 - unreachable -} - -declare void @Xrsvd(i32, i32, i32, i32) ssp noredzone noimplicitfloat diff --git a/test/CodeGen/X86/2009-09-19-SchedCustomLoweringBug.ll b/test/CodeGen/X86/2009-09-19-SchedCustomLoweringBug.ll deleted file mode 100644 index 8cb538b..0000000 --- a/test/CodeGen/X86/2009-09-19-SchedCustomLoweringBug.ll +++ /dev/null @@ -1,29 +0,0 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin10 -post-RA-scheduler=true | FileCheck %s - -; PR4958 - -define i32 @main() nounwind ssp { -entry: -; CHECK: main: - %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] - br label %bb - -bb: ; preds = %bb1, %entry -; CHECK: addl $1 -; CHECK-NEXT: movl %e -; CHECK-NEXT: adcl $0 - %i.0 = phi i64 [ 0, %entry ], [ %0, %bb1 ] ; <i64> [#uses=1] - %0 = add nsw i64 %i.0, 1 ; <i64> [#uses=2] - %1 = icmp sgt i32 0, 0 ; <i1> [#uses=1] - br i1 %1, label %bb2, label %bb1 - -bb1: ; preds = %bb - %2 = icmp sle i64 %0, 1 ; <i1> [#uses=1] - br i1 %2, label %bb, label %bb2 - -bb2: ; preds = %bb1, %bb - br label %return - -return: ; preds = %bb2 - ret i32 0 -} diff --git a/test/CodeGen/X86/2009-12-12-CoalescerBug.ll b/test/CodeGen/X86/2009-12-12-CoalescerBug.ll deleted file mode 100644 index 4e8f5fd..0000000 --- a/test/CodeGen/X86/2009-12-12-CoalescerBug.ll +++ /dev/null @@ -1,40 +0,0 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin | FileCheck %s - -define i32 @do_loop(i32* nocapture %sdp, i32* nocapture %ddp, i8* %mdp, i8* nocapture %cdp, i32 %w) nounwind readonly optsize ssp { -entry: - br label %bb - -bb: ; preds = %bb5, %entry - %mask.1.in = load i8* undef, align 1 ; <i8> [#uses=3] - %0 = icmp eq i8 %mask.1.in, 0 ; <i1> [#uses=1] - br i1 %0, label %bb5, label %bb1 - -bb1: ; preds = %bb - br i1 undef, label %bb2, label %bb3 - -bb2: ; preds = %bb1 -; CHECK: %bb2 -; CHECK: movb %ch, %al - %1 = zext i8 %mask.1.in to i32 ; <i32> [#uses=1] - %2 = zext i8 undef to i32 ; <i32> [#uses=1] - %3 = mul i32 %2, %1 ; <i32> [#uses=1] - %4 = add i32 %3, 1 ; <i32> [#uses=1] - %5 = add i32 %4, 0 ; <i32> [#uses=1] - %6 = lshr i32 %5, 8 ; <i32> [#uses=1] - %retval12.i = trunc i32 %6 to i8 ; <i8> [#uses=1] - br label %bb3 - -bb3: ; preds = %bb2, %bb1 - %mask.0.in = phi i8 [ %retval12.i, %bb2 ], [ %mask.1.in, %bb1 ] ; <i8> [#uses=1] - %7 = icmp eq i8 %mask.0.in, 0 ; <i1> [#uses=1] - br i1 %7, label %bb5, label %bb4 - -bb4: ; preds = %bb3 - br label %bb5 - -bb5: ; preds = %bb4, %bb3, %bb - br i1 undef, label %bb6, label %bb - -bb6: ; preds = %bb5 - ret i32 undef -} diff --git a/test/CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll b/test/CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll index eb21dc2..7325f4a 100644 --- a/test/CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll +++ b/test/CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll @@ -9,11 +9,11 @@ ; lowering of arguments potentially overwrites the value. ; ; Move return address (76(%esp)) to a temporary register (%ebp) -; CHECK: movl 76(%esp), %ebp +; CHECK: movl 76(%esp), [[REGISTER:%[a-z]+]] ; Overwrite return addresss -; CHECK: movl %ecx, 76(%esp) +; CHECK: movl %ebx, 76(%esp) ; Move return address from temporary register (%ebp) to new stack location (60(%esp)) -; CHECK: movl %ebp, 60(%esp) +; CHECK: movl [[REGISTER]], 60(%esp) %tupl_p = type [9 x i32]* diff --git a/test/CodeGen/X86/2010-03-17-ISelBug.ll b/test/CodeGen/X86/2010-03-17-ISelBug.ll index 609b4e2..ba21902 100644 --- a/test/CodeGen/X86/2010-03-17-ISelBug.ll +++ b/test/CodeGen/X86/2010-03-17-ISelBug.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -mtriple=i386-apple-darwin5 + ; rdar://7761790 %"struct..0$_485" = type { i16, i16, i32 } @@ -37,3 +38,30 @@ bb169: ; preds = %bb169, %bb.nph380 %4 = add nsw i32 %index.6379, 1 ; <i32> [#uses=1] br label %bb169 } + +; PR7368 + +%struct.bufBit_s = type { i8*, i8 } + +define fastcc void @printSwipe([2 x [256 x %struct.bufBit_s]]* nocapture %colourLines) nounwind { +entry: + br label %for.body190 + +for.body261.i: ; preds = %for.body261.i, %for.body190 + %line.3300.i = phi i32 [ undef, %for.body190 ], [ %add292.i, %for.body261.i ] ; <i32> [#uses=3] + %conv268.i = and i32 %line.3300.i, 255 ; <i32> [#uses=1] + %tmp278.i = getelementptr [2 x [256 x %struct.bufBit_s]]* %colourLines, i32 undef, i32 %pen.1100, i32 %conv268.i, i32 0 ; <i8**> [#uses=1] + store i8* undef, i8** %tmp278.i + %tmp338 = shl i32 %line.3300.i, 3 ; <i32> [#uses=1] + %tmp339 = and i32 %tmp338, 2040 ; <i32> [#uses=1] + %tmp285.i = getelementptr i8* %scevgep328, i32 %tmp339 ; <i8*> [#uses=1] + store i8 undef, i8* %tmp285.i + %add292.i = add nsw i32 0, %line.3300.i ; <i32> [#uses=1] + br i1 undef, label %for.body190, label %for.body261.i + +for.body190: ; preds = %for.body261.i, %for.body190, %bb.nph104 + %pen.1100 = phi i32 [ 0, %entry ], [ %inc230, %for.body261.i ], [ %inc230, %for.body190 ] ; <i32> [#uses=3] + %scevgep328 = getelementptr [2 x [256 x %struct.bufBit_s]]* %colourLines, i32 undef, i32 %pen.1100, i32 0, i32 1 ; <i8*> [#uses=1] + %inc230 = add i32 %pen.1100, 1 ; <i32> [#uses=2] + br i1 undef, label %for.body190, label %for.body261.i +} diff --git a/test/CodeGen/X86/2010-04-30-LocalAlloc-LandingPad.ll b/test/CodeGen/X86/2010-04-30-LocalAlloc-LandingPad.ll index 4c95179..e20f1d8 100644 --- a/test/CodeGen/X86/2010-04-30-LocalAlloc-LandingPad.ll +++ b/test/CodeGen/X86/2010-04-30-LocalAlloc-LandingPad.ll @@ -1,4 +1,3 @@ -; RUN: llc < %s -O0 -regalloc=local -relocation-model=pic -disable-fp-elim | FileCheck %s ; RUN: llc < %s -O0 -regalloc=fast -relocation-model=pic -disable-fp-elim | FileCheck %s target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32" target triple = "i386-apple-darwin10.0.0" diff --git a/test/CodeGen/X86/2010-05-05-LocalAllocEarlyClobber.ll b/test/CodeGen/X86/2010-05-05-LocalAllocEarlyClobber.ll index 375f424..74a5ec2 100644 --- a/test/CodeGen/X86/2010-05-05-LocalAllocEarlyClobber.ll +++ b/test/CodeGen/X86/2010-05-05-LocalAllocEarlyClobber.ll @@ -1,4 +1,3 @@ -; RUN-XFAIL: llc < %s -O0 -regalloc=local | FileCheck %s ; RUN: llc < %s -O0 -regalloc=fast | FileCheck %s ; PR6520 diff --git a/test/CodeGen/X86/2010-05-06-LocalInlineAsmClobber.ll b/test/CodeGen/X86/2010-05-06-LocalInlineAsmClobber.ll index e554f9f..90eb84d 100644 --- a/test/CodeGen/X86/2010-05-06-LocalInlineAsmClobber.ll +++ b/test/CodeGen/X86/2010-05-06-LocalInlineAsmClobber.ll @@ -1,4 +1,3 @@ -; RUN: llc -regalloc=local %s -o %t ; RUN: llc -regalloc=fast %s -o %t ; PR7066 diff --git a/test/CodeGen/X86/2010-06-09-FastAllocRegisters.ll b/test/CodeGen/X86/2010-06-09-FastAllocRegisters.ll new file mode 100644 index 0000000..7c7792a --- /dev/null +++ b/test/CodeGen/X86/2010-06-09-FastAllocRegisters.ll @@ -0,0 +1,17 @@ +; RUN: llc < %s -O0 -disable-fp-elim -relocation-model=pic +; PR7313 +; +; The inline asm in this function clobbers almost all allocatable registers. +; Make sure that the register allocator recovers. +; +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-unknown-linux-gnu" + +declare void @snapshot() + +define void @test_too_many_longs() nounwind { +entry: + call void asm sideeffect "xor %rax, %rax\0A\09xor %rbx, %rbx\0A\09xor %rcx, %rcx\0A\09xor %rdx, %rdx\0A\09xor %rsi, %rsi\0A\09xor %rdi, %rdi\0A\09xor %r8, %r8\0A\09xor %r9, %r9\0A\09xor %r10, %r10\0A\09xor %r11, %r11\0A\09xor %r12, %r12\0A\09xor %r13, %r13\0A\09xor %r14, %r14\0A\09xor %r15, %r15\0A\09", "~{fpsr},~{flags},~{r15},~{r14},~{r13},~{r12},~{r11},~{r10},~{r9},~{r8},~{rdi},~{rsi},~{rdx},~{rcx},~{rbx},~{rax}"() nounwind + call void bitcast (void ()* @snapshot to void (i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64)*)(i64 32, i64 33, i64 34, i64 35, i64 36, i64 37, i64 38, i64 39, i64 40, i64 41, i64 42, i64 43) nounwind + ret void +} diff --git a/test/CodeGen/X86/2010-06-14-fast-isel-fs-load.ll b/test/CodeGen/X86/2010-06-14-fast-isel-fs-load.ll new file mode 100644 index 0000000..b22a391 --- /dev/null +++ b/test/CodeGen/X86/2010-06-14-fast-isel-fs-load.ll @@ -0,0 +1,6 @@ +; RUN: llc -fast-isel -march=x86 < %s | grep %fs: + +define i32 @test1(i32 addrspace(257)* %arg) nounwind { + %tmp = load i32 addrspace(257)* %arg + ret i32 %tmp +} diff --git a/test/CodeGen/X86/2010-06-15-FastAllocEarlyCLobber.ll b/test/CodeGen/X86/2010-06-15-FastAllocEarlyCLobber.ll new file mode 100644 index 0000000..4639866 --- /dev/null +++ b/test/CodeGen/X86/2010-06-15-FastAllocEarlyCLobber.ll @@ -0,0 +1,29 @@ +; RUN: llc -regalloc=fast < %s | FileCheck %s +; PR7382 +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-unknown-linux-gnu" + +@.str = private constant [23 x i8] c"This should be -1: %d\0A\00" ; <[23 x i8]*> [#uses=1] + +define i32 @main() { +entry: + %retval = alloca i32, align 4 ; <i32*> [#uses=3] + %v = alloca i32, align 4 ; <i32*> [#uses=3] + store i32 0, i32* %retval + %zero = load i32* %retval +; The earlyclobber register EC0 should not be spilled before the inline asm. +; Yes, check-not can refer to FileCheck variables defined in the future. +; CHECK-NOT: [[EC0]]{{.*}}(%rsp) +; CHECK: bsr {{[^,]*}}, [[EC0:%...]] + %0 = call i32 asm "bsr $1, $0\0A\09cmovz $2, $0", "=&r,ro,r,~{cc},~{dirflag},~{fpsr},~{flags}"(i32 %zero, i32 -1) nounwind, !srcloc !0 ; <i32> [#uses=1] + store i32 %0, i32* %v + %tmp = load i32* %v ; <i32> [#uses=1] + %call1 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([23 x i8]* @.str, i32 0, i32 0), i32 %tmp) ; <i32> [#uses=0] + store i32 0, i32* %retval + %1 = load i32* %retval ; <i32> [#uses=1] + ret i32 %0 +} + +declare i32 @printf(i8*, ...) + +!0 = metadata !{i32 191} diff --git a/test/CodeGen/X86/2010-06-24-g-constraint-crash.ll b/test/CodeGen/X86/2010-06-24-g-constraint-crash.ll new file mode 100644 index 0000000..2a938d9 --- /dev/null +++ b/test/CodeGen/X86/2010-06-24-g-constraint-crash.ll @@ -0,0 +1,15 @@ +; RUN: llc %s -mtriple=x86_64-apple-darwin10 -disable-fp-elim -o /dev/null +; Formerly crashed, rdar://8015842 + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" + +%0 = type { i64, i64, i64, i64, i64 } + +@utcbs.1559 = internal global [3 x i64] zeroinitializer ; <[3 x i64]*> [#uses=1] + +define void @bar() nounwind ssp { +entry: + %asmtmp.i.i = tail call %0 asm sideeffect "push %rbp; syscall; pop %rbp\0A", "={ax},={di},={si},={dx},={bx},{ax},{di},{si},{dx},{bx},~{dirflag},~{fpsr},~{flags},~{memory},~{r15},~{r14},~{r13},~{r12},~{r11},~{r10},~{r9},~{r8},~{rcx}"(i32 7, i64 -1, i64 0, i64 -1, i64 -1) nounwind ; <%0> [#uses=0] + %asmtmp.i1.i = tail call %0 asm sideeffect "mov $10, %r8;\0Amov $11, %r9;\0Amov $12, %r10;\0Apush %rbp; syscall; pop %rbp\0A", "={ax},={di},={si},={dx},={bx},{ax},{di},{si},{dx},{bx},imr,imr,imr,~{dirflag},~{fpsr},~{flags},~{memory},~{r15},~{r14},~{r13},~{r12},~{r11},~{r10},~{r9},~{r8},~{rcx}"(i32 8, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 0, i8* bitcast (i64* getelementptr inbounds ([3 x i64]* @utcbs.1559, i64 0, i64 2) to i8*)) nounwind ; <%0> [#uses=0] + ret void +} diff --git a/test/CodeGen/X86/2010-06-25-CoalescerSubRegDefDead.ll b/test/CodeGen/X86/2010-06-25-CoalescerSubRegDefDead.ll new file mode 100644 index 0000000..c6421a2 --- /dev/null +++ b/test/CodeGen/X86/2010-06-25-CoalescerSubRegDefDead.ll @@ -0,0 +1,39 @@ +; RUN: llc -O1 -mtriple=x86_64-apple-darwin10 -relocation-model=pic -disable-fp-elim < %s | FileCheck %s +; <rdar://problem/8124405> + +%struct.type = type { %struct.subtype*, i32, i8, i32, i8, i32, i32, i32, i32, i32, i8, i32, i32, i32, i32, i32, [256 x i32], i32, [257 x i32], [257 x i32], i32*, i16*, i8*, i32, i32, i32, i32, i32, [256 x i8], [16 x i8], [256 x i8], [4096 x i8], [16 x i32], [18002 x i8], [18002 x i8], [6 x [258 x i8]], [6 x [258 x i32]], [6 x [258 x i32]], [6 x [258 x i32]], [6 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32*, i32*, i32* } +%struct.subtype = type { i8*, i32, i32, i32, i8*, i32, i32, i32, i8*, i8* (i8*, i32, i32)*, void (i8*, i8*)*, i8* } + +define i32 @func(%struct.type* %s) nounwind optsize ssp { +entry: + %tmp1 = getelementptr inbounds %struct.type* %s, i32 0, i32 1 + %tmp2 = load i32* %tmp1, align 8 + %tmp3 = icmp eq i32 %tmp2, 10 + %tmp4 = getelementptr inbounds %struct.type* %s, i32 0, i32 40 + br i1 %tmp3, label %bb, label %entry.bb1_crit_edge + +entry.bb1_crit_edge: + br label %bb1 + +bb: + +; The point of this code is that %rdi is set to %rdi+64036 for the rep;stosl +; statement. It can be an ADD or LEA instruction, it's not important which one +; it is. +; +; CHECK: ## %bb +; CHECK-NEXT: addq $64036, %rdi +; CHECK: rep;stosl + + %tmp5 = bitcast i32* %tmp4 to i8* + call void @llvm.memset.p0i8.i64(i8* %tmp5, i8 0, i64 84, i32 4, i1 false) + %tmp6 = getelementptr inbounds %struct.type* %s, i32 0, i32 62 + store i32* null, i32** %tmp6, align 8 + br label %bb1 + +bb1: + store i32 10, i32* %tmp1, align 8 + ret i32 42 +} + +declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind diff --git a/test/CodeGen/X86/2010-06-25-asm-RA-crash.ll b/test/CodeGen/X86/2010-06-25-asm-RA-crash.ll new file mode 100644 index 0000000..68a6a13 --- /dev/null +++ b/test/CodeGen/X86/2010-06-25-asm-RA-crash.ll @@ -0,0 +1,19 @@ +; RUN: llc < %s -disable-fp-elim -mtriple=i686-pc-mingw32 + +%struct.__SEH2Frame = type {} + +define void @_SEH2FrameHandler() nounwind { +entry: + %target.addr.i = alloca i8*, align 4 ; <i8**> [#uses=2] + %frame = alloca %struct.__SEH2Frame*, align 4 ; <%struct.__SEH2Frame**> [#uses=1] + %tmp = load %struct.__SEH2Frame** %frame ; <%struct.__SEH2Frame*> [#uses=1] + %conv = bitcast %struct.__SEH2Frame* %tmp to i8* ; <i8*> [#uses=1] + store i8* %conv, i8** %target.addr.i + %tmp.i = load i8** %target.addr.i ; <i8*> [#uses=1] + call void asm sideeffect "push %ebp\0Apush $$0\0Apush $$0\0Apush $$Return${:uid}\0Apush $0\0Acall ${1:c}\0AReturn${:uid}: pop %ebp\0A", "imr,imr,~{ax},~{bx},~{cx},~{dx},~{si},~{di},~{flags},~{memory},~{dirflag},~{fpsr},~{flags}"(i8* %tmp.i, void (...)* @RtlUnwind) nounwind, !srcloc !0 + ret void +} + +declare x86_stdcallcc void @RtlUnwind(...) + +!0 = metadata !{i32 215} diff --git a/test/CodeGen/X86/2010-06-28-FastAllocTiedOperand.ll b/test/CodeGen/X86/2010-06-28-FastAllocTiedOperand.ll new file mode 100644 index 0000000..e1491a0 --- /dev/null +++ b/test/CodeGen/X86/2010-06-28-FastAllocTiedOperand.ll @@ -0,0 +1,22 @@ +; RUN: llc < %s -march=x86 -O0 | FileCheck %s +; PR7509 +target triple = "i386-apple-darwin10" +%asmtype = type { i32, i8*, i32, i32 } + +; Arguments 1 and 4 must be the same. No other output arguments may be +; allocated %eax. + +; CHECK: InlineAsm Start +; CHECK: arg1 %[[A1:...]] +; CHECK-NOT: ax +; CHECK: arg4 %[[A1]] +; CHECK: InlineAsm End + +define i32 @func(i8* %s) nounwind ssp { +entry: + %0 = tail call %asmtype asm "arg0 $0\0A\09arg1 $1\0A\09arg2 $2\0A\09arg3 $3\0A\09arg4 $4", "={ax},=r,=r,=r,1,~{dirflag},~{fpsr},~{flags}"(i8* %s) nounwind, !srcloc !0 ; <%0> [#uses=1] + %asmresult = extractvalue %asmtype %0, 0 ; <i64> [#uses=1] + ret i32 %asmresult +} + +!0 = metadata !{i32 108} diff --git a/test/CodeGen/X86/2010-06-28-matched-g-constraint.ll b/test/CodeGen/X86/2010-06-28-matched-g-constraint.ll new file mode 100644 index 0000000..82dac9d --- /dev/null +++ b/test/CodeGen/X86/2010-06-28-matched-g-constraint.ll @@ -0,0 +1,11 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin11 | FileCheck %s +; Any register is OK for %0, but it must be a register, not memory. + +define i32 @foo() nounwind ssp { +entry: +; CHECK: GCROOT %eax + %_r = alloca i32, align 4 ; <i32*> [#uses=2] + call void asm "/* GCROOT $0 */", "=*imr,0,~{dirflag},~{fpsr},~{flags}"(i32* %_r, i32 4) nounwind + %0 = load i32* %_r, align 4 ; <i32> [#uses=1] + ret i32 %0 +} diff --git a/test/CodeGen/X86/2010-07-02-UnfoldBug.ll b/test/CodeGen/X86/2010-07-02-UnfoldBug.ll new file mode 100644 index 0000000..79219dc --- /dev/null +++ b/test/CodeGen/X86/2010-07-02-UnfoldBug.ll @@ -0,0 +1,99 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin +; rdar://8154265 + +declare <4 x float> @llvm.x86.sse.max.ss(<4 x float>, <4 x float>) nounwind readnone + +declare <4 x float> @llvm.x86.sse.min.ss(<4 x float>, <4 x float>) nounwind readnone + +define void @_ZN2CA3OGL20fill_surface_mesh_3dERNS0_7ContextEPKNS_6Render13MeshTransformEPKNS0_5LayerEPNS0_7SurfaceEfNS0_13TextureFilterESC_f() nounwind optsize ssp { +entry: + br i1 undef, label %bb2.thread, label %bb2 + +bb2.thread: ; preds = %entry + br i1 undef, label %bb41, label %bb10.preheader + +bb2: ; preds = %entry + unreachable + +bb10.preheader: ; preds = %bb2.thread + br i1 undef, label %bb9, label %bb12 + +bb9: ; preds = %bb9, %bb10.preheader + br i1 undef, label %bb9, label %bb12 + +bb12: ; preds = %bb9, %bb10.preheader + br i1 undef, label %bb4.i.i, label %bb3.i.i + +bb3.i.i: ; preds = %bb12 + unreachable + +bb4.i.i: ; preds = %bb12 + br i1 undef, label %bb8.i.i, label %_ZN2CA3OGL12_GLOBAL__N_16LightsC1ERNS0_7ContextEPKNS0_5LayerEPKNS_6Render13MeshTransformERKNS_4Vec3IfEESF_.exit + +bb8.i.i: ; preds = %bb4.i.i + br i1 undef, label %_ZN2CA3OGL12_GLOBAL__N_16LightsC1ERNS0_7ContextEPKNS0_5LayerEPKNS_6Render13MeshTransformERKNS_4Vec3IfEESF_.exit, label %bb9.i.i + +bb9.i.i: ; preds = %bb8.i.i + br i1 undef, label %bb11.i.i, label %bb10.i.i + +bb10.i.i: ; preds = %bb9.i.i + unreachable + +bb11.i.i: ; preds = %bb9.i.i + unreachable + +_ZN2CA3OGL12_GLOBAL__N_16LightsC1ERNS0_7ContextEPKNS0_5LayerEPKNS_6Render13MeshTransformERKNS_4Vec3IfEESF_.exit: ; preds = %bb8.i.i, %bb4.i.i + br i1 undef, label %bb19, label %bb14 + +bb14: ; preds = %_ZN2CA3OGL12_GLOBAL__N_16LightsC1ERNS0_7ContextEPKNS0_5LayerEPKNS_6Render13MeshTransformERKNS_4Vec3IfEESF_.exit + unreachable + +bb19: ; preds = %_ZN2CA3OGL12_GLOBAL__N_16LightsC1ERNS0_7ContextEPKNS0_5LayerEPKNS_6Render13MeshTransformERKNS_4Vec3IfEESF_.exit + br i1 undef, label %bb.i50, label %bb6.i + +bb.i50: ; preds = %bb19 + unreachable + +bb6.i: ; preds = %bb19 + br i1 undef, label %bb28, label %bb.nph106 + +bb22: ; preds = %bb24.preheader + br i1 undef, label %bb2.i.i, label %bb.i.i49 + +bb.i.i49: ; preds = %bb22 + %0 = load float* undef, align 4 ; <float> [#uses=1] + %1 = insertelement <4 x float> undef, float %0, i32 0 ; <<4 x float>> [#uses=1] + %2 = call <4 x float> @llvm.x86.sse.min.ss(<4 x float> <float 1.000000e+00, float undef, float undef, float undef>, <4 x float> %1) nounwind readnone ; <<4 x float>> [#uses=1] + %3 = call <4 x float> @llvm.x86.sse.max.ss(<4 x float> %2, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>) nounwind readnone ; <<4 x float>> [#uses=1] + %4 = extractelement <4 x float> %3, i32 0 ; <float> [#uses=1] + store float %4, float* undef, align 4 + %5 = call <4 x float> @llvm.x86.sse.min.ss(<4 x float> <float 1.000000e+00, float undef, float undef, float undef>, <4 x float> undef) nounwind readnone ; <<4 x float>> [#uses=1] + %6 = call <4 x float> @llvm.x86.sse.max.ss(<4 x float> %5, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>) nounwind readnone ; <<4 x float>> [#uses=1] + %7 = extractelement <4 x float> %6, i32 0 ; <float> [#uses=1] + store float %7, float* undef, align 4 + unreachable + +bb2.i.i: ; preds = %bb22 + unreachable + +bb26.loopexit: ; preds = %bb24.preheader + br i1 undef, label %bb28, label %bb24.preheader + +bb.nph106: ; preds = %bb6.i + br label %bb24.preheader + +bb24.preheader: ; preds = %bb.nph106, %bb26.loopexit + br i1 undef, label %bb22, label %bb26.loopexit + +bb28: ; preds = %bb26.loopexit, %bb6.i + unreachable + +bb41: ; preds = %bb2.thread + br i1 undef, label %return, label %bb46 + +bb46: ; preds = %bb41 + ret void + +return: ; preds = %bb41 + ret void +} diff --git a/test/CodeGen/X86/2010-07-02-asm-alignstack.ll b/test/CodeGen/X86/2010-07-02-asm-alignstack.ll new file mode 100644 index 0000000..cb47d20 --- /dev/null +++ b/test/CodeGen/X86/2010-07-02-asm-alignstack.ll @@ -0,0 +1,31 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | FileCheck %s + +define void @foo() nounwind ssp { +entry: +; CHECK: foo +; CHECK: subq $8, %rsp +; CHECK: int $3 + call void asm sideeffect alignstack "# top of block", "~{dirflag},~{fpsr},~{flags},~{edi},~{esi},~{edx},~{ecx},~{eax}"() nounwind + call void asm sideeffect alignstack ".file \22small.c\22", "~{dirflag},~{fpsr},~{flags}"() nounwind + call void asm sideeffect alignstack ".line 3", "~{dirflag},~{fpsr},~{flags}"() nounwind + call void asm sideeffect alignstack "int $$3", "~{dirflag},~{fpsr},~{flags},~{memory}"() nounwind + br label %return + +return: ; preds = %entry + ret void +} + +define void @bar() nounwind ssp { +entry: +; CHECK: bar +; CHECK-NOT: subq $8, %rsp +; CHECK: int $3 + call void asm sideeffect "# top of block", "~{dirflag},~{fpsr},~{flags},~{edi},~{esi},~{edx},~{ecx},~{eax}"() nounwind + call void asm sideeffect ".file \22small.c\22", "~{dirflag},~{fpsr},~{flags}"() nounwind + call void asm sideeffect ".line 3", "~{dirflag},~{fpsr},~{flags}"() nounwind + call void asm sideeffect "int $$3", "~{dirflag},~{fpsr},~{flags},~{memory}"() nounwind + br label %return + +return: ; preds = %entry + ret void +} diff --git a/test/CodeGen/X86/2010-07-06-DbgCrash.ll b/test/CodeGen/X86/2010-07-06-DbgCrash.ll new file mode 100644 index 0000000..edd6015 --- /dev/null +++ b/test/CodeGen/X86/2010-07-06-DbgCrash.ll @@ -0,0 +1,29 @@ +; RUN: llc -O0 -relocation-model pic < %s -o /dev/null +; PR7545 +@.str = private constant [4 x i8] c"one\00", align 1 ; <[4 x i8]*> [#uses=1] +@.str1 = private constant [4 x i8] c"two\00", align 1 ; <[5 x i8]*> [#uses=1] +@C.9.2167 = internal constant [2 x i8*] [i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), i8* getelementptr inbounds ([4 x i8]* @.str1, i64 0, i64 0)] +!38 = metadata !{i32 524329, metadata !"pbmsrch.c", metadata !"/Users/grawp/LLVM/test-suite/MultiSource/Benchmarks/MiBench/office-stringsearch", metadata !39} ; [ DW_TAG_file_type ] +!39 = metadata !{i32 524305, i32 0, i32 1, metadata !"pbmsrch.c", metadata !"/Users/grawp/LLVM/test-suite/MultiSource/Benchmarks/MiBench/office-stringsearch", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build 9999)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!46 = metadata !{i32 524303, metadata !38, metadata !"", metadata !38, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !47} ; [ DW_TAG_pointer_type ]!97 = metadata !{i32 524334, i32 0, metadata !38, metadata !"main", metadata !"main", metadata !"main", metadata !38, i32 73, metadata !98, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ]!101 = metadata !{[2 x i8*]* @C.9.2167} +!47 = metadata !{i32 524324, metadata !38, metadata !"char", metadata !38, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ] +!97 = metadata !{i32 524334, i32 0, metadata !38, metadata !"main", metadata !"main", metadata !"main", metadata !38, i32 73, metadata !98, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ] +!98 = metadata !{i32 524309, metadata !38, metadata !"", metadata !38, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !99, i32 0, null} ; [ DW_TAG_subroutine_type ] +!99 = metadata !{metadata !100} +!100 = metadata !{i32 524324, metadata !38, metadata !"int", metadata !38, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!101 = metadata !{[2 x i8*]* @C.9.2167} +!102 = metadata !{i32 524544, metadata !103, metadata !"find_strings", metadata !38, i32 75, metadata !104} ; [ DW_TAG_auto_variable ] +!103 = metadata !{i32 524299, metadata !97, i32 73, i32 0} ; [ DW_TAG_lexical_block ] +!104 = metadata !{i32 524289, metadata !38, metadata !"", metadata !38, i32 0, i64 85312, i64 64, i64 0, i32 0, metadata !46, metadata !105, i32 0, null} ; [ DW_TAG_array_type ] +!105 = metadata !{metadata !106} +!106 = metadata !{i32 524321, i64 0, i64 1332} ; [ DW_TAG_subrange_type ] +!107 = metadata !{i32 73, i32 0, metadata !103, null} + +define i32 @main() nounwind ssp { +bb.nph: + tail call void @llvm.dbg.declare(metadata !101, metadata !102), !dbg !107 + ret i32 0, !dbg !107 +} + +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + diff --git a/test/CodeGen/X86/2010-07-06-asm-RIP.ll b/test/CodeGen/X86/2010-07-06-asm-RIP.ll new file mode 100644 index 0000000..f646afa --- /dev/null +++ b/test/CodeGen/X86/2010-07-06-asm-RIP.ll @@ -0,0 +1,21 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s +; PR 7528 + +@n = global i32 0 ; <i32*> [#uses=2] + +define void @f(i32*) nounwind ssp { + ret void +} + +define void @g() nounwind ssp { +entry: +; CHECK: _g: +; CHECK: push $_f$_f +; CHECK: call _f(%rip) + call void asm sideeffect "push\09$1$1\0A\09call\09${1:a}\0A\09pop\09%edx", "imr,i,~{dirflag},~{fpsr},~{flags},~{memory},~{cc},~{edi},~{esi},~{edx},~{ecx},~{ebx},~{eax}"(i32* @n, void (i32*)* @f) nounwind + br label %return + +return: ; preds = %entry + ret void +} + diff --git a/test/CodeGen/X86/alloca-align-rounding-32.ll b/test/CodeGen/X86/alloca-align-rounding-32.ll new file mode 100644 index 0000000..c0f1a18 --- /dev/null +++ b/test/CodeGen/X86/alloca-align-rounding-32.ll @@ -0,0 +1,15 @@ +; RUN: llc < %s -march=x86 -mtriple=i686-apple-darwin | grep and | count 1 + +declare void @bar(<2 x i64>* %n) + +define void @foo(i32 %h) { + %p = alloca <2 x i64>, i32 %h + call void @bar(<2 x i64>* %p) + ret void +} + +define void @foo2(i32 %h) { + %p = alloca <2 x i64>, i32 %h, align 32 + call void @bar(<2 x i64>* %p) + ret void +} diff --git a/test/CodeGen/X86/alloca-align-rounding.ll b/test/CodeGen/X86/alloca-align-rounding.ll index f45e9b8..3c87dbf 100644 --- a/test/CodeGen/X86/alloca-align-rounding.ll +++ b/test/CodeGen/X86/alloca-align-rounding.ll @@ -1,16 +1,15 @@ -; RUN: llc < %s -march=x86 -mtriple=i686-apple-darwin | grep and | count 1 ; RUN: llc < %s -march=x86-64 -mtriple=i686-pc-linux | grep and | count 1 declare void @bar(<2 x i64>* %n) -define void @foo(i32 %h) { - %p = alloca <2 x i64>, i32 %h +define void @foo(i64 %h) { + %p = alloca <2 x i64>, i64 %h call void @bar(<2 x i64>* %p) ret void } -define void @foo2(i32 %h) { - %p = alloca <2 x i64>, i32 %h, align 32 +define void @foo2(i64 %h) { + %p = alloca <2 x i64>, i64 %h, align 32 call void @bar(<2 x i64>* %p) ret void } diff --git a/test/CodeGen/X86/break-sse-dep.ll b/test/CodeGen/X86/break-sse-dep.ll index acc0647..094cbc7 100644 --- a/test/CodeGen/X86/break-sse-dep.ll +++ b/test/CodeGen/X86/break-sse-dep.ll @@ -4,7 +4,7 @@ define double @t1(float* nocapture %x) nounwind readonly ssp { entry: ; CHECK: t1: ; CHECK: movss (%rdi), %xmm0 -; CHECK; cvtss2sd %xmm0, %xmm0 +; CHECK: cvtss2sd %xmm0, %xmm0 %0 = load float* %x, align 4 %1 = fpext float %0 to double @@ -14,8 +14,49 @@ entry: define float @t2(double* nocapture %x) nounwind readonly ssp optsize { entry: ; CHECK: t2: -; CHECK; cvtsd2ss (%rdi), %xmm0 +; CHECK: cvtsd2ss (%rdi), %xmm0 %0 = load double* %x, align 8 %1 = fptrunc double %0 to float ret float %1 } + +define float @squirtf(float* %x) nounwind { +entry: +; CHECK: squirtf: +; CHECK: movss (%rdi), %xmm0 +; CHECK: sqrtss %xmm0, %xmm0 + %z = load float* %x + %t = call float @llvm.sqrt.f32(float %z) + ret float %t +} + +define double @squirt(double* %x) nounwind { +entry: +; CHECK: squirt: +; CHECK: movsd (%rdi), %xmm0 +; CHECK: sqrtsd %xmm0, %xmm0 + %z = load double* %x + %t = call double @llvm.sqrt.f64(double %z) + ret double %t +} + +define float @squirtf_size(float* %x) nounwind optsize { +entry: +; CHECK: squirtf_size: +; CHECK: sqrtss (%rdi), %xmm0 + %z = load float* %x + %t = call float @llvm.sqrt.f32(float %z) + ret float %t +} + +define double @squirt_size(double* %x) nounwind optsize { +entry: +; CHECK: squirt_size: +; CHECK: sqrtsd (%rdi), %xmm0 + %z = load double* %x + %t = call double @llvm.sqrt.f64(double %z) + ret double %t +} + +declare float @llvm.sqrt.f32(float) +declare double @llvm.sqrt.f64(double) diff --git a/test/CodeGen/X86/crash-O0.ll b/test/CodeGen/X86/crash-O0.ll new file mode 100644 index 0000000..956d43b --- /dev/null +++ b/test/CodeGen/X86/crash-O0.ll @@ -0,0 +1,31 @@ +; RUN: llc -O0 -relocation-model=pic -disable-fp-elim < %s +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin10" + +; This file contains functions that may crash llc -O0 + +; The DIV8 instruction produces results in AH and AL, but we don't want to use +; AH in 64-bit mode. The hack used must not generate copyFromReg nodes for +; aliased registers (AX and AL) - RegAllocFast does not like that. +; PR7312 +define i32 @div8() nounwind { +entry: + %0 = trunc i64 undef to i8 ; <i8> [#uses=3] + %1 = udiv i8 0, %0 ; <i8> [#uses=1] + %2 = urem i8 0, %0 ; <i8> [#uses=1] + %3 = icmp uge i8 %2, %0 ; <i1> [#uses=1] + br i1 %3, label %"40", label %"39" + +"39": ; preds = %"36" + %4 = zext i8 %1 to i32 ; <i32> [#uses=1] + %5 = mul nsw i32 %4, undef ; <i32> [#uses=1] + %6 = add nsw i32 %5, undef ; <i32> [#uses=1] + %7 = icmp ne i32 %6, undef ; <i1> [#uses=1] + br i1 %7, label %"40", label %"41" + +"40": ; preds = %"39", %"36" + unreachable + +"41": ; preds = %"39" + unreachable +} diff --git a/test/CodeGen/X86/crash.ll b/test/CodeGen/X86/crash.ll index 2f27f35..a14a48b 100644 --- a/test/CodeGen/X86/crash.ll +++ b/test/CodeGen/X86/crash.ll @@ -130,3 +130,14 @@ bb14: bb67: ret void } + +; Crash when trying to copy AH to AL. +; PR7540 +define void @copy8bitregs() nounwind { +entry: + %div.i = sdiv i32 115200, 0 + %shr8.i = lshr i32 %div.i, 8 + %conv4.i = trunc i32 %shr8.i to i8 + call void asm sideeffect "outb $0, ${1:w}", "{ax},N{dx},~{dirflag},~{fpsr},~{flags}"(i8 %conv4.i, i32 1017) nounwind + unreachable +} diff --git a/test/CodeGen/X86/fast-isel-bc.ll b/test/CodeGen/X86/fast-isel-bc.ll index f2696ce..8d7dc8f 100644 --- a/test/CodeGen/X86/fast-isel-bc.ll +++ b/test/CodeGen/X86/fast-isel-bc.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -O0 -march=x86-64 -mattr=+mmx | FileCheck %s +; RUN: llc < %s -O0 -regalloc=linearscan -march=x86-64 -mattr=+mmx | FileCheck %s ; PR4684 target datalayout = diff --git a/test/CodeGen/X86/fast-isel-gep.ll b/test/CodeGen/X86/fast-isel-gep.ll index 5b8acec..1270ab7 100644 --- a/test/CodeGen/X86/fast-isel-gep.ll +++ b/test/CodeGen/X86/fast-isel-gep.ll @@ -51,3 +51,22 @@ entry: ; X64: ret } + +define double @test4(i64 %x, double* %p) nounwind { +entry: + %x.addr = alloca i64, align 8 ; <i64*> [#uses=2] + %p.addr = alloca double*, align 8 ; <double**> [#uses=2] + store i64 %x, i64* %x.addr + store double* %p, double** %p.addr + %tmp = load i64* %x.addr ; <i64> [#uses=1] + %add = add nsw i64 %tmp, 16 ; <i64> [#uses=1] + %tmp1 = load double** %p.addr ; <double*> [#uses=1] + %arrayidx = getelementptr inbounds double* %tmp1, i64 %add ; <double*> [#uses=1] + %tmp2 = load double* %arrayidx ; <double> [#uses=1] + ret double %tmp2 + +; X32: test4: +; X32: 128(%e{{.*}},%e{{.*}},8) +; X64: test4: +; X64: 128(%r{{.*}},%r{{.*}},8) +} diff --git a/test/CodeGen/X86/fast-isel-loads.ll b/test/CodeGen/X86/fast-isel-loads.ll new file mode 100644 index 0000000..2fbb46c --- /dev/null +++ b/test/CodeGen/X86/fast-isel-loads.ll @@ -0,0 +1,23 @@ +; RUN: llc -march=x86-64 -O0 -asm-verbose=false < %s | FileCheck %s + +; Fast-isel shouldn't reload the argument values from the stack. + +; CHECK: foo: +; CHECK-NEXT: movq %rdi, -8(%rsp) +; CHECK-NEXT: movq %rsi, -16(%rsp) +; CHECK-NEXT: movsd 128(%rsi,%rdi,8), %xmm0 +; CHECK-NEXT: ret + +define double @foo(i64 %x, double* %p) nounwind { +entry: + %x.addr = alloca i64, align 8 ; <i64*> [#uses=2] + %p.addr = alloca double*, align 8 ; <double**> [#uses=2] + store i64 %x, i64* %x.addr + store double* %p, double** %p.addr + %tmp = load i64* %x.addr ; <i64> [#uses=1] + %tmp1 = load double** %p.addr ; <double*> [#uses=1] + %add = add nsw i64 %tmp, 16 ; <i64> [#uses=1] + %arrayidx = getelementptr inbounds double* %tmp1, i64 %add ; <double*> [#uses=1] + %tmp2 = load double* %arrayidx ; <double> [#uses=1] + ret double %tmp2 +} diff --git a/test/CodeGen/X86/fast-isel-shift-imm.ll b/test/CodeGen/X86/fast-isel-shift-imm.ll index 35f7a72..7759bb0 100644 --- a/test/CodeGen/X86/fast-isel-shift-imm.ll +++ b/test/CodeGen/X86/fast-isel-shift-imm.ll @@ -1,7 +1,8 @@ ; RUN: llc < %s -march=x86 -O0 | grep {sarl \$80, %eax} ; PR3242 -define i32 @foo(i32 %x) nounwind { +define void @foo(i32 %x, i32* %p) nounwind { %y = ashr i32 %x, 50000 - ret i32 %y + store i32 %y, i32* %p + ret void } diff --git a/test/CodeGen/X86/fast-isel-x86.ll b/test/CodeGen/X86/fast-isel-x86.ll new file mode 100644 index 0000000..56aeb3a --- /dev/null +++ b/test/CodeGen/X86/fast-isel-x86.ll @@ -0,0 +1,33 @@ +; RUN: llc -march=x86 -relocation-model=pic < %s + +; This should use flds to set the return value. +; CHECK: test0: +; CHECK: flds +; CHECK: ret +@G = external global float +define float @test0() nounwind { + %t = load float* @G + ret float %t +} + +; This should pop 4 bytes on return. +; CHECK: test1: +; CHECK: ret $4 +define void @test1({i32, i32, i32, i32}* sret %p) nounwind { + store {i32, i32, i32, i32} zeroinitializer, {i32, i32, i32, i32}* %p + ret void +} + +; Properly initialize the pic base. +; CHECK: test2: +; CHECK-NOT: HHH +; CHECK: call{{.*}}L2$pb +; CHECK-NEXT: L2$pb: +; CHECK-NEXT: pop +; CHECK: HHH +; CHECK: ret +@HHH = external global i32 +define i32 @test2() nounwind { + %t = load i32* @HHH + ret i32 %t +} diff --git a/test/CodeGen/X86/fast-isel.ll b/test/CodeGen/X86/fast-isel.ll index 3d26ae7..177c06b 100644 --- a/test/CodeGen/X86/fast-isel.ll +++ b/test/CodeGen/X86/fast-isel.ll @@ -49,9 +49,10 @@ entry: ret i32 %tmp2 } -define i1 @ptrtoint_i1(i8* %p) nounwind { +define void @ptrtoint_i1(i8* %p, i1* %q) nounwind { %t = ptrtoint i8* %p to i1 - ret i1 %t + store i1 %t, i1* %q + ret void } define i8* @inttoptr_i1(i1 %p) nounwind { %t = inttoptr i1 %p to i8* @@ -86,11 +87,8 @@ define i8 @mul_i8(i8 %a) nounwind { ret i8 %tmp } -define void @store_i1(i1* %p, i1 %t) nounwind { - store i1 %t, i1* %p - ret void -} -define i1 @load_i1(i1* %p) nounwind { +define void @load_store_i1(i1* %p, i1* %q) nounwind { %t = load i1* %p - ret i1 %t + store i1 %t, i1* %q + ret void } diff --git a/test/CodeGen/X86/fp-stack-O0-crash.ll b/test/CodeGen/X86/fp-stack-O0-crash.ll index bbadca5..9b629c0 100644 --- a/test/CodeGen/X86/fp-stack-O0-crash.ll +++ b/test/CodeGen/X86/fp-stack-O0-crash.ll @@ -1,4 +1,3 @@ -; RUN: llc %s -O0 -fast-isel -regalloc=local -o - ; RUN: llc %s -O0 -fast-isel -regalloc=fast -o - ; PR4767 diff --git a/test/CodeGen/X86/hidden-vis-5.ll b/test/CodeGen/X86/hidden-vis-pic.ll index 88fae37..ba130a2 100644 --- a/test/CodeGen/X86/hidden-vis-5.ll +++ b/test/CodeGen/X86/hidden-vis-pic.ll @@ -1,4 +1,27 @@ ; RUN: llc < %s -mtriple=i386-apple-darwin9 -relocation-model=pic -disable-fp-elim -unwind-tables | FileCheck %s + + + +; PR7353 PR7334 rdar://8072315 rdar://8018308 + +define available_externally hidden +void @_ZNSbIcED1Ev() nounwind readnone ssp align 2 { +entry: + ret void +} + +define void()* @test1() nounwind { +entry: + ret void()* @_ZNSbIcED1Ev +} + +; This must use movl of the stub, not an lea, since the function isn't being +; emitted here. +; CHECK: movl L__ZNSbIcED1Ev$non_lazy_ptr-L1$pb( + + + + ; <rdar://problem/7383328> @.str = private constant [12 x i8] c"hello world\00", align 1 ; <[12 x i8]*> [#uses=1] @@ -28,3 +51,5 @@ return: ; preds = %entry ; CHECK: .private_extern _func.eh ; CHECK: .private_extern _main.eh + + diff --git a/test/CodeGen/X86/imp-def-copies.ll b/test/CodeGen/X86/imp-def-copies.ll deleted file mode 100644 index 9117840..0000000 --- a/test/CodeGen/X86/imp-def-copies.ll +++ /dev/null @@ -1,29 +0,0 @@ -; RUN: llc < %s -march=x86 | not grep mov - - %struct.active_line = type { %struct.gs_fixed_point, %struct.gs_fixed_point, i32, i32, i32, %struct.line_segment*, i32, i16, i16, %struct.active_line*, %struct.active_line* } - %struct.gs_fixed_point = type { i32, i32 } - %struct.line_list = type { %struct.active_line*, i32, i16, %struct.active_line*, %struct.active_line*, %struct.active_line*, %struct.active_line, i32 } - %struct.line_segment = type { %struct.line_segment*, %struct.line_segment*, i32, %struct.gs_fixed_point } - %struct.subpath = type { %struct.line_segment*, %struct.line_segment*, i32, %struct.gs_fixed_point, %struct.line_segment*, i32, i32, i8 } - -define fastcc void @add_y_list(%struct.subpath* %ppath.0.4.val, i16 signext %tag, %struct.line_list* %ll, i32 %pbox.0.0.1.val, i32 %pbox.0.1.0.val, i32 %pbox.0.1.1.val) nounwind { -entry: - br i1 false, label %return, label %bb -bb: ; preds = %bb280, %entry - %psub.1.reg2mem.0 = phi %struct.subpath* [ %psub.0.reg2mem.0, %bb280 ], [ undef, %entry ] ; <%struct.subpath*> [#uses=1] - %plast.1.reg2mem.0 = phi %struct.line_segment* [ %plast.0.reg2mem.0, %bb280 ], [ undef, %entry ] ; <%struct.line_segment*> [#uses=1] - %prev_dir.0.reg2mem.0 = phi i32 [ %dir.0.reg2mem.0, %bb280 ], [ undef, %entry ] ; <i32> [#uses=1] - br i1 false, label %bb280, label %bb109 -bb109: ; preds = %bb - %tmp113 = icmp sgt i32 0, %prev_dir.0.reg2mem.0 ; <i1> [#uses=1] - br i1 %tmp113, label %bb116, label %bb280 -bb116: ; preds = %bb109 - ret void -bb280: ; preds = %bb109, %bb - %psub.0.reg2mem.0 = phi %struct.subpath* [ null, %bb ], [ %psub.1.reg2mem.0, %bb109 ] ; <%struct.subpath*> [#uses=1] - %plast.0.reg2mem.0 = phi %struct.line_segment* [ null, %bb ], [ %plast.1.reg2mem.0, %bb109 ] ; <%struct.line_segment*> [#uses=1] - %dir.0.reg2mem.0 = phi i32 [ 0, %bb ], [ 0, %bb109 ] ; <i32> [#uses=1] - br i1 false, label %return, label %bb -return: ; preds = %bb280, %entry - ret void -} diff --git a/test/CodeGen/X86/inline-asm-fpstack.ll b/test/CodeGen/X86/inline-asm-fpstack.ll index 09b0929..6348fca 100644 --- a/test/CodeGen/X86/inline-asm-fpstack.ll +++ b/test/CodeGen/X86/inline-asm-fpstack.ll @@ -1,42 +1,87 @@ -; RUN: llc < %s -march=x86 +; RUN: llc < %s -mtriple=i386-apple-darwin | FileCheck %s +; There should be no stack manipulations between the inline asm and ret. +; CHECK: test1 +; CHECK: InlineAsm End +; CHECK-NEXT: ret define x86_fp80 @test1() { %tmp85 = call x86_fp80 asm sideeffect "fld0", "={st(0)}"() ret x86_fp80 %tmp85 } +; CHECK: test2 +; CHECK: InlineAsm End +; CHECK-NEXT: ret define double @test2() { %tmp85 = call double asm sideeffect "fld0", "={st(0)}"() ret double %tmp85 } +; Setting up argument in st(0) should be a single fld. +; CHECK: test3 +; CHECK: fld +; CHECK-NEXT: InlineAsm Start +; Asm consumes stack, nothing should be popped. +; CHECK: InlineAsm End +; CHECK-NOT: fstp +; CHECK: ret define void @test3(x86_fp80 %X) { call void asm sideeffect "frob ", "{st(0)},~{dirflag},~{fpsr},~{flags}"( x86_fp80 %X) ret void } +; CHECK: test4 +; CHECK: fld +; CHECK-NEXT: InlineAsm Start +; CHECK: InlineAsm End +; CHECK-NOT: fstp +; CHECK: ret define void @test4(double %X) { call void asm sideeffect "frob ", "{st(0)},~{dirflag},~{fpsr},~{flags}"( double %X) ret void } +; Same as test3/4, but using value from fadd. +; The fadd can be done in xmm or x87 regs - we don't test that. +; CHECK: test5 +; CHECK: InlineAsm End +; CHECK-NOT: fstp +; CHECK: ret define void @test5(double %X) { %Y = fadd double %X, 123.0 call void asm sideeffect "frob ", "{st(0)},~{dirflag},~{fpsr},~{flags}"( double %Y) ret void } +; CHECK: test6 define void @test6(double %A, double %B, double %C, double %D, double %E) nounwind { entry: - ; Uses the same value twice, should have one fstp after the asm. +; Uses the same value twice, should have one fstp after the asm. +; CHECK: foo +; CHECK: InlineAsm End +; CHECK-NEXT: fstp +; CHECK-NOT: fstp tail call void asm sideeffect "foo $0 $1", "f,f,~{dirflag},~{fpsr},~{flags}"( double %A, double %A ) nounwind - ; Uses two different values, should be in st(0)/st(1) and both be popped. +; Uses two different values, should be in st(0)/st(1) and both be popped. +; CHECK: bar +; CHECK: InlineAsm End +; CHECK-NEXT: fstp +; CHECK-NEXT: fstp tail call void asm sideeffect "bar $0 $1", "f,f,~{dirflag},~{fpsr},~{flags}"( double %B, double %C ) nounwind - ; Uses two different values, one of which isn't killed in this asm, it - ; should not be popped after the asm. +; Uses two different values, one of which isn't killed in this asm, it +; should not be popped after the asm. +; CHECK: baz +; CHECK: InlineAsm End +; CHECK-NEXT: fstp +; CHECK-NOT: fstp tail call void asm sideeffect "baz $0 $1", "f,f,~{dirflag},~{fpsr},~{flags}"( double %D, double %E ) nounwind - ; This is the last use of %D, so it should be popped after. +; This is the last use of %D, so it should be popped after. +; CHECK: baz +; CHECK: InlineAsm End +; CHECK-NEXT: fstp +; CHECK-NOT: fstp +; CHECK: ret tail call void asm sideeffect "baz $0", "f,~{dirflag},~{fpsr},~{flags}"( double %D ) nounwind ret void } diff --git a/test/CodeGen/X86/inline-asm-fpstack2.ll b/test/CodeGen/X86/inline-asm-fpstack2.ll index ffa6ee6..78037e0 100644 --- a/test/CodeGen/X86/inline-asm-fpstack2.ll +++ b/test/CodeGen/X86/inline-asm-fpstack2.ll @@ -1,10 +1,21 @@ -; RUN: llc < %s -march=x86 > %t -; RUN: grep {fld %%st(0)} %t +; RUN: llc < %s -march=x86 | FileCheck %s ; PR4185 +; Passing a non-killed value to asm in {st}. +; Make sure it is duped before. +; asm kills st(0), so we shouldn't pop anything +; CHECK: fld %st(0) +; CHECK: fistpl +; CHECK-NOT: fstp +; CHECK: fistpl +; CHECK-NOT: fstp +; CHECK: ret define void @test() { return: call void asm sideeffect "fistpl $0", "{st}"(double 1.000000e+06) call void asm sideeffect "fistpl $0", "{st}"(double 1.000000e+06) ret void } + +; A valid alternative would be to remat the constant pool load before each +; inline asm. diff --git a/test/CodeGen/X86/inline-asm-fpstack3.ll b/test/CodeGen/X86/inline-asm-fpstack3.ll index 17945fe..a609681 100644 --- a/test/CodeGen/X86/inline-asm-fpstack3.ll +++ b/test/CodeGen/X86/inline-asm-fpstack3.ll @@ -1,11 +1,14 @@ -; RUN: llc < %s -march=x86 > %t -; RUN: grep {fld %%st(0)} %t +; RUN: llc < %s -march=x86 | FileCheck %s ; PR4459 -declare x86_fp80 @ceil(x86_fp80) - -declare void @test(x86_fp80) - +; The return value from ceil must be duped before being consumed by asm. +; CHECK: ceil +; CHECK: fld %st(0) +; CHECK-NOT: fxch +; CHECK: fistpl +; CHECK-NOT: fxch +; CHECK: fstpt +; CHECK: test define void @test2(x86_fp80 %a) { entry: %0 = call x86_fp80 @ceil(x86_fp80 %a) @@ -13,3 +16,5 @@ entry: call void @test(x86_fp80 %0 ) ret void } +declare x86_fp80 @ceil(x86_fp80) +declare void @test(x86_fp80) diff --git a/test/CodeGen/X86/inline-asm-fpstack4.ll b/test/CodeGen/X86/inline-asm-fpstack4.ll index bae2970..ec572b4 100644 --- a/test/CodeGen/X86/inline-asm-fpstack4.ll +++ b/test/CodeGen/X86/inline-asm-fpstack4.ll @@ -1,10 +1,17 @@ -; RUN: llc < %s -march=x86 +; RUN: llc < %s -march=x86 | FileCheck %s ; PR4484 -declare x86_fp80 @ceil() - -declare void @test(x86_fp80) - +; ceil leaves a value on the stack that is needed after the asm. +; CHECK: ceil +; CHECK-NOT: fstp +; Load %a from stack after ceil +; CHECK: fldt +; CHECK-NOT: fxch +; CHECK: fistpl +; CHECK-NOT: fstp +; Set up call to test. +; CHECK: fstpt +; CHECK: test define void @test2(x86_fp80 %a) { entry: %0 = call x86_fp80 @ceil() @@ -13,3 +20,5 @@ entry: ret void } +declare x86_fp80 @ceil() +declare void @test(x86_fp80) diff --git a/test/CodeGen/X86/inline-asm-tied.ll b/test/CodeGen/X86/inline-asm-tied.ll index 1f4a13f..79b6885 100644 --- a/test/CodeGen/X86/inline-asm-tied.ll +++ b/test/CodeGen/X86/inline-asm-tied.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin9 -O0 | grep {movl %edx, 12(%esp)} | count 2 +; RUN: llc < %s -mtriple=i386-apple-darwin9 -O0 -regalloc=linearscan | grep {movl %edx, 4(%esp)} | count 2 ; rdar://6992609 target triple = "i386-apple-darwin9.0" diff --git a/test/CodeGen/X86/ins_subreg_coalesce-3.ll b/test/CodeGen/X86/ins_subreg_coalesce-3.ll index 8c1c409..63881e0 100644 --- a/test/CodeGen/X86/ins_subreg_coalesce-3.ll +++ b/test/CodeGen/X86/ins_subreg_coalesce-3.ll @@ -39,8 +39,7 @@ bb650: ; preds = %bb650, %bb428 %tmp659 = icmp eq i8 %tmp658, 0 ; <i1> [#uses=1] br i1 %tmp659, label %bb650, label %bb662 bb662: ; preds = %bb650 - %tmp685 = icmp eq %struct.rec* null, null ; <i1> [#uses=1] - br i1 %tmp685, label %bb761, label %bb688 + br label %bb761 bb688: ; preds = %bb662 ret void bb761: ; preds = %bb662 diff --git a/test/CodeGen/X86/iv-users-in-other-loops.ll b/test/CodeGen/X86/iv-users-in-other-loops.ll index 408fb20..8385a29 100644 --- a/test/CodeGen/X86/iv-users-in-other-loops.ll +++ b/test/CodeGen/X86/iv-users-in-other-loops.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=x86-64 -o %t ; RUN: not grep inc %t ; RUN: grep dec %t | count 2 -; RUN: grep addq %t | count 13 +; RUN: grep addq %t | count 12 ; RUN: not grep addb %t ; RUN: not grep leaq %t ; RUN: not grep leal %t diff --git a/test/CodeGen/X86/leaf-fp-elim.ll b/test/CodeGen/X86/leaf-fp-elim.ll new file mode 100644 index 0000000..607dc72 --- /dev/null +++ b/test/CodeGen/X86/leaf-fp-elim.ll @@ -0,0 +1,30 @@ +; RUN: llc < %s -disable-non-leaf-fp-elim -relocation-model=pic -mtriple=x86_64-apple-darwin | FileCheck %s +; <rdar://problem/8170192> +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin11.0" + +@msg = internal global i8* null ; <i8**> [#uses=1] +@.str = private constant [2 x i8] c"x\00", align 1 ; <[2 x i8]*> [#uses=1] + +define void @test(i8* %p) nounwind optsize ssp { + +; No stack frame, please. +; CHECK: _test +; CHECK-NOT: pushq %rbp +; CHECK-NOT: movq %rsp, %rbp +; CHECK: InlineAsm Start + +entry: + %0 = icmp eq i8* %p, null ; <i1> [#uses=1] + br i1 %0, label %return, label %bb + +bb: ; preds = %entry + tail call void asm "mov $1, $0", "=*m,{cx},~{dirflag},~{fpsr},~{flags}"(i8** @msg, i8* getelementptr inbounds ([2 x i8]* @.str, i64 0, i64 0)) nounwind + tail call void @llvm.trap() + unreachable + +return: ; preds = %entry + ret void +} + +declare void @llvm.trap() nounwind diff --git a/test/CodeGen/X86/licm-nested.ll b/test/CodeGen/X86/licm-nested.ll new file mode 100644 index 0000000..71685bb --- /dev/null +++ b/test/CodeGen/X86/licm-nested.ll @@ -0,0 +1,89 @@ +; RUN: llc -mtriple=x86_64-apple-darwin -march=x86-64 < %s -stats -info-output-file - | grep machine-licm | grep 2 + +; MachineLICM should be able to hoist the symbolic addresses out of +; the inner loops. + +@main.flags = internal global [8193 x i8] zeroinitializer, align 16 ; <[8193 x i8]*> [#uses=3] +@.str = private constant [11 x i8] c"Count: %d\0A\00" ; <[11 x i8]*> [#uses=1] + +define i32 @main(i32 %argc, i8** nocapture %argv) nounwind ssp { +entry: + %cmp = icmp eq i32 %argc, 2 ; <i1> [#uses=1] + br i1 %cmp, label %while.cond.preheader, label %bb.nph53 + +while.cond.preheader: ; preds = %entry + %arrayidx = getelementptr inbounds i8** %argv, i64 1 ; <i8**> [#uses=1] + %tmp2 = load i8** %arrayidx ; <i8*> [#uses=1] + %call = tail call i32 @atoi(i8* %tmp2) nounwind ; <i32> [#uses=2] + %tobool51 = icmp eq i32 %call, 0 ; <i1> [#uses=1] + br i1 %tobool51, label %while.end, label %bb.nph53 + +while.cond.loopexit: ; preds = %for.inc35 + %indvar.next77 = add i32 %indvar76, 1 ; <i32> [#uses=2] + %exitcond78 = icmp eq i32 %indvar.next77, %NUM.0.ph80 ; <i1> [#uses=1] + br i1 %exitcond78, label %while.end, label %bb.nph + +bb.nph53: ; preds = %entry, %while.cond.preheader + %NUM.0.ph80 = phi i32 [ %call, %while.cond.preheader ], [ 17000, %entry ] ; <i32> [#uses=1] + br label %bb.nph + +bb.nph: ; preds = %while.cond.loopexit, %bb.nph53 + %indvar76 = phi i32 [ 0, %bb.nph53 ], [ %indvar.next77, %while.cond.loopexit ] ; <i32> [#uses=1] + br label %for.body + +for.body: ; preds = %for.body, %bb.nph + %indvar = phi i64 [ 0, %bb.nph ], [ %indvar.next, %for.body ] ; <i64> [#uses=2] + %tmp = add i64 %indvar, 2 ; <i64> [#uses=1] + %arrayidx10 = getelementptr [8193 x i8]* @main.flags, i64 0, i64 %tmp ; <i8*> [#uses=1] + store i8 1, i8* %arrayidx10 + %indvar.next = add i64 %indvar, 1 ; <i64> [#uses=2] + %exitcond = icmp eq i64 %indvar.next, 8191 ; <i1> [#uses=1] + br i1 %exitcond, label %for.body15, label %for.body + +for.body15: ; preds = %for.body, %for.inc35 + %indvar57 = phi i64 [ %indvar.next58, %for.inc35 ], [ 0, %for.body ] ; <i64> [#uses=4] + %count.248 = phi i32 [ %count.1, %for.inc35 ], [ 0, %for.body ] ; <i32> [#uses=2] + %tmp68 = add i64 %indvar57, 2 ; <i64> [#uses=2] + %tmp70 = mul i64 %indvar57, 3 ; <i64> [#uses=1] + %tmp71 = add i64 %tmp70, 6 ; <i64> [#uses=1] + %tmp73 = shl i64 %indvar57, 1 ; <i64> [#uses=1] + %add = add i64 %tmp73, 4 ; <i64> [#uses=2] + %arrayidx17 = getelementptr [8193 x i8]* @main.flags, i64 0, i64 %tmp68 ; <i8*> [#uses=1] + %tmp18 = load i8* %arrayidx17 ; <i8> [#uses=1] + %tobool19 = icmp eq i8 %tmp18, 0 ; <i1> [#uses=1] + br i1 %tobool19, label %for.inc35, label %if.then + +if.then: ; preds = %for.body15 + %cmp2443 = icmp slt i64 %add, 8193 ; <i1> [#uses=1] + br i1 %cmp2443, label %for.body25, label %for.end32 + +for.body25: ; preds = %if.then, %for.body25 + %indvar55 = phi i64 [ %indvar.next56, %for.body25 ], [ 0, %if.then ] ; <i64> [#uses=2] + %tmp60 = mul i64 %tmp68, %indvar55 ; <i64> [#uses=2] + %tmp75 = add i64 %add, %tmp60 ; <i64> [#uses=1] + %arrayidx27 = getelementptr [8193 x i8]* @main.flags, i64 0, i64 %tmp75 ; <i8*> [#uses=1] + store i8 0, i8* %arrayidx27 + %add31 = add i64 %tmp71, %tmp60 ; <i64> [#uses=1] + %cmp24 = icmp slt i64 %add31, 8193 ; <i1> [#uses=1] + %indvar.next56 = add i64 %indvar55, 1 ; <i64> [#uses=1] + br i1 %cmp24, label %for.body25, label %for.end32 + +for.end32: ; preds = %for.body25, %if.then + %inc34 = add nsw i32 %count.248, 1 ; <i32> [#uses=1] + br label %for.inc35 + +for.inc35: ; preds = %for.body15, %for.end32 + %count.1 = phi i32 [ %inc34, %for.end32 ], [ %count.248, %for.body15 ] ; <i32> [#uses=2] + %indvar.next58 = add i64 %indvar57, 1 ; <i64> [#uses=2] + %exitcond67 = icmp eq i64 %indvar.next58, 8191 ; <i1> [#uses=1] + br i1 %exitcond67, label %while.cond.loopexit, label %for.body15 + +while.end: ; preds = %while.cond.loopexit, %while.cond.preheader + %count.0.lcssa = phi i32 [ 0, %while.cond.preheader ], [ %count.1, %while.cond.loopexit ] ; <i32> [#uses=1] + %call40 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8]* @.str, i64 0, i64 0), i32 %count.0.lcssa) nounwind ; <i32> [#uses=0] + ret i32 0 +} + +declare i32 @atoi(i8* nocapture) nounwind readonly + +declare i32 @printf(i8* nocapture, ...) nounwind diff --git a/test/CodeGen/X86/liveness-local-regalloc.ll b/test/CodeGen/X86/liveness-local-regalloc.ll index 8cac3f8..b469d083 100644 --- a/test/CodeGen/X86/liveness-local-regalloc.ll +++ b/test/CodeGen/X86/liveness-local-regalloc.ll @@ -1,4 +1,3 @@ -; RUN: llc < %s -O3 -regalloc=local -mtriple=x86_64-apple-darwin10 ; RUN: llc < %s -O3 -regalloc=fast -mtriple=x86_64-apple-darwin10 ; <rdar://problem/7755473> diff --git a/test/CodeGen/X86/local-liveness.ll b/test/CodeGen/X86/local-liveness.ll deleted file mode 100644 index 321f208..0000000 --- a/test/CodeGen/X86/local-liveness.ll +++ /dev/null @@ -1,31 +0,0 @@ -; RUN: llc < %s -march=x86 -regalloc=local | grep {subl %eax, %edx} - -; Local regalloc shouldn't assume that both the uses of the -; sub instruction are kills, because one of them is tied -; to an output. Previously, it was allocating both inputs -; in the same register. - -define i32 @func_3() nounwind { -entry: - %retval = alloca i32 ; <i32*> [#uses=2] - %g_323 = alloca i8 ; <i8*> [#uses=2] - %p_5 = alloca i64, align 8 ; <i64*> [#uses=2] - %0 = alloca i32 ; <i32*> [#uses=2] - %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] - store i64 0, i64* %p_5, align 8 - store i8 1, i8* %g_323, align 1 - %1 = load i8* %g_323, align 1 ; <i8> [#uses=1] - %2 = sext i8 %1 to i64 ; <i64> [#uses=1] - %3 = load i64* %p_5, align 8 ; <i64> [#uses=1] - %4 = sub i64 %3, %2 ; <i64> [#uses=1] - %5 = icmp sge i64 %4, 0 ; <i1> [#uses=1] - %6 = zext i1 %5 to i32 ; <i32> [#uses=1] - store i32 %6, i32* %0, align 4 - %7 = load i32* %0, align 4 ; <i32> [#uses=1] - store i32 %7, i32* %retval, align 4 - br label %return - -return: ; preds = %entry - %retval1 = load i32* %retval ; <i32> [#uses=1] - ret i32 %retval1 -} diff --git a/test/CodeGen/X86/loop-strength-reduce6.ll b/test/CodeGen/X86/loop-strength-reduce6.ll index bbafcf7c..919f836 100644 --- a/test/CodeGen/X86/loop-strength-reduce6.ll +++ b/test/CodeGen/X86/loop-strength-reduce6.ll @@ -2,22 +2,22 @@ define fastcc i32 @decodeMP3(i32 %isize, i32* %done) nounwind { entry: - br i1 false, label %cond_next191, label %cond_true189 + br label %cond_true189 cond_true189: ; preds = %entry ret i32 0 cond_next191: ; preds = %entry - br i1 false, label %cond_next37.i, label %cond_false.i9 + br label %cond_false.i9 cond_false.i9: ; preds = %cond_next191 ret i32 0 cond_next37.i: ; preds = %cond_next191 - br i1 false, label %cond_false50.i, label %cond_true44.i + br label %cond_true44.i cond_true44.i: ; preds = %cond_next37.i - br i1 false, label %cond_true11.i.i, label %bb414.preheader.i + br label %bb414.preheader.i cond_true11.i.i: ; preds = %cond_true44.i ret i32 0 @@ -26,19 +26,19 @@ cond_false50.i: ; preds = %cond_next37.i ret i32 0 bb414.preheader.i: ; preds = %cond_true44.i - br i1 false, label %bb.i18, label %do_layer3.exit + br label %do_layer3.exit bb.i18: ; preds = %bb414.preheader.i - br i1 false, label %bb358.i, label %cond_true79.i + br label %cond_true79.i cond_true79.i: ; preds = %bb.i18 ret i32 0 bb331.i: ; preds = %bb358.i, %cond_true.i149.i - br i1 false, label %cond_true.i149.i, label %cond_false.i151.i + br label %cond_false.i151.i cond_true.i149.i: ; preds = %bb331.i - br i1 false, label %bb178.preheader.i.i, label %bb331.i + br label %bb331.i cond_false.i151.i: ; preds = %bb331.i ret i32 0 @@ -56,7 +56,7 @@ bb178.preheader.i.i: ; preds = %bb163.i.i, %cond_true.i149.i br label %bb163.i.i bb358.i: ; preds = %bb.i18 - br i1 false, label %bb331.i, label %bb406.i + br label %bb406.i bb406.i: ; preds = %bb358.i ret i32 0 diff --git a/test/CodeGen/X86/lsr-delayed-fold.ll b/test/CodeGen/X86/lsr-delayed-fold.ll index 8afbb0d..8ed97e4 100644 --- a/test/CodeGen/X86/lsr-delayed-fold.ll +++ b/test/CodeGen/X86/lsr-delayed-fold.ll @@ -132,3 +132,47 @@ for.inc131: ; preds = %for.body123, %for.b for.end134: ; preds = %for.inc131 ret void } + +; LSR needs to remember inserted instructions even in postinc mode, because +; there could be multiple subexpressions within a single expansion which +; require insert point adjustment. +; PR7306 + +define fastcc i32 @GetOptimum() nounwind { +bb: + br label %bb1 + +bb1: ; preds = %bb1, %bb + %t = phi i32 [ 0, %bb ], [ %t2, %bb1 ] ; <i32> [#uses=1] + %t2 = add i32 %t, undef ; <i32> [#uses=3] + br i1 undef, label %bb1, label %bb3 + +bb3: ; preds = %bb1 + %t4 = add i32 undef, -1 ; <i32> [#uses=1] + br label %bb5 + +bb5: ; preds = %bb16, %bb3 + %t6 = phi i32 [ %t17, %bb16 ], [ 0, %bb3 ] ; <i32> [#uses=3] + %t7 = add i32 undef, %t6 ; <i32> [#uses=2] + %t8 = add i32 %t4, %t6 ; <i32> [#uses=1] + br i1 undef, label %bb9, label %bb10 + +bb9: ; preds = %bb5 + br label %bb10 + +bb10: ; preds = %bb9, %bb5 + br i1 undef, label %bb11, label %bb16 + +bb11: ; preds = %bb10 + %t12 = icmp ugt i32 %t7, %t2 ; <i1> [#uses=1] + %t13 = select i1 %t12, i32 %t2, i32 %t7 ; <i32> [#uses=1] + br label %bb14 + +bb14: ; preds = %bb11 + store i32 %t13, i32* null + ret i32 %t8 + +bb16: ; preds = %bb10 + %t17 = add i32 %t6, 1 ; <i32> [#uses=1] + br label %bb5 +} diff --git a/test/CodeGen/X86/lsr-loop-exit-cond.ll b/test/CodeGen/X86/lsr-loop-exit-cond.ll index 474450a..938023f 100644 --- a/test/CodeGen/X86/lsr-loop-exit-cond.ll +++ b/test/CodeGen/X86/lsr-loop-exit-cond.ll @@ -7,7 +7,7 @@ @Te1 = external global [256 x i32] ; <[256 x i32]*> [#uses=4] @Te3 = external global [256 x i32] ; <[256 x i32]*> [#uses=2] -define void @t(i8* nocapture %in, i8* nocapture %out, i32* nocapture %rk, i32 %r) nounwind ssp { +define void @t(i8* nocapture %in, i8* nocapture %out, i32* nocapture %rk, i32 %r) nounwind { entry: %0 = load i32* %rk, align 4 ; <i32> [#uses=1] %1 = getelementptr i32* %rk, i64 1 ; <i32*> [#uses=1] diff --git a/test/CodeGen/X86/lsr-nonaffine.ll b/test/CodeGen/X86/lsr-nonaffine.ll new file mode 100644 index 0000000..b0d3064 --- /dev/null +++ b/test/CodeGen/X86/lsr-nonaffine.ll @@ -0,0 +1,23 @@ +; RUN: llc -march=x86-64 < %s | FileCheck %s + +; LSR should compute the correct starting values for this loop. Note that +; it's not necessarily LSR's job to compute loop exit expressions; that's +; indvars' job. +; CHECK: movl $12 +; CHECK: movl $42 + +define i32 @real_symmetric_eigen(i32 %n) nounwind { +while.body127: ; preds = %while.cond122 + br label %while.cond141 + +while.cond141: ; preds = %while.cond141, %while.body127 + %0 = phi i32 [ 7, %while.body127 ], [ %indvar.next67, %while.cond141 ] ; <i32> [#uses=3] + %indvar.next67 = add i32 %0, 1 ; <i32> [#uses=1] + %t = icmp slt i32 %indvar.next67, %n + br i1 %t, label %if.then171, label %while.cond141 + +if.then171: ; preds = %while.cond141 + %mul150 = mul i32 %0, %0 ; <i32> [#uses=1] + %add174 = add i32 %mul150, %0 ; <i32> [#uses=1] + ret i32 %add174 +} diff --git a/test/CodeGen/X86/lsr-reuse.ll b/test/CodeGen/X86/lsr-reuse.ll index b80ee08..b7e69b8 100644 --- a/test/CodeGen/X86/lsr-reuse.ll +++ b/test/CodeGen/X86/lsr-reuse.ll @@ -440,3 +440,312 @@ bb5: ; preds = %bb3, %entry %s.1.lcssa = phi i32 [ 0, %entry ], [ %s.0.lcssa, %bb3 ] ; <i32> [#uses=1] ret i32 %s.1.lcssa } + +; Two loops here are of particular interest; the one at %bb21, where +; we don't want to leave extra induction variables around, or use an +; lea to compute an exit condition inside the loop: + +; CHECK: test: + +; CHECK: BB10_4: +; CHECK-NEXT: movaps %xmm{{.*}}, %xmm{{.*}} +; CHECK-NEXT: addss %xmm{{.*}}, %xmm{{.*}} +; CHECK-NEXT: mulss (%r{{[^,]*}}), %xmm{{.*}} +; CHECK-NEXT: movss %xmm{{.*}}, (%r{{[^,]*}}) +; CHECK-NEXT: addq $4, %r{{.*}} +; CHECK-NEXT: decq %r{{.*}} +; CHECK-NEXT: addq $4, %r{{.*}} +; CHECK-NEXT: movaps %xmm{{.*}}, %xmm{{.*}} +; CHECK-NEXT: BB10_2: +; CHECK-NEXT: testq %r{{.*}}, %r{{.*}} +; CHECK-NEXT: jle +; CHECK-NEXT: testb $15, %r{{.*}} +; CHECK-NEXT: jne + +; And the one at %bb68, where we want to be sure to use superhero mode: + +; CHECK: BB10_10: +; CHECK-NEXT: movaps 48(%r{{[^,]*}}), %xmm{{.*}} +; CHECK-NEXT: mulps %xmm{{.*}}, %xmm{{.*}} +; CHECK-NEXT: movaps 32(%r{{[^,]*}}), %xmm{{.*}} +; CHECK-NEXT: mulps %xmm{{.*}}, %xmm{{.*}} +; CHECK-NEXT: movaps 16(%r{{[^,]*}}), %xmm{{.*}} +; CHECK-NEXT: mulps %xmm{{.*}}, %xmm{{.*}} +; CHECK-NEXT: movaps (%r{{[^,]*}}), %xmm{{.*}} +; CHECK-NEXT: mulps %xmm{{.*}}, %xmm{{.*}} +; CHECK-NEXT: movaps %xmm{{.*}}, (%r{{[^,]*}}) +; CHECK-NEXT: movaps %xmm{{.*}}, 16(%r{{[^,]*}}) +; CHECK-NEXT: movaps %xmm{{.*}}, 32(%r{{[^,]*}}) +; CHECK-NEXT: movaps %xmm{{.*}}, 48(%r{{[^,]*}}) +; CHECK-NEXT: addps %xmm{{.*}}, %xmm{{.*}} +; CHECK-NEXT: addps %xmm{{.*}}, %xmm{{.*}} +; CHECK-NEXT: addps %xmm{{.*}}, %xmm{{.*}} +; CHECK-NEXT: addps %xmm{{.*}}, %xmm{{.*}} +; CHECK-NEXT: addq $64, %r{{.*}} +; CHECK-NEXT: addq $64, %r{{.*}} +; CHECK-NEXT: addq $-16, %r{{.*}} +; CHECK-NEXT: BB10_11: +; CHECK-NEXT: cmpq $15, %r{{.*}} +; CHECK-NEXT: jg + +define void @test(float* %arg, i64 %arg1, float* nocapture %arg2, float* nocapture %arg3, float* %arg4, i64 %arg5, i64 %arg6) nounwind { +bb: + %t = alloca float, align 4 ; <float*> [#uses=3] + %t7 = alloca float, align 4 ; <float*> [#uses=2] + %t8 = load float* %arg3 ; <float> [#uses=8] + %t9 = ptrtoint float* %arg to i64 ; <i64> [#uses=1] + %t10 = ptrtoint float* %arg4 to i64 ; <i64> [#uses=1] + %t11 = xor i64 %t10, %t9 ; <i64> [#uses=1] + %t12 = and i64 %t11, 15 ; <i64> [#uses=1] + %t13 = icmp eq i64 %t12, 0 ; <i1> [#uses=1] + %t14 = xor i64 %arg1, 1 ; <i64> [#uses=1] + %t15 = xor i64 %arg5, 1 ; <i64> [#uses=1] + %t16 = or i64 %t15, %t14 ; <i64> [#uses=1] + %t17 = trunc i64 %t16 to i32 ; <i32> [#uses=1] + %t18 = icmp eq i32 %t17, 0 ; <i1> [#uses=1] + br i1 %t18, label %bb19, label %bb213 + +bb19: ; preds = %bb + %t20 = load float* %arg2 ; <float> [#uses=1] + br label %bb21 + +bb21: ; preds = %bb32, %bb19 + %t22 = phi i64 [ %t36, %bb32 ], [ 0, %bb19 ] ; <i64> [#uses=21] + %t23 = phi float [ %t35, %bb32 ], [ %t20, %bb19 ] ; <float> [#uses=6] + %t24 = sub i64 %arg6, %t22 ; <i64> [#uses=4] + %t25 = getelementptr float* %arg4, i64 %t22 ; <float*> [#uses=4] + %t26 = getelementptr float* %arg, i64 %t22 ; <float*> [#uses=3] + %t27 = icmp sgt i64 %t24, 0 ; <i1> [#uses=1] + br i1 %t27, label %bb28, label %bb37 + +bb28: ; preds = %bb21 + %t29 = ptrtoint float* %t25 to i64 ; <i64> [#uses=1] + %t30 = and i64 %t29, 15 ; <i64> [#uses=1] + %t31 = icmp eq i64 %t30, 0 ; <i1> [#uses=1] + br i1 %t31, label %bb37, label %bb32 + +bb32: ; preds = %bb28 + %t33 = load float* %t26 ; <float> [#uses=1] + %t34 = fmul float %t23, %t33 ; <float> [#uses=1] + store float %t34, float* %t25 + %t35 = fadd float %t23, %t8 ; <float> [#uses=1] + %t36 = add i64 %t22, 1 ; <i64> [#uses=1] + br label %bb21 + +bb37: ; preds = %bb28, %bb21 + %t38 = fmul float %t8, 4.000000e+00 ; <float> [#uses=1] + store float %t38, float* %t + %t39 = fmul float %t8, 1.600000e+01 ; <float> [#uses=1] + store float %t39, float* %t7 + %t40 = fmul float %t8, 0.000000e+00 ; <float> [#uses=1] + %t41 = fadd float %t23, %t40 ; <float> [#uses=1] + %t42 = insertelement <4 x float> undef, float %t41, i32 0 ; <<4 x float>> [#uses=1] + %t43 = fadd float %t23, %t8 ; <float> [#uses=1] + %t44 = insertelement <4 x float> %t42, float %t43, i32 1 ; <<4 x float>> [#uses=1] + %t45 = fmul float %t8, 2.000000e+00 ; <float> [#uses=1] + %t46 = fadd float %t23, %t45 ; <float> [#uses=1] + %t47 = insertelement <4 x float> %t44, float %t46, i32 2 ; <<4 x float>> [#uses=1] + %t48 = fmul float %t8, 3.000000e+00 ; <float> [#uses=1] + %t49 = fadd float %t23, %t48 ; <float> [#uses=1] + %t50 = insertelement <4 x float> %t47, float %t49, i32 3 ; <<4 x float>> [#uses=5] + %t51 = call <4 x float> asm "movss $1, $0\09\0Apshufd $$0, $0, $0", "=x,*m,~{dirflag},~{fpsr},~{flags}"(float* %t) nounwind ; <<4 x float>> [#uses=3] + %t52 = fadd <4 x float> %t50, %t51 ; <<4 x float>> [#uses=3] + %t53 = fadd <4 x float> %t52, %t51 ; <<4 x float>> [#uses=3] + %t54 = fadd <4 x float> %t53, %t51 ; <<4 x float>> [#uses=2] + %t55 = call <4 x float> asm "movss $1, $0\09\0Apshufd $$0, $0, $0", "=x,*m,~{dirflag},~{fpsr},~{flags}"(float* %t7) nounwind ; <<4 x float>> [#uses=8] + %t56 = icmp sgt i64 %t24, 15 ; <i1> [#uses=2] + br i1 %t13, label %bb57, label %bb118 + +bb57: ; preds = %bb37 + br i1 %t56, label %bb61, label %bb112 + +bb58: ; preds = %bb68 + %t59 = getelementptr float* %arg, i64 %t78 ; <float*> [#uses=1] + %t60 = getelementptr float* %arg4, i64 %t78 ; <float*> [#uses=1] + br label %bb112 + +bb61: ; preds = %bb57 + %t62 = add i64 %t22, 16 ; <i64> [#uses=1] + %t63 = add i64 %t22, 4 ; <i64> [#uses=1] + %t64 = add i64 %t22, 8 ; <i64> [#uses=1] + %t65 = add i64 %t22, 12 ; <i64> [#uses=1] + %t66 = add i64 %arg6, -16 ; <i64> [#uses=1] + %t67 = sub i64 %t66, %t22 ; <i64> [#uses=1] + br label %bb68 + +bb68: ; preds = %bb68, %bb61 + %t69 = phi i64 [ 0, %bb61 ], [ %t111, %bb68 ] ; <i64> [#uses=3] + %t70 = phi <4 x float> [ %t54, %bb61 ], [ %t107, %bb68 ] ; <<4 x float>> [#uses=2] + %t71 = phi <4 x float> [ %t50, %bb61 ], [ %t103, %bb68 ] ; <<4 x float>> [#uses=2] + %t72 = phi <4 x float> [ %t53, %bb61 ], [ %t108, %bb68 ] ; <<4 x float>> [#uses=2] + %t73 = phi <4 x float> [ %t52, %bb61 ], [ %t109, %bb68 ] ; <<4 x float>> [#uses=2] + %t74 = shl i64 %t69, 4 ; <i64> [#uses=5] + %t75 = add i64 %t22, %t74 ; <i64> [#uses=2] + %t76 = getelementptr float* %arg, i64 %t75 ; <float*> [#uses=1] + %t77 = bitcast float* %t76 to <4 x float>* ; <<4 x float>*> [#uses=1] + %t78 = add i64 %t62, %t74 ; <i64> [#uses=2] + %t79 = add i64 %t63, %t74 ; <i64> [#uses=2] + %t80 = getelementptr float* %arg, i64 %t79 ; <float*> [#uses=1] + %t81 = bitcast float* %t80 to <4 x float>* ; <<4 x float>*> [#uses=1] + %t82 = add i64 %t64, %t74 ; <i64> [#uses=2] + %t83 = getelementptr float* %arg, i64 %t82 ; <float*> [#uses=1] + %t84 = bitcast float* %t83 to <4 x float>* ; <<4 x float>*> [#uses=1] + %t85 = add i64 %t65, %t74 ; <i64> [#uses=2] + %t86 = getelementptr float* %arg, i64 %t85 ; <float*> [#uses=1] + %t87 = bitcast float* %t86 to <4 x float>* ; <<4 x float>*> [#uses=1] + %t88 = getelementptr float* %arg4, i64 %t75 ; <float*> [#uses=1] + %t89 = bitcast float* %t88 to <4 x float>* ; <<4 x float>*> [#uses=1] + %t90 = getelementptr float* %arg4, i64 %t79 ; <float*> [#uses=1] + %t91 = bitcast float* %t90 to <4 x float>* ; <<4 x float>*> [#uses=1] + %t92 = getelementptr float* %arg4, i64 %t82 ; <float*> [#uses=1] + %t93 = bitcast float* %t92 to <4 x float>* ; <<4 x float>*> [#uses=1] + %t94 = getelementptr float* %arg4, i64 %t85 ; <float*> [#uses=1] + %t95 = bitcast float* %t94 to <4 x float>* ; <<4 x float>*> [#uses=1] + %t96 = mul i64 %t69, -16 ; <i64> [#uses=1] + %t97 = add i64 %t67, %t96 ; <i64> [#uses=2] + %t98 = load <4 x float>* %t77 ; <<4 x float>> [#uses=1] + %t99 = load <4 x float>* %t81 ; <<4 x float>> [#uses=1] + %t100 = load <4 x float>* %t84 ; <<4 x float>> [#uses=1] + %t101 = load <4 x float>* %t87 ; <<4 x float>> [#uses=1] + %t102 = fmul <4 x float> %t98, %t71 ; <<4 x float>> [#uses=1] + %t103 = fadd <4 x float> %t71, %t55 ; <<4 x float>> [#uses=2] + %t104 = fmul <4 x float> %t99, %t73 ; <<4 x float>> [#uses=1] + %t105 = fmul <4 x float> %t100, %t72 ; <<4 x float>> [#uses=1] + %t106 = fmul <4 x float> %t101, %t70 ; <<4 x float>> [#uses=1] + store <4 x float> %t102, <4 x float>* %t89 + store <4 x float> %t104, <4 x float>* %t91 + store <4 x float> %t105, <4 x float>* %t93 + store <4 x float> %t106, <4 x float>* %t95 + %t107 = fadd <4 x float> %t70, %t55 ; <<4 x float>> [#uses=1] + %t108 = fadd <4 x float> %t72, %t55 ; <<4 x float>> [#uses=1] + %t109 = fadd <4 x float> %t73, %t55 ; <<4 x float>> [#uses=1] + %t110 = icmp sgt i64 %t97, 15 ; <i1> [#uses=1] + %t111 = add i64 %t69, 1 ; <i64> [#uses=1] + br i1 %t110, label %bb68, label %bb58 + +bb112: ; preds = %bb58, %bb57 + %t113 = phi float* [ %t59, %bb58 ], [ %t26, %bb57 ] ; <float*> [#uses=1] + %t114 = phi float* [ %t60, %bb58 ], [ %t25, %bb57 ] ; <float*> [#uses=1] + %t115 = phi <4 x float> [ %t103, %bb58 ], [ %t50, %bb57 ] ; <<4 x float>> [#uses=1] + %t116 = phi i64 [ %t97, %bb58 ], [ %t24, %bb57 ] ; <i64> [#uses=1] + %t117 = call <4 x float> asm "movss $1, $0\09\0Apshufd $$0, $0, $0", "=x,*m,~{dirflag},~{fpsr},~{flags}"(float* %t) nounwind ; <<4 x float>> [#uses=0] + br label %bb194 + +bb118: ; preds = %bb37 + br i1 %t56, label %bb122, label %bb194 + +bb119: ; preds = %bb137 + %t120 = getelementptr float* %arg, i64 %t145 ; <float*> [#uses=1] + %t121 = getelementptr float* %arg4, i64 %t145 ; <float*> [#uses=1] + br label %bb194 + +bb122: ; preds = %bb118 + %t123 = add i64 %t22, -1 ; <i64> [#uses=1] + %t124 = getelementptr inbounds float* %arg, i64 %t123 ; <float*> [#uses=1] + %t125 = bitcast float* %t124 to <4 x float>* ; <<4 x float>*> [#uses=1] + %t126 = load <4 x float>* %t125 ; <<4 x float>> [#uses=1] + %t127 = add i64 %t22, 16 ; <i64> [#uses=1] + %t128 = add i64 %t22, 3 ; <i64> [#uses=1] + %t129 = add i64 %t22, 7 ; <i64> [#uses=1] + %t130 = add i64 %t22, 11 ; <i64> [#uses=1] + %t131 = add i64 %t22, 15 ; <i64> [#uses=1] + %t132 = add i64 %t22, 4 ; <i64> [#uses=1] + %t133 = add i64 %t22, 8 ; <i64> [#uses=1] + %t134 = add i64 %t22, 12 ; <i64> [#uses=1] + %t135 = add i64 %arg6, -16 ; <i64> [#uses=1] + %t136 = sub i64 %t135, %t22 ; <i64> [#uses=1] + br label %bb137 + +bb137: ; preds = %bb137, %bb122 + %t138 = phi i64 [ 0, %bb122 ], [ %t193, %bb137 ] ; <i64> [#uses=3] + %t139 = phi <4 x float> [ %t54, %bb122 ], [ %t189, %bb137 ] ; <<4 x float>> [#uses=2] + %t140 = phi <4 x float> [ %t50, %bb122 ], [ %t185, %bb137 ] ; <<4 x float>> [#uses=2] + %t141 = phi <4 x float> [ %t53, %bb122 ], [ %t190, %bb137 ] ; <<4 x float>> [#uses=2] + %t142 = phi <4 x float> [ %t52, %bb122 ], [ %t191, %bb137 ] ; <<4 x float>> [#uses=2] + %t143 = phi <4 x float> [ %t126, %bb122 ], [ %t175, %bb137 ] ; <<4 x float>> [#uses=1] + %t144 = shl i64 %t138, 4 ; <i64> [#uses=9] + %t145 = add i64 %t127, %t144 ; <i64> [#uses=2] + %t146 = add i64 %t128, %t144 ; <i64> [#uses=1] + %t147 = getelementptr float* %arg, i64 %t146 ; <float*> [#uses=1] + %t148 = bitcast float* %t147 to <4 x float>* ; <<4 x float>*> [#uses=1] + %t149 = add i64 %t129, %t144 ; <i64> [#uses=1] + %t150 = getelementptr float* %arg, i64 %t149 ; <float*> [#uses=1] + %t151 = bitcast float* %t150 to <4 x float>* ; <<4 x float>*> [#uses=1] + %t152 = add i64 %t130, %t144 ; <i64> [#uses=1] + %t153 = getelementptr float* %arg, i64 %t152 ; <float*> [#uses=1] + %t154 = bitcast float* %t153 to <4 x float>* ; <<4 x float>*> [#uses=1] + %t155 = add i64 %t131, %t144 ; <i64> [#uses=1] + %t156 = getelementptr float* %arg, i64 %t155 ; <float*> [#uses=1] + %t157 = bitcast float* %t156 to <4 x float>* ; <<4 x float>*> [#uses=1] + %t158 = add i64 %t22, %t144 ; <i64> [#uses=1] + %t159 = getelementptr float* %arg4, i64 %t158 ; <float*> [#uses=1] + %t160 = bitcast float* %t159 to <4 x float>* ; <<4 x float>*> [#uses=1] + %t161 = add i64 %t132, %t144 ; <i64> [#uses=1] + %t162 = getelementptr float* %arg4, i64 %t161 ; <float*> [#uses=1] + %t163 = bitcast float* %t162 to <4 x float>* ; <<4 x float>*> [#uses=1] + %t164 = add i64 %t133, %t144 ; <i64> [#uses=1] + %t165 = getelementptr float* %arg4, i64 %t164 ; <float*> [#uses=1] + %t166 = bitcast float* %t165 to <4 x float>* ; <<4 x float>*> [#uses=1] + %t167 = add i64 %t134, %t144 ; <i64> [#uses=1] + %t168 = getelementptr float* %arg4, i64 %t167 ; <float*> [#uses=1] + %t169 = bitcast float* %t168 to <4 x float>* ; <<4 x float>*> [#uses=1] + %t170 = mul i64 %t138, -16 ; <i64> [#uses=1] + %t171 = add i64 %t136, %t170 ; <i64> [#uses=2] + %t172 = load <4 x float>* %t148 ; <<4 x float>> [#uses=2] + %t173 = load <4 x float>* %t151 ; <<4 x float>> [#uses=2] + %t174 = load <4 x float>* %t154 ; <<4 x float>> [#uses=2] + %t175 = load <4 x float>* %t157 ; <<4 x float>> [#uses=2] + %t176 = shufflevector <4 x float> %t143, <4 x float> %t172, <4 x i32> <i32 4, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1] + %t177 = shufflevector <4 x float> %t176, <4 x float> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 0> ; <<4 x float>> [#uses=1] + %t178 = shufflevector <4 x float> %t172, <4 x float> %t173, <4 x i32> <i32 4, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1] + %t179 = shufflevector <4 x float> %t178, <4 x float> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 0> ; <<4 x float>> [#uses=1] + %t180 = shufflevector <4 x float> %t173, <4 x float> %t174, <4 x i32> <i32 4, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1] + %t181 = shufflevector <4 x float> %t180, <4 x float> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 0> ; <<4 x float>> [#uses=1] + %t182 = shufflevector <4 x float> %t174, <4 x float> %t175, <4 x i32> <i32 4, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1] + %t183 = shufflevector <4 x float> %t182, <4 x float> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 0> ; <<4 x float>> [#uses=1] + %t184 = fmul <4 x float> %t177, %t140 ; <<4 x float>> [#uses=1] + %t185 = fadd <4 x float> %t140, %t55 ; <<4 x float>> [#uses=2] + %t186 = fmul <4 x float> %t179, %t142 ; <<4 x float>> [#uses=1] + %t187 = fmul <4 x float> %t181, %t141 ; <<4 x float>> [#uses=1] + %t188 = fmul <4 x float> %t183, %t139 ; <<4 x float>> [#uses=1] + store <4 x float> %t184, <4 x float>* %t160 + store <4 x float> %t186, <4 x float>* %t163 + store <4 x float> %t187, <4 x float>* %t166 + store <4 x float> %t188, <4 x float>* %t169 + %t189 = fadd <4 x float> %t139, %t55 ; <<4 x float>> [#uses=1] + %t190 = fadd <4 x float> %t141, %t55 ; <<4 x float>> [#uses=1] + %t191 = fadd <4 x float> %t142, %t55 ; <<4 x float>> [#uses=1] + %t192 = icmp sgt i64 %t171, 15 ; <i1> [#uses=1] + %t193 = add i64 %t138, 1 ; <i64> [#uses=1] + br i1 %t192, label %bb137, label %bb119 + +bb194: ; preds = %bb119, %bb118, %bb112 + %t195 = phi i64 [ %t116, %bb112 ], [ %t171, %bb119 ], [ %t24, %bb118 ] ; <i64> [#uses=2] + %t196 = phi <4 x float> [ %t115, %bb112 ], [ %t185, %bb119 ], [ %t50, %bb118 ] ; <<4 x float>> [#uses=1] + %t197 = phi float* [ %t114, %bb112 ], [ %t121, %bb119 ], [ %t25, %bb118 ] ; <float*> [#uses=1] + %t198 = phi float* [ %t113, %bb112 ], [ %t120, %bb119 ], [ %t26, %bb118 ] ; <float*> [#uses=1] + %t199 = extractelement <4 x float> %t196, i32 0 ; <float> [#uses=2] + %t200 = icmp sgt i64 %t195, 0 ; <i1> [#uses=1] + br i1 %t200, label %bb201, label %bb211 + +bb201: ; preds = %bb201, %bb194 + %t202 = phi i64 [ %t209, %bb201 ], [ 0, %bb194 ] ; <i64> [#uses=3] + %t203 = phi float [ %t208, %bb201 ], [ %t199, %bb194 ] ; <float> [#uses=2] + %t204 = getelementptr float* %t198, i64 %t202 ; <float*> [#uses=1] + %t205 = getelementptr float* %t197, i64 %t202 ; <float*> [#uses=1] + %t206 = load float* %t204 ; <float> [#uses=1] + %t207 = fmul float %t203, %t206 ; <float> [#uses=1] + store float %t207, float* %t205 + %t208 = fadd float %t203, %t8 ; <float> [#uses=2] + %t209 = add i64 %t202, 1 ; <i64> [#uses=2] + %t210 = icmp eq i64 %t209, %t195 ; <i1> [#uses=1] + br i1 %t210, label %bb211, label %bb201 + +bb211: ; preds = %bb201, %bb194 + %t212 = phi float [ %t199, %bb194 ], [ %t208, %bb201 ] ; <float> [#uses=1] + store float %t212, float* %arg2 + ret void + +bb213: ; preds = %bb + ret void +} diff --git a/test/CodeGen/X86/memcpy.ll b/test/CodeGen/X86/memcpy.ll index 5a3ae77..7bc31be 100644 --- a/test/CodeGen/X86/memcpy.ll +++ b/test/CodeGen/X86/memcpy.ll @@ -1,17 +1,57 @@ -; RUN: llc < %s -march=x86-64 | grep call.*memcpy | count 2 +; RUN: llc < %s -march=x86-64 | FileCheck %s -declare void @llvm.memcpy.i64(i8*, i8*, i64, i32) +declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind -define i8* @my_memcpy(i8* %a, i8* %b, i64 %n) nounwind { + +; Variable memcpy's should lower to calls. +define i8* @test1(i8* %a, i8* %b, i64 %n) nounwind { entry: - tail call void @llvm.memcpy.i64( i8* %a, i8* %b, i64 %n, i32 1 ) + tail call void @llvm.memcpy.p0i8.p0i8.i64( i8* %a, i8* %b, i64 %n, i32 1, i1 0 ) ret i8* %a + +; CHECK: test1: +; CHECK: memcpy } -define i8* @my_memcpy2(i64* %a, i64* %b, i64 %n) nounwind { +; Variable memcpy's should lower to calls. +define i8* @test2(i64* %a, i64* %b, i64 %n) nounwind { entry: %tmp14 = bitcast i64* %a to i8* %tmp25 = bitcast i64* %b to i8* - tail call void @llvm.memcpy.i64(i8* %tmp14, i8* %tmp25, i64 %n, i32 8 ) + tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp14, i8* %tmp25, i64 %n, i32 8, i1 0 ) ret i8* %tmp14 + +; CHECK: test2: +; CHECK: memcpy +} + +; Large constant memcpy's should lower to a call when optimizing for size. +; PR6623 +define void @test3(i8* nocapture %A, i8* nocapture %B) nounwind optsize noredzone { +entry: + tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %A, i8* %B, i64 64, i32 1, i1 false) + ret void +; CHECK: test3: +; CHECK: memcpy } + +; Large constant memcpy's should be inlined when not optimizing for size. +define void @test4(i8* nocapture %A, i8* nocapture %B) nounwind noredzone { +entry: + tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %A, i8* %B, i64 64, i32 1, i1 false) + ret void +; CHECK: test4: +; CHECK: movq +; CHECK: movq +; CHECK: movq +; CHECK: movq +; CHECK: movq +; CHECK: movq +; CHECK: movq +; CHECK: movq +; CHECK: movq +; CHECK: movq +; CHECK: movq +; CHECK: movq +} + diff --git a/test/CodeGen/X86/object-size.ll b/test/CodeGen/X86/object-size.ll index bbe6b23..0493edc 100644 --- a/test/CodeGen/X86/object-size.ll +++ b/test/CodeGen/X86/object-size.ll @@ -1,4 +1,4 @@ -; RUN: llc -O0 < %s -march=x86-64 | FileCheck %s -check-prefix=X64 +; RUN: llc -O0 -regalloc=linearscan < %s -march=x86-64 | FileCheck %s -check-prefix=X64 ; ModuleID = 'ts.c' target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" diff --git a/test/CodeGen/X86/optimize-max-3.ll b/test/CodeGen/X86/optimize-max-3.ll index bf8bfa2..f1e3c27 100644 --- a/test/CodeGen/X86/optimize-max-3.ll +++ b/test/CodeGen/X86/optimize-max-3.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86-64 | FileCheck %s +; RUN: llc < %s -march=x86-64 -asm-verbose=false | FileCheck %s ; LSR's OptimizeMax should eliminate the select (max). @@ -30,3 +30,47 @@ for.body: ; preds = %for.body.preheader, for.end: ; preds = %for.body, %entry ret void } + +; In this case, one of the max operands is another max, which folds, +; leaving a two-operand max which doesn't fit the usual pattern. +; OptimizeMax should handle this case. +; PR7454 + +; CHECK: _Z18GenerateStatusPagei: + +; CHECK: jle +; CHECK-NOT: cmov +; CHECK: xorl %edi, %edi +; CHECK-NEXT: align +; CHECK-NEXT: BB1_2: +; CHECK-NEXT: callq +; CHECK-NEXT: incl %ebx +; CHECK-NEXT: cmpl %r14d, %ebx +; CHECK-NEXT: movq %rax, %rdi +; CHECK-NEXT: jl + +define void @_Z18GenerateStatusPagei(i32 %jobs_to_display) nounwind { +entry: + %cmp.i = icmp sgt i32 %jobs_to_display, 0 ; <i1> [#uses=1] + %tmp = select i1 %cmp.i, i32 %jobs_to_display, i32 0 ; <i32> [#uses=3] + %cmp8 = icmp sgt i32 %tmp, 0 ; <i1> [#uses=1] + br i1 %cmp8, label %bb.nph, label %for.end + +bb.nph: ; preds = %entry + %tmp11 = icmp sgt i32 %tmp, 1 ; <i1> [#uses=1] + %smax = select i1 %tmp11, i32 %tmp, i32 1 ; <i32> [#uses=1] + br label %for.body + +for.body: ; preds = %for.body, %bb.nph + %i.010 = phi i32 [ 0, %bb.nph ], [ %inc, %for.body ] ; <i32> [#uses=1] + %it.0.09 = phi float* [ null, %bb.nph ], [ %call.i, %for.body ] ; <float*> [#uses=1] + %call.i = call float* @_ZSt18_Rb_tree_decrementPKSt18_Rb_tree_node_base(float* %it.0.09) ; <float*> [#uses=1] + %inc = add nsw i32 %i.010, 1 ; <i32> [#uses=2] + %exitcond = icmp eq i32 %inc, %smax ; <i1> [#uses=1] + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body, %entry + ret void +} + +declare float* @_ZSt18_Rb_tree_decrementPKSt18_Rb_tree_node_base(float*) diff --git a/test/CodeGen/X86/phys-reg-local-regalloc.ll b/test/CodeGen/X86/phys-reg-local-regalloc.ll index 045841e..8b9ea17 100644 --- a/test/CodeGen/X86/phys-reg-local-regalloc.ll +++ b/test/CodeGen/X86/phys-reg-local-regalloc.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=x86 -mtriple=i386-apple-darwin9 -regalloc=local | FileCheck %s -; RUN: llc -O0 < %s -march=x86 -mtriple=i386-apple-darwin9 -regalloc=local | FileCheck %s +; RUN: llc < %s -march=x86 -mtriple=i386-apple-darwin9 -regalloc=fast | FileCheck %s +; RUN: llc -O0 < %s -march=x86 -mtriple=i386-apple-darwin9 -regalloc=fast | FileCheck %s ; CHECKed instructions should be the same with or without -O0. @.str = private constant [12 x i8] c"x + y = %i\0A\00", align 1 ; <[12 x i8]*> [#uses=1] diff --git a/test/CodeGen/X86/pic.ll b/test/CodeGen/X86/pic.ll index 9506c9b..a1a9759 100644 --- a/test/CodeGen/X86/pic.ll +++ b/test/CodeGen/X86/pic.ll @@ -78,8 +78,8 @@ entry: ; LINUX: call .L3$pb ; LINUX-NEXT: .L3$pb: ; LINUX: popl -; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L3$pb), -; LINUX: movl pfoo@GOT(%esi), +; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L3$pb), %[[REG3:e..]] +; LINUX: movl pfoo@GOT(%[[REG3]]), ; LINUX: call afoo@PLT ; LINUX: call * } @@ -189,7 +189,7 @@ bb12: ; LINUX: call .L7$pb ; LINUX: .L7$pb: ; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L7$pb), -; LINUX: addl .LJTI7_0@GOTOFF( +; LINUX: .LJTI7_0@GOTOFF( ; LINUX: jmpl * ; LINUX: .LJTI7_0: diff --git a/test/CodeGen/X86/pr2659.ll b/test/CodeGen/X86/pr2659.ll index 27047df..e5daf5d 100644 --- a/test/CodeGen/X86/pr2659.ll +++ b/test/CodeGen/X86/pr2659.ll @@ -17,7 +17,7 @@ forcond.preheader: ; preds = %entry ; CHECK: %forcond.preheader.forbody_crit_edge ; CHECK: movl $1 ; CHECK-NOT: xorl -; CHECK-NEXT: movl $1 +; CHECK-NEXT: movl ifthen: ; preds = %entry ret i32 0 diff --git a/test/CodeGen/X86/promote-assert-zext.ll b/test/CodeGen/X86/promote-assert-zext.ll new file mode 100644 index 0000000..b582806 --- /dev/null +++ b/test/CodeGen/X86/promote-assert-zext.ll @@ -0,0 +1,22 @@ +; RUN: llc < %s | FileCheck %s +; rdar://8051990 + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin11" + +; ISel doesn't yet know how to eliminate this extra zero-extend. But until +; it knows how to do so safely, it shouldn;t eliminate it. +; CHECK: movzbl (%rdi), %eax +; CHECK: movzwl %ax, %eax + +define i64 @_ZL5matchPKtPKhiR9MatchData(i8* %tmp13) nounwind { +entry: + %tmp14 = load i8* %tmp13, align 1 + %tmp17 = zext i8 %tmp14 to i16 + br label %bb341 + +bb341: + %tmp18 = add i16 %tmp17, -1 + %tmp23 = sext i16 %tmp18 to i64 + ret i64 %tmp23 +} diff --git a/test/CodeGen/X86/shift-folding.ll b/test/CodeGen/X86/shift-folding.ll index 872817f..48ca36c 100644 --- a/test/CodeGen/X86/shift-folding.ll +++ b/test/CodeGen/X86/shift-folding.ll @@ -21,3 +21,8 @@ define i32* @test3(i32* %P, i32 %X) { ret i32* %P2 } +define fastcc i32 @test4(i32* %d) nounwind { + %tmp4 = load i32* %d + %tmp512 = lshr i32 %tmp4, 24 + ret i32 %tmp512 +} diff --git a/test/CodeGen/X86/sibcall-3.ll b/test/CodeGen/X86/sibcall-3.ll new file mode 100644 index 0000000..f0d66cf --- /dev/null +++ b/test/CodeGen/X86/sibcall-3.ll @@ -0,0 +1,16 @@ +; RUN: llc < %s -mtriple=i386-unknown-unknown | FileCheck %s +; PR7193 + +define void @t1(i8* inreg %dst, i8* inreg %src, i8* inreg %len) nounwind { +; CHECK: t1: +; CHECK: call 0 + tail call void null(i8* inreg %dst, i8* inreg %src, i8* inreg %len) nounwind + ret void +} + +define void @t2(i8* inreg %dst, i8* inreg %src, i8* inreg %len) nounwind { +; CHECK: t2: +; CHECK: jmpl + tail call void null(i8* inreg %dst, i8* inreg %src) nounwind + ret void +} diff --git a/test/CodeGen/X86/sink-hoist.ll b/test/CodeGen/X86/sink-hoist.ll index 031c01e..acba528 100644 --- a/test/CodeGen/X86/sink-hoist.ll +++ b/test/CodeGen/X86/sink-hoist.ll @@ -44,26 +44,33 @@ return: ; Sink instructions with dead EFLAGS defs. -; CHECK: zzz: -; CHECK: je -; CHECK-NEXT: orb - -define zeroext i8 @zzz(i8 zeroext %a, i8 zeroext %b) nounwind readnone { -entry: - %tmp = zext i8 %a to i32 ; <i32> [#uses=1] - %tmp2 = icmp eq i8 %a, 0 ; <i1> [#uses=1] - %tmp3 = or i8 %b, -128 ; <i8> [#uses=1] - %tmp4 = and i8 %b, 127 ; <i8> [#uses=1] - %b_addr.0 = select i1 %tmp2, i8 %tmp4, i8 %tmp3 ; <i8> [#uses=1] - ret i8 %b_addr.0 -} +; FIXME: Unfail the zzz test if we can correctly mark pregs with the kill flag. +; +; See <rdar://problem/8030636>. This test isn't valid after we made machine +; sinking more conservative about sinking instructions that define a preg into a +; block when we don't know if the preg is killed within the current block. + + +; FIXMEHECK: zzz: +; FIXMEHECK: je +; FIXMEHECK-NEXT: orb + +; define zeroext i8 @zzz(i8 zeroext %a, i8 zeroext %b) nounwind readnone { +; entry: +; %tmp = zext i8 %a to i32 ; <i32> [#uses=1] +; %tmp2 = icmp eq i8 %a, 0 ; <i1> [#uses=1] +; %tmp3 = or i8 %b, -128 ; <i8> [#uses=1] +; %tmp4 = and i8 %b, 127 ; <i8> [#uses=1] +; %b_addr.0 = select i1 %tmp2, i8 %tmp4, i8 %tmp3 ; <i8> [#uses=1] +; ret i8 %b_addr.0 +; } ; Codegen should hoist and CSE these constants. ; CHECK: vv: -; CHECK: LCPI3_0(%rip), %xmm0 -; CHECK: LCPI3_1(%rip), %xmm1 -; CHECK: LCPI3_2(%rip), %xmm2 +; CHECK: LCPI2_0(%rip), %xmm0 +; CHECK: LCPI2_1(%rip), %xmm1 +; CHECK: LCPI2_2(%rip), %xmm2 ; CHECK: align ; CHECK-NOT: LCPI ; CHECK: ret diff --git a/test/CodeGen/X86/sse-commute.ll b/test/CodeGen/X86/sse-commute.ll new file mode 100644 index 0000000..38ed644 --- /dev/null +++ b/test/CodeGen/X86/sse-commute.ll @@ -0,0 +1,20 @@ +; RUN: llc -march=x86-64 < %s | FileCheck %s + +; Commute the comparison to avoid a move. +; PR7500. + +; CHECK: a: +; CHECK-NOT: mov +; CHECK: pcmpeqd +define <2 x double> @a(<2 x double>, <2 x double>) nounwind readnone { +entry: + %tmp6 = bitcast <2 x double> %0 to <4 x i32> ; <<4 x i32>> [#uses=2] + %tmp4 = bitcast <2 x double> %1 to <4 x i32> ; <<4 x i32>> [#uses=1] + %cmp = icmp eq <4 x i32> %tmp6, %tmp4 ; <<4 x i1>> [#uses=1] + %sext = sext <4 x i1> %cmp to <4 x i32> ; <<4 x i32>> [#uses=1] + %and = and <4 x i32> %tmp6, %sext ; <<4 x i32>> [#uses=1] + %tmp8 = bitcast <4 x i32> %and to <2 x double> ; <<2 x double>> [#uses=1] + ret <2 x double> %tmp8 +} + + diff --git a/test/CodeGen/X86/sse-minmax.ll b/test/CodeGen/X86/sse-minmax.ll index 19fbed0..d265bd7 100644 --- a/test/CodeGen/X86/sse-minmax.ll +++ b/test/CodeGen/X86/sse-minmax.ll @@ -44,15 +44,15 @@ define double @olt(double %x, double %y) nounwind { ; CHECK: ogt_inverse: ; CHECK-NEXT: minsd %xmm0, %xmm1 -; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; CHECK-NEXT: ret ; UNSAFE: ogt_inverse: ; UNSAFE-NEXT: minsd %xmm0, %xmm1 -; UNSAFE-NEXT: movapd %xmm1, %xmm0 +; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; UNSAFE-NEXT: ret ; FINITE: ogt_inverse: ; FINITE-NEXT: minsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 +; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; FINITE-NEXT: ret define double @ogt_inverse(double %x, double %y) nounwind { %c = fcmp ogt double %x, %y @@ -62,15 +62,15 @@ define double @ogt_inverse(double %x, double %y) nounwind { ; CHECK: olt_inverse: ; CHECK-NEXT: maxsd %xmm0, %xmm1 -; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; CHECK-NEXT: ret ; UNSAFE: olt_inverse: ; UNSAFE-NEXT: maxsd %xmm0, %xmm1 -; UNSAFE-NEXT: movapd %xmm1, %xmm0 +; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; UNSAFE-NEXT: ret ; FINITE: olt_inverse: ; FINITE-NEXT: maxsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 +; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; FINITE-NEXT: ret define double @olt_inverse(double %x, double %y) nounwind { %c = fcmp olt double %x, %y @@ -108,11 +108,11 @@ define double @ole(double %x, double %y) nounwind { ; CHECK-NEXT: ucomisd %xmm1, %xmm0 ; UNSAFE: oge_inverse: ; UNSAFE-NEXT: minsd %xmm0, %xmm1 -; UNSAFE-NEXT: movapd %xmm1, %xmm0 +; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; UNSAFE-NEXT: ret ; FINITE: oge_inverse: ; FINITE-NEXT: minsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 +; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; FINITE-NEXT: ret define double @oge_inverse(double %x, double %y) nounwind { %c = fcmp oge double %x, %y @@ -124,11 +124,11 @@ define double @oge_inverse(double %x, double %y) nounwind { ; CHECK-NEXT: ucomisd %xmm0, %xmm1 ; UNSAFE: ole_inverse: ; UNSAFE-NEXT: maxsd %xmm0, %xmm1 -; UNSAFE-NEXT: movapd %xmm1, %xmm0 +; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; UNSAFE-NEXT: ret ; FINITE: ole_inverse: ; FINITE-NEXT: maxsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 +; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; FINITE-NEXT: ret define double @ole_inverse(double %x, double %y) nounwind { %c = fcmp ole double %x, %y @@ -175,17 +175,17 @@ define double @x_olt(double %x) nounwind { ; CHECK: x_ogt_inverse: ; CHECK-NEXT: pxor %xmm1, %xmm1 ; CHECK-NEXT: minsd %xmm0, %xmm1 -; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; CHECK-NEXT: ret ; UNSAFE: x_ogt_inverse: ; UNSAFE-NEXT: pxor %xmm1, %xmm1 ; UNSAFE-NEXT: minsd %xmm0, %xmm1 -; UNSAFE-NEXT: movapd %xmm1, %xmm0 +; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; UNSAFE-NEXT: ret ; FINITE: x_ogt_inverse: ; FINITE-NEXT: pxor %xmm1, %xmm1 ; FINITE-NEXT: minsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 +; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; FINITE-NEXT: ret define double @x_ogt_inverse(double %x) nounwind { %c = fcmp ogt double %x, 0.000000e+00 @@ -196,17 +196,17 @@ define double @x_ogt_inverse(double %x) nounwind { ; CHECK: x_olt_inverse: ; CHECK-NEXT: pxor %xmm1, %xmm1 ; CHECK-NEXT: maxsd %xmm0, %xmm1 -; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; CHECK-NEXT: ret ; UNSAFE: x_olt_inverse: ; UNSAFE-NEXT: pxor %xmm1, %xmm1 ; UNSAFE-NEXT: maxsd %xmm0, %xmm1 -; UNSAFE-NEXT: movapd %xmm1, %xmm0 +; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; UNSAFE-NEXT: ret ; FINITE: x_olt_inverse: ; FINITE-NEXT: pxor %xmm1, %xmm1 ; FINITE-NEXT: maxsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 +; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; FINITE-NEXT: ret define double @x_olt_inverse(double %x) nounwind { %c = fcmp olt double %x, 0.000000e+00 @@ -251,12 +251,12 @@ define double @x_ole(double %x) nounwind { ; UNSAFE: x_oge_inverse: ; UNSAFE-NEXT: pxor %xmm1, %xmm1 ; UNSAFE-NEXT: minsd %xmm0, %xmm1 -; UNSAFE-NEXT: movapd %xmm1, %xmm0 +; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; UNSAFE-NEXT: ret ; FINITE: x_oge_inverse: ; FINITE-NEXT: pxor %xmm1, %xmm1 ; FINITE-NEXT: minsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 +; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; FINITE-NEXT: ret define double @x_oge_inverse(double %x) nounwind { %c = fcmp oge double %x, 0.000000e+00 @@ -269,12 +269,12 @@ define double @x_oge_inverse(double %x) nounwind { ; UNSAFE: x_ole_inverse: ; UNSAFE-NEXT: pxor %xmm1, %xmm1 ; UNSAFE-NEXT: maxsd %xmm0, %xmm1 -; UNSAFE-NEXT: movapd %xmm1, %xmm0 +; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; UNSAFE-NEXT: ret ; FINITE: x_ole_inverse: ; FINITE-NEXT: pxor %xmm1, %xmm1 ; FINITE-NEXT: maxsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 +; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; FINITE-NEXT: ret define double @x_ole_inverse(double %x) nounwind { %c = fcmp ole double %x, 0.000000e+00 @@ -314,11 +314,11 @@ define double @ult(double %x, double %y) nounwind { ; CHECK: ucomisd %xmm0, %xmm1 ; UNSAFE: ugt_inverse: ; UNSAFE-NEXT: minsd %xmm0, %xmm1 -; UNSAFE-NEXT: movapd %xmm1, %xmm0 +; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; UNSAFE-NEXT: ret ; FINITE: ugt_inverse: ; FINITE-NEXT: minsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 +; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; FINITE-NEXT: ret define double @ugt_inverse(double %x, double %y) nounwind { %c = fcmp ugt double %x, %y @@ -330,11 +330,11 @@ define double @ugt_inverse(double %x, double %y) nounwind { ; CHECK: ucomisd %xmm1, %xmm0 ; UNSAFE: ult_inverse: ; UNSAFE-NEXT: maxsd %xmm0, %xmm1 -; UNSAFE-NEXT: movapd %xmm1, %xmm0 +; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; UNSAFE-NEXT: ret ; FINITE: ult_inverse: ; FINITE-NEXT: maxsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 +; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; FINITE-NEXT: ret define double @ult_inverse(double %x, double %y) nounwind { %c = fcmp ult double %x, %y @@ -344,7 +344,7 @@ define double @ult_inverse(double %x, double %y) nounwind { ; CHECK: uge: ; CHECK-NEXT: maxsd %xmm0, %xmm1 -; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; CHECK-NEXT: ret ; UNSAFE: uge: ; UNSAFE-NEXT: maxsd %xmm1, %xmm0 @@ -360,7 +360,7 @@ define double @uge(double %x, double %y) nounwind { ; CHECK: ule: ; CHECK-NEXT: minsd %xmm0, %xmm1 -; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; CHECK-NEXT: ret ; UNSAFE: ule: ; UNSAFE-NEXT: minsd %xmm1, %xmm0 @@ -379,11 +379,11 @@ define double @ule(double %x, double %y) nounwind { ; CHECK-NEXT: ret ; UNSAFE: uge_inverse: ; UNSAFE-NEXT: minsd %xmm0, %xmm1 -; UNSAFE-NEXT: movapd %xmm1, %xmm0 +; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; UNSAFE-NEXT: ret ; FINITE: uge_inverse: ; FINITE-NEXT: minsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 +; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; FINITE-NEXT: ret define double @uge_inverse(double %x, double %y) nounwind { %c = fcmp uge double %x, %y @@ -396,11 +396,11 @@ define double @uge_inverse(double %x, double %y) nounwind { ; CHECK-NEXT: ret ; UNSAFE: ule_inverse: ; UNSAFE-NEXT: maxsd %xmm0, %xmm1 -; UNSAFE-NEXT: movapd %xmm1, %xmm0 +; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; UNSAFE-NEXT: ret ; FINITE: ule_inverse: ; FINITE-NEXT: maxsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 +; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; FINITE-NEXT: ret define double @ule_inverse(double %x, double %y) nounwind { %c = fcmp ule double %x, %y @@ -445,12 +445,12 @@ define double @x_ult(double %x) nounwind { ; UNSAFE: x_ugt_inverse: ; UNSAFE-NEXT: pxor %xmm1, %xmm1 ; UNSAFE-NEXT: minsd %xmm0, %xmm1 -; UNSAFE-NEXT: movapd %xmm1, %xmm0 +; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; UNSAFE-NEXT: ret ; FINITE: x_ugt_inverse: ; FINITE-NEXT: pxor %xmm1, %xmm1 ; FINITE-NEXT: minsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 +; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; FINITE-NEXT: ret define double @x_ugt_inverse(double %x) nounwind { %c = fcmp ugt double %x, 0.000000e+00 @@ -463,12 +463,12 @@ define double @x_ugt_inverse(double %x) nounwind { ; UNSAFE: x_ult_inverse: ; UNSAFE-NEXT: pxor %xmm1, %xmm1 ; UNSAFE-NEXT: maxsd %xmm0, %xmm1 -; UNSAFE-NEXT: movapd %xmm1, %xmm0 +; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; UNSAFE-NEXT: ret ; FINITE: x_ult_inverse: ; FINITE-NEXT: pxor %xmm1, %xmm1 ; FINITE-NEXT: maxsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 +; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; FINITE-NEXT: ret define double @x_ult_inverse(double %x) nounwind { %c = fcmp ult double %x, 0.000000e+00 @@ -479,7 +479,7 @@ define double @x_ult_inverse(double %x) nounwind { ; CHECK: x_uge: ; CHECK-NEXT: pxor %xmm1, %xmm1 ; CHECK-NEXT: maxsd %xmm0, %xmm1 -; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; CHECK-NEXT: ret ; UNSAFE: x_uge: ; UNSAFE-NEXT: pxor %xmm1, %xmm1 @@ -498,7 +498,7 @@ define double @x_uge(double %x) nounwind { ; CHECK: x_ule: ; CHECK-NEXT: pxor %xmm1, %xmm1 ; CHECK-NEXT: minsd %xmm0, %xmm1 -; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; CHECK-NEXT: ret ; UNSAFE: x_ule: ; UNSAFE-NEXT: pxor %xmm1, %xmm1 @@ -521,12 +521,12 @@ define double @x_ule(double %x) nounwind { ; UNSAFE: x_uge_inverse: ; UNSAFE-NEXT: pxor %xmm1, %xmm1 ; UNSAFE-NEXT: minsd %xmm0, %xmm1 -; UNSAFE-NEXT: movapd %xmm1, %xmm0 +; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; UNSAFE-NEXT: ret ; FINITE: x_uge_inverse: ; FINITE-NEXT: pxor %xmm1, %xmm1 ; FINITE-NEXT: minsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 +; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; FINITE-NEXT: ret define double @x_uge_inverse(double %x) nounwind { %c = fcmp uge double %x, 0.000000e+00 @@ -541,12 +541,12 @@ define double @x_uge_inverse(double %x) nounwind { ; UNSAFE: x_ule_inverse: ; UNSAFE-NEXT: pxor %xmm1, %xmm1 ; UNSAFE-NEXT: maxsd %xmm0, %xmm1 -; UNSAFE-NEXT: movapd %xmm1, %xmm0 +; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; UNSAFE-NEXT: ret ; FINITE: x_ule_inverse: ; FINITE-NEXT: pxor %xmm1, %xmm1 ; FINITE-NEXT: maxsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 +; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; FINITE-NEXT: ret define double @x_ule_inverse(double %x) nounwind { %c = fcmp ule double %x, 0.000000e+00 @@ -587,17 +587,17 @@ define double @y_olt(double %x) nounwind { ; CHECK: y_ogt_inverse: ; CHECK-NEXT: movsd {{[^,]*}}, %xmm1 ; CHECK-NEXT: minsd %xmm0, %xmm1 -; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; CHECK-NEXT: ret ; UNSAFE: y_ogt_inverse: ; UNSAFE-NEXT: movsd {{[^,]*}}, %xmm1 ; UNSAFE-NEXT: minsd %xmm0, %xmm1 -; UNSAFE-NEXT: movapd %xmm1, %xmm0 +; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; UNSAFE-NEXT: ret ; FINITE: y_ogt_inverse: ; FINITE-NEXT: movsd {{[^,]*}}, %xmm1 ; FINITE-NEXT: minsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 +; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; FINITE-NEXT: ret define double @y_ogt_inverse(double %x) nounwind { %c = fcmp ogt double %x, -0.000000e+00 @@ -608,17 +608,17 @@ define double @y_ogt_inverse(double %x) nounwind { ; CHECK: y_olt_inverse: ; CHECK-NEXT: movsd {{[^,]*}}, %xmm1 ; CHECK-NEXT: maxsd %xmm0, %xmm1 -; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; CHECK-NEXT: ret ; UNSAFE: y_olt_inverse: ; UNSAFE-NEXT: movsd {{[^,]*}}, %xmm1 ; UNSAFE-NEXT: maxsd %xmm0, %xmm1 -; UNSAFE-NEXT: movapd %xmm1, %xmm0 +; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; UNSAFE-NEXT: ret ; FINITE: y_olt_inverse: ; FINITE-NEXT: movsd {{[^,]*}}, %xmm1 ; FINITE-NEXT: maxsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 +; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; FINITE-NEXT: ret define double @y_olt_inverse(double %x) nounwind { %c = fcmp olt double %x, -0.000000e+00 @@ -659,12 +659,12 @@ define double @y_ole(double %x) nounwind { ; UNSAFE: y_oge_inverse: ; UNSAFE-NEXT: movsd {{[^,]*}}, %xmm1 ; UNSAFE-NEXT: minsd %xmm0, %xmm1 -; UNSAFE-NEXT: movapd %xmm1, %xmm0 +; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; UNSAFE-NEXT: ret ; FINITE: y_oge_inverse: ; FINITE-NEXT: movsd {{[^,]*}}, %xmm1 ; FINITE-NEXT: minsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 +; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; FINITE-NEXT: ret define double @y_oge_inverse(double %x) nounwind { %c = fcmp oge double %x, -0.000000e+00 @@ -677,12 +677,12 @@ define double @y_oge_inverse(double %x) nounwind { ; UNSAFE: y_ole_inverse: ; UNSAFE-NEXT: movsd {{[^,]*}}, %xmm1 ; UNSAFE-NEXT: maxsd %xmm0, %xmm1 -; UNSAFE-NEXT: movapd %xmm1, %xmm0 +; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; UNSAFE-NEXT: ret ; FINITE: y_ole_inverse: ; FINITE-NEXT: movsd {{[^,]*}}, %xmm1 ; FINITE-NEXT: maxsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 +; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; FINITE-NEXT: ret define double @y_ole_inverse(double %x) nounwind { %c = fcmp ole double %x, -0.000000e+00 @@ -723,12 +723,12 @@ define double @y_ult(double %x) nounwind { ; UNSAFE: y_ugt_inverse: ; UNSAFE-NEXT: movsd {{[^,]*}}, %xmm1 ; UNSAFE-NEXT: minsd %xmm0, %xmm1 -; UNSAFE-NEXT: movapd %xmm1, %xmm0 +; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; UNSAFE-NEXT: ret ; FINITE: y_ugt_inverse: ; FINITE-NEXT: movsd {{[^,]*}}, %xmm1 ; FINITE-NEXT: minsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 +; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; FINITE-NEXT: ret define double @y_ugt_inverse(double %x) nounwind { %c = fcmp ugt double %x, -0.000000e+00 @@ -741,12 +741,12 @@ define double @y_ugt_inverse(double %x) nounwind { ; UNSAFE: y_ult_inverse: ; UNSAFE-NEXT: movsd {{[^,]*}}, %xmm1 ; UNSAFE-NEXT: maxsd %xmm0, %xmm1 -; UNSAFE-NEXT: movapd %xmm1, %xmm0 +; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; UNSAFE-NEXT: ret ; FINITE: y_ult_inverse: ; FINITE-NEXT: movsd {{[^,]*}}, %xmm1 ; FINITE-NEXT: maxsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 +; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; FINITE-NEXT: ret define double @y_ult_inverse(double %x) nounwind { %c = fcmp ult double %x, -0.000000e+00 @@ -757,7 +757,7 @@ define double @y_ult_inverse(double %x) nounwind { ; CHECK: y_uge: ; CHECK-NEXT: movsd {{[^,]*}}, %xmm1 ; CHECK-NEXT: maxsd %xmm0, %xmm1 -; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; CHECK-NEXT: ret ; UNSAFE: y_uge: ; UNSAFE-NEXT: maxsd {{[^,]*}}, %xmm0 @@ -774,7 +774,7 @@ define double @y_uge(double %x) nounwind { ; CHECK: y_ule: ; CHECK-NEXT: movsd {{[^,]*}}, %xmm1 ; CHECK-NEXT: minsd %xmm0, %xmm1 -; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; CHECK-NEXT: ret ; UNSAFE: y_ule: ; UNSAFE-NEXT: minsd {{[^,]*}}, %xmm0 @@ -794,12 +794,12 @@ define double @y_ule(double %x) nounwind { ; UNSAFE: y_uge_inverse: ; UNSAFE-NEXT: movsd {{[^,]*}}, %xmm1 ; UNSAFE-NEXT: minsd %xmm0, %xmm1 -; UNSAFE-NEXT: movapd %xmm1, %xmm0 +; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; UNSAFE-NEXT: ret ; FINITE: y_uge_inverse: ; FINITE-NEXT: movsd {{[^,]*}}, %xmm1 ; FINITE-NEXT: minsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 +; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; FINITE-NEXT: ret define double @y_uge_inverse(double %x) nounwind { %c = fcmp uge double %x, -0.000000e+00 @@ -813,12 +813,12 @@ define double @y_uge_inverse(double %x) nounwind { ; UNSAFE: y_ule_inverse: ; UNSAFE-NEXT: movsd {{[^,]*}}, %xmm1 ; UNSAFE-NEXT: maxsd %xmm0, %xmm1 -; UNSAFE-NEXT: movapd %xmm1, %xmm0 +; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; UNSAFE-NEXT: ret ; FINITE: y_ule_inverse: ; FINITE-NEXT: movsd {{[^,]*}}, %xmm1 ; FINITE-NEXT: maxsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 +; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0 ; FINITE-NEXT: ret define double @y_ule_inverse(double %x) nounwind { %c = fcmp ule double %x, -0.000000e+00 diff --git a/test/CodeGen/X86/sse3.ll b/test/CodeGen/X86/sse3.ll index b969ecb..206cdff 100644 --- a/test/CodeGen/X86/sse3.ll +++ b/test/CodeGen/X86/sse3.ll @@ -63,10 +63,10 @@ define <8 x i16> @t4(<8 x i16> %A, <8 x i16> %B) nounwind { ret <8 x i16> %tmp ; X64: t4: ; X64: pextrw $7, %xmm0, %eax -; X64: pshufhw $100, %xmm0, %xmm2 -; X64: pinsrw $1, %eax, %xmm2 +; X64: pshufhw $100, %xmm0, %xmm1 +; X64: pinsrw $1, %eax, %xmm1 ; X64: pextrw $1, %xmm0, %eax -; X64: movdqa %xmm2, %xmm0 +; X64: movdqa %xmm1, %xmm0 ; X64: pinsrw $4, %eax, %xmm0 ; X64: ret } diff --git a/test/CodeGen/X86/stack-align.ll b/test/CodeGen/X86/stack-align.ll index 271ad1a..8ca0b12 100644 --- a/test/CodeGen/X86/stack-align.ll +++ b/test/CodeGen/X86/stack-align.ll @@ -9,14 +9,15 @@ target triple = "i686-apple-darwin8" define void @test({ double, double }* byval %z, double* %P) { entry: + %tmp3 = load double* @G, align 16 ; <double> [#uses=1] + %tmp4 = tail call double @fabs( double %tmp3 ) ; <double> [#uses=1] + volatile store double %tmp4, double* %P %tmp = getelementptr { double, double }* %z, i32 0, i32 0 ; <double*> [#uses=1] - %tmp1 = load double* %tmp, align 8 ; <double> [#uses=1] + %tmp1 = volatile load double* %tmp, align 8 ; <double> [#uses=1] %tmp2 = tail call double @fabs( double %tmp1 ) ; <double> [#uses=1] ; CHECK: andpd{{.*}}4(%esp), %xmm - %tmp3 = load double* @G, align 16 ; <double> [#uses=1] - %tmp4 = tail call double @fabs( double %tmp3 ) ; <double> [#uses=1] %tmp6 = fadd double %tmp4, %tmp2 ; <double> [#uses=1] - store double %tmp6, double* %P, align 8 + volatile store double %tmp6, double* %P, align 8 ret void } diff --git a/test/CodeGen/X86/stack-protector-linux.ll b/test/CodeGen/X86/stack-protector-linux.ll new file mode 100644 index 0000000..fe2a9c5 --- /dev/null +++ b/test/CodeGen/X86/stack-protector-linux.ll @@ -0,0 +1,28 @@ +; RUN: llc -mtriple=i386-pc-linux-gnu < %s -o - | grep %gs: +; RUN: llc -mtriple=x86_64-pc-linux-gnu < %s -o - | grep %fs: +; RUN: llc -code-model=kernel -mtriple=x86_64-pc-linux-gnu < %s -o - | grep %gs: +; RUN: llc -mtriple=x86_64-apple-darwin < %s -o - | grep {__stack_chk_guard} +; RUN: llc -mtriple=x86_64-apple-darwin < %s -o - | grep {__stack_chk_fail} + +@"\01LC" = internal constant [11 x i8] c"buf == %s\0A\00" ; <[11 x i8]*> [#uses=1] + +define void @test(i8* %a) nounwind ssp { +entry: + %a_addr = alloca i8* ; <i8**> [#uses=2] + %buf = alloca [8 x i8] ; <[8 x i8]*> [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] + store i8* %a, i8** %a_addr + %buf1 = bitcast [8 x i8]* %buf to i8* ; <i8*> [#uses=1] + %0 = load i8** %a_addr, align 4 ; <i8*> [#uses=1] + %1 = call i8* @strcpy(i8* %buf1, i8* %0) nounwind ; <i8*> [#uses=0] + %buf2 = bitcast [8 x i8]* %buf to i8* ; <i8*> [#uses=1] + %2 = call i32 (i8*, ...)* @printf(i8* getelementptr ([11 x i8]* @"\01LC", i32 0, i32 0), i8* %buf2) nounwind ; <i32> [#uses=0] + br label %return + +return: ; preds = %entry + ret void +} + +declare i8* @strcpy(i8*, i8*) nounwind + +declare i32 @printf(i8*, ...) nounwind diff --git a/test/CodeGen/X86/store-narrow.ll b/test/CodeGen/X86/store-narrow.ll index b1100fa..5682e7c 100644 --- a/test/CodeGen/X86/store-narrow.ll +++ b/test/CodeGen/X86/store-narrow.ll @@ -67,7 +67,7 @@ entry: ; X64: movw %si, 2(%rdi) ; X32: test4: -; X32: movzwl 8(%esp), %eax +; X32: movl 8(%esp), %eax ; X32: movw %ax, 2(%{{.*}}) } diff --git a/test/CodeGen/X86/switch-bt.ll b/test/CodeGen/X86/switch-bt.ll new file mode 100644 index 0000000..ed3266e --- /dev/null +++ b/test/CodeGen/X86/switch-bt.ll @@ -0,0 +1,51 @@ +; RUN: llc -march=x86-64 -asm-verbose=false < %s | FileCheck %s + +; This switch should use bit tests, and the third bit test case is just +; testing for one possible value, so it doesn't need a bt. + +; CHECK: movabsq $2305843009482129440, %r +; CHECK-NEXT: btq %rax, %r +; CHECK-NEXT: jb +; CHECK-NEXT: movl $671088640, %e +; CHECK-NEXT: btq %rax, %r +; CHECK-NEXT: jb +; CHECK-NEXT: testq %rax, %r +; CHECK-NEXT: j + +define void @test(i8* %l) nounwind { +entry: + %l.addr = alloca i8*, align 8 ; <i8**> [#uses=2] + store i8* %l, i8** %l.addr + %tmp = load i8** %l.addr ; <i8*> [#uses=1] + %tmp1 = load i8* %tmp ; <i8> [#uses=1] + %conv = sext i8 %tmp1 to i32 ; <i32> [#uses=1] + switch i32 %conv, label %sw.default [ + i32 62, label %sw.bb + i32 60, label %sw.bb + i32 38, label %sw.bb2 + i32 94, label %sw.bb2 + i32 61, label %sw.bb2 + i32 33, label %sw.bb4 + ] + +sw.bb: ; preds = %entry, %entry + call void @foo(i32 0) + br label %sw.epilog + +sw.bb2: ; preds = %entry, %entry, %entry + call void @foo(i32 1) + br label %sw.epilog + +sw.bb4: ; preds = %entry + call void @foo(i32 3) + br label %sw.epilog + +sw.default: ; preds = %entry + call void @foo(i32 97) + br label %sw.epilog + +sw.epilog: ; preds = %sw.default, %sw.bb4, %sw.bb2, %sw.bb + ret void +} + +declare void @foo(i32) diff --git a/test/CodeGen/X86/tailcallstack64.ll b/test/CodeGen/X86/tailcallstack64.ll index d05dff8..107bdf9 100644 --- a/test/CodeGen/X86/tailcallstack64.ll +++ b/test/CodeGen/X86/tailcallstack64.ll @@ -2,9 +2,11 @@ ; Check that lowered arguments on the stack do not overwrite each other. ; Add %in1 %p1 to a different temporary register (%eax). -; CHECK: movl %edi, %eax +; CHECK: movl 32(%rsp), %eax ; Move param %in1 to temp register (%r10d). ; CHECK: movl 40(%rsp), %r10d +; Add %in1 %p1 to a different temporary register (%eax). +; CHECK: addl %edi, %eax ; Move param %in2 to stack. ; CHECK: movl %r10d, 32(%rsp) ; Move result of addition to stack. diff --git a/test/CodeGen/X86/tls-1.ll b/test/CodeGen/X86/tls-1.ll index 5f6cbe0..de694d8 100644 --- a/test/CodeGen/X86/tls-1.ll +++ b/test/CodeGen/X86/tls-1.ll @@ -7,13 +7,13 @@ ; CHECK: .section __DATA,__thread_vars,thread_local_variables ; CHECK: .globl _a ; CHECK: _a: -; CHECK: .quad ___tlv_bootstrap +; CHECK: .quad __tlv_bootstrap ; CHECK: .quad 0 ; CHECK: .quad _a$tlv$init ; CHECK: .tbss _b$tlv$init, 4, 2 ; CHECK: .globl _b ; CHECK: _b: -; CHECK: .quad ___tlv_bootstrap +; CHECK: .quad __tlv_bootstrap ; CHECK: .quad 0 ; CHECK: .quad _b$tlv$init diff --git a/test/CodeGen/X86/v-binop-widen.ll b/test/CodeGen/X86/v-binop-widen.ll new file mode 100644 index 0000000..3bee700 --- /dev/null +++ b/test/CodeGen/X86/v-binop-widen.ll @@ -0,0 +1,12 @@ +; RUN: llc -march=x86 -mattr=+sse < %s | FileCheck %s +; CHECK: divss +; CHECK: divps +; CHECK: divps + +%vec = type <9 x float> +define %vec @vecdiv( %vec %p1, %vec %p2) +{ + %result = fdiv %vec %p1, %p2 + ret %vec %result +} + diff --git a/test/CodeGen/X86/v-binop-widen2.ll b/test/CodeGen/X86/v-binop-widen2.ll new file mode 100644 index 0000000..ae3f55a --- /dev/null +++ b/test/CodeGen/X86/v-binop-widen2.ll @@ -0,0 +1,40 @@ +; RUN: llc -march=x86 -mattr=+sse < %s | FileCheck %s + +%vec = type <6 x float> +; CHECK: divss +; CHECK: divss +; CHECK: divps +define %vec @vecdiv( %vec %p1, %vec %p2) +{ + %result = fdiv %vec %p1, %p2 + ret %vec %result +} + +@a = constant %vec < float 2.0, float 4.0, float 8.0, float 16.0, float 32.0, float 64.0 > +@b = constant %vec < float 2.0, float 2.0, float 2.0, float 2.0, float 2.0, float 2.0 > + +; Expected result: < 1.0, 2.0, 4.0, ..., 2.0^(n-1) > +; main() returns 0 if the result is expected and 1 otherwise +; to execute, use llvm-as < %s | lli +define i32 @main() nounwind { +entry: + %avec = load %vec* @a + %bvec = load %vec* @b + + %res = call %vec @vecdiv(%vec %avec, %vec %bvec) + br label %loop +loop: + %idx = phi i32 [0, %entry], [%nextInd, %looptail] + %expected = phi float [1.0, %entry], [%nextExpected, %looptail] + %elem = extractelement %vec %res, i32 %idx + %expcmp = fcmp oeq float %elem, %expected + br i1 %expcmp, label %looptail, label %return +looptail: + %nextExpected = fmul float %expected, 2.0 + %nextInd = add i32 %idx, 1 + %cmp = icmp slt i32 %nextInd, 6 + br i1 %cmp, label %loop, label %return +return: + %retval = phi i32 [0, %looptail], [1, %loop] + ret i32 %retval +} diff --git a/test/CodeGen/X86/v2f32.ll b/test/CodeGen/X86/v2f32.ll new file mode 100644 index 0000000..9c4b773 --- /dev/null +++ b/test/CodeGen/X86/v2f32.ll @@ -0,0 +1,39 @@ +; RUN: llc < %s -march=x86-64 -mcpu=penryn -asm-verbose=0 -o - | FileCheck %s -check-prefix=X64 +; RUN: llc < %s -mcpu=yonah -march=x86 -asm-verbose=0 -o - | FileCheck %s -check-prefix=X32 + +; PR7518 +define void @test1(<2 x float> %Q, float *%P2) nounwind { + %a = extractelement <2 x float> %Q, i32 0 + %b = extractelement <2 x float> %Q, i32 1 + %c = fadd float %a, %b + + store float %c, float* %P2 + ret void +; X64: test1: +; X64-NEXT: addss %xmm1, %xmm0 +; X64-NEXT: movss %xmm0, (%rdi) +; X64-NEXT: ret + +; X32: test1: +; X32-NEXT: movss 4(%esp), %xmm0 +; X32-NEXT: addss 8(%esp), %xmm0 +; X32-NEXT: movl 12(%esp), %eax +; X32-NEXT: movss %xmm0, (%eax) +; X32-NEXT: ret +} + + +define <2 x float> @test2(<2 x float> %Q, <2 x float> %R, <2 x float> *%P) nounwind { + %Z = fadd <2 x float> %Q, %R + ret <2 x float> %Z + +; X64: test2: +; X64-NEXT: insertps $0 +; X64-NEXT: insertps $16 +; X64-NEXT: insertps $0 +; X64-NEXT: insertps $16 +; X64-NEXT: addps +; X64-NEXT: movaps +; X64-NEXT: pshufd +; X64-NEXT: ret +} diff --git a/test/CodeGen/X86/vec-trunc-store.ll b/test/CodeGen/X86/vec-trunc-store.ll index ea1a151..2f57d7b 100644 --- a/test/CodeGen/X86/vec-trunc-store.ll +++ b/test/CodeGen/X86/vec-trunc-store.ll @@ -1,13 +1,15 @@ -; RUN: llc < %s -march=x86-64 -disable-mmx | grep punpcklwd | count 2 +; RUN: llc < %s -march=x86-64 -disable-mmx >/dev/null -define void @foo() nounwind { - %cti69 = trunc <8 x i32> undef to <8 x i16> ; <<8 x i16>> [#uses=1] +define void @foo(<8 x i32>* %p) nounwind { + %t = load <8 x i32>* %p + %cti69 = trunc <8 x i32> %t to <8 x i16> ; <<8 x i16>> [#uses=1] store <8 x i16> %cti69, <8 x i16>* undef ret void } -define void @bar() nounwind { - %cti44 = trunc <4 x i32> undef to <4 x i16> ; <<4 x i16>> [#uses=1] +define void @bar(<4 x i32>* %p) nounwind { + %t = load <4 x i32>* %p + %cti44 = trunc <4 x i32> %t to <4 x i16> ; <<4 x i16>> [#uses=1] store <4 x i16> %cti44, <4 x i16>* undef ret void } diff --git a/test/CodeGen/X86/vec_shuffle-6.ll b/test/CodeGen/X86/vec_shuffle-6.ll index f034b0a..28fd59b 100644 --- a/test/CodeGen/X86/vec_shuffle-6.ll +++ b/test/CodeGen/X86/vec_shuffle-6.ll @@ -4,7 +4,7 @@ ; RUN: grep movups %t | count 2 target triple = "i686-apple-darwin" -@x = global [4 x i32] [ i32 1, i32 2, i32 3, i32 4 ] ; <[4 x i32]*> [#uses=4] +@x = external global [4 x i32] define <2 x i64> @test1() { %tmp = load i32* getelementptr ([4 x i32]* @x, i32 0, i32 0) ; <i32> [#uses=1] diff --git a/test/CodeGen/X86/vector-intrinsics.ll b/test/CodeGen/X86/vector-intrinsics.ll index edf58b9..cabacb5 100644 --- a/test/CodeGen/X86/vector-intrinsics.ll +++ b/test/CodeGen/X86/vector-intrinsics.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86-64 | grep call | count 16 +; RUN: llc < %s -march=x86-64 | grep call | count 43 declare <4 x double> @llvm.sin.v4f64(<4 x double> %p) declare <4 x double> @llvm.cos.v4f64(<4 x double> %p) @@ -25,3 +25,28 @@ define <4 x double> @zoo(<4 x double> %p, i32 %q) %t = call <4 x double> @llvm.powi.v4f64(<4 x double> %p, i32 %q) ret <4 x double> %t } + + +declare <9 x double> @llvm.exp.v9f64(<9 x double> %a) +declare <9 x double> @llvm.pow.v9f64(<9 x double> %a, <9 x double> %b) +declare <9 x double> @llvm.powi.v9f64(<9 x double> %a, i32) + +define void @a(<9 x double>* %p) nounwind { + %a = load <9 x double>* %p + %r = call <9 x double> @llvm.exp.v9f64(<9 x double> %a) + store <9 x double> %r, <9 x double>* %p + ret void +} +define void @b(<9 x double>* %p, <9 x double>* %q) nounwind { + %a = load <9 x double>* %p + %b = load <9 x double>* %q + %r = call <9 x double> @llvm.pow.v9f64(<9 x double> %a, <9 x double> %b) + store <9 x double> %r, <9 x double>* %p + ret void +} +define void @c(<9 x double>* %p, i32 %n) nounwind { + %a = load <9 x double>* %p + %r = call <9 x double> @llvm.powi.v9f64(<9 x double> %a, i32 %n) + store <9 x double> %r, <9 x double>* %p + ret void +} diff --git a/test/CodeGen/X86/volatile.ll b/test/CodeGen/X86/volatile.ll index 5e1e0c8..2e5742a 100644 --- a/test/CodeGen/X86/volatile.ll +++ b/test/CodeGen/X86/volatile.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=x86 -mattr=sse2 | grep movsd | count 5 -; RUN: llc < %s -march=x86 -mattr=sse2 -O0 | grep movsd | count 5 +; RUN: llc < %s -march=x86 -mattr=sse2 -O0 | grep -v esp | grep movsd | count 5 @x = external global double diff --git a/test/CodeGen/X86/widen_shuffle-1.ll b/test/CodeGen/X86/widen_shuffle-1.ll index 47dba4b..25dde57 100644 --- a/test/CodeGen/X86/widen_shuffle-1.ll +++ b/test/CodeGen/X86/widen_shuffle-1.ll @@ -1,13 +1,46 @@ ; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s -; CHECK: insertps -; CHECK: extractps ; widening shuffle v3float and then a add - define void @shuf(<3 x float>* %dst.addr, <3 x float> %src1,<3 x float> %src2) nounwind { entry: +; CHECK: insertps +; CHECK: extractps %x = shufflevector <3 x float> %src1, <3 x float> %src2, <3 x i32> < i32 0, i32 1, i32 2> %val = fadd <3 x float> %x, %src2 store <3 x float> %val, <3 x float>* %dst.addr ret void } + + +; widening shuffle v3float with a different mask and then a add +define void @shuf2(<3 x float>* %dst.addr, <3 x float> %src1,<3 x float> %src2) nounwind { +entry: +; CHECK: insertps +; CHECK: extractps + %x = shufflevector <3 x float> %src1, <3 x float> %src2, <3 x i32> < i32 0, i32 4, i32 2> + %val = fadd <3 x float> %x, %src2 + store <3 x float> %val, <3 x float>* %dst.addr + ret void +} + +; Example of when widening a v3float operation causes the DAG to replace a node +; with the operation that we are currently widening, i.e. when replacing +; opA with opB, the DAG will produce new operations with opA. +define void @shuf3(<4 x float> %tmp10, <4 x float> %vecinit15, <4 x float>* %dst) { +entry: +; CHECK: pshufd + %shuffle.i.i.i12 = shufflevector <4 x float> %tmp10, <4 x float> %vecinit15, <4 x i32> <i32 0, i32 1, i32 4, i32 5> + %tmp25.i.i = shufflevector <4 x float> %shuffle.i.i.i12, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2> + %tmp1.i.i = shufflevector <3 x float> %tmp25.i.i, <3 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3> + %tmp3.i13 = shufflevector <4 x float> %tmp1.i.i, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2> ; <<3 x float>> + %tmp6.i14 = shufflevector <3 x float> %tmp3.i13, <3 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3> + %tmp97.i = shufflevector <4 x float> %tmp6.i14, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2> + %tmp2.i18 = shufflevector <3 x float> %tmp97.i, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2> + %t5 = bitcast <4 x float> %tmp2.i18 to <4 x i32> + %shr.i.i19 = lshr <4 x i32> %t5, <i32 19, i32 19, i32 19, i32 19> + %and.i.i20 = and <4 x i32> %shr.i.i19, <i32 4080, i32 4080, i32 4080, i32 4080> + %shuffle.i.i.i21 = shufflevector <4 x float> %tmp2.i18, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 2, i32 3> + store <4 x float> %shuffle.i.i.i21, <4 x float>* %dst + ret void +} + diff --git a/test/CodeGen/X86/widen_shuffle-2.ll b/test/CodeGen/X86/widen_shuffle-2.ll deleted file mode 100644 index 9374a02..0000000 --- a/test/CodeGen/X86/widen_shuffle-2.ll +++ /dev/null @@ -1,13 +0,0 @@ -; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s -; CHECK: insertps -; CHECK: extractps - -; widening shuffle v3float and then a add - -define void @shuf(<3 x float>* %dst.addr, <3 x float> %src1,<3 x float> %src2) nounwind { -entry: - %x = shufflevector <3 x float> %src1, <3 x float> %src2, <3 x i32> < i32 0, i32 4, i32 2> - %val = fadd <3 x float> %x, %src2 - store <3 x float> %val, <3 x float>* %dst.addr - ret void -} diff --git a/test/CodeGen/X86/x86-64-tls-1.ll b/test/CodeGen/X86/x86-64-tls-1.ll new file mode 100644 index 0000000..8d3b300 --- /dev/null +++ b/test/CodeGen/X86/x86-64-tls-1.ll @@ -0,0 +1,6 @@ +; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s +@tm_nest_level = internal thread_local global i32 0 +define i64 @z() nounwind { +; CHECK: movabsq $tm_nest_level@TPOFF, %rcx + ret i64 and (i64 ptrtoint (i32* @tm_nest_level to i64), i64 100) +} diff --git a/test/CodeGen/X86/zext-sext.ll b/test/CodeGen/X86/zext-sext.ll new file mode 100644 index 0000000..bd109b9 --- /dev/null +++ b/test/CodeGen/X86/zext-sext.ll @@ -0,0 +1,53 @@ +; RUN: llc < %s -march=x86-64 | FileCheck %s +; <rdar://problem/8006248> + +@llvm.used = appending global [1 x i8*] [i8* bitcast (void ([40 x i16]*, i32*, i16**, i64*)* @func to i8*)], section "llvm.metadata" + +define void @func([40 x i16]* %a, i32* %b, i16** %c, i64* %d) nounwind { +entry: + %tmp103 = getelementptr inbounds [40 x i16]* %a, i64 0, i64 4 + %tmp104 = load i16* %tmp103, align 2 + %tmp105 = sext i16 %tmp104 to i32 + %tmp106 = load i32* %b, align 4 + %tmp107 = sub nsw i32 4, %tmp106 + %tmp108 = load i16** %c, align 8 + %tmp109 = sext i32 %tmp107 to i64 + %tmp110 = getelementptr inbounds i16* %tmp108, i64 %tmp109 + %tmp111 = load i16* %tmp110, align 1 + %tmp112 = sext i16 %tmp111 to i32 + %tmp = mul i32 355244649, %tmp112 + %tmp1 = mul i32 %tmp, %tmp105 + %tmp2 = add i32 %tmp1, 2138875574 + %tmp3 = add i32 %tmp2, 1546991088 + %tmp4 = mul i32 %tmp3, 2122487257 + %tmp5 = icmp sge i32 %tmp4, 2138875574 + %tmp6 = icmp slt i32 %tmp4, -8608074 + %tmp7 = or i1 %tmp5, %tmp6 + %outSign = select i1 %tmp7, i32 1, i32 -1 + %tmp8 = icmp slt i32 %tmp4, 0 + %tmp9 = icmp eq i32 %outSign, 1 + %tmp10 = and i1 %tmp8, %tmp9 + %tmp11 = sext i32 %tmp4 to i64 + %tmp12 = add i64 %tmp11, 5089792279245435153 + +; CHECK: addl $2138875574, %e[[REGISTER_zext:[a-z]+]] +; CHECK-NEXT: movslq %e[[REGISTER_zext]], [[REGISTER_tmp:%[a-z]+]] +; CHECK: movq [[REGISTER_tmp]], [[REGISTER_sext:%[a-z]+]] +; CHECK-NEXT: subq %r[[REGISTER_zext]], [[REGISTER_sext]] + + %tmp13 = sub i64 %tmp12, 2138875574 + %tmp14 = zext i32 %tmp4 to i64 + %tmp15 = sub i64 %tmp11, %tmp14 + %tmp16 = select i1 %tmp10, i64 %tmp15, i64 0 + %tmp17 = sub i64 %tmp13, %tmp16 + %tmp18 = mul i64 %tmp17, 4540133155013554595 + %tmp19 = sub i64 %tmp18, 5386586244038704851 + %tmp20 = add i64 %tmp19, -1368057358110947217 + %tmp21 = mul i64 %tmp20, -422037402840850817 + %tmp115 = load i64* %d, align 8 + %alphaX = mul i64 468858157810230901, %tmp21 + %alphaXbetaY = add i64 %alphaX, %tmp115 + %transformed = add i64 %alphaXbetaY, 9040145182981852475 + store i64 %transformed, i64* %d, align 8 + ret void +} diff --git a/test/DebugInfo/2010-05-25-DotDebugLoc.ll b/test/DebugInfo/2010-05-25-DotDebugLoc.ll index 4c477ee..52e9484 100644 --- a/test/DebugInfo/2010-05-25-DotDebugLoc.ll +++ b/test/DebugInfo/2010-05-25-DotDebugLoc.ll @@ -1,4 +1,4 @@ -; RUN: llc -O2 < %s | grep debug_loc12 +; RUN: llc -O2 < %s -mtriple=x86_64-apple-darwin | grep debug_loc12 ; Test to check .debug_loc support. This test case emits 13 debug_loc entries. %0 = type { double } diff --git a/test/DebugInfo/2010-05-28-Crash.ll b/test/DebugInfo/2010-05-28-Crash.ll new file mode 100644 index 0000000..80643d0 --- /dev/null +++ b/test/DebugInfo/2010-05-28-Crash.ll @@ -0,0 +1,44 @@ +; RUN: llc -mtriple=x86_64-apple-darwin < %s | FileCheck %s +; Test to check separate label for inlined function argument. + +define i32 @foo(i32 %y) nounwind optsize ssp { +entry: + tail call void @llvm.dbg.value(metadata !{i32 %y}, i64 0, metadata !0) + %0 = tail call i32 (...)* @zoo(i32 %y) nounwind, !dbg !9 ; <i32> [#uses=1] + ret i32 %0, !dbg !9 +} + +declare i32 @zoo(...) + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone + +define i32 @bar(i32 %x) nounwind optsize ssp { +entry: + tail call void @llvm.dbg.value(metadata !{i32 %x}, i64 0, metadata !7) + tail call void @llvm.dbg.value(metadata !11, i64 0, metadata !0) nounwind + %0 = tail call i32 (...)* @zoo(i32 1) nounwind, !dbg !12 ; <i32> [#uses=1] + %1 = add nsw i32 %0, %x, !dbg !13 ; <i32> [#uses=1] + ret i32 %1, !dbg !13 +} + +!llvm.dbg.lv = !{!0, !7} + +!0 = metadata !{i32 524545, metadata !1, metadata !"y", metadata !2, i32 2, metadata !6} ; [ DW_TAG_arg_variable ] +!1 = metadata !{i32 524334, i32 0, metadata !2, metadata !"foo", metadata !"foo", metadata !"foo", metadata !2, i32 2, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true} ; [ DW_TAG_subprogram ] +!2 = metadata !{i32 524329, metadata !"f.c", metadata !"/tmp", metadata !3} ; [ DW_TAG_file_type ] +!3 = metadata !{i32 524305, i32 0, i32 1, metadata !"f.c", metadata !"/tmp", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!4 = metadata !{i32 524309, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ] +!5 = metadata !{metadata !6, metadata !6} +!6 = metadata !{i32 524324, metadata !2, metadata !"int", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!7 = metadata !{i32 524545, metadata !8, metadata !"x", metadata !2, i32 6, metadata !6} ; [ DW_TAG_arg_variable ] +!8 = metadata !{i32 524334, i32 0, metadata !2, metadata !"bar", metadata !"bar", metadata !"bar", metadata !2, i32 6, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true} ; [ DW_TAG_subprogram ] +!9 = metadata !{i32 3, i32 0, metadata !10, null} +!10 = metadata !{i32 524299, metadata !1, i32 2, i32 0} ; [ DW_TAG_lexical_block ] +!11 = metadata !{i32 1} +!12 = metadata !{i32 3, i32 0, metadata !10, metadata !13} +!13 = metadata !{i32 7, i32 0, metadata !14, null} +!14 = metadata !{i32 524299, metadata !8, i32 6, i32 0} ; [ DW_TAG_lexical_block ] + +;CHECK: DEBUG_VALUE: bar:x <- EBX+0 +;CHECK-NEXT:Ltmp +;CHECK-NEXT: DEBUG_VALUE: foo:y <- 1+0 diff --git a/test/DebugInfo/2010-06-01-DeadArg-DbgInfo.ll b/test/DebugInfo/2010-06-01-DeadArg-DbgInfo.ll new file mode 100644 index 0000000..812d372 --- /dev/null +++ b/test/DebugInfo/2010-06-01-DeadArg-DbgInfo.ll @@ -0,0 +1,53 @@ +; RUN: llc -O2 < %s | FileCheck %s +; Test to check that unused argument 'this' is not undefined in debug info. + +target triple = "x86_64-apple-darwin10.2" +%struct.foo = type { i32 } + +@llvm.used = appending global [1 x i8*] [i8* bitcast (i32 (%struct.foo*, i32)* @_ZN3foo3bazEi to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] + +define i32 @_ZN3foo3bazEi(%struct.foo* nocapture %this, i32 %x) nounwind readnone optsize noinline ssp align 2 { +;CHECK: DEBUG_VALUE: baz:this <- RDI+0 +entry: + tail call void @llvm.dbg.value(metadata !{%struct.foo* %this}, i64 0, metadata !15) + tail call void @llvm.dbg.value(metadata !{i32 %x}, i64 0, metadata !16) + %0 = mul nsw i32 %x, 7, !dbg !29 ; <i32> [#uses=1] + %1 = add nsw i32 %0, 1, !dbg !29 ; <i32> [#uses=1] + ret i32 %1, !dbg !29 +} + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone + +!llvm.dbg.lv = !{!0, !14, !15, !16, !17, !24, !25, !28} + +!0 = metadata !{i32 524545, metadata !1, metadata !"this", metadata !3, i32 11, metadata !12} ; [ DW_TAG_arg_variable ] +!1 = metadata !{i32 524334, i32 0, metadata !2, metadata !"bar", metadata !"bar", metadata !"_ZN3foo3barEi", metadata !3, i32 11, metadata !9, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true} ; [ DW_TAG_subprogram ] +!2 = metadata !{i32 524307, metadata !3, metadata !"foo", metadata !3, i32 3, i64 32, i64 32, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_structure_type ] +!3 = metadata !{i32 524329, metadata !"foo.cp", metadata !"/tmp/", metadata !4} ; [ DW_TAG_file_type ] +!4 = metadata !{i32 524305, i32 0, i32 4, metadata !"foo.cp", metadata !"/tmp/", metadata !"4.2.1 LLVM build", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!5 = metadata !{metadata !6, metadata !1, metadata !8} +!6 = metadata !{i32 524301, metadata !2, metadata !"y", metadata !3, i32 8, i64 32, i64 32, i64 0, i32 0, metadata !7} ; [ DW_TAG_member ] +!7 = metadata !{i32 524324, metadata !3, metadata !"int", metadata !3, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!8 = metadata !{i32 524334, i32 0, metadata !2, metadata !"baz", metadata !"baz", metadata !"_ZN3foo3bazEi", metadata !3, i32 15, metadata !9, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true} ; [ DW_TAG_subprogram ] +!9 = metadata !{i32 524309, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !10, i32 0, null} ; [ DW_TAG_subroutine_type ] +!10 = metadata !{metadata !7, metadata !11, metadata !7} +!11 = metadata !{i32 524303, metadata !3, metadata !"", metadata !3, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !2} ; [ DW_TAG_pointer_type ] +!12 = metadata !{i32 524326, metadata !3, metadata !"", metadata !3, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !13} ; [ DW_TAG_const_type ] +!13 = metadata !{i32 524303, metadata !3, metadata !"", metadata !3, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !2} ; [ DW_TAG_pointer_type ] +!14 = metadata !{i32 524545, metadata !1, metadata !"x", metadata !3, i32 11, metadata !7} ; [ DW_TAG_arg_variable ] +!15 = metadata !{i32 524545, metadata !8, metadata !"this", metadata !3, i32 15, metadata !12} ; [ DW_TAG_arg_variable ] +!16 = metadata !{i32 524545, metadata !8, metadata !"x", metadata !3, i32 15, metadata !7} ; [ DW_TAG_arg_variable ] +!17 = metadata !{i32 524545, metadata !18, metadata !"argc", metadata !3, i32 19, metadata !7} ; [ DW_TAG_arg_variable ] +!18 = metadata !{i32 524334, i32 0, metadata !3, metadata !"main", metadata !"main", metadata !"main", metadata !3, i32 19, metadata !19, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true} ; [ DW_TAG_subprogram ] +!19 = metadata !{i32 524309, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !20, i32 0, null} ; [ DW_TAG_subroutine_type ] +!20 = metadata !{metadata !7, metadata !7, metadata !21} +!21 = metadata !{i32 524303, metadata !3, metadata !"", metadata !3, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !22} ; [ DW_TAG_pointer_type ] +!22 = metadata !{i32 524303, metadata !3, metadata !"", metadata !3, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !23} ; [ DW_TAG_pointer_type ] +!23 = metadata !{i32 524324, metadata !3, metadata !"char", metadata !3, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ] +!24 = metadata !{i32 524545, metadata !18, metadata !"argv", metadata !3, i32 19, metadata !21} ; [ DW_TAG_arg_variable ] +!25 = metadata !{i32 524544, metadata !26, metadata !"a", metadata !3, i32 20, metadata !2} ; [ DW_TAG_auto_variable ] +!26 = metadata !{i32 524299, metadata !27, i32 19, i32 0} ; [ DW_TAG_lexical_block ] +!27 = metadata !{i32 524299, metadata !18, i32 19, i32 0} ; [ DW_TAG_lexical_block ] +!28 = metadata !{i32 524544, metadata !26, metadata !"b", metadata !3, i32 21, metadata !7} ; [ DW_TAG_auto_variable ] +!29 = metadata !{i32 16, i32 0, metadata !30, null} +!30 = metadata !{i32 524299, metadata !8, i32 15, i32 0} ; [ DW_TAG_lexical_block ] diff --git a/test/DebugInfo/2010-06-29-InlinedFnLocalVar.ll b/test/DebugInfo/2010-06-29-InlinedFnLocalVar.ll new file mode 100644 index 0000000..1d67cb4 --- /dev/null +++ b/test/DebugInfo/2010-06-29-InlinedFnLocalVar.ll @@ -0,0 +1,52 @@ +; RUN: llc -O2 %s -o - | FileCheck %s +; Check struct X for dead variable xyz from inlined function foo. + +; CHECK: DW_TAG_structure_type +; CHECK-NEXT: DW_AT_sibling +; CHECK-NEXT: DW_AT_name + + +@i = common global i32 0 ; <i32*> [#uses=2] + +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone + +define i32 @bar() nounwind ssp { +entry: + %0 = load i32* @i, align 4, !dbg !17 ; <i32> [#uses=2] + tail call void @llvm.dbg.value(metadata !{i32 %0}, i64 0, metadata !9), !dbg !19 + tail call void @llvm.dbg.declare(metadata !20, metadata !10), !dbg !21 + %1 = mul nsw i32 %0, %0, !dbg !22 ; <i32> [#uses=2] + store i32 %1, i32* @i, align 4, !dbg !17 + ret i32 %1, !dbg !23 +} + +!llvm.dbg.sp = !{!0, !6} +!llvm.dbg.lv.foo = !{!9, !10} +!llvm.dbg.gv = !{!16} + +!0 = metadata !{i32 524334, i32 0, metadata !1, metadata !"foo", metadata !"foo", metadata !"", metadata !1, i32 9, metadata !3, i1 true, i1 true, i32 0, i32 0, null, i1 false, i1 true, null} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 524329, metadata !"bar.c", metadata !"/tmp/", metadata !2} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 524305, i32 0, i32 1, metadata !"bar.c", metadata !"/tmp/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 524309, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] +!4 = metadata !{metadata !5, metadata !5} +!5 = metadata !{i32 524324, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 524334, i32 0, metadata !1, metadata !"bar", metadata !"bar", metadata !"bar", metadata !1, i32 14, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, i32 ()* @bar} ; [ DW_TAG_subprogram ] +!7 = metadata !{i32 524309, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, null} ; [ DW_TAG_subroutine_type ] +!8 = metadata !{metadata !5} +!9 = metadata !{i32 524545, metadata !0, metadata !"j", metadata !1, i32 9, metadata !5} ; [ DW_TAG_arg_variable ] +!10 = metadata !{i32 524544, metadata !11, metadata !"xyz", metadata !1, i32 10, metadata !12} ; [ DW_TAG_auto_variable ] +!11 = metadata !{i32 524299, metadata !0, i32 9, i32 0} ; [ DW_TAG_lexical_block ] +!12 = metadata !{i32 524307, metadata !0, metadata !"X", metadata !1, i32 10, i64 64, i64 32, i64 0, i32 0, null, metadata !13, i32 0, null} ; [ DW_TAG_structure_type ] +!13 = metadata !{metadata !14, metadata !15} +!14 = metadata !{i32 524301, metadata !12, metadata !"a", metadata !1, i32 10, i64 32, i64 32, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] +!15 = metadata !{i32 524301, metadata !12, metadata !"b", metadata !1, i32 10, i64 32, i64 32, i64 32, i32 0, metadata !5} ; [ DW_TAG_member ] +!16 = metadata !{i32 524340, i32 0, metadata !1, metadata !"i", metadata !"i", metadata !"", metadata !1, i32 5, metadata !5, i1 false, i1 true, i32* @i} ; [ DW_TAG_variable ] +!17 = metadata !{i32 15, i32 0, metadata !18, null} +!18 = metadata !{i32 524299, metadata !6, i32 14, i32 0} ; [ DW_TAG_lexical_block ] +!19 = metadata !{i32 9, i32 0, metadata !0, metadata !17} +!20 = metadata !{null} +!21 = metadata !{i32 9, i32 0, metadata !11, metadata !17} +!22 = metadata !{i32 11, i32 0, metadata !11, metadata !17} +!23 = metadata !{i32 16, i32 0, metadata !18, null} diff --git a/test/Feature/linker_private_linkages.ll b/test/Feature/linker_private_linkages.ll new file mode 100644 index 0000000..19bcbb4 --- /dev/null +++ b/test/Feature/linker_private_linkages.ll @@ -0,0 +1,6 @@ +; RUN: llvm-as < %s | llvm-dis > %t1.ll +; RUN: llvm-as %t1.ll -o - | llvm-dis > %t2.ll +; RUN: diff %t1.ll %t2.ll + +@foo = linker_private hidden global i32 0 +@bar = linker_private_weak hidden global i32 0 diff --git a/test/FrontendC++/2010-02-17-DbgArtificialArg.cpp b/test/FrontendC++/2010-02-17-DbgArtificialArg.cpp index 2a9f1f1..ff45412 100644 --- a/test/FrontendC++/2010-02-17-DbgArtificialArg.cpp +++ b/test/FrontendC++/2010-02-17-DbgArtificialArg.cpp @@ -1,4 +1,4 @@ -// RUN: %llvmgcc -g -S %s -o - | grep DW_TAG_pointer_type | grep "i32 524303, metadata .., metadata ..., metadata .., i32 ., i64 .., i64 .., i64 0, i32 64, metadata ..." +// RUN: %llvmgcc -g -S %s -o - | FileCheck %s // Here, second to last argument "i32 64" indicates that artificial type is set. // Test to artificial attribute attahed to "this" pointer type. // Radar 7655792 and 7655002 @@ -10,5 +10,7 @@ public: int foo() { A a; + // Matching "i32 64, metadata !<number>} ; [ DW_TAG_pointer_type ]" + // CHECK: i32 64, metadata {{![0-9]+\} ; \[ DW_TAG_pointer_type \]}} return a.fn1(1); } diff --git a/test/FrontendC++/2010-04-30-OptimizedMethod-Dbg.cpp b/test/FrontendC++/2010-04-30-OptimizedMethod-Dbg.cpp index dc9b16c..7052dc0 100644 --- a/test/FrontendC++/2010-04-30-OptimizedMethod-Dbg.cpp +++ b/test/FrontendC++/2010-04-30-OptimizedMethod-Dbg.cpp @@ -1,5 +1,4 @@ -// RUN: %llvmgcc -g -S -O2 %s -o %t -// RUN: grep "i1 false, i1 true. . . DW_TAG_subprogram" %t | count 2 +// RUN: %llvmgcc -g -S -O2 %s -o - | FileCheck %s class foo { public: @@ -8,10 +7,12 @@ public: }; int foo::bar(int x) { + // CHECK: {{i1 false, i1 true(, i[0-9]+ [^\}]+[}]|[}]) ; \[ DW_TAG_subprogram \]}} return x*4 + 1; } int foo::baz(int x) { + // CHECK: {{i1 false, i1 true(, i[0-9]+ [^\},]+[}]|[}]) ; \[ DW_TAG_subprogram \]}} return x*4 + 1; } diff --git a/test/FrontendC++/2010-06-21-LocalVarDbg.cpp b/test/FrontendC++/2010-06-21-LocalVarDbg.cpp new file mode 100644 index 0000000..48d8215 --- /dev/null +++ b/test/FrontendC++/2010-06-21-LocalVarDbg.cpp @@ -0,0 +1,13 @@ +// RUN: %llvmgxx -g -Os -S %s -o - | llvm-as -disable-output +// Do not use function name to create named metadata used to hold +// local variable info. For example. llvm.dbg.lv.~A is an invalid name. +class A { +public: + ~A() { int i = 0; i++; } +}; + +int foo(int i) { + A a; + return 0; +} + diff --git a/test/FrontendC++/2010-06-22-BitfieldInit.cpp b/test/FrontendC++/2010-06-22-BitfieldInit.cpp new file mode 100644 index 0000000..1cfe1f9 --- /dev/null +++ b/test/FrontendC++/2010-06-22-BitfieldInit.cpp @@ -0,0 +1,20 @@ +// RUN: %llvmgxx -g -c %s +struct TEST2 +{ + int subid:32; + int :0; +}; + +typedef struct _TEST3 +{ + TEST2 foo; + TEST2 foo2; +} TEST3; + +TEST3 test = + { + {0}, + {0} + }; + +int main() { return 0; } diff --git a/test/FrontendC++/2010-06-22-ZeroBitfield.cpp b/test/FrontendC++/2010-06-22-ZeroBitfield.cpp new file mode 100644 index 0000000..c979f8d --- /dev/null +++ b/test/FrontendC++/2010-06-22-ZeroBitfield.cpp @@ -0,0 +1,5 @@ +// RUN: %llvmgxx -g -c %s +struct s8_0 { unsigned : 0; }; +struct s8_1 { double x; }; +struct s8 { s8_0 a; s8_1 b; }; +s8 f8() { return s8(); } diff --git a/test/FrontendC++/thunk-weak-odr.cpp b/test/FrontendC++/thunk-linkonce-odr.cpp index 1d9d4dd..ad72e64 100644 --- a/test/FrontendC++/thunk-weak-odr.cpp +++ b/test/FrontendC++/thunk-linkonce-odr.cpp @@ -1,5 +1,5 @@ // RUN: %llvmgxx %s -S -o - | FileCheck %s -// <rdar://problem/7929157> +// <rdar://problem/7929157> & <rdar://problem/8104369> struct A { virtual int f() { return 1; } @@ -27,7 +27,7 @@ int g() { return f(&d); } -// Thunks should be marked as "weak ODR", not just "weak". +// Thunks should be marked as "linkonce ODR" not "weak". // -// CHECK: define weak_odr i32 @_ZThn{{[48]}}_N1C1fEv -// CHECK: define weak_odr i32 @_ZThn{{[48]}}_N1D1fEv +// CHECK: define linkonce_odr i32 @_ZThn{{[48]}}_N1C1fEv +// CHECK: define linkonce_odr i32 @_ZThn{{[48]}}_N1D1fEv diff --git a/test/FrontendC/2010-05-31-palignr.c b/test/FrontendC/2010-05-31-palignr.c new file mode 100644 index 0000000..9da3145 --- /dev/null +++ b/test/FrontendC/2010-05-31-palignr.c @@ -0,0 +1,24 @@ +// RUN: not %llvmgcc -mssse3 -S -o /dev/null %s |& grep "error: mask must be an immediate" +// XFAIL: * +// XTARGET: x86,i386,i686 + +#include <tmmintrin.h> + +extern int i; + +int main () +{ +#if defined( __SSSE3__ ) + + typedef int16_t vSInt16 __attribute__ ((__vector_size__ (16))); + + short dtbl[] = {1,2,3,4,5,6,7,8}; + vSInt16 *vdtbl = (vSInt16*) dtbl; + + vSInt16 v0; + v0 = *vdtbl; + v0 = _mm_alignr_epi8(v0, v0, i); + + return 0; +#endif +} diff --git a/test/FrontendC/2010-06-11-SaveExpr.c b/test/FrontendC/2010-06-11-SaveExpr.c new file mode 100644 index 0000000..d1c122d --- /dev/null +++ b/test/FrontendC/2010-06-11-SaveExpr.c @@ -0,0 +1,8 @@ +// RUN: %llvmgcc -S %s +// Test case by Eric Postpischil! +void foo(void) +{ + char a[1]; + int t = 1; + ((char (*)[t]) a)[0][0] = 0; +} diff --git a/test/FrontendC/2010-06-17-asmcrash.c b/test/FrontendC/2010-06-17-asmcrash.c new file mode 100644 index 0000000..5063054 --- /dev/null +++ b/test/FrontendC/2010-06-17-asmcrash.c @@ -0,0 +1,16 @@ +// RUN: %llvmgcc -S -o - %s | llc -mtriple=x86_64-apple-darwin | FileCheck %s +// XFAIL: * +// XTARGET: x86,i386,i686 + +typedef long long int64_t; +typedef unsigned char uint8_t; +typedef int64_t x86_reg; + +void avg_pixels8_mmx2(uint8_t *block, const uint8_t *pixels, int line_size, int h) +{ + __asm__ volatile("# %0 %1 %2 %3" + :"+g"(h), "+S"(pixels), "+D"(block) + :"r" ((x86_reg)line_size) + :"%""rax", "memory"); +// CHECK: # %ecx %rsi %rdi %rdx + } diff --git a/test/FrontendC/2010-06-28-DbgEntryPC.c b/test/FrontendC/2010-06-28-DbgEntryPC.c new file mode 100644 index 0000000..76a6b51 --- /dev/null +++ b/test/FrontendC/2010-06-28-DbgEntryPC.c @@ -0,0 +1,50 @@ +// RUN: %llvmgcc -S -O2 -g %s -o - | llc -O2 -mtriple=i386-apple-darwin | FileCheck %s +// Use DW_FORM_addr for DW_AT_entry_pc. +// Radar 8094785 + +// XFAIL: * +// XTARGET: x86,i386,i686 +// CHECK: .byte 17 ## DW_TAG_compile_unit +// CHECK-NEXT: .byte 1 ## DW_CHILDREN_yes +// CHECK-NEXT: .byte 37 ## DW_AT_producer +// CHECK-NEXT: .byte 8 ## DW_FORM_string +// CHECK-NEXT: .byte 19 ## DW_AT_language +// CHECK-NEXT: .byte 11 ## DW_FORM_data1 +// CHECK-NEXT: .byte 3 ## DW_AT_name +// CHECK-NEXT: .byte 8 ## DW_FORM_string +// CHECK-NEXT: .byte 82 ## DW_AT_entry_pc +// CHECK-NEXT: .byte 1 ## DW_FORM_addr +// CHECK-NEXT: .byte 16 ## DW_AT_stmt_list +// CHECK-NEXT: .byte 6 ## DW_FORM_data4 +// CHECK-NEXT: .byte 27 ## DW_AT_comp_dir +// CHECK-NEXT: .byte 8 ## DW_FORM_string +// CHECK-NEXT: .byte 225 ## DW_AT_APPLE_optimized + +struct a { + int c; + struct a *d; +}; + +int ret; + +void foo(int x) __attribute__((noinline)); +void *bar(struct a *b) __attribute__((noinline)); + +void foo(int x) +{ + ret = x; +} + +void *bar(struct a *b) { + foo(b->c); + return b; +} + +int main(int argc, char *argv[]) { + struct a e; + e.c = 4; + e.d = &e; + + (void)bar(&e); + return ret; +} diff --git a/test/FrontendC/2010-06-28-DbgLocalVar.c b/test/FrontendC/2010-06-28-DbgLocalVar.c new file mode 100644 index 0000000..e5df885 --- /dev/null +++ b/test/FrontendC/2010-06-28-DbgLocalVar.c @@ -0,0 +1,14 @@ +// RUN: %llvmgcc -S -O2 -g %s -o - | llc -O2 -o %t.s +// RUN: grep DW_TAG_structure_type %t.s | count 2 +// Radar 8122864 + +// Code is not generated for function foo, but preserve type information of +// local variable xyz. +static foo() { + struct X { int a; int b; } xyz; +} + +int bar() { + foo(); + return 1; +} diff --git a/test/FrontendC/2010-06-28-nowarn.c b/test/FrontendC/2010-06-28-nowarn.c new file mode 100644 index 0000000..9cfb663 --- /dev/null +++ b/test/FrontendC/2010-06-28-nowarn.c @@ -0,0 +1,21 @@ +// RUN: %llvmgcc %s -c -m32 -fasm-blocks -o /dev/null +// This should not warn about unreferenced label. 7729514. +// XFAIL: * +// XTARGET: x86,i386,i686 + +void quarterAsm(int array[], int len) +{ + __asm + { + mov esi, array; + mov ecx, len; + shr ecx, 2; +loop: + movdqa xmm0, [esi]; + psrad xmm0, 2; + movdqa [esi], xmm0; + add esi, 16; + sub ecx, 1; + jnz loop; + } +} diff --git a/test/FrontendC/2010-07-08-DeclDebugLineNo.c b/test/FrontendC/2010-07-08-DeclDebugLineNo.c new file mode 100644 index 0000000..491b7db --- /dev/null +++ b/test/FrontendC/2010-07-08-DeclDebugLineNo.c @@ -0,0 +1,10 @@ +// RUN: %llvmgcc -S -O0 -g %s -o - | FileCheck %s +// Insure that dbg.declare lines for locals refer to correct line number records. +// Radar 8152866. +void foo() { + int l = 0; // line #4: CHECK: {{call.*llvm.dbg.declare.*%l.*\!dbg }}[[variable_l:![0-9]+]] + int p = 0; // line #5: CHECK: {{call.*llvm.dbg.declare.*%p.*\!dbg }}[[variable_p:![0-9]+]] +} +// Now match the line number records: +// CHECK: {{^}}[[variable_l]]{{ = metadata ![{]i32 5,}} +// CHECK: {{^}}[[variable_p]]{{ = metadata ![{]i32 6,}} diff --git a/test/FrontendC/pr5406.c b/test/FrontendC/pr5406.c index c873e51..492bdaf 100644 --- a/test/FrontendC/pr5406.c +++ b/test/FrontendC/pr5406.c @@ -8,7 +8,7 @@ typedef struct { char x[3]; } A0; void foo (int i, ...); -// CHECK: call arm_aapcscc void (i32, ...)* @foo(i32 1, i32 {{.*}}) nounwind +// CHECK: call void (i32, ...)* @foo(i32 1, i32 {{.*}}) nounwind int main (void) { A0 a3; diff --git a/test/FrontendObjC/2010-06-04-UnnamedCFString-dbg.m b/test/FrontendObjC/2010-06-04-UnnamedCFString-dbg.m new file mode 100644 index 0000000..bded9ea --- /dev/null +++ b/test/FrontendObjC/2010-06-04-UnnamedCFString-dbg.m @@ -0,0 +1,6 @@ +// RUN: %llvmgcc -S -O0 -g %s -o - | grep DW_TAG_variable | count 1 + +// Do not emit debug info for unnamed builtin CFString variable. +@interface Foo +@end +Foo *FooName = @"FooBar"; diff --git a/test/LLVMC/C++/filelist.cpp b/test/LLVMC/C++/filelist.cpp new file mode 100644 index 0000000..6f5f6f7 --- /dev/null +++ b/test/LLVMC/C++/filelist.cpp @@ -0,0 +1,3 @@ +// Test that the -filelist option works correctly with -linker=c++. +// RUN: llvmc --dry-run -filelist DUMMY -linker c++ |& grep llvm-g++ +// XFAIL: vg diff --git a/test/MC/AsmParser/X86/x86_32-encoding.s b/test/MC/AsmParser/X86/x86_32-encoding.s index 994dbb8..ea4a36e 100644 --- a/test/MC/AsmParser/X86/x86_32-encoding.s +++ b/test/MC/AsmParser/X86/x86_32-encoding.s @@ -9967,12 +9967,6 @@ // CHECK: encoding: [0x66,0x0f,0x3a,0xdf,0x14,0x82,0x80] aeskeygenassist $128, %xmm1, %xmm2 -// rdar://7840289 -// CHECK: pshufb CPI1_0(%rip), %xmm1 -// CHECK: encoding: [0x66,0x0f,0x38,0x00,0x0d,A,A,A,A] -// CHECK: fixup A - offset: 5, value: CPI1_0-4 -pshufb CPI1_0(%rip), %xmm1 - // rdar://7910087 // CHECK: bsfw %bx, %bx // CHECK: encoding: [0x66,0x0f,0xbc,0xdb] @@ -10052,3 +10046,2555 @@ pshufb CPI1_0(%rip), %xmm1 // CHECK: ficomps 32493 // CHECK: encoding: [0xde,0x1d,0xed,0x7e,0x00,0x00] ficomps 32493 + +// CHECK: vaddss %xmm4, %xmm6, %xmm2 +// CHECK: encoding: [0xc5,0xca,0x58,0xd4] + vaddss %xmm4, %xmm6, %xmm2 + +// CHECK: vmulss %xmm4, %xmm6, %xmm2 +// CHECK: encoding: [0xc5,0xca,0x59,0xd4] + vmulss %xmm4, %xmm6, %xmm2 + +// CHECK: vsubss %xmm4, %xmm6, %xmm2 +// CHECK: encoding: [0xc5,0xca,0x5c,0xd4] + vsubss %xmm4, %xmm6, %xmm2 + +// CHECK: vdivss %xmm4, %xmm6, %xmm2 +// CHECK: encoding: [0xc5,0xca,0x5e,0xd4] + vdivss %xmm4, %xmm6, %xmm2 + +// CHECK: vaddsd %xmm4, %xmm6, %xmm2 +// CHECK: encoding: [0xc5,0xcb,0x58,0xd4] + vaddsd %xmm4, %xmm6, %xmm2 + +// CHECK: vmulsd %xmm4, %xmm6, %xmm2 +// CHECK: encoding: [0xc5,0xcb,0x59,0xd4] + vmulsd %xmm4, %xmm6, %xmm2 + +// CHECK: vsubsd %xmm4, %xmm6, %xmm2 +// CHECK: encoding: [0xc5,0xcb,0x5c,0xd4] + vsubsd %xmm4, %xmm6, %xmm2 + +// CHECK: vdivsd %xmm4, %xmm6, %xmm2 +// CHECK: encoding: [0xc5,0xcb,0x5e,0xd4] + vdivsd %xmm4, %xmm6, %xmm2 + +// CHECK: vaddss 3735928559(%ebx,%ecx,8), %xmm2, %xmm5 +// CHECK: encoding: [0xc5,0xea,0x58,0xac,0xcb,0xef,0xbe,0xad,0xde] + vaddss 3735928559(%ebx,%ecx,8), %xmm2, %xmm5 + +// CHECK: vsubss 3735928559(%ebx,%ecx,8), %xmm2, %xmm5 +// CHECK: encoding: [0xc5,0xea,0x5c,0xac,0xcb,0xef,0xbe,0xad,0xde] + vsubss 3735928559(%ebx,%ecx,8), %xmm2, %xmm5 + +// CHECK: vmulss 3735928559(%ebx,%ecx,8), %xmm2, %xmm5 +// CHECK: encoding: [0xc5,0xea,0x59,0xac,0xcb,0xef,0xbe,0xad,0xde] + vmulss 3735928559(%ebx,%ecx,8), %xmm2, %xmm5 + +// CHECK: vdivss 3735928559(%ebx,%ecx,8), %xmm2, %xmm5 +// CHECK: encoding: [0xc5,0xea,0x5e,0xac,0xcb,0xef,0xbe,0xad,0xde] + vdivss 3735928559(%ebx,%ecx,8), %xmm2, %xmm5 + +// CHECK: vaddsd 3735928559(%ebx,%ecx,8), %xmm2, %xmm5 +// CHECK: encoding: [0xc5,0xeb,0x58,0xac,0xcb,0xef,0xbe,0xad,0xde] + vaddsd 3735928559(%ebx,%ecx,8), %xmm2, %xmm5 + +// CHECK: vsubsd 3735928559(%ebx,%ecx,8), %xmm2, %xmm5 +// CHECK: encoding: [0xc5,0xeb,0x5c,0xac,0xcb,0xef,0xbe,0xad,0xde] + vsubsd 3735928559(%ebx,%ecx,8), %xmm2, %xmm5 + +// CHECK: vmulsd 3735928559(%ebx,%ecx,8), %xmm2, %xmm5 +// CHECK: encoding: [0xc5,0xeb,0x59,0xac,0xcb,0xef,0xbe,0xad,0xde] + vmulsd 3735928559(%ebx,%ecx,8), %xmm2, %xmm5 + +// CHECK: vdivsd 3735928559(%ebx,%ecx,8), %xmm2, %xmm5 +// CHECK: encoding: [0xc5,0xeb,0x5e,0xac,0xcb,0xef,0xbe,0xad,0xde] + vdivsd 3735928559(%ebx,%ecx,8), %xmm2, %xmm5 + +// CHECK: vaddps %xmm4, %xmm6, %xmm2 +// CHECK: encoding: [0xc5,0xc8,0x58,0xd4] + vaddps %xmm4, %xmm6, %xmm2 + +// CHECK: vsubps %xmm4, %xmm6, %xmm2 +// CHECK: encoding: [0xc5,0xc8,0x5c,0xd4] + vsubps %xmm4, %xmm6, %xmm2 + +// CHECK: vmulps %xmm4, %xmm6, %xmm2 +// CHECK: encoding: [0xc5,0xc8,0x59,0xd4] + vmulps %xmm4, %xmm6, %xmm2 + +// CHECK: vdivps %xmm4, %xmm6, %xmm2 +// CHECK: encoding: [0xc5,0xc8,0x5e,0xd4] + vdivps %xmm4, %xmm6, %xmm2 + +// CHECK: vaddpd %xmm4, %xmm6, %xmm2 +// CHECK: encoding: [0xc5,0xc9,0x58,0xd4] + vaddpd %xmm4, %xmm6, %xmm2 + +// CHECK: vsubpd %xmm4, %xmm6, %xmm2 +// CHECK: encoding: [0xc5,0xc9,0x5c,0xd4] + vsubpd %xmm4, %xmm6, %xmm2 + +// CHECK: vmulpd %xmm4, %xmm6, %xmm2 +// CHECK: encoding: [0xc5,0xc9,0x59,0xd4] + vmulpd %xmm4, %xmm6, %xmm2 + +// CHECK: vdivpd %xmm4, %xmm6, %xmm2 +// CHECK: encoding: [0xc5,0xc9,0x5e,0xd4] + vdivpd %xmm4, %xmm6, %xmm2 + +// CHECK: vaddps 3735928559(%ebx,%ecx,8), %xmm2, %xmm5 +// CHECK: encoding: [0xc5,0xe8,0x58,0xac,0xcb,0xef,0xbe,0xad,0xde] + vaddps 3735928559(%ebx,%ecx,8), %xmm2, %xmm5 + +// CHECK: vsubps 3735928559(%ebx,%ecx,8), %xmm2, %xmm5 +// CHECK: encoding: [0xc5,0xe8,0x5c,0xac,0xcb,0xef,0xbe,0xad,0xde] + vsubps 3735928559(%ebx,%ecx,8), %xmm2, %xmm5 + +// CHECK: vmulps 3735928559(%ebx,%ecx,8), %xmm2, %xmm5 +// CHECK: encoding: [0xc5,0xe8,0x59,0xac,0xcb,0xef,0xbe,0xad,0xde] + vmulps 3735928559(%ebx,%ecx,8), %xmm2, %xmm5 + +// CHECK: vdivps 3735928559(%ebx,%ecx,8), %xmm2, %xmm5 +// CHECK: encoding: [0xc5,0xe8,0x5e,0xac,0xcb,0xef,0xbe,0xad,0xde] + vdivps 3735928559(%ebx,%ecx,8), %xmm2, %xmm5 + +// CHECK: vaddpd 3735928559(%ebx,%ecx,8), %xmm2, %xmm5 +// CHECK: encoding: [0xc5,0xe9,0x58,0xac,0xcb,0xef,0xbe,0xad,0xde] + vaddpd 3735928559(%ebx,%ecx,8), %xmm2, %xmm5 + +// CHECK: vsubpd 3735928559(%ebx,%ecx,8), %xmm2, %xmm5 +// CHECK: encoding: [0xc5,0xe9,0x5c,0xac,0xcb,0xef,0xbe,0xad,0xde] + vsubpd 3735928559(%ebx,%ecx,8), %xmm2, %xmm5 + +// CHECK: vmulpd 3735928559(%ebx,%ecx,8), %xmm2, %xmm5 +// CHECK: encoding: [0xc5,0xe9,0x59,0xac,0xcb,0xef,0xbe,0xad,0xde] + vmulpd 3735928559(%ebx,%ecx,8), %xmm2, %xmm5 + +// CHECK: vdivpd 3735928559(%ebx,%ecx,8), %xmm2, %xmm5 +// CHECK: encoding: [0xc5,0xe9,0x5e,0xac,0xcb,0xef,0xbe,0xad,0xde] + vdivpd 3735928559(%ebx,%ecx,8), %xmm2, %xmm5 +// CHECK: vmaxss %xmm2, %xmm4, %xmm6 +// CHECK: encoding: [0xc5,0xda,0x5f,0xf2] + vmaxss %xmm2, %xmm4, %xmm6 + +// CHECK: vmaxsd %xmm2, %xmm4, %xmm6 +// CHECK: encoding: [0xc5,0xdb,0x5f,0xf2] + vmaxsd %xmm2, %xmm4, %xmm6 + +// CHECK: vminss %xmm2, %xmm4, %xmm6 +// CHECK: encoding: [0xc5,0xda,0x5d,0xf2] + vminss %xmm2, %xmm4, %xmm6 + +// CHECK: vminsd %xmm2, %xmm4, %xmm6 +// CHECK: encoding: [0xc5,0xdb,0x5d,0xf2] + vminsd %xmm2, %xmm4, %xmm6 + +// CHECK: vmaxss -4(%ebx,%ecx,8), %xmm2, %xmm5 +// CHECK: encoding: [0xc5,0xea,0x5f,0x6c,0xcb,0xfc] + vmaxss -4(%ebx,%ecx,8), %xmm2, %xmm5 + +// CHECK: vmaxsd -4(%ebx,%ecx,8), %xmm2, %xmm5 +// CHECK: encoding: [0xc5,0xeb,0x5f,0x6c,0xcb,0xfc] + vmaxsd -4(%ebx,%ecx,8), %xmm2, %xmm5 + +// CHECK: vminss -4(%ebx,%ecx,8), %xmm2, %xmm5 +// CHECK: encoding: [0xc5,0xea,0x5d,0x6c,0xcb,0xfc] + vminss -4(%ebx,%ecx,8), %xmm2, %xmm5 + +// CHECK: vminsd -4(%ebx,%ecx,8), %xmm2, %xmm5 +// CHECK: encoding: [0xc5,0xeb,0x5d,0x6c,0xcb,0xfc] + vminsd -4(%ebx,%ecx,8), %xmm2, %xmm5 + +// CHECK: vmaxps %xmm2, %xmm4, %xmm6 +// CHECK: encoding: [0xc5,0xd8,0x5f,0xf2] + vmaxps %xmm2, %xmm4, %xmm6 + +// CHECK: vmaxpd %xmm2, %xmm4, %xmm6 +// CHECK: encoding: [0xc5,0xd9,0x5f,0xf2] + vmaxpd %xmm2, %xmm4, %xmm6 + +// CHECK: vminps %xmm2, %xmm4, %xmm6 +// CHECK: encoding: [0xc5,0xd8,0x5d,0xf2] + vminps %xmm2, %xmm4, %xmm6 + +// CHECK: vminpd %xmm2, %xmm4, %xmm6 +// CHECK: encoding: [0xc5,0xd9,0x5d,0xf2] + vminpd %xmm2, %xmm4, %xmm6 + +// CHECK: vmaxps -4(%ebx,%ecx,8), %xmm2, %xmm5 +// CHECK: encoding: [0xc5,0xe8,0x5f,0x6c,0xcb,0xfc] + vmaxps -4(%ebx,%ecx,8), %xmm2, %xmm5 + +// CHECK: vmaxpd -4(%ebx,%ecx,8), %xmm2, %xmm5 +// CHECK: encoding: [0xc5,0xe9,0x5f,0x6c,0xcb,0xfc] + vmaxpd -4(%ebx,%ecx,8), %xmm2, %xmm5 + +// CHECK: vminps -4(%ebx,%ecx,8), %xmm2, %xmm5 +// CHECK: encoding: [0xc5,0xe8,0x5d,0x6c,0xcb,0xfc] + vminps -4(%ebx,%ecx,8), %xmm2, %xmm5 + +// CHECK: vminpd -4(%ebx,%ecx,8), %xmm2, %xmm5 +// CHECK: encoding: [0xc5,0xe9,0x5d,0x6c,0xcb,0xfc] + vminpd -4(%ebx,%ecx,8), %xmm2, %xmm5 + +// CHECK: vandps %xmm2, %xmm4, %xmm6 +// CHECK: encoding: [0xc5,0xd8,0x54,0xf2] + vandps %xmm2, %xmm4, %xmm6 + +// CHECK: vandpd %xmm2, %xmm4, %xmm6 +// CHECK: encoding: [0xc5,0xd9,0x54,0xf2] + vandpd %xmm2, %xmm4, %xmm6 + +// CHECK: vandps -4(%ebx,%ecx,8), %xmm2, %xmm5 +// CHECK: encoding: [0xc5,0xe8,0x54,0x6c,0xcb,0xfc] + vandps -4(%ebx,%ecx,8), %xmm2, %xmm5 + +// CHECK: vandpd -4(%ebx,%ecx,8), %xmm2, %xmm5 +// CHECK: encoding: [0xc5,0xe9,0x54,0x6c,0xcb,0xfc] + vandpd -4(%ebx,%ecx,8), %xmm2, %xmm5 + +// CHECK: vorps %xmm2, %xmm4, %xmm6 +// CHECK: encoding: [0xc5,0xd8,0x56,0xf2] + vorps %xmm2, %xmm4, %xmm6 + +// CHECK: vorpd %xmm2, %xmm4, %xmm6 +// CHECK: encoding: [0xc5,0xd9,0x56,0xf2] + vorpd %xmm2, %xmm4, %xmm6 + +// CHECK: vorps -4(%ebx,%ecx,8), %xmm2, %xmm5 +// CHECK: encoding: [0xc5,0xe8,0x56,0x6c,0xcb,0xfc] + vorps -4(%ebx,%ecx,8), %xmm2, %xmm5 + +// CHECK: vorpd -4(%ebx,%ecx,8), %xmm2, %xmm5 +// CHECK: encoding: [0xc5,0xe9,0x56,0x6c,0xcb,0xfc] + vorpd -4(%ebx,%ecx,8), %xmm2, %xmm5 + +// CHECK: vxorps %xmm2, %xmm4, %xmm6 +// CHECK: encoding: [0xc5,0xd8,0x57,0xf2] + vxorps %xmm2, %xmm4, %xmm6 + +// CHECK: vxorpd %xmm2, %xmm4, %xmm6 +// CHECK: encoding: [0xc5,0xd9,0x57,0xf2] + vxorpd %xmm2, %xmm4, %xmm6 + +// CHECK: vxorps -4(%ebx,%ecx,8), %xmm2, %xmm5 +// CHECK: encoding: [0xc5,0xe8,0x57,0x6c,0xcb,0xfc] + vxorps -4(%ebx,%ecx,8), %xmm2, %xmm5 + +// CHECK: vxorpd -4(%ebx,%ecx,8), %xmm2, %xmm5 +// CHECK: encoding: [0xc5,0xe9,0x57,0x6c,0xcb,0xfc] + vxorpd -4(%ebx,%ecx,8), %xmm2, %xmm5 + +// CHECK: vandnps %xmm2, %xmm4, %xmm6 +// CHECK: encoding: [0xc5,0xd8,0x55,0xf2] + vandnps %xmm2, %xmm4, %xmm6 + +// CHECK: vandnpd %xmm2, %xmm4, %xmm6 +// CHECK: encoding: [0xc5,0xd9,0x55,0xf2] + vandnpd %xmm2, %xmm4, %xmm6 + +// CHECK: vandnps -4(%ebx,%ecx,8), %xmm2, %xmm5 +// CHECK: encoding: [0xc5,0xe8,0x55,0x6c,0xcb,0xfc] + vandnps -4(%ebx,%ecx,8), %xmm2, %xmm5 + +// CHECK: vandnpd -4(%ebx,%ecx,8), %xmm2, %xmm5 +// CHECK: encoding: [0xc5,0xe9,0x55,0x6c,0xcb,0xfc] + vandnpd -4(%ebx,%ecx,8), %xmm2, %xmm5 + +// CHECK: vmovss -4(%ebx,%ecx,8), %xmm5 +// CHECK: encoding: [0xc5,0xfa,0x10,0x6c,0xcb,0xfc] + vmovss -4(%ebx,%ecx,8), %xmm5 + +// CHECK: vmovss %xmm4, %xmm2, %xmm5 +// CHECK: encoding: [0xc5,0xea,0x10,0xec] + vmovss %xmm4, %xmm2, %xmm5 + +// CHECK: vmovsd -4(%ebx,%ecx,8), %xmm5 +// CHECK: encoding: [0xc5,0xfb,0x10,0x6c,0xcb,0xfc] + vmovsd -4(%ebx,%ecx,8), %xmm5 + +// CHECK: vmovsd %xmm4, %xmm2, %xmm5 +// CHECK: encoding: [0xc5,0xeb,0x10,0xec] + vmovsd %xmm4, %xmm2, %xmm5 + +// CHECK: vunpckhps %xmm1, %xmm2, %xmm4 +// CHECK: encoding: [0xc5,0xe8,0x15,0xe1] + vunpckhps %xmm1, %xmm2, %xmm4 + +// CHECK: vunpckhpd %xmm1, %xmm2, %xmm4 +// CHECK: encoding: [0xc5,0xe9,0x15,0xe1] + vunpckhpd %xmm1, %xmm2, %xmm4 + +// CHECK: vunpcklps %xmm1, %xmm2, %xmm4 +// CHECK: encoding: [0xc5,0xe8,0x14,0xe1] + vunpcklps %xmm1, %xmm2, %xmm4 + +// CHECK: vunpcklpd %xmm1, %xmm2, %xmm4 +// CHECK: encoding: [0xc5,0xe9,0x14,0xe1] + vunpcklpd %xmm1, %xmm2, %xmm4 + +// CHECK: vunpckhps -4(%ebx,%ecx,8), %xmm2, %xmm5 +// CHECK: encoding: [0xc5,0xe8,0x15,0x6c,0xcb,0xfc] + vunpckhps -4(%ebx,%ecx,8), %xmm2, %xmm5 + +// CHECK: vunpckhpd -4(%ebx,%ecx,8), %xmm2, %xmm5 +// CHECK: encoding: [0xc5,0xe9,0x15,0x6c,0xcb,0xfc] + vunpckhpd -4(%ebx,%ecx,8), %xmm2, %xmm5 + +// CHECK: vunpcklps -4(%ebx,%ecx,8), %xmm2, %xmm5 +// CHECK: encoding: [0xc5,0xe8,0x14,0x6c,0xcb,0xfc] + vunpcklps -4(%ebx,%ecx,8), %xmm2, %xmm5 + +// CHECK: vunpcklpd -4(%ebx,%ecx,8), %xmm2, %xmm5 +// CHECK: encoding: [0xc5,0xe9,0x14,0x6c,0xcb,0xfc] + vunpcklpd -4(%ebx,%ecx,8), %xmm2, %xmm5 + +// CHECK: vcmpps $0, %xmm0, %xmm6, %xmm1 +// CHECK: encoding: [0xc5,0xc8,0xc2,0xc8,0x00] + vcmpps $0, %xmm0, %xmm6, %xmm1 + +// CHECK: vcmpps $0, (%eax), %xmm6, %xmm1 +// CHECK: encoding: [0xc5,0xc8,0xc2,0x08,0x00] + vcmpps $0, (%eax), %xmm6, %xmm1 + +// CHECK: vcmpps $7, %xmm0, %xmm6, %xmm1 +// CHECK: encoding: [0xc5,0xc8,0xc2,0xc8,0x07] + vcmpps $7, %xmm0, %xmm6, %xmm1 + +// CHECK: vcmppd $0, %xmm0, %xmm6, %xmm1 +// CHECK: encoding: [0xc5,0xc9,0xc2,0xc8,0x00] + vcmppd $0, %xmm0, %xmm6, %xmm1 + +// CHECK: vcmppd $0, (%eax), %xmm6, %xmm1 +// CHECK: encoding: [0xc5,0xc9,0xc2,0x08,0x00] + vcmppd $0, (%eax), %xmm6, %xmm1 + +// CHECK: vcmppd $7, %xmm0, %xmm6, %xmm1 +// CHECK: encoding: [0xc5,0xc9,0xc2,0xc8,0x07] + vcmppd $7, %xmm0, %xmm6, %xmm1 + +// CHECK: vshufps $8, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe8,0xc6,0xd9,0x08] + vshufps $8, %xmm1, %xmm2, %xmm3 + +// CHECK: vshufps $8, -4(%ebx,%ecx,8), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe8,0xc6,0x5c,0xcb,0xfc,0x08] + vshufps $8, -4(%ebx,%ecx,8), %xmm2, %xmm3 + +// CHECK: vshufpd $8, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xc6,0xd9,0x08] + vshufpd $8, %xmm1, %xmm2, %xmm3 + +// CHECK: vshufpd $8, -4(%ebx,%ecx,8), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xc6,0x5c,0xcb,0xfc,0x08] + vshufpd $8, -4(%ebx,%ecx,8), %xmm2, %xmm3 + +// CHECK: vcmpps $0, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x00] + vcmpeqps %xmm1, %xmm2, %xmm3 + +// CHECK: vcmpps $2, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x02] + vcmpleps %xmm1, %xmm2, %xmm3 + +// CHECK: vcmpps $1, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x01] + vcmpltps %xmm1, %xmm2, %xmm3 + +// CHECK: vcmpps $4, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x04] + vcmpneqps %xmm1, %xmm2, %xmm3 + +// CHECK: vcmpps $6, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x06] + vcmpnleps %xmm1, %xmm2, %xmm3 + +// CHECK: vcmpps $5, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x05] + vcmpnltps %xmm1, %xmm2, %xmm3 + +// CHECK: vcmpps $7, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x07] + vcmpordps %xmm1, %xmm2, %xmm3 + +// CHECK: vcmpps $3, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x03] + vcmpunordps %xmm1, %xmm2, %xmm3 + +// CHECK: vcmpps $0, -4(%ebx,%ecx,8), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe8,0xc2,0x5c,0xcb,0xfc,0x00] + vcmpeqps -4(%ebx,%ecx,8), %xmm2, %xmm3 + +// CHECK: vcmpps $2, -4(%ebx,%ecx,8), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe8,0xc2,0x5c,0xcb,0xfc,0x02] + vcmpleps -4(%ebx,%ecx,8), %xmm2, %xmm3 + +// CHECK: vcmpps $1, -4(%ebx,%ecx,8), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe8,0xc2,0x5c,0xcb,0xfc,0x01] + vcmpltps -4(%ebx,%ecx,8), %xmm2, %xmm3 + +// CHECK: vcmpps $4, -4(%ebx,%ecx,8), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe8,0xc2,0x5c,0xcb,0xfc,0x04] + vcmpneqps -4(%ebx,%ecx,8), %xmm2, %xmm3 + +// CHECK: vcmpps $6, -4(%ebx,%ecx,8), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe8,0xc2,0x5c,0xcb,0xfc,0x06] + vcmpnleps -4(%ebx,%ecx,8), %xmm2, %xmm3 + +// CHECK: vcmpps $5, -4(%ebx,%ecx,8), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe8,0xc2,0x5c,0xcb,0xfc,0x05] + vcmpnltps -4(%ebx,%ecx,8), %xmm2, %xmm3 + +// CHECK: vcmpps $7, -4(%ebx,%ecx,8), %xmm6, %xmm2 +// CHECK: encoding: [0xc5,0xc8,0xc2,0x54,0xcb,0xfc,0x07] + vcmpordps -4(%ebx,%ecx,8), %xmm6, %xmm2 + +// CHECK: vcmpps $3, -4(%ebx,%ecx,8), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe8,0xc2,0x5c,0xcb,0xfc,0x03] + vcmpunordps -4(%ebx,%ecx,8), %xmm2, %xmm3 + +// CHECK: vcmppd $0, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xc2,0xd9,0x00] + vcmpeqpd %xmm1, %xmm2, %xmm3 + +// CHECK: vcmppd $2, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xc2,0xd9,0x02] + vcmplepd %xmm1, %xmm2, %xmm3 + +// CHECK: vcmppd $1, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xc2,0xd9,0x01] + vcmpltpd %xmm1, %xmm2, %xmm3 + +// CHECK: vcmppd $4, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xc2,0xd9,0x04] + vcmpneqpd %xmm1, %xmm2, %xmm3 + +// CHECK: vcmppd $6, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xc2,0xd9,0x06] + vcmpnlepd %xmm1, %xmm2, %xmm3 + +// CHECK: vcmppd $5, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xc2,0xd9,0x05] + vcmpnltpd %xmm1, %xmm2, %xmm3 + +// CHECK: vcmppd $7, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xc2,0xd9,0x07] + vcmpordpd %xmm1, %xmm2, %xmm3 + +// CHECK: vcmppd $3, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xc2,0xd9,0x03] + vcmpunordpd %xmm1, %xmm2, %xmm3 + +// CHECK: vcmppd $0, -4(%ebx,%ecx,8), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xc2,0x5c,0xcb,0xfc,0x00] + vcmpeqpd -4(%ebx,%ecx,8), %xmm2, %xmm3 + +// CHECK: vcmppd $2, -4(%ebx,%ecx,8), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xc2,0x5c,0xcb,0xfc,0x02] + vcmplepd -4(%ebx,%ecx,8), %xmm2, %xmm3 + +// CHECK: vcmppd $1, -4(%ebx,%ecx,8), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xc2,0x5c,0xcb,0xfc,0x01] + vcmpltpd -4(%ebx,%ecx,8), %xmm2, %xmm3 + +// CHECK: vcmppd $4, -4(%ebx,%ecx,8), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xc2,0x5c,0xcb,0xfc,0x04] + vcmpneqpd -4(%ebx,%ecx,8), %xmm2, %xmm3 + +// CHECK: vcmppd $6, -4(%ebx,%ecx,8), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xc2,0x5c,0xcb,0xfc,0x06] + vcmpnlepd -4(%ebx,%ecx,8), %xmm2, %xmm3 + +// CHECK: vcmppd $5, -4(%ebx,%ecx,8), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xc2,0x5c,0xcb,0xfc,0x05] + vcmpnltpd -4(%ebx,%ecx,8), %xmm2, %xmm3 + +// CHECK: vcmppd $7, -4(%ebx,%ecx,8), %xmm6, %xmm2 +// CHECK: encoding: [0xc5,0xc9,0xc2,0x54,0xcb,0xfc,0x07] + vcmpordpd -4(%ebx,%ecx,8), %xmm6, %xmm2 + +// CHECK: vcmppd $3, -4(%ebx,%ecx,8), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xc2,0x5c,0xcb,0xfc,0x03] + vcmpunordpd -4(%ebx,%ecx,8), %xmm2, %xmm3 + +// CHECK: vmovmskps %xmm2, %eax +// CHECK: encoding: [0xc5,0xf8,0x50,0xc2] + vmovmskps %xmm2, %eax + +// CHECK: vmovmskpd %xmm2, %eax +// CHECK: encoding: [0xc5,0xf9,0x50,0xc2] + vmovmskpd %xmm2, %eax + +// CHECK: vcmpss $0, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xea,0xc2,0xd9,0x00] + vcmpeqss %xmm1, %xmm2, %xmm3 + +// CHECK: vcmpss $2, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xea,0xc2,0xd9,0x02] + vcmpless %xmm1, %xmm2, %xmm3 + +// CHECK: vcmpss $1, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xea,0xc2,0xd9,0x01] + vcmpltss %xmm1, %xmm2, %xmm3 + +// CHECK: vcmpss $4, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xea,0xc2,0xd9,0x04] + vcmpneqss %xmm1, %xmm2, %xmm3 + +// CHECK: vcmpss $6, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xea,0xc2,0xd9,0x06] + vcmpnless %xmm1, %xmm2, %xmm3 + +// CHECK: vcmpss $5, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xea,0xc2,0xd9,0x05] + vcmpnltss %xmm1, %xmm2, %xmm3 + +// CHECK: vcmpss $7, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xea,0xc2,0xd9,0x07] + vcmpordss %xmm1, %xmm2, %xmm3 + +// CHECK: vcmpss $3, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xea,0xc2,0xd9,0x03] + vcmpunordss %xmm1, %xmm2, %xmm3 + +// CHECK: vcmpss $0, -4(%ebx,%ecx,8), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xea,0xc2,0x5c,0xcb,0xfc,0x00] + vcmpeqss -4(%ebx,%ecx,8), %xmm2, %xmm3 + +// CHECK: vcmpss $2, -4(%ebx,%ecx,8), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xea,0xc2,0x5c,0xcb,0xfc,0x02] + vcmpless -4(%ebx,%ecx,8), %xmm2, %xmm3 + +// CHECK: vcmpss $1, -4(%ebx,%ecx,8), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xea,0xc2,0x5c,0xcb,0xfc,0x01] + vcmpltss -4(%ebx,%ecx,8), %xmm2, %xmm3 + +// CHECK: vcmpss $4, -4(%ebx,%ecx,8), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xea,0xc2,0x5c,0xcb,0xfc,0x04] + vcmpneqss -4(%ebx,%ecx,8), %xmm2, %xmm3 + +// CHECK: vcmpss $6, -4(%ebx,%ecx,8), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xea,0xc2,0x5c,0xcb,0xfc,0x06] + vcmpnless -4(%ebx,%ecx,8), %xmm2, %xmm3 + +// CHECK: vcmpss $5, -4(%ebx,%ecx,8), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xea,0xc2,0x5c,0xcb,0xfc,0x05] + vcmpnltss -4(%ebx,%ecx,8), %xmm2, %xmm3 + +// CHECK: vcmpss $7, -4(%ebx,%ecx,8), %xmm6, %xmm2 +// CHECK: encoding: [0xc5,0xca,0xc2,0x54,0xcb,0xfc,0x07] + vcmpordss -4(%ebx,%ecx,8), %xmm6, %xmm2 + +// CHECK: vcmpss $3, -4(%ebx,%ecx,8), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xea,0xc2,0x5c,0xcb,0xfc,0x03] + vcmpunordss -4(%ebx,%ecx,8), %xmm2, %xmm3 + +// CHECK: vcmpsd $0, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xeb,0xc2,0xd9,0x00] + vcmpeqsd %xmm1, %xmm2, %xmm3 + +// CHECK: vcmpsd $2, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xeb,0xc2,0xd9,0x02] + vcmplesd %xmm1, %xmm2, %xmm3 + +// CHECK: vcmpsd $1, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xeb,0xc2,0xd9,0x01] + vcmpltsd %xmm1, %xmm2, %xmm3 + +// CHECK: vcmpsd $4, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xeb,0xc2,0xd9,0x04] + vcmpneqsd %xmm1, %xmm2, %xmm3 + +// CHECK: vcmpsd $6, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xeb,0xc2,0xd9,0x06] + vcmpnlesd %xmm1, %xmm2, %xmm3 + +// CHECK: vcmpsd $5, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xeb,0xc2,0xd9,0x05] + vcmpnltsd %xmm1, %xmm2, %xmm3 + +// CHECK: vcmpsd $7, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xeb,0xc2,0xd9,0x07] + vcmpordsd %xmm1, %xmm2, %xmm3 + +// CHECK: vcmpsd $3, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xeb,0xc2,0xd9,0x03] + vcmpunordsd %xmm1, %xmm2, %xmm3 + +// CHECK: vcmpsd $0, -4(%ebx,%ecx,8), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xeb,0xc2,0x5c,0xcb,0xfc,0x00] + vcmpeqsd -4(%ebx,%ecx,8), %xmm2, %xmm3 + +// CHECK: vcmpsd $2, -4(%ebx,%ecx,8), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xeb,0xc2,0x5c,0xcb,0xfc,0x02] + vcmplesd -4(%ebx,%ecx,8), %xmm2, %xmm3 + +// CHECK: vcmpsd $1, -4(%ebx,%ecx,8), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xeb,0xc2,0x5c,0xcb,0xfc,0x01] + vcmpltsd -4(%ebx,%ecx,8), %xmm2, %xmm3 + +// CHECK: vcmpsd $4, -4(%ebx,%ecx,8), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xeb,0xc2,0x5c,0xcb,0xfc,0x04] + vcmpneqsd -4(%ebx,%ecx,8), %xmm2, %xmm3 + +// CHECK: vcmpsd $6, -4(%ebx,%ecx,8), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xeb,0xc2,0x5c,0xcb,0xfc,0x06] + vcmpnlesd -4(%ebx,%ecx,8), %xmm2, %xmm3 + +// CHECK: vcmpsd $5, -4(%ebx,%ecx,8), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xeb,0xc2,0x5c,0xcb,0xfc,0x05] + vcmpnltsd -4(%ebx,%ecx,8), %xmm2, %xmm3 + +// CHECK: vcmpsd $7, -4(%ebx,%ecx,8), %xmm6, %xmm2 +// CHECK: encoding: [0xc5,0xcb,0xc2,0x54,0xcb,0xfc,0x07] + vcmpordsd -4(%ebx,%ecx,8), %xmm6, %xmm2 + +// CHECK: vcmpsd $3, -4(%ebx,%ecx,8), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xeb,0xc2,0x5c,0xcb,0xfc,0x03] + vcmpunordsd -4(%ebx,%ecx,8), %xmm2, %xmm3 + +// CHECK: vucomiss %xmm1, %xmm2 +// CHECK: encoding: [0xc5,0xf8,0x2e,0xd1] + vucomiss %xmm1, %xmm2 + +// CHECK: vucomiss (%eax), %xmm2 +// CHECK: encoding: [0xc5,0xf8,0x2e,0x10] + vucomiss (%eax), %xmm2 + +// CHECK: vcomiss %xmm1, %xmm2 +// CHECK: encoding: [0xc5,0xf8,0x2f,0xd1] + vcomiss %xmm1, %xmm2 + +// CHECK: vcomiss (%eax), %xmm2 +// CHECK: encoding: [0xc5,0xf8,0x2f,0x10] + vcomiss (%eax), %xmm2 + +// CHECK: vucomisd %xmm1, %xmm2 +// CHECK: encoding: [0xc5,0xf9,0x2e,0xd1] + vucomisd %xmm1, %xmm2 + +// CHECK: vucomisd (%eax), %xmm2 +// CHECK: encoding: [0xc5,0xf9,0x2e,0x10] + vucomisd (%eax), %xmm2 + +// CHECK: vcomisd %xmm1, %xmm2 +// CHECK: encoding: [0xc5,0xf9,0x2f,0xd1] + vcomisd %xmm1, %xmm2 + +// CHECK: vcomisd (%eax), %xmm2 +// CHECK: encoding: [0xc5,0xf9,0x2f,0x10] + vcomisd (%eax), %xmm2 + +// CHECK: vcvttss2si %xmm1, %eax +// CHECK: encoding: [0xc5,0xfa,0x2c,0xc1] + vcvttss2si %xmm1, %eax + +// CHECK: vcvttss2si (%ecx), %eax +// CHECK: encoding: [0xc5,0xfa,0x2c,0x01] + vcvttss2si (%ecx), %eax + +// CHECK: vcvtsi2ss (%eax), %xmm1, %xmm2 +// CHECK: encoding: [0xc5,0xf2,0x2a,0x10] + vcvtsi2ss (%eax), %xmm1, %xmm2 + +// CHECK: vcvtsi2ss (%eax), %xmm1, %xmm2 +// CHECK: encoding: [0xc5,0xf2,0x2a,0x10] + vcvtsi2ss (%eax), %xmm1, %xmm2 + +// CHECK: vcvttsd2si %xmm1, %eax +// CHECK: encoding: [0xc5,0xfb,0x2c,0xc1] + vcvttsd2si %xmm1, %eax + +// CHECK: vcvttsd2si (%ecx), %eax +// CHECK: encoding: [0xc5,0xfb,0x2c,0x01] + vcvttsd2si (%ecx), %eax + +// CHECK: vcvtsi2sd (%eax), %xmm1, %xmm2 +// CHECK: encoding: [0xc5,0xf3,0x2a,0x10] + vcvtsi2sd (%eax), %xmm1, %xmm2 + +// CHECK: vcvtsi2sd (%eax), %xmm1, %xmm2 +// CHECK: encoding: [0xc5,0xf3,0x2a,0x10] + vcvtsi2sd (%eax), %xmm1, %xmm2 + +// CHECK: vmovaps (%eax), %xmm2 +// CHECK: encoding: [0xc5,0xf8,0x28,0x10] + vmovaps (%eax), %xmm2 + +// CHECK: vmovaps %xmm1, %xmm2 +// CHECK: encoding: [0xc5,0xf8,0x28,0xd1] + vmovaps %xmm1, %xmm2 + +// CHECK: vmovaps %xmm1, (%eax) +// CHECK: encoding: [0xc5,0xf8,0x29,0x08] + vmovaps %xmm1, (%eax) + +// CHECK: vmovapd (%eax), %xmm2 +// CHECK: encoding: [0xc5,0xf9,0x28,0x10] + vmovapd (%eax), %xmm2 + +// CHECK: vmovapd %xmm1, %xmm2 +// CHECK: encoding: [0xc5,0xf9,0x28,0xd1] + vmovapd %xmm1, %xmm2 + +// CHECK: vmovapd %xmm1, (%eax) +// CHECK: encoding: [0xc5,0xf9,0x29,0x08] + vmovapd %xmm1, (%eax) + +// CHECK: vmovups (%eax), %xmm2 +// CHECK: encoding: [0xc5,0xf8,0x10,0x10] + vmovups (%eax), %xmm2 + +// CHECK: vmovups %xmm1, %xmm2 +// CHECK: encoding: [0xc5,0xf8,0x10,0xd1] + vmovups %xmm1, %xmm2 + +// CHECK: vmovups %xmm1, (%eax) +// CHECK: encoding: [0xc5,0xf8,0x11,0x08] + vmovups %xmm1, (%eax) + +// CHECK: vmovupd (%eax), %xmm2 +// CHECK: encoding: [0xc5,0xf9,0x10,0x10] + vmovupd (%eax), %xmm2 + +// CHECK: vmovupd %xmm1, %xmm2 +// CHECK: encoding: [0xc5,0xf9,0x10,0xd1] + vmovupd %xmm1, %xmm2 + +// CHECK: vmovupd %xmm1, (%eax) +// CHECK: encoding: [0xc5,0xf9,0x11,0x08] + vmovupd %xmm1, (%eax) + +// CHECK: vmovlps %xmm1, (%eax) +// CHECK: encoding: [0xc5,0xf8,0x13,0x08] + vmovlps %xmm1, (%eax) + +// CHECK: vmovlps (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe8,0x12,0x18] + vmovlps (%eax), %xmm2, %xmm3 + +// CHECK: vmovlpd %xmm1, (%eax) +// CHECK: encoding: [0xc5,0xf9,0x13,0x08] + vmovlpd %xmm1, (%eax) + +// CHECK: vmovlpd (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0x12,0x18] + vmovlpd (%eax), %xmm2, %xmm3 + +// CHECK: vmovhps %xmm1, (%eax) +// CHECK: encoding: [0xc5,0xf8,0x17,0x08] + vmovhps %xmm1, (%eax) + +// CHECK: vmovhps (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe8,0x16,0x18] + vmovhps (%eax), %xmm2, %xmm3 + +// CHECK: vmovhpd %xmm1, (%eax) +// CHECK: encoding: [0xc5,0xf9,0x17,0x08] + vmovhpd %xmm1, (%eax) + +// CHECK: vmovhpd (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0x16,0x18] + vmovhpd (%eax), %xmm2, %xmm3 + +// CHECK: vmovlhps %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe8,0x16,0xd9] + vmovlhps %xmm1, %xmm2, %xmm3 + +// CHECK: vmovhlps %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe8,0x12,0xd9] + vmovhlps %xmm1, %xmm2, %xmm3 + +// CHECK: vcvtss2sil %xmm1, %eax +// CHECK: encoding: [0xc5,0xfa,0x2d,0xc1] + vcvtss2si %xmm1, %eax + +// CHECK: vcvtss2sil (%eax), %ebx +// CHECK: encoding: [0xc5,0xfa,0x2d,0x18] + vcvtss2si (%eax), %ebx + +// CHECK: vcvtdq2ps %xmm5, %xmm6 +// CHECK: encoding: [0xc5,0xf8,0x5b,0xf5] + vcvtdq2ps %xmm5, %xmm6 + +// CHECK: vcvtdq2ps (%eax), %xmm6 +// CHECK: encoding: [0xc5,0xf8,0x5b,0x30] + vcvtdq2ps (%eax), %xmm6 + +// CHECK: vcvtsd2ss %xmm2, %xmm4, %xmm6 +// CHECK: encoding: [0xc5,0xdb,0x5a,0xf2] + vcvtsd2ss %xmm2, %xmm4, %xmm6 + +// CHECK: vcvtsd2ss (%eax), %xmm4, %xmm6 +// CHECK: encoding: [0xc5,0xdb,0x5a,0x30] + vcvtsd2ss (%eax), %xmm4, %xmm6 + +// CHECK: vcvtps2dq %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xf9,0x5b,0xda] + vcvtps2dq %xmm2, %xmm3 + +// CHECK: vcvtps2dq (%eax), %xmm3 +// CHECK: encoding: [0xc5,0xf9,0x5b,0x18] + vcvtps2dq (%eax), %xmm3 + +// CHECK: vcvtss2sd %xmm2, %xmm4, %xmm6 +// CHECK: encoding: [0xc5,0xda,0x5a,0xf2] + vcvtss2sd %xmm2, %xmm4, %xmm6 + +// CHECK: vcvtss2sd (%eax), %xmm4, %xmm6 +// CHECK: encoding: [0xc5,0xda,0x5a,0x30] + vcvtss2sd (%eax), %xmm4, %xmm6 + +// CHECK: vcvtdq2ps %xmm4, %xmm6 +// CHECK: encoding: [0xc5,0xf8,0x5b,0xf4] + vcvtdq2ps %xmm4, %xmm6 + +// CHECK: vcvtdq2ps (%ecx), %xmm4 +// CHECK: encoding: [0xc5,0xf8,0x5b,0x21] + vcvtdq2ps (%ecx), %xmm4 + +// CHECK: vcvttps2dq %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xfa,0x5b,0xda] + vcvttps2dq %xmm2, %xmm3 + +// CHECK: vcvttps2dq (%eax), %xmm3 +// CHECK: encoding: [0xc5,0xfa,0x5b,0x18] + vcvttps2dq (%eax), %xmm3 + +// CHECK: vcvtps2pd %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xf8,0x5a,0xda] + vcvtps2pd %xmm2, %xmm3 + +// CHECK: vcvtps2pd (%eax), %xmm3 +// CHECK: encoding: [0xc5,0xf8,0x5a,0x18] + vcvtps2pd (%eax), %xmm3 + +// CHECK: vcvtpd2ps %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xf9,0x5a,0xda] + vcvtpd2ps %xmm2, %xmm3 + +// CHECK: vsqrtpd %xmm1, %xmm2 +// CHECK: encoding: [0xc5,0xf9,0x51,0xd1] + vsqrtpd %xmm1, %xmm2 + +// CHECK: vsqrtpd (%eax), %xmm2 +// CHECK: encoding: [0xc5,0xf9,0x51,0x10] + vsqrtpd (%eax), %xmm2 + +// CHECK: vsqrtps %xmm1, %xmm2 +// CHECK: encoding: [0xc5,0xf8,0x51,0xd1] + vsqrtps %xmm1, %xmm2 + +// CHECK: vsqrtps (%eax), %xmm2 +// CHECK: encoding: [0xc5,0xf8,0x51,0x10] + vsqrtps (%eax), %xmm2 + +// CHECK: vsqrtsd %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xeb,0x51,0xd9] + vsqrtsd %xmm1, %xmm2, %xmm3 + +// CHECK: vsqrtsd (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xeb,0x51,0x18] + vsqrtsd (%eax), %xmm2, %xmm3 + +// CHECK: vsqrtss %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xea,0x51,0xd9] + vsqrtss %xmm1, %xmm2, %xmm3 + +// CHECK: vsqrtss (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xea,0x51,0x18] + vsqrtss (%eax), %xmm2, %xmm3 + +// CHECK: vrsqrtps %xmm1, %xmm2 +// CHECK: encoding: [0xc5,0xf8,0x52,0xd1] + vrsqrtps %xmm1, %xmm2 + +// CHECK: vrsqrtps (%eax), %xmm2 +// CHECK: encoding: [0xc5,0xf8,0x52,0x10] + vrsqrtps (%eax), %xmm2 + +// CHECK: vrsqrtss %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xea,0x52,0xd9] + vrsqrtss %xmm1, %xmm2, %xmm3 + +// CHECK: vrsqrtss (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xea,0x52,0x18] + vrsqrtss (%eax), %xmm2, %xmm3 + +// CHECK: vrcpps %xmm1, %xmm2 +// CHECK: encoding: [0xc5,0xf8,0x53,0xd1] + vrcpps %xmm1, %xmm2 + +// CHECK: vrcpps (%eax), %xmm2 +// CHECK: encoding: [0xc5,0xf8,0x53,0x10] + vrcpps (%eax), %xmm2 + +// CHECK: vrcpss %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xea,0x53,0xd9] + vrcpss %xmm1, %xmm2, %xmm3 + +// CHECK: vrcpss (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xea,0x53,0x18] + vrcpss (%eax), %xmm2, %xmm3 + +// CHECK: vmovntdq %xmm1, (%eax) +// CHECK: encoding: [0xc5,0xf9,0xe7,0x08] + vmovntdq %xmm1, (%eax) + +// CHECK: vmovntpd %xmm1, (%eax) +// CHECK: encoding: [0xc5,0xf9,0x2b,0x08] + vmovntpd %xmm1, (%eax) + +// CHECK: vmovntps %xmm1, (%eax) +// CHECK: encoding: [0xc5,0xf8,0x2b,0x08] + vmovntps %xmm1, (%eax) + +// CHECK: vldmxcsr (%eax) +// CHECK: encoding: [0xc5,0xf8,0xae,0x10] + vldmxcsr (%eax) + +// CHECK: vstmxcsr (%eax) +// CHECK: encoding: [0xc5,0xf8,0xae,0x18] + vstmxcsr (%eax) + +// CHECK: vldmxcsr 3735928559 +// CHECK: encoding: [0xc5,0xf8,0xae,0x15,0xef,0xbe,0xad,0xde] + vldmxcsr 0xdeadbeef + +// CHECK: vstmxcsr 3735928559 +// CHECK: encoding: [0xc5,0xf8,0xae,0x1d,0xef,0xbe,0xad,0xde] + vstmxcsr 0xdeadbeef + +// CHECK: vpsubb %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xf8,0xd9] + vpsubb %xmm1, %xmm2, %xmm3 + +// CHECK: vpsubb (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xf8,0x18] + vpsubb (%eax), %xmm2, %xmm3 + +// CHECK: vpsubw %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xf9,0xd9] + vpsubw %xmm1, %xmm2, %xmm3 + +// CHECK: vpsubw (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xf9,0x18] + vpsubw (%eax), %xmm2, %xmm3 + +// CHECK: vpsubd %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xfa,0xd9] + vpsubd %xmm1, %xmm2, %xmm3 + +// CHECK: vpsubd (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xfa,0x18] + vpsubd (%eax), %xmm2, %xmm3 + +// CHECK: vpsubq %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xfb,0xd9] + vpsubq %xmm1, %xmm2, %xmm3 + +// CHECK: vpsubq (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xfb,0x18] + vpsubq (%eax), %xmm2, %xmm3 + +// CHECK: vpsubsb %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xe8,0xd9] + vpsubsb %xmm1, %xmm2, %xmm3 + +// CHECK: vpsubsb (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xe8,0x18] + vpsubsb (%eax), %xmm2, %xmm3 + +// CHECK: vpsubsw %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xe9,0xd9] + vpsubsw %xmm1, %xmm2, %xmm3 + +// CHECK: vpsubsw (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xe9,0x18] + vpsubsw (%eax), %xmm2, %xmm3 + +// CHECK: vpsubusb %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xd8,0xd9] + vpsubusb %xmm1, %xmm2, %xmm3 + +// CHECK: vpsubusb (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xd8,0x18] + vpsubusb (%eax), %xmm2, %xmm3 + +// CHECK: vpsubusw %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xd9,0xd9] + vpsubusw %xmm1, %xmm2, %xmm3 + +// CHECK: vpsubusw (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xd9,0x18] + vpsubusw (%eax), %xmm2, %xmm3 + +// CHECK: vpaddb %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xfc,0xd9] + vpaddb %xmm1, %xmm2, %xmm3 + +// CHECK: vpaddb (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xfc,0x18] + vpaddb (%eax), %xmm2, %xmm3 + +// CHECK: vpaddw %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xfd,0xd9] + vpaddw %xmm1, %xmm2, %xmm3 + +// CHECK: vpaddw (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xfd,0x18] + vpaddw (%eax), %xmm2, %xmm3 + +// CHECK: vpaddd %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xfe,0xd9] + vpaddd %xmm1, %xmm2, %xmm3 + +// CHECK: vpaddd (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xfe,0x18] + vpaddd (%eax), %xmm2, %xmm3 + +// CHECK: vpaddq %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xd4,0xd9] + vpaddq %xmm1, %xmm2, %xmm3 + +// CHECK: vpaddq (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xd4,0x18] + vpaddq (%eax), %xmm2, %xmm3 + +// CHECK: vpaddsb %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xec,0xd9] + vpaddsb %xmm1, %xmm2, %xmm3 + +// CHECK: vpaddsb (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xec,0x18] + vpaddsb (%eax), %xmm2, %xmm3 + +// CHECK: vpaddsw %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xed,0xd9] + vpaddsw %xmm1, %xmm2, %xmm3 + +// CHECK: vpaddsw (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xed,0x18] + vpaddsw (%eax), %xmm2, %xmm3 + +// CHECK: vpaddusb %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xdc,0xd9] + vpaddusb %xmm1, %xmm2, %xmm3 + +// CHECK: vpaddusb (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xdc,0x18] + vpaddusb (%eax), %xmm2, %xmm3 + +// CHECK: vpaddusw %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xdd,0xd9] + vpaddusw %xmm1, %xmm2, %xmm3 + +// CHECK: vpaddusw (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xdd,0x18] + vpaddusw (%eax), %xmm2, %xmm3 + +// CHECK: vpmulhuw %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xe4,0xd9] + vpmulhuw %xmm1, %xmm2, %xmm3 + +// CHECK: vpmulhuw (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xe4,0x18] + vpmulhuw (%eax), %xmm2, %xmm3 + +// CHECK: vpmulhw %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xe5,0xd9] + vpmulhw %xmm1, %xmm2, %xmm3 + +// CHECK: vpmulhw (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xe5,0x18] + vpmulhw (%eax), %xmm2, %xmm3 + +// CHECK: vpmullw %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xd5,0xd9] + vpmullw %xmm1, %xmm2, %xmm3 + +// CHECK: vpmullw (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xd5,0x18] + vpmullw (%eax), %xmm2, %xmm3 + +// CHECK: vpmuludq %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xf4,0xd9] + vpmuludq %xmm1, %xmm2, %xmm3 + +// CHECK: vpmuludq (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xf4,0x18] + vpmuludq (%eax), %xmm2, %xmm3 + +// CHECK: vpavgb %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xe0,0xd9] + vpavgb %xmm1, %xmm2, %xmm3 + +// CHECK: vpavgb (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xe0,0x18] + vpavgb (%eax), %xmm2, %xmm3 + +// CHECK: vpavgw %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xe3,0xd9] + vpavgw %xmm1, %xmm2, %xmm3 + +// CHECK: vpavgw (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xe3,0x18] + vpavgw (%eax), %xmm2, %xmm3 + +// CHECK: vpminsw %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xea,0xd9] + vpminsw %xmm1, %xmm2, %xmm3 + +// CHECK: vpminsw (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xea,0x18] + vpminsw (%eax), %xmm2, %xmm3 + +// CHECK: vpminub %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xda,0xd9] + vpminub %xmm1, %xmm2, %xmm3 + +// CHECK: vpminub (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xda,0x18] + vpminub (%eax), %xmm2, %xmm3 + +// CHECK: vpmaxsw %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xee,0xd9] + vpmaxsw %xmm1, %xmm2, %xmm3 + +// CHECK: vpmaxsw (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xee,0x18] + vpmaxsw (%eax), %xmm2, %xmm3 + +// CHECK: vpmaxub %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xde,0xd9] + vpmaxub %xmm1, %xmm2, %xmm3 + +// CHECK: vpmaxub (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xde,0x18] + vpmaxub (%eax), %xmm2, %xmm3 + +// CHECK: vpsadbw %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xf6,0xd9] + vpsadbw %xmm1, %xmm2, %xmm3 + +// CHECK: vpsadbw (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xf6,0x18] + vpsadbw (%eax), %xmm2, %xmm3 + +// CHECK: vpsllw %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xf1,0xd9] + vpsllw %xmm1, %xmm2, %xmm3 + +// CHECK: vpsllw (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xf1,0x18] + vpsllw (%eax), %xmm2, %xmm3 + +// CHECK: vpslld %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xf2,0xd9] + vpslld %xmm1, %xmm2, %xmm3 + +// CHECK: vpslld (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xf2,0x18] + vpslld (%eax), %xmm2, %xmm3 + +// CHECK: vpsllq %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xf3,0xd9] + vpsllq %xmm1, %xmm2, %xmm3 + +// CHECK: vpsllq (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xf3,0x18] + vpsllq (%eax), %xmm2, %xmm3 + +// CHECK: vpsraw %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xe1,0xd9] + vpsraw %xmm1, %xmm2, %xmm3 + +// CHECK: vpsraw (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xe1,0x18] + vpsraw (%eax), %xmm2, %xmm3 + +// CHECK: vpsrad %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xe2,0xd9] + vpsrad %xmm1, %xmm2, %xmm3 + +// CHECK: vpsrad (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xe2,0x18] + vpsrad (%eax), %xmm2, %xmm3 + +// CHECK: vpsrlw %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xd1,0xd9] + vpsrlw %xmm1, %xmm2, %xmm3 + +// CHECK: vpsrlw (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xd1,0x18] + vpsrlw (%eax), %xmm2, %xmm3 + +// CHECK: vpsrld %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xd2,0xd9] + vpsrld %xmm1, %xmm2, %xmm3 + +// CHECK: vpsrld (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xd2,0x18] + vpsrld (%eax), %xmm2, %xmm3 + +// CHECK: vpsrlq %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xd3,0xd9] + vpsrlq %xmm1, %xmm2, %xmm3 + +// CHECK: vpsrlq (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xd3,0x18] + vpsrlq (%eax), %xmm2, %xmm3 + +// CHECK: vpslld $10, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe1,0x72,0xf2,0x0a] + vpslld $10, %xmm2, %xmm3 + +// CHECK: vpslldq $10, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe1,0x73,0xfa,0x0a] + vpslldq $10, %xmm2, %xmm3 + +// CHECK: vpsllq $10, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe1,0x73,0xf2,0x0a] + vpsllq $10, %xmm2, %xmm3 + +// CHECK: vpsllw $10, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe1,0x71,0xf2,0x0a] + vpsllw $10, %xmm2, %xmm3 + +// CHECK: vpsrad $10, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe1,0x72,0xe2,0x0a] + vpsrad $10, %xmm2, %xmm3 + +// CHECK: vpsraw $10, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe1,0x71,0xe2,0x0a] + vpsraw $10, %xmm2, %xmm3 + +// CHECK: vpsrld $10, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe1,0x72,0xd2,0x0a] + vpsrld $10, %xmm2, %xmm3 + +// CHECK: vpsrldq $10, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe1,0x73,0xda,0x0a] + vpsrldq $10, %xmm2, %xmm3 + +// CHECK: vpsrlq $10, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe1,0x73,0xd2,0x0a] + vpsrlq $10, %xmm2, %xmm3 + +// CHECK: vpsrlw $10, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe1,0x71,0xd2,0x0a] + vpsrlw $10, %xmm2, %xmm3 + +// CHECK: vpslld $10, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe1,0x72,0xf2,0x0a] + vpslld $10, %xmm2, %xmm3 + +// CHECK: vpand %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xdb,0xd9] + vpand %xmm1, %xmm2, %xmm3 + +// CHECK: vpand (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xdb,0x18] + vpand (%eax), %xmm2, %xmm3 + +// CHECK: vpor %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xeb,0xd9] + vpor %xmm1, %xmm2, %xmm3 + +// CHECK: vpor (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xeb,0x18] + vpor (%eax), %xmm2, %xmm3 + +// CHECK: vpxor %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xef,0xd9] + vpxor %xmm1, %xmm2, %xmm3 + +// CHECK: vpxor (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xef,0x18] + vpxor (%eax), %xmm2, %xmm3 + +// CHECK: vpandn %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xdf,0xd9] + vpandn %xmm1, %xmm2, %xmm3 + +// CHECK: vpandn (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xdf,0x18] + vpandn (%eax), %xmm2, %xmm3 + +// CHECK: vpcmpeqb %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0x74,0xd9] + vpcmpeqb %xmm1, %xmm2, %xmm3 + +// CHECK: vpcmpeqb (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0x74,0x18] + vpcmpeqb (%eax), %xmm2, %xmm3 + +// CHECK: vpcmpeqw %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0x75,0xd9] + vpcmpeqw %xmm1, %xmm2, %xmm3 + +// CHECK: vpcmpeqw (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0x75,0x18] + vpcmpeqw (%eax), %xmm2, %xmm3 + +// CHECK: vpcmpeqd %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0x76,0xd9] + vpcmpeqd %xmm1, %xmm2, %xmm3 + +// CHECK: vpcmpeqd (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0x76,0x18] + vpcmpeqd (%eax), %xmm2, %xmm3 + +// CHECK: vpcmpgtb %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0x64,0xd9] + vpcmpgtb %xmm1, %xmm2, %xmm3 + +// CHECK: vpcmpgtb (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0x64,0x18] + vpcmpgtb (%eax), %xmm2, %xmm3 + +// CHECK: vpcmpgtw %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0x65,0xd9] + vpcmpgtw %xmm1, %xmm2, %xmm3 + +// CHECK: vpcmpgtw (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0x65,0x18] + vpcmpgtw (%eax), %xmm2, %xmm3 + +// CHECK: vpcmpgtd %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0x66,0xd9] + vpcmpgtd %xmm1, %xmm2, %xmm3 + +// CHECK: vpcmpgtd (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0x66,0x18] + vpcmpgtd (%eax), %xmm2, %xmm3 + +// CHECK: vpacksswb %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0x63,0xd9] + vpacksswb %xmm1, %xmm2, %xmm3 + +// CHECK: vpacksswb (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0x63,0x18] + vpacksswb (%eax), %xmm2, %xmm3 + +// CHECK: vpackssdw %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0x6b,0xd9] + vpackssdw %xmm1, %xmm2, %xmm3 + +// CHECK: vpackssdw (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0x6b,0x18] + vpackssdw (%eax), %xmm2, %xmm3 + +// CHECK: vpackuswb %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0x67,0xd9] + vpackuswb %xmm1, %xmm2, %xmm3 + +// CHECK: vpackuswb (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0x67,0x18] + vpackuswb (%eax), %xmm2, %xmm3 + +// CHECK: vpshufd $4, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xf9,0x70,0xda,0x04] + vpshufd $4, %xmm2, %xmm3 + +// CHECK: vpshufd $4, (%eax), %xmm3 +// CHECK: encoding: [0xc5,0xf9,0x70,0x18,0x04] + vpshufd $4, (%eax), %xmm3 + +// CHECK: vpshufhw $4, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xfa,0x70,0xda,0x04] + vpshufhw $4, %xmm2, %xmm3 + +// CHECK: vpshufhw $4, (%eax), %xmm3 +// CHECK: encoding: [0xc5,0xfa,0x70,0x18,0x04] + vpshufhw $4, (%eax), %xmm3 + +// CHECK: vpshuflw $4, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xfb,0x70,0xda,0x04] + vpshuflw $4, %xmm2, %xmm3 + +// CHECK: vpshuflw $4, (%eax), %xmm3 +// CHECK: encoding: [0xc5,0xfb,0x70,0x18,0x04] + vpshuflw $4, (%eax), %xmm3 + +// CHECK: vpunpcklbw %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0x60,0xd9] + vpunpcklbw %xmm1, %xmm2, %xmm3 + +// CHECK: vpunpcklbw (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0x60,0x18] + vpunpcklbw (%eax), %xmm2, %xmm3 + +// CHECK: vpunpcklwd %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0x61,0xd9] + vpunpcklwd %xmm1, %xmm2, %xmm3 + +// CHECK: vpunpcklwd (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0x61,0x18] + vpunpcklwd (%eax), %xmm2, %xmm3 + +// CHECK: vpunpckldq %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0x62,0xd9] + vpunpckldq %xmm1, %xmm2, %xmm3 + +// CHECK: vpunpckldq (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0x62,0x18] + vpunpckldq (%eax), %xmm2, %xmm3 + +// CHECK: vpunpcklqdq %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0x6c,0xd9] + vpunpcklqdq %xmm1, %xmm2, %xmm3 + +// CHECK: vpunpcklqdq (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0x6c,0x18] + vpunpcklqdq (%eax), %xmm2, %xmm3 + +// CHECK: vpunpckhbw %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0x68,0xd9] + vpunpckhbw %xmm1, %xmm2, %xmm3 + +// CHECK: vpunpckhbw (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0x68,0x18] + vpunpckhbw (%eax), %xmm2, %xmm3 + +// CHECK: vpunpckhwd %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0x69,0xd9] + vpunpckhwd %xmm1, %xmm2, %xmm3 + +// CHECK: vpunpckhwd (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0x69,0x18] + vpunpckhwd (%eax), %xmm2, %xmm3 + +// CHECK: vpunpckhdq %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0x6a,0xd9] + vpunpckhdq %xmm1, %xmm2, %xmm3 + +// CHECK: vpunpckhdq (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0x6a,0x18] + vpunpckhdq (%eax), %xmm2, %xmm3 + +// CHECK: vpunpckhqdq %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0x6d,0xd9] + vpunpckhqdq %xmm1, %xmm2, %xmm3 + +// CHECK: vpunpckhqdq (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0x6d,0x18] + vpunpckhqdq (%eax), %xmm2, %xmm3 + +// CHECK: vpinsrw $7, %eax, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xc4,0xd8,0x07] + vpinsrw $7, %eax, %xmm2, %xmm3 + +// CHECK: vpinsrw $7, (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xc4,0x18,0x07] + vpinsrw $7, (%eax), %xmm2, %xmm3 + +// CHECK: vpextrw $7, %xmm2, %eax +// CHECK: encoding: [0xc5,0xf9,0xc5,0xc2,0x07] + vpextrw $7, %xmm2, %eax + +// CHECK: vpmovmskb %xmm1, %eax +// CHECK: encoding: [0xc5,0xf9,0xd7,0xc1] + vpmovmskb %xmm1, %eax + +// CHECK: vmaskmovdqu %xmm1, %xmm2 +// CHECK: encoding: [0xc5,0xf9,0xf7,0xd1] + vmaskmovdqu %xmm1, %xmm2 + +// CHECK: vmovd %xmm1, %eax +// CHECK: encoding: [0xc5,0xf9,0x7e,0xc8] + vmovd %xmm1, %eax + +// CHECK: vmovd %xmm1, (%eax) +// CHECK: encoding: [0xc5,0xf9,0x7e,0x08] + vmovd %xmm1, (%eax) + +// CHECK: vmovd %eax, %xmm1 +// CHECK: encoding: [0xc5,0xf9,0x6e,0xc8] + vmovd %eax, %xmm1 + +// CHECK: vmovd (%eax), %xmm1 +// CHECK: encoding: [0xc5,0xf9,0x6e,0x08] + vmovd (%eax), %xmm1 + +// CHECK: vmovq %xmm1, (%eax) +// CHECK: encoding: [0xc5,0xf9,0xd6,0x08] + vmovq %xmm1, (%eax) + +// CHECK: vmovq %xmm1, %xmm2 +// CHECK: encoding: [0xc5,0xfa,0x7e,0xd1] + vmovq %xmm1, %xmm2 + +// CHECK: vmovq (%eax), %xmm1 +// CHECK: encoding: [0xc5,0xfa,0x7e,0x08] + vmovq (%eax), %xmm1 + +// CHECK: vcvtpd2dq %xmm1, %xmm2 +// CHECK: encoding: [0xc5,0xfb,0xe6,0xd1] + vcvtpd2dq %xmm1, %xmm2 + +// CHECK: vcvtdq2pd %xmm1, %xmm2 +// CHECK: encoding: [0xc5,0xfa,0xe6,0xd1] + vcvtdq2pd %xmm1, %xmm2 + +// CHECK: vcvtdq2pd (%eax), %xmm2 +// CHECK: encoding: [0xc5,0xfa,0xe6,0x10] + vcvtdq2pd (%eax), %xmm2 + +// CHECK: vmovshdup %xmm1, %xmm2 +// CHECK: encoding: [0xc5,0xfa,0x16,0xd1] + vmovshdup %xmm1, %xmm2 + +// CHECK: vmovshdup (%eax), %xmm2 +// CHECK: encoding: [0xc5,0xfa,0x16,0x10] + vmovshdup (%eax), %xmm2 + +// CHECK: vmovsldup %xmm1, %xmm2 +// CHECK: encoding: [0xc5,0xfa,0x12,0xd1] + vmovsldup %xmm1, %xmm2 + +// CHECK: vmovsldup (%eax), %xmm2 +// CHECK: encoding: [0xc5,0xfa,0x12,0x10] + vmovsldup (%eax), %xmm2 + +// CHECK: vmovddup %xmm1, %xmm2 +// CHECK: encoding: [0xc5,0xfb,0x12,0xd1] + vmovddup %xmm1, %xmm2 + +// CHECK: vmovddup (%eax), %xmm2 +// CHECK: encoding: [0xc5,0xfb,0x12,0x10] + vmovddup (%eax), %xmm2 + +// CHECK: vaddsubps %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xeb,0xd0,0xd9] + vaddsubps %xmm1, %xmm2, %xmm3 + +// CHECK: vaddsubps (%eax), %xmm1, %xmm2 +// CHECK: encoding: [0xc5,0xf3,0xd0,0x10] + vaddsubps (%eax), %xmm1, %xmm2 + +// CHECK: vaddsubpd %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0xd0,0xd9] + vaddsubpd %xmm1, %xmm2, %xmm3 + +// CHECK: vaddsubpd (%eax), %xmm1, %xmm2 +// CHECK: encoding: [0xc5,0xf1,0xd0,0x10] + vaddsubpd (%eax), %xmm1, %xmm2 + +// CHECK: vhaddps %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xeb,0x7c,0xd9] + vhaddps %xmm1, %xmm2, %xmm3 + +// CHECK: vhaddps (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xeb,0x7c,0x18] + vhaddps (%eax), %xmm2, %xmm3 + +// CHECK: vhaddpd %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0x7c,0xd9] + vhaddpd %xmm1, %xmm2, %xmm3 + +// CHECK: vhaddpd (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0x7c,0x18] + vhaddpd (%eax), %xmm2, %xmm3 + +// CHECK: vhsubps %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xeb,0x7d,0xd9] + vhsubps %xmm1, %xmm2, %xmm3 + +// CHECK: vhsubps (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xeb,0x7d,0x18] + vhsubps (%eax), %xmm2, %xmm3 + +// CHECK: vhsubpd %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0x7d,0xd9] + vhsubpd %xmm1, %xmm2, %xmm3 + +// CHECK: vhsubpd (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe9,0x7d,0x18] + vhsubpd (%eax), %xmm2, %xmm3 + +// CHECK: vpabsb %xmm1, %xmm2 +// CHECK: encoding: [0xc4,0xe2,0x79,0x1c,0xd1] + vpabsb %xmm1, %xmm2 + +// CHECK: vpabsb (%eax), %xmm2 +// CHECK: encoding: [0xc4,0xe2,0x79,0x1c,0x10] + vpabsb (%eax), %xmm2 + +// CHECK: vpabsw %xmm1, %xmm2 +// CHECK: encoding: [0xc4,0xe2,0x79,0x1d,0xd1] + vpabsw %xmm1, %xmm2 + +// CHECK: vpabsw (%eax), %xmm2 +// CHECK: encoding: [0xc4,0xe2,0x79,0x1d,0x10] + vpabsw (%eax), %xmm2 + +// CHECK: vpabsd %xmm1, %xmm2 +// CHECK: encoding: [0xc4,0xe2,0x79,0x1e,0xd1] + vpabsd %xmm1, %xmm2 + +// CHECK: vpabsd (%eax), %xmm2 +// CHECK: encoding: [0xc4,0xe2,0x79,0x1e,0x10] + vpabsd (%eax), %xmm2 + +// CHECK: vphaddw %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc4,0xe2,0x69,0x01,0xd9] + vphaddw %xmm1, %xmm2, %xmm3 + +// CHECK: vphaddw (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc4,0xe2,0x69,0x01,0x18] + vphaddw (%eax), %xmm2, %xmm3 + +// CHECK: vphaddd %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc4,0xe2,0x69,0x02,0xd9] + vphaddd %xmm1, %xmm2, %xmm3 + +// CHECK: vphaddd (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc4,0xe2,0x69,0x02,0x18] + vphaddd (%eax), %xmm2, %xmm3 + +// CHECK: vphaddsw %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc4,0xe2,0x69,0x03,0xd9] + vphaddsw %xmm1, %xmm2, %xmm3 + +// CHECK: vphaddsw (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc4,0xe2,0x69,0x03,0x18] + vphaddsw (%eax), %xmm2, %xmm3 + +// CHECK: vphsubw %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc4,0xe2,0x69,0x05,0xd9] + vphsubw %xmm1, %xmm2, %xmm3 + +// CHECK: vphsubw (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc4,0xe2,0x69,0x05,0x18] + vphsubw (%eax), %xmm2, %xmm3 + +// CHECK: vphsubd %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc4,0xe2,0x69,0x06,0xd9] + vphsubd %xmm1, %xmm2, %xmm3 + +// CHECK: vphsubd (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc4,0xe2,0x69,0x06,0x18] + vphsubd (%eax), %xmm2, %xmm3 + +// CHECK: vphsubsw %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc4,0xe2,0x69,0x07,0xd9] + vphsubsw %xmm1, %xmm2, %xmm3 + +// CHECK: vphsubsw (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc4,0xe2,0x69,0x07,0x18] + vphsubsw (%eax), %xmm2, %xmm3 + +// CHECK: vpmaddubsw %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc4,0xe2,0x69,0x04,0xd9] + vpmaddubsw %xmm1, %xmm2, %xmm3 + +// CHECK: vpmaddubsw (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc4,0xe2,0x69,0x04,0x18] + vpmaddubsw (%eax), %xmm2, %xmm3 + +// CHECK: vpshufb %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc4,0xe2,0x69,0x00,0xd9] + vpshufb %xmm1, %xmm2, %xmm3 + +// CHECK: vpshufb (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc4,0xe2,0x69,0x00,0x18] + vpshufb (%eax), %xmm2, %xmm3 + +// CHECK: vpsignb %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc4,0xe2,0x69,0x08,0xd9] + vpsignb %xmm1, %xmm2, %xmm3 + +// CHECK: vpsignb (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc4,0xe2,0x69,0x08,0x18] + vpsignb (%eax), %xmm2, %xmm3 + +// CHECK: vpsignw %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc4,0xe2,0x69,0x09,0xd9] + vpsignw %xmm1, %xmm2, %xmm3 + +// CHECK: vpsignw (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc4,0xe2,0x69,0x09,0x18] + vpsignw (%eax), %xmm2, %xmm3 + +// CHECK: vpsignd %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc4,0xe2,0x69,0x0a,0xd9] + vpsignd %xmm1, %xmm2, %xmm3 + +// CHECK: vpsignd (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc4,0xe2,0x69,0x0a,0x18] + vpsignd (%eax), %xmm2, %xmm3 + +// CHECK: vpmulhrsw %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc4,0xe2,0x69,0x0b,0xd9] + vpmulhrsw %xmm1, %xmm2, %xmm3 + +// CHECK: vpmulhrsw (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc4,0xe2,0x69,0x0b,0x18] + vpmulhrsw (%eax), %xmm2, %xmm3 + +// CHECK: vpalignr $7, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc4,0xe3,0x69,0x0f,0xd9,0x07] + vpalignr $7, %xmm1, %xmm2, %xmm3 + +// CHECK: vpalignr $7, (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc4,0xe3,0x69,0x0f,0x18,0x07] + vpalignr $7, (%eax), %xmm2, %xmm3 + +// CHECK: vroundsd $7, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc4,0xe3,0x69,0x0b,0xd9,0x07] + vroundsd $7, %xmm1, %xmm2, %xmm3 + +// CHECK: vroundsd $7, (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc4,0xe3,0x69,0x0b,0x18,0x07] + vroundsd $7, (%eax), %xmm2, %xmm3 + +// CHECK: vroundss $7, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc4,0xe3,0x69,0x0a,0xd9,0x07] + vroundss $7, %xmm1, %xmm2, %xmm3 + +// CHECK: vroundss $7, (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc4,0xe3,0x69,0x0a,0x18,0x07] + vroundss $7, (%eax), %xmm2, %xmm3 + +// CHECK: vroundpd $7, %xmm2, %xmm3 +// CHECK: encoding: [0xc4,0xe3,0x79,0x09,0xda,0x07] + vroundpd $7, %xmm2, %xmm3 + +// CHECK: vroundpd $7, (%eax), %xmm3 +// CHECK: encoding: [0xc4,0xe3,0x79,0x09,0x18,0x07] + vroundpd $7, (%eax), %xmm3 + +// CHECK: vroundps $7, %xmm2, %xmm3 +// CHECK: encoding: [0xc4,0xe3,0x79,0x08,0xda,0x07] + vroundps $7, %xmm2, %xmm3 + +// CHECK: vroundps $7, (%eax), %xmm3 +// CHECK: encoding: [0xc4,0xe3,0x79,0x08,0x18,0x07] + vroundps $7, (%eax), %xmm3 + +// CHECK: vphminposuw %xmm2, %xmm3 +// CHECK: encoding: [0xc4,0xe2,0x79,0x41,0xda] + vphminposuw %xmm2, %xmm3 + +// CHECK: vphminposuw (%eax), %xmm2 +// CHECK: encoding: [0xc4,0xe2,0x79,0x41,0x10] + vphminposuw (%eax), %xmm2 + +// CHECK: vpackusdw %xmm2, %xmm3, %xmm1 +// CHECK: encoding: [0xc4,0xe2,0x61,0x2b,0xca] + vpackusdw %xmm2, %xmm3, %xmm1 + +// CHECK: vpackusdw (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc4,0xe2,0x69,0x2b,0x18] + vpackusdw (%eax), %xmm2, %xmm3 + +// CHECK: vpcmpeqq %xmm2, %xmm3, %xmm1 +// CHECK: encoding: [0xc4,0xe2,0x61,0x29,0xca] + vpcmpeqq %xmm2, %xmm3, %xmm1 + +// CHECK: vpcmpeqq (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc4,0xe2,0x69,0x29,0x18] + vpcmpeqq (%eax), %xmm2, %xmm3 + +// CHECK: vpminsb %xmm2, %xmm3, %xmm1 +// CHECK: encoding: [0xc4,0xe2,0x61,0x38,0xca] + vpminsb %xmm2, %xmm3, %xmm1 + +// CHECK: vpminsb (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc4,0xe2,0x69,0x38,0x18] + vpminsb (%eax), %xmm2, %xmm3 + +// CHECK: vpminsd %xmm2, %xmm3, %xmm1 +// CHECK: encoding: [0xc4,0xe2,0x61,0x39,0xca] + vpminsd %xmm2, %xmm3, %xmm1 + +// CHECK: vpminsd (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc4,0xe2,0x69,0x39,0x18] + vpminsd (%eax), %xmm2, %xmm3 + +// CHECK: vpminud %xmm2, %xmm3, %xmm1 +// CHECK: encoding: [0xc4,0xe2,0x61,0x3b,0xca] + vpminud %xmm2, %xmm3, %xmm1 + +// CHECK: vpminud (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc4,0xe2,0x69,0x3b,0x18] + vpminud (%eax), %xmm2, %xmm3 + +// CHECK: vpminuw %xmm2, %xmm3, %xmm1 +// CHECK: encoding: [0xc4,0xe2,0x61,0x3a,0xca] + vpminuw %xmm2, %xmm3, %xmm1 + +// CHECK: vpminuw (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc4,0xe2,0x69,0x3a,0x18] + vpminuw (%eax), %xmm2, %xmm3 + +// CHECK: vpmaxsb %xmm2, %xmm3, %xmm1 +// CHECK: encoding: [0xc4,0xe2,0x61,0x3c,0xca] + vpmaxsb %xmm2, %xmm3, %xmm1 + +// CHECK: vpmaxsb (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc4,0xe2,0x69,0x3c,0x18] + vpmaxsb (%eax), %xmm2, %xmm3 + +// CHECK: vpmaxsd %xmm2, %xmm3, %xmm1 +// CHECK: encoding: [0xc4,0xe2,0x61,0x3d,0xca] + vpmaxsd %xmm2, %xmm3, %xmm1 + +// CHECK: vpmaxsd (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc4,0xe2,0x69,0x3d,0x18] + vpmaxsd (%eax), %xmm2, %xmm3 + +// CHECK: vpmaxud %xmm2, %xmm3, %xmm1 +// CHECK: encoding: [0xc4,0xe2,0x61,0x3f,0xca] + vpmaxud %xmm2, %xmm3, %xmm1 + +// CHECK: vpmaxud (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc4,0xe2,0x69,0x3f,0x18] + vpmaxud (%eax), %xmm2, %xmm3 + +// CHECK: vpmaxuw %xmm2, %xmm3, %xmm1 +// CHECK: encoding: [0xc4,0xe2,0x61,0x3e,0xca] + vpmaxuw %xmm2, %xmm3, %xmm1 + +// CHECK: vpmaxuw (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc4,0xe2,0x69,0x3e,0x18] + vpmaxuw (%eax), %xmm2, %xmm3 + +// CHECK: vpmuldq %xmm2, %xmm3, %xmm1 +// CHECK: encoding: [0xc4,0xe2,0x61,0x28,0xca] + vpmuldq %xmm2, %xmm3, %xmm1 + +// CHECK: vpmuldq (%eax), %xmm2, %xmm3 +// CHECK: encoding: [0xc4,0xe2,0x69,0x28,0x18] + vpmuldq (%eax), %xmm2, %xmm3 + +// CHECK: vpmulld %xmm2, %xmm5, %xmm1 +// CHECK: encoding: [0xc4,0xe2,0x51,0x40,0xca] + vpmulld %xmm2, %xmm5, %xmm1 + +// CHECK: vpmulld (%eax), %xmm5, %xmm3 +// CHECK: encoding: [0xc4,0xe2,0x51,0x40,0x18] + vpmulld (%eax), %xmm5, %xmm3 + +// CHECK: vblendps $3, %xmm2, %xmm5, %xmm1 +// CHECK: encoding: [0xc4,0xe3,0x51,0x0c,0xca,0x03] + vblendps $3, %xmm2, %xmm5, %xmm1 + +// CHECK: vblendps $3, (%eax), %xmm5, %xmm1 +// CHECK: encoding: [0xc4,0xe3,0x51,0x0c,0x08,0x03] + vblendps $3, (%eax), %xmm5, %xmm1 + +// CHECK: vblendpd $3, %xmm2, %xmm5, %xmm1 +// CHECK: encoding: [0xc4,0xe3,0x51,0x0d,0xca,0x03] + vblendpd $3, %xmm2, %xmm5, %xmm1 + +// CHECK: vblendpd $3, (%eax), %xmm5, %xmm1 +// CHECK: encoding: [0xc4,0xe3,0x51,0x0d,0x08,0x03] + vblendpd $3, (%eax), %xmm5, %xmm1 + +// CHECK: vpblendw $3, %xmm2, %xmm5, %xmm1 +// CHECK: encoding: [0xc4,0xe3,0x51,0x0e,0xca,0x03] + vpblendw $3, %xmm2, %xmm5, %xmm1 + +// CHECK: vpblendw $3, (%eax), %xmm5, %xmm1 +// CHECK: encoding: [0xc4,0xe3,0x51,0x0e,0x08,0x03] + vpblendw $3, (%eax), %xmm5, %xmm1 + +// CHECK: vmpsadbw $3, %xmm2, %xmm5, %xmm1 +// CHECK: encoding: [0xc4,0xe3,0x51,0x42,0xca,0x03] + vmpsadbw $3, %xmm2, %xmm5, %xmm1 + +// CHECK: vmpsadbw $3, (%eax), %xmm5, %xmm1 +// CHECK: encoding: [0xc4,0xe3,0x51,0x42,0x08,0x03] + vmpsadbw $3, (%eax), %xmm5, %xmm1 + +// CHECK: vdpps $3, %xmm2, %xmm5, %xmm1 +// CHECK: encoding: [0xc4,0xe3,0x51,0x40,0xca,0x03] + vdpps $3, %xmm2, %xmm5, %xmm1 + +// CHECK: vdpps $3, (%eax), %xmm5, %xmm1 +// CHECK: encoding: [0xc4,0xe3,0x51,0x40,0x08,0x03] + vdpps $3, (%eax), %xmm5, %xmm1 + +// CHECK: vdppd $3, %xmm2, %xmm5, %xmm1 +// CHECK: encoding: [0xc4,0xe3,0x51,0x41,0xca,0x03] + vdppd $3, %xmm2, %xmm5, %xmm1 + +// CHECK: vdppd $3, (%eax), %xmm5, %xmm1 +// CHECK: encoding: [0xc4,0xe3,0x51,0x41,0x08,0x03] + vdppd $3, (%eax), %xmm5, %xmm1 + +// CHECK: vblendvpd %xmm2, %xmm5, %xmm1, %xmm3 +// CHECK: encoding: [0xc4,0xe3,0x71,0x4b,0xdd,0x20] + vblendvpd %xmm2, %xmm5, %xmm1, %xmm3 + +// CHECK: vblendvpd %xmm2, (%eax), %xmm1, %xmm3 +// CHECK: encoding: [0xc4,0xe3,0x71,0x4b,0x18,0x20] + vblendvpd %xmm2, (%eax), %xmm1, %xmm3 + +// CHECK: vblendvps %xmm2, %xmm5, %xmm1, %xmm3 +// CHECK: encoding: [0xc4,0xe3,0x71,0x4a,0xdd,0x20] + vblendvps %xmm2, %xmm5, %xmm1, %xmm3 + +// CHECK: vblendvps %xmm2, (%eax), %xmm1, %xmm3 +// CHECK: encoding: [0xc4,0xe3,0x71,0x4a,0x18,0x20] + vblendvps %xmm2, (%eax), %xmm1, %xmm3 + +// CHECK: vpblendvb %xmm2, %xmm5, %xmm1, %xmm3 +// CHECK: encoding: [0xc4,0xe3,0x71,0x4c,0xdd,0x20] + vpblendvb %xmm2, %xmm5, %xmm1, %xmm3 + +// CHECK: vpblendvb %xmm2, (%eax), %xmm1, %xmm3 +// CHECK: encoding: [0xc4,0xe3,0x71,0x4c,0x18,0x20] + vpblendvb %xmm2, (%eax), %xmm1, %xmm3 + +// CHECK: vpmovsxbw %xmm2, %xmm5 +// CHECK: encoding: [0xc4,0xe2,0x79,0x20,0xea] + vpmovsxbw %xmm2, %xmm5 + +// CHECK: vpmovsxbw (%eax), %xmm2 +// CHECK: encoding: [0xc4,0xe2,0x79,0x20,0x10] + vpmovsxbw (%eax), %xmm2 + +// CHECK: vpmovsxwd %xmm2, %xmm5 +// CHECK: encoding: [0xc4,0xe2,0x79,0x23,0xea] + vpmovsxwd %xmm2, %xmm5 + +// CHECK: vpmovsxwd (%eax), %xmm2 +// CHECK: encoding: [0xc4,0xe2,0x79,0x23,0x10] + vpmovsxwd (%eax), %xmm2 + +// CHECK: vpmovsxdq %xmm2, %xmm5 +// CHECK: encoding: [0xc4,0xe2,0x79,0x25,0xea] + vpmovsxdq %xmm2, %xmm5 + +// CHECK: vpmovsxdq (%eax), %xmm2 +// CHECK: encoding: [0xc4,0xe2,0x79,0x25,0x10] + vpmovsxdq (%eax), %xmm2 + +// CHECK: vpmovzxbw %xmm2, %xmm5 +// CHECK: encoding: [0xc4,0xe2,0x79,0x30,0xea] + vpmovzxbw %xmm2, %xmm5 + +// CHECK: vpmovzxbw (%eax), %xmm2 +// CHECK: encoding: [0xc4,0xe2,0x79,0x30,0x10] + vpmovzxbw (%eax), %xmm2 + +// CHECK: vpmovzxwd %xmm2, %xmm5 +// CHECK: encoding: [0xc4,0xe2,0x79,0x33,0xea] + vpmovzxwd %xmm2, %xmm5 + +// CHECK: vpmovzxwd (%eax), %xmm2 +// CHECK: encoding: [0xc4,0xe2,0x79,0x33,0x10] + vpmovzxwd (%eax), %xmm2 + +// CHECK: vpmovzxdq %xmm2, %xmm5 +// CHECK: encoding: [0xc4,0xe2,0x79,0x35,0xea] + vpmovzxdq %xmm2, %xmm5 + +// CHECK: vpmovzxdq (%eax), %xmm2 +// CHECK: encoding: [0xc4,0xe2,0x79,0x35,0x10] + vpmovzxdq (%eax), %xmm2 + +// CHECK: vpmovsxbq %xmm2, %xmm5 +// CHECK: encoding: [0xc4,0xe2,0x79,0x22,0xea] + vpmovsxbq %xmm2, %xmm5 + +// CHECK: vpmovsxbq (%eax), %xmm2 +// CHECK: encoding: [0xc4,0xe2,0x79,0x22,0x10] + vpmovsxbq (%eax), %xmm2 + +// CHECK: vpmovzxbq %xmm2, %xmm5 +// CHECK: encoding: [0xc4,0xe2,0x79,0x32,0xea] + vpmovzxbq %xmm2, %xmm5 + +// CHECK: vpmovzxbq (%eax), %xmm2 +// CHECK: encoding: [0xc4,0xe2,0x79,0x32,0x10] + vpmovzxbq (%eax), %xmm2 + +// CHECK: vpmovsxbd %xmm2, %xmm5 +// CHECK: encoding: [0xc4,0xe2,0x79,0x21,0xea] + vpmovsxbd %xmm2, %xmm5 + +// CHECK: vpmovsxbd (%eax), %xmm2 +// CHECK: encoding: [0xc4,0xe2,0x79,0x21,0x10] + vpmovsxbd (%eax), %xmm2 + +// CHECK: vpmovsxwq %xmm2, %xmm5 +// CHECK: encoding: [0xc4,0xe2,0x79,0x24,0xea] + vpmovsxwq %xmm2, %xmm5 + +// CHECK: vpmovsxwq (%eax), %xmm2 +// CHECK: encoding: [0xc4,0xe2,0x79,0x24,0x10] + vpmovsxwq (%eax), %xmm2 + +// CHECK: vpmovzxbd %xmm2, %xmm5 +// CHECK: encoding: [0xc4,0xe2,0x79,0x31,0xea] + vpmovzxbd %xmm2, %xmm5 + +// CHECK: vpmovzxbd (%eax), %xmm2 +// CHECK: encoding: [0xc4,0xe2,0x79,0x31,0x10] + vpmovzxbd (%eax), %xmm2 + +// CHECK: vpmovzxwq %xmm2, %xmm5 +// CHECK: encoding: [0xc4,0xe2,0x79,0x34,0xea] + vpmovzxwq %xmm2, %xmm5 + +// CHECK: vpmovzxwq (%eax), %xmm2 +// CHECK: encoding: [0xc4,0xe2,0x79,0x34,0x10] + vpmovzxwq (%eax), %xmm2 + +// CHECK: vpextrw $7, %xmm2, %eax +// CHECK: encoding: [0xc5,0xf9,0xc5,0xc2,0x07] + vpextrw $7, %xmm2, %eax + +// CHECK: vpextrw $7, %xmm2, (%eax) +// CHECK: encoding: [0xc4,0xe3,0x79,0x15,0x10,0x07] + vpextrw $7, %xmm2, (%eax) + +// CHECK: vpextrd $7, %xmm2, %eax +// CHECK: encoding: [0xc4,0xe3,0x79,0x16,0xd0,0x07] + vpextrd $7, %xmm2, %eax + +// CHECK: vpextrd $7, %xmm2, (%eax) +// CHECK: encoding: [0xc4,0xe3,0x79,0x16,0x10,0x07] + vpextrd $7, %xmm2, (%eax) + +// CHECK: vpextrb $7, %xmm2, %eax +// CHECK: encoding: [0xc4,0xe3,0x79,0x14,0xd0,0x07] + vpextrb $7, %xmm2, %eax + +// CHECK: vpextrb $7, %xmm2, (%eax) +// CHECK: encoding: [0xc4,0xe3,0x79,0x14,0x10,0x07] + vpextrb $7, %xmm2, (%eax) + +// CHECK: vextractps $7, %xmm2, (%eax) +// CHECK: encoding: [0xc4,0xe3,0x79,0x17,0x10,0x07] + vextractps $7, %xmm2, (%eax) + +// CHECK: vextractps $7, %xmm2, %eax +// CHECK: encoding: [0xc4,0xe3,0x79,0x17,0xd0,0x07] + vextractps $7, %xmm2, %eax + +// CHECK: vpinsrw $7, %eax, %xmm2, %xmm5 +// CHECK: encoding: [0xc5,0xe9,0xc4,0xe8,0x07] + vpinsrw $7, %eax, %xmm2, %xmm5 + +// CHECK: vpinsrw $7, (%eax), %xmm2, %xmm5 +// CHECK: encoding: [0xc5,0xe9,0xc4,0x28,0x07] + vpinsrw $7, (%eax), %xmm2, %xmm5 + +// CHECK: vpinsrb $7, %eax, %xmm2, %xmm5 +// CHECK: encoding: [0xc4,0xe3,0x69,0x20,0xe8,0x07] + vpinsrb $7, %eax, %xmm2, %xmm5 + +// CHECK: vpinsrb $7, (%eax), %xmm2, %xmm5 +// CHECK: encoding: [0xc4,0xe3,0x69,0x20,0x28,0x07] + vpinsrb $7, (%eax), %xmm2, %xmm5 + +// CHECK: vpinsrd $7, %eax, %xmm2, %xmm5 +// CHECK: encoding: [0xc4,0xe3,0x69,0x22,0xe8,0x07] + vpinsrd $7, %eax, %xmm2, %xmm5 + +// CHECK: vpinsrd $7, (%eax), %xmm2, %xmm5 +// CHECK: encoding: [0xc4,0xe3,0x69,0x22,0x28,0x07] + vpinsrd $7, (%eax), %xmm2, %xmm5 + +// CHECK: vinsertps $7, %xmm2, %xmm5, %xmm1 +// CHECK: encoding: [0xc4,0xe3,0x51,0x21,0xca,0x07] + vinsertps $7, %xmm2, %xmm5, %xmm1 + +// CHECK: vinsertps $7, (%eax), %xmm5, %xmm1 +// CHECK: encoding: [0xc4,0xe3,0x51,0x21,0x08,0x07] + vinsertps $7, (%eax), %xmm5, %xmm1 + +// CHECK: vptest %xmm2, %xmm5 +// CHECK: encoding: [0xc4,0xe2,0x79,0x17,0xea] + vptest %xmm2, %xmm5 + +// CHECK: vptest (%eax), %xmm2 +// CHECK: encoding: [0xc4,0xe2,0x79,0x17,0x10] + vptest (%eax), %xmm2 + +// CHECK: vmovntdqa (%eax), %xmm2 +// CHECK: encoding: [0xc4,0xe2,0x79,0x2a,0x10] + vmovntdqa (%eax), %xmm2 + +// CHECK: vpcmpgtq %xmm2, %xmm5, %xmm1 +// CHECK: encoding: [0xc4,0xe2,0x51,0x37,0xca] + vpcmpgtq %xmm2, %xmm5, %xmm1 + +// CHECK: vpcmpgtq (%eax), %xmm5, %xmm3 +// CHECK: encoding: [0xc4,0xe2,0x51,0x37,0x18] + vpcmpgtq (%eax), %xmm5, %xmm3 + +// CHECK: vpcmpistrm $7, %xmm2, %xmm5 +// CHECK: encoding: [0xc4,0xe3,0x79,0x62,0xea,0x07] + vpcmpistrm $7, %xmm2, %xmm5 + +// CHECK: vpcmpistrm $7, (%eax), %xmm5 +// CHECK: encoding: [0xc4,0xe3,0x79,0x62,0x28,0x07] + vpcmpistrm $7, (%eax), %xmm5 + +// CHECK: vpcmpestrm $7, %xmm2, %xmm5 +// CHECK: encoding: [0xc4,0xe3,0x79,0x60,0xea,0x07] + vpcmpestrm $7, %xmm2, %xmm5 + +// CHECK: vpcmpestrm $7, (%eax), %xmm5 +// CHECK: encoding: [0xc4,0xe3,0x79,0x60,0x28,0x07] + vpcmpestrm $7, (%eax), %xmm5 + +// CHECK: vpcmpistri $7, %xmm2, %xmm5 +// CHECK: encoding: [0xc4,0xe3,0x79,0x63,0xea,0x07] + vpcmpistri $7, %xmm2, %xmm5 + +// CHECK: vpcmpistri $7, (%eax), %xmm5 +// CHECK: encoding: [0xc4,0xe3,0x79,0x63,0x28,0x07] + vpcmpistri $7, (%eax), %xmm5 + +// CHECK: vpcmpestri $7, %xmm2, %xmm5 +// CHECK: encoding: [0xc4,0xe3,0x79,0x61,0xea,0x07] + vpcmpestri $7, %xmm2, %xmm5 + +// CHECK: vpcmpestri $7, (%eax), %xmm5 +// CHECK: encoding: [0xc4,0xe3,0x79,0x61,0x28,0x07] + vpcmpestri $7, (%eax), %xmm5 + +// CHECK: vaesimc %xmm2, %xmm5 +// CHECK: encoding: [0xc4,0xe2,0x79,0xdb,0xea] + vaesimc %xmm2, %xmm5 + +// CHECK: vaesimc (%eax), %xmm2 +// CHECK: encoding: [0xc4,0xe2,0x79,0xdb,0x10] + vaesimc (%eax), %xmm2 + +// CHECK: vaesenc %xmm2, %xmm5, %xmm1 +// CHECK: encoding: [0xc4,0xe2,0x51,0xdc,0xca] + vaesenc %xmm2, %xmm5, %xmm1 + +// CHECK: vaesenc (%eax), %xmm5, %xmm3 +// CHECK: encoding: [0xc4,0xe2,0x51,0xdc,0x18] + vaesenc (%eax), %xmm5, %xmm3 + +// CHECK: vaesenclast %xmm2, %xmm5, %xmm1 +// CHECK: encoding: [0xc4,0xe2,0x51,0xdd,0xca] + vaesenclast %xmm2, %xmm5, %xmm1 + +// CHECK: vaesenclast (%eax), %xmm5, %xmm3 +// CHECK: encoding: [0xc4,0xe2,0x51,0xdd,0x18] + vaesenclast (%eax), %xmm5, %xmm3 + +// CHECK: vaesdec %xmm2, %xmm5, %xmm1 +// CHECK: encoding: [0xc4,0xe2,0x51,0xde,0xca] + vaesdec %xmm2, %xmm5, %xmm1 + +// CHECK: vaesdec (%eax), %xmm5, %xmm3 +// CHECK: encoding: [0xc4,0xe2,0x51,0xde,0x18] + vaesdec (%eax), %xmm5, %xmm3 + +// CHECK: vaesdeclast %xmm2, %xmm5, %xmm1 +// CHECK: encoding: [0xc4,0xe2,0x51,0xdf,0xca] + vaesdeclast %xmm2, %xmm5, %xmm1 + +// CHECK: vaesdeclast (%eax), %xmm5, %xmm3 +// CHECK: encoding: [0xc4,0xe2,0x51,0xdf,0x18] + vaesdeclast (%eax), %xmm5, %xmm3 + +// CHECK: vaeskeygenassist $7, %xmm2, %xmm5 +// CHECK: encoding: [0xc4,0xe3,0x79,0xdf,0xea,0x07] + vaeskeygenassist $7, %xmm2, %xmm5 + +// CHECK: vaeskeygenassist $7, (%eax), %xmm5 +// CHECK: encoding: [0xc4,0xe3,0x79,0xdf,0x28,0x07] + vaeskeygenassist $7, (%eax), %xmm5 + +// CHECK: vcmpps $8, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x08] + vcmpeq_uqps %xmm1, %xmm2, %xmm3 + +// CHECK: vcmpps $9, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x09] + vcmpngeps %xmm1, %xmm2, %xmm3 + +// CHECK: vcmpps $10, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x0a] + vcmpngtps %xmm1, %xmm2, %xmm3 + +// CHECK: vcmpps $11, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x0b] + vcmpfalseps %xmm1, %xmm2, %xmm3 + +// CHECK: vcmpps $12, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x0c] + vcmpneq_oqps %xmm1, %xmm2, %xmm3 + +// CHECK: vcmpps $13, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x0d] + vcmpgeps %xmm1, %xmm2, %xmm3 + +// CHECK: vcmpps $14, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x0e] + vcmpgtps %xmm1, %xmm2, %xmm3 + +// CHECK: vcmpps $15, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x0f] + vcmptrueps %xmm1, %xmm2, %xmm3 + +// CHECK: vcmpps $16, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x10] + vcmpeq_osps %xmm1, %xmm2, %xmm3 + +// CHECK: vcmpps $17, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x11] + vcmplt_oqps %xmm1, %xmm2, %xmm3 + +// CHECK: vcmpps $18, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x12] + vcmple_oqps %xmm1, %xmm2, %xmm3 + +// CHECK: vcmpps $19, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x13] + vcmpunord_sps %xmm1, %xmm2, %xmm3 + +// CHECK: vcmpps $20, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x14] + vcmpneq_usps %xmm1, %xmm2, %xmm3 + +// CHECK: vcmpps $21, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x15] + vcmpnlt_uqps %xmm1, %xmm2, %xmm3 + +// CHECK: vcmpps $22, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x16] + vcmpnle_uqps %xmm1, %xmm2, %xmm3 + +// CHECK: vcmpps $23, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x17] + vcmpord_sps %xmm1, %xmm2, %xmm3 + +// CHECK: vcmpps $24, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x18] + vcmpeq_usps %xmm1, %xmm2, %xmm3 + +// CHECK: vcmpps $25, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x19] + vcmpnge_uqps %xmm1, %xmm2, %xmm3 + +// CHECK: vcmpps $26, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x1a] + vcmpngt_uqps %xmm1, %xmm2, %xmm3 + +// CHECK: vcmpps $27, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x1b] + vcmpfalse_osps %xmm1, %xmm2, %xmm3 + +// CHECK: vcmpps $28, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x1c] + vcmpneq_osps %xmm1, %xmm2, %xmm3 + +// CHECK: vcmpps $29, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x1d] + vcmpge_oqps %xmm1, %xmm2, %xmm3 + +// CHECK: vcmpps $30, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x1e] + vcmpgt_oqps %xmm1, %xmm2, %xmm3 + +// CHECK: vcmpps $31, %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x1f] + vcmptrue_usps %xmm1, %xmm2, %xmm3 + +// CHECK: vmovaps (%eax), %ymm2 +// CHECK: encoding: [0xc5,0xfc,0x28,0x10] + vmovaps (%eax), %ymm2 + +// CHECK: vmovaps %ymm1, %ymm2 +// CHECK: encoding: [0xc5,0xfc,0x28,0xd1] + vmovaps %ymm1, %ymm2 + +// CHECK: vmovaps %ymm1, (%eax) +// CHECK: encoding: [0xc5,0xfc,0x29,0x08] + vmovaps %ymm1, (%eax) + +// CHECK: vmovapd (%eax), %ymm2 +// CHECK: encoding: [0xc5,0xfd,0x28,0x10] + vmovapd (%eax), %ymm2 + +// CHECK: vmovapd %ymm1, %ymm2 +// CHECK: encoding: [0xc5,0xfd,0x28,0xd1] + vmovapd %ymm1, %ymm2 + +// CHECK: vmovapd %ymm1, (%eax) +// CHECK: encoding: [0xc5,0xfd,0x29,0x08] + vmovapd %ymm1, (%eax) + +// CHECK: vmovups (%eax), %ymm2 +// CHECK: encoding: [0xc5,0xfc,0x10,0x10] + vmovups (%eax), %ymm2 + +// CHECK: vmovups %ymm1, %ymm2 +// CHECK: encoding: [0xc5,0xfc,0x10,0xd1] + vmovups %ymm1, %ymm2 + +// CHECK: vmovups %ymm1, (%eax) +// CHECK: encoding: [0xc5,0xfc,0x11,0x08] + vmovups %ymm1, (%eax) + +// CHECK: vmovupd (%eax), %ymm2 +// CHECK: encoding: [0xc5,0xfd,0x10,0x10] + vmovupd (%eax), %ymm2 + +// CHECK: vmovupd %ymm1, %ymm2 +// CHECK: encoding: [0xc5,0xfd,0x10,0xd1] + vmovupd %ymm1, %ymm2 + +// CHECK: vmovupd %ymm1, (%eax) +// CHECK: encoding: [0xc5,0xfd,0x11,0x08] + vmovupd %ymm1, (%eax) + +// CHECK: vunpckhps %ymm1, %ymm2, %ymm4 +// CHECK: encoding: [0xc5,0xec,0x15,0xe1] + vunpckhps %ymm1, %ymm2, %ymm4 + +// CHECK: vunpckhpd %ymm1, %ymm2, %ymm4 +// CHECK: encoding: [0xc5,0xed,0x15,0xe1] + vunpckhpd %ymm1, %ymm2, %ymm4 + +// CHECK: vunpcklps %ymm1, %ymm2, %ymm4 +// CHECK: encoding: [0xc5,0xec,0x14,0xe1] + vunpcklps %ymm1, %ymm2, %ymm4 + +// CHECK: vunpcklpd %ymm1, %ymm2, %ymm4 +// CHECK: encoding: [0xc5,0xed,0x14,0xe1] + vunpcklpd %ymm1, %ymm2, %ymm4 + +// CHECK: vunpckhps -4(%ebx,%ecx,8), %ymm2, %ymm5 +// CHECK: encoding: [0xc5,0xec,0x15,0x6c,0xcb,0xfc] + vunpckhps -4(%ebx,%ecx,8), %ymm2, %ymm5 + +// CHECK: vunpckhpd -4(%ebx,%ecx,8), %ymm2, %ymm5 +// CHECK: encoding: [0xc5,0xed,0x15,0x6c,0xcb,0xfc] + vunpckhpd -4(%ebx,%ecx,8), %ymm2, %ymm5 + +// CHECK: vunpcklps -4(%ebx,%ecx,8), %ymm2, %ymm5 +// CHECK: encoding: [0xc5,0xec,0x14,0x6c,0xcb,0xfc] + vunpcklps -4(%ebx,%ecx,8), %ymm2, %ymm5 + +// CHECK: vunpcklpd -4(%ebx,%ecx,8), %ymm2, %ymm5 +// CHECK: encoding: [0xc5,0xed,0x14,0x6c,0xcb,0xfc] + vunpcklpd -4(%ebx,%ecx,8), %ymm2, %ymm5 + +// CHECK: vmovntdq %ymm1, (%eax) +// CHECK: encoding: [0xc5,0xfd,0xe7,0x08] + vmovntdq %ymm1, (%eax) + +// CHECK: vmovntpd %ymm1, (%eax) +// CHECK: encoding: [0xc5,0xfd,0x2b,0x08] + vmovntpd %ymm1, (%eax) + +// CHECK: vmovntps %ymm1, (%eax) +// CHECK: encoding: [0xc5,0xfc,0x2b,0x08] + vmovntps %ymm1, (%eax) + +// CHECK: vmovmskps %xmm2, %eax +// CHECK: encoding: [0xc5,0xf8,0x50,0xc2] + vmovmskps %xmm2, %eax + +// CHECK: vmovmskpd %xmm2, %eax +// CHECK: encoding: [0xc5,0xf9,0x50,0xc2] + vmovmskpd %xmm2, %eax + +// CHECK: vmaxps %ymm2, %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdc,0x5f,0xf2] + vmaxps %ymm2, %ymm4, %ymm6 + +// CHECK: vmaxpd %ymm2, %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdd,0x5f,0xf2] + vmaxpd %ymm2, %ymm4, %ymm6 + +// CHECK: vminps %ymm2, %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdc,0x5d,0xf2] + vminps %ymm2, %ymm4, %ymm6 + +// CHECK: vminpd %ymm2, %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdd,0x5d,0xf2] + vminpd %ymm2, %ymm4, %ymm6 + +// CHECK: vsubps %ymm2, %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdc,0x5c,0xf2] + vsubps %ymm2, %ymm4, %ymm6 + +// CHECK: vsubpd %ymm2, %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdd,0x5c,0xf2] + vsubpd %ymm2, %ymm4, %ymm6 + +// CHECK: vdivps %ymm2, %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdc,0x5e,0xf2] + vdivps %ymm2, %ymm4, %ymm6 + +// CHECK: vdivpd %ymm2, %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdd,0x5e,0xf2] + vdivpd %ymm2, %ymm4, %ymm6 + +// CHECK: vaddps %ymm2, %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdc,0x58,0xf2] + vaddps %ymm2, %ymm4, %ymm6 + +// CHECK: vaddpd %ymm2, %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdd,0x58,0xf2] + vaddpd %ymm2, %ymm4, %ymm6 + +// CHECK: vmulps %ymm2, %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdc,0x59,0xf2] + vmulps %ymm2, %ymm4, %ymm6 + +// CHECK: vmulpd %ymm2, %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdd,0x59,0xf2] + vmulpd %ymm2, %ymm4, %ymm6 + +// CHECK: vmaxps (%eax), %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdc,0x5f,0x30] + vmaxps (%eax), %ymm4, %ymm6 + +// CHECK: vmaxpd (%eax), %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdd,0x5f,0x30] + vmaxpd (%eax), %ymm4, %ymm6 + +// CHECK: vminps (%eax), %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdc,0x5d,0x30] + vminps (%eax), %ymm4, %ymm6 + +// CHECK: vminpd (%eax), %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdd,0x5d,0x30] + vminpd (%eax), %ymm4, %ymm6 + +// CHECK: vsubps (%eax), %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdc,0x5c,0x30] + vsubps (%eax), %ymm4, %ymm6 + +// CHECK: vsubpd (%eax), %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdd,0x5c,0x30] + vsubpd (%eax), %ymm4, %ymm6 + +// CHECK: vdivps (%eax), %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdc,0x5e,0x30] + vdivps (%eax), %ymm4, %ymm6 + +// CHECK: vdivpd (%eax), %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdd,0x5e,0x30] + vdivpd (%eax), %ymm4, %ymm6 + +// CHECK: vaddps (%eax), %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdc,0x58,0x30] + vaddps (%eax), %ymm4, %ymm6 + +// CHECK: vaddpd (%eax), %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdd,0x58,0x30] + vaddpd (%eax), %ymm4, %ymm6 + +// CHECK: vmulps (%eax), %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdc,0x59,0x30] + vmulps (%eax), %ymm4, %ymm6 + +// CHECK: vmulpd (%eax), %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdd,0x59,0x30] + vmulpd (%eax), %ymm4, %ymm6 + +// CHECK: vsqrtpd %ymm1, %ymm2 +// CHECK: encoding: [0xc5,0xfd,0x51,0xd1] + vsqrtpd %ymm1, %ymm2 + +// CHECK: vsqrtpd (%eax), %ymm2 +// CHECK: encoding: [0xc5,0xfd,0x51,0x10] + vsqrtpd (%eax), %ymm2 + +// CHECK: vsqrtps %ymm1, %ymm2 +// CHECK: encoding: [0xc5,0xfc,0x51,0xd1] + vsqrtps %ymm1, %ymm2 + +// CHECK: vsqrtps (%eax), %ymm2 +// CHECK: encoding: [0xc5,0xfc,0x51,0x10] + vsqrtps (%eax), %ymm2 + +// CHECK: vrsqrtps %ymm1, %ymm2 +// CHECK: encoding: [0xc5,0xfc,0x52,0xd1] + vrsqrtps %ymm1, %ymm2 + +// CHECK: vrsqrtps (%eax), %ymm2 +// CHECK: encoding: [0xc5,0xfc,0x52,0x10] + vrsqrtps (%eax), %ymm2 + +// CHECK: vrcpps %ymm1, %ymm2 +// CHECK: encoding: [0xc5,0xfc,0x53,0xd1] + vrcpps %ymm1, %ymm2 + +// CHECK: vrcpps (%eax), %ymm2 +// CHECK: encoding: [0xc5,0xfc,0x53,0x10] + vrcpps (%eax), %ymm2 + +// CHECK: vandps %ymm2, %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdc,0x54,0xf2] + vandps %ymm2, %ymm4, %ymm6 + +// CHECK: vandpd %ymm2, %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdd,0x54,0xf2] + vandpd %ymm2, %ymm4, %ymm6 + +// CHECK: vandps -4(%ebx,%ecx,8), %ymm2, %ymm5 +// CHECK: encoding: [0xc5,0xec,0x54,0x6c,0xcb,0xfc] + vandps -4(%ebx,%ecx,8), %ymm2, %ymm5 + +// CHECK: vandpd -4(%ebx,%ecx,8), %ymm2, %ymm5 +// CHECK: encoding: [0xc5,0xed,0x54,0x6c,0xcb,0xfc] + vandpd -4(%ebx,%ecx,8), %ymm2, %ymm5 + +// CHECK: vorps %ymm2, %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdc,0x56,0xf2] + vorps %ymm2, %ymm4, %ymm6 + +// CHECK: vorpd %ymm2, %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdd,0x56,0xf2] + vorpd %ymm2, %ymm4, %ymm6 + +// CHECK: vorps -4(%ebx,%ecx,8), %ymm2, %ymm5 +// CHECK: encoding: [0xc5,0xec,0x56,0x6c,0xcb,0xfc] + vorps -4(%ebx,%ecx,8), %ymm2, %ymm5 + +// CHECK: vorpd -4(%ebx,%ecx,8), %ymm2, %ymm5 +// CHECK: encoding: [0xc5,0xed,0x56,0x6c,0xcb,0xfc] + vorpd -4(%ebx,%ecx,8), %ymm2, %ymm5 + +// CHECK: vxorps %ymm2, %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdc,0x57,0xf2] + vxorps %ymm2, %ymm4, %ymm6 + +// CHECK: vxorpd %ymm2, %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdd,0x57,0xf2] + vxorpd %ymm2, %ymm4, %ymm6 + +// CHECK: vxorps -4(%ebx,%ecx,8), %ymm2, %ymm5 +// CHECK: encoding: [0xc5,0xec,0x57,0x6c,0xcb,0xfc] + vxorps -4(%ebx,%ecx,8), %ymm2, %ymm5 + +// CHECK: vxorpd -4(%ebx,%ecx,8), %ymm2, %ymm5 +// CHECK: encoding: [0xc5,0xed,0x57,0x6c,0xcb,0xfc] + vxorpd -4(%ebx,%ecx,8), %ymm2, %ymm5 + +// CHECK: vandnps %ymm2, %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdc,0x55,0xf2] + vandnps %ymm2, %ymm4, %ymm6 + +// CHECK: vandnpd %ymm2, %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdd,0x55,0xf2] + vandnpd %ymm2, %ymm4, %ymm6 + +// CHECK: vandnps -4(%ebx,%ecx,8), %ymm2, %ymm5 +// CHECK: encoding: [0xc5,0xec,0x55,0x6c,0xcb,0xfc] + vandnps -4(%ebx,%ecx,8), %ymm2, %ymm5 + +// CHECK: vandnpd -4(%ebx,%ecx,8), %ymm2, %ymm5 +// CHECK: encoding: [0xc5,0xed,0x55,0x6c,0xcb,0xfc] + vandnpd -4(%ebx,%ecx,8), %ymm2, %ymm5 + diff --git a/test/MC/AsmParser/X86/x86_32-new-encoder.s b/test/MC/AsmParser/X86/x86_32-new-encoder.s index 0b7d327..e97e494 100644 --- a/test/MC/AsmParser/X86/x86_32-new-encoder.s +++ b/test/MC/AsmParser/X86/x86_32-new-encoder.s @@ -331,3 +331,87 @@ retl // CHECK: movw (%eax), %cs // CHECK: encoding: [0x66,0x8e,0x08] movw (%eax), %cs + +// radr://8033374 +// CHECK: movl %cr0, %eax +// CHECK: encoding: [0x0f,0x20,0xc0] + movl %cr0,%eax + +// CHECK: movl %cr1, %eax +// CHECK: encoding: [0x0f,0x20,0xc8] + movl %cr1,%eax + +// CHECK: movl %cr2, %eax +// CHECK: encoding: [0x0f,0x20,0xd0] + movl %cr2,%eax + +// CHECK: movl %cr3, %eax +// CHECK: encoding: [0x0f,0x20,0xd8] + movl %cr3,%eax + +// CHECK: movl %cr4, %eax +// CHECK: encoding: [0x0f,0x20,0xe0] + movl %cr4,%eax + +// CHECK: movl %dr0, %eax +// CHECK: encoding: [0x0f,0x21,0xc0] + movl %dr0,%eax + +// CHECK: movl %dr1, %eax +// CHECK: encoding: [0x0f,0x21,0xc8] + movl %dr1,%eax + +// CHECK: movl %dr1, %eax +// CHECK: encoding: [0x0f,0x21,0xc8] + movl %dr1,%eax + +// CHECK: movl %dr2, %eax +// CHECK: encoding: [0x0f,0x21,0xd0] + movl %dr2,%eax + +// CHECK: movl %dr3, %eax +// CHECK: encoding: [0x0f,0x21,0xd8] + movl %dr3,%eax + +// CHECK: movl %dr4, %eax +// CHECK: encoding: [0x0f,0x21,0xe0] + movl %dr4,%eax + +// CHECK: movl %dr5, %eax +// CHECK: encoding: [0x0f,0x21,0xe8] + movl %dr5,%eax + +// CHECK: movl %dr6, %eax +// CHECK: encoding: [0x0f,0x21,0xf0] + movl %dr6,%eax + +// CHECK: movl %dr7, %eax +// CHECK: encoding: [0x0f,0x21,0xf8] + movl %dr7,%eax + +// radr://8017522 +// CHECK: wait +// CHECK: encoding: [0x9b] + fwait + +// rdar://7873482 +// CHECK: [0x65,0x8b,0x05,0x7c,0x00,0x00,0x00] +// FIXME: This is a correct bug poor encoding: Use 65 a1 7c 00 00 00 + movl %gs:124, %eax + +// CHECK: pusha +// CHECK: encoding: [0x60] + pusha + +// CHECK: popa +// CHECK: encoding: [0x61] + popa + +// CHECK: pushal +// CHECK: encoding: [0x60] + pushal + +// CHECK: popal +// CHECK: encoding: [0x61] + popal + diff --git a/test/MC/AsmParser/X86/x86_64-encoding.s b/test/MC/AsmParser/X86/x86_64-encoding.s index 036f7d4..4efcbc7 100644 --- a/test/MC/AsmParser/X86/x86_64-encoding.s +++ b/test/MC/AsmParser/X86/x86_64-encoding.s @@ -1,5 +1,15 @@ // RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s +// PR7195 +// CHECK: callw 42 +// CHECK: encoding: [0x66,0xe8,A,A] + callw 42 + +// rdar://8127102 +// CHECK: movq %gs:(%rdi), %rax +// CHECK: encoding: [0x65,0x48,0x8b,0x07] +movq %gs:(%rdi), %rax + // CHECK: crc32b %bl, %eax // CHECK: encoding: [0xf2,0x0f,0x38,0xf0,0xc3] crc32b %bl, %eax @@ -103,3 +113,2562 @@ movd %mm1, %rdx // CHECK: movd %mm1, %edx // CHECK: encoding: [0x0f,0x7e,0xca] movd %mm1, %edx + +// CHECK: vaddss %xmm8, %xmm9, %xmm10 +// CHECK: encoding: [0xc4,0x41,0x32,0x58,0xd0] +vaddss %xmm8, %xmm9, %xmm10 + +// CHECK: vmulss %xmm8, %xmm9, %xmm10 +// CHECK: encoding: [0xc4,0x41,0x32,0x59,0xd0] +vmulss %xmm8, %xmm9, %xmm10 + +// CHECK: vsubss %xmm8, %xmm9, %xmm10 +// CHECK: encoding: [0xc4,0x41,0x32,0x5c,0xd0] +vsubss %xmm8, %xmm9, %xmm10 + +// CHECK: vdivss %xmm8, %xmm9, %xmm10 +// CHECK: encoding: [0xc4,0x41,0x32,0x5e,0xd0] +vdivss %xmm8, %xmm9, %xmm10 + +// CHECK: vaddsd %xmm8, %xmm9, %xmm10 +// CHECK: encoding: [0xc4,0x41,0x33,0x58,0xd0] +vaddsd %xmm8, %xmm9, %xmm10 + +// CHECK: vmulsd %xmm8, %xmm9, %xmm10 +// CHECK: encoding: [0xc4,0x41,0x33,0x59,0xd0] +vmulsd %xmm8, %xmm9, %xmm10 + +// CHECK: vsubsd %xmm8, %xmm9, %xmm10 +// CHECK: encoding: [0xc4,0x41,0x33,0x5c,0xd0] +vsubsd %xmm8, %xmm9, %xmm10 + +// CHECK: vdivsd %xmm8, %xmm9, %xmm10 +// CHECK: encoding: [0xc4,0x41,0x33,0x5e,0xd0] +vdivsd %xmm8, %xmm9, %xmm10 + +// CHECK: vaddss -4(%rcx,%rbx,8), %xmm10, %xmm11 +// CHECK: encoding: [0xc5,0x2a,0x58,0x5c,0xd9,0xfc] +vaddss -4(%rcx,%rbx,8), %xmm10, %xmm11 + +// CHECK: vsubss -4(%rcx,%rbx,8), %xmm10, %xmm11 +// CHECK: encoding: [0xc5,0x2a,0x5c,0x5c,0xd9,0xfc] +vsubss -4(%rcx,%rbx,8), %xmm10, %xmm11 + +// CHECK: vmulss -4(%rcx,%rbx,8), %xmm10, %xmm11 +// CHECK: encoding: [0xc5,0x2a,0x59,0x5c,0xd9,0xfc] +vmulss -4(%rcx,%rbx,8), %xmm10, %xmm11 + +// CHECK: vdivss -4(%rcx,%rbx,8), %xmm10, %xmm11 +// CHECK: encoding: [0xc5,0x2a,0x5e,0x5c,0xd9,0xfc] +vdivss -4(%rcx,%rbx,8), %xmm10, %xmm11 + +// CHECK: vaddsd -4(%rcx,%rbx,8), %xmm10, %xmm11 +// CHECK: encoding: [0xc5,0x2b,0x58,0x5c,0xd9,0xfc] +vaddsd -4(%rcx,%rbx,8), %xmm10, %xmm11 + +// CHECK: vsubsd -4(%rcx,%rbx,8), %xmm10, %xmm11 +// CHECK: encoding: [0xc5,0x2b,0x5c,0x5c,0xd9,0xfc] +vsubsd -4(%rcx,%rbx,8), %xmm10, %xmm11 + +// CHECK: vmulsd -4(%rcx,%rbx,8), %xmm10, %xmm11 +// CHECK: encoding: [0xc5,0x2b,0x59,0x5c,0xd9,0xfc] +vmulsd -4(%rcx,%rbx,8), %xmm10, %xmm11 + +// CHECK: vdivsd -4(%rcx,%rbx,8), %xmm10, %xmm11 +// CHECK: encoding: [0xc5,0x2b,0x5e,0x5c,0xd9,0xfc] +vdivsd -4(%rcx,%rbx,8), %xmm10, %xmm11 + +// CHECK: vaddps %xmm10, %xmm11, %xmm15 +// CHECK: encoding: [0xc4,0x41,0x20,0x58,0xfa] +vaddps %xmm10, %xmm11, %xmm15 + +// CHECK: vsubps %xmm10, %xmm11, %xmm15 +// CHECK: encoding: [0xc4,0x41,0x20,0x5c,0xfa] +vsubps %xmm10, %xmm11, %xmm15 + +// CHECK: vmulps %xmm10, %xmm11, %xmm15 +// CHECK: encoding: [0xc4,0x41,0x20,0x59,0xfa] +vmulps %xmm10, %xmm11, %xmm15 + +// CHECK: vdivps %xmm10, %xmm11, %xmm15 +// CHECK: encoding: [0xc4,0x41,0x20,0x5e,0xfa] +vdivps %xmm10, %xmm11, %xmm15 + +// CHECK: vaddpd %xmm10, %xmm11, %xmm15 +// CHECK: encoding: [0xc4,0x41,0x21,0x58,0xfa] +vaddpd %xmm10, %xmm11, %xmm15 + +// CHECK: vsubpd %xmm10, %xmm11, %xmm15 +// CHECK: encoding: [0xc4,0x41,0x21,0x5c,0xfa] +vsubpd %xmm10, %xmm11, %xmm15 + +// CHECK: vmulpd %xmm10, %xmm11, %xmm15 +// CHECK: encoding: [0xc4,0x41,0x21,0x59,0xfa] +vmulpd %xmm10, %xmm11, %xmm15 + +// CHECK: vdivpd %xmm10, %xmm11, %xmm15 +// CHECK: encoding: [0xc4,0x41,0x21,0x5e,0xfa] +vdivpd %xmm10, %xmm11, %xmm15 + +// CHECK: vaddps -4(%rcx,%rbx,8), %xmm10, %xmm11 +// CHECK: encoding: [0xc5,0x28,0x58,0x5c,0xd9,0xfc] +vaddps -4(%rcx,%rbx,8), %xmm10, %xmm11 + +// CHECK: vsubps -4(%rcx,%rbx,8), %xmm10, %xmm11 +// CHECK: encoding: [0xc5,0x28,0x5c,0x5c,0xd9,0xfc] +vsubps -4(%rcx,%rbx,8), %xmm10, %xmm11 + +// CHECK: vmulps -4(%rcx,%rbx,8), %xmm10, %xmm11 +// CHECK: encoding: [0xc5,0x28,0x59,0x5c,0xd9,0xfc] +vmulps -4(%rcx,%rbx,8), %xmm10, %xmm11 + +// CHECK: vdivps -4(%rcx,%rbx,8), %xmm10, %xmm11 +// CHECK: encoding: [0xc5,0x28,0x5e,0x5c,0xd9,0xfc] +vdivps -4(%rcx,%rbx,8), %xmm10, %xmm11 + +// CHECK: vaddpd -4(%rcx,%rbx,8), %xmm10, %xmm11 +// CHECK: encoding: [0xc5,0x29,0x58,0x5c,0xd9,0xfc] +vaddpd -4(%rcx,%rbx,8), %xmm10, %xmm11 + +// CHECK: vsubpd -4(%rcx,%rbx,8), %xmm10, %xmm11 +// CHECK: encoding: [0xc5,0x29,0x5c,0x5c,0xd9,0xfc] +vsubpd -4(%rcx,%rbx,8), %xmm10, %xmm11 + +// CHECK: vmulpd -4(%rcx,%rbx,8), %xmm10, %xmm11 +// CHECK: encoding: [0xc5,0x29,0x59,0x5c,0xd9,0xfc] +vmulpd -4(%rcx,%rbx,8), %xmm10, %xmm11 + +// CHECK: vdivpd -4(%rcx,%rbx,8), %xmm10, %xmm11 +// CHECK: encoding: [0xc5,0x29,0x5e,0x5c,0xd9,0xfc] +vdivpd -4(%rcx,%rbx,8), %xmm10, %xmm11 + +// CHECK: vmaxss %xmm10, %xmm14, %xmm12 +// CHECK: encoding: [0xc4,0x41,0x0a,0x5f,0xe2] + vmaxss %xmm10, %xmm14, %xmm12 + +// CHECK: vmaxsd %xmm10, %xmm14, %xmm12 +// CHECK: encoding: [0xc4,0x41,0x0b,0x5f,0xe2] + vmaxsd %xmm10, %xmm14, %xmm12 + +// CHECK: vminss %xmm10, %xmm14, %xmm12 +// CHECK: encoding: [0xc4,0x41,0x0a,0x5d,0xe2] + vminss %xmm10, %xmm14, %xmm12 + +// CHECK: vminsd %xmm10, %xmm14, %xmm12 +// CHECK: encoding: [0xc4,0x41,0x0b,0x5d,0xe2] + vminsd %xmm10, %xmm14, %xmm12 + +// CHECK: vmaxss -4(%rbx,%rcx,8), %xmm12, %xmm10 +// CHECK: encoding: [0xc5,0x1a,0x5f,0x54,0xcb,0xfc] + vmaxss -4(%rbx,%rcx,8), %xmm12, %xmm10 + +// CHECK: vmaxsd -4(%rbx,%rcx,8), %xmm12, %xmm10 +// CHECK: encoding: [0xc5,0x1b,0x5f,0x54,0xcb,0xfc] + vmaxsd -4(%rbx,%rcx,8), %xmm12, %xmm10 + +// CHECK: vminss -4(%rbx,%rcx,8), %xmm12, %xmm10 +// CHECK: encoding: [0xc5,0x1a,0x5d,0x54,0xcb,0xfc] + vminss -4(%rbx,%rcx,8), %xmm12, %xmm10 + +// CHECK: vminsd -4(%rbx,%rcx,8), %xmm12, %xmm10 +// CHECK: encoding: [0xc5,0x1b,0x5d,0x54,0xcb,0xfc] + vminsd -4(%rbx,%rcx,8), %xmm12, %xmm10 + +// CHECK: vmaxps %xmm10, %xmm14, %xmm12 +// CHECK: encoding: [0xc4,0x41,0x08,0x5f,0xe2] + vmaxps %xmm10, %xmm14, %xmm12 + +// CHECK: vmaxpd %xmm10, %xmm14, %xmm12 +// CHECK: encoding: [0xc4,0x41,0x09,0x5f,0xe2] + vmaxpd %xmm10, %xmm14, %xmm12 + +// CHECK: vminps %xmm10, %xmm14, %xmm12 +// CHECK: encoding: [0xc4,0x41,0x08,0x5d,0xe2] + vminps %xmm10, %xmm14, %xmm12 + +// CHECK: vminpd %xmm10, %xmm14, %xmm12 +// CHECK: encoding: [0xc4,0x41,0x09,0x5d,0xe2] + vminpd %xmm10, %xmm14, %xmm12 + +// CHECK: vmaxps -4(%rbx,%rcx,8), %xmm12, %xmm10 +// CHECK: encoding: [0xc5,0x18,0x5f,0x54,0xcb,0xfc] + vmaxps -4(%rbx,%rcx,8), %xmm12, %xmm10 + +// CHECK: vmaxpd -4(%rbx,%rcx,8), %xmm12, %xmm10 +// CHECK: encoding: [0xc5,0x19,0x5f,0x54,0xcb,0xfc] + vmaxpd -4(%rbx,%rcx,8), %xmm12, %xmm10 + +// CHECK: vminps -4(%rbx,%rcx,8), %xmm12, %xmm10 +// CHECK: encoding: [0xc5,0x18,0x5d,0x54,0xcb,0xfc] + vminps -4(%rbx,%rcx,8), %xmm12, %xmm10 + +// CHECK: vminpd -4(%rbx,%rcx,8), %xmm12, %xmm10 +// CHECK: encoding: [0xc5,0x19,0x5d,0x54,0xcb,0xfc] + vminpd -4(%rbx,%rcx,8), %xmm12, %xmm10 + +// CHECK: vandps %xmm10, %xmm14, %xmm12 +// CHECK: encoding: [0xc4,0x41,0x08,0x54,0xe2] + vandps %xmm10, %xmm14, %xmm12 + +// CHECK: vandpd %xmm10, %xmm14, %xmm12 +// CHECK: encoding: [0xc4,0x41,0x09,0x54,0xe2] + vandpd %xmm10, %xmm14, %xmm12 + +// CHECK: vandps -4(%rbx,%rcx,8), %xmm12, %xmm10 +// CHECK: encoding: [0xc5,0x18,0x54,0x54,0xcb,0xfc] + vandps -4(%rbx,%rcx,8), %xmm12, %xmm10 + +// CHECK: vandpd -4(%rbx,%rcx,8), %xmm12, %xmm10 +// CHECK: encoding: [0xc5,0x19,0x54,0x54,0xcb,0xfc] + vandpd -4(%rbx,%rcx,8), %xmm12, %xmm10 + +// CHECK: vorps %xmm10, %xmm14, %xmm12 +// CHECK: encoding: [0xc4,0x41,0x08,0x56,0xe2] + vorps %xmm10, %xmm14, %xmm12 + +// CHECK: vorpd %xmm10, %xmm14, %xmm12 +// CHECK: encoding: [0xc4,0x41,0x09,0x56,0xe2] + vorpd %xmm10, %xmm14, %xmm12 + +// CHECK: vorps -4(%rbx,%rcx,8), %xmm12, %xmm10 +// CHECK: encoding: [0xc5,0x18,0x56,0x54,0xcb,0xfc] + vorps -4(%rbx,%rcx,8), %xmm12, %xmm10 + +// CHECK: vorpd -4(%rbx,%rcx,8), %xmm12, %xmm10 +// CHECK: encoding: [0xc5,0x19,0x56,0x54,0xcb,0xfc] + vorpd -4(%rbx,%rcx,8), %xmm12, %xmm10 + +// CHECK: vxorps %xmm10, %xmm14, %xmm12 +// CHECK: encoding: [0xc4,0x41,0x08,0x57,0xe2] + vxorps %xmm10, %xmm14, %xmm12 + +// CHECK: vxorpd %xmm10, %xmm14, %xmm12 +// CHECK: encoding: [0xc4,0x41,0x09,0x57,0xe2] + vxorpd %xmm10, %xmm14, %xmm12 + +// CHECK: vxorps -4(%rbx,%rcx,8), %xmm12, %xmm10 +// CHECK: encoding: [0xc5,0x18,0x57,0x54,0xcb,0xfc] + vxorps -4(%rbx,%rcx,8), %xmm12, %xmm10 + +// CHECK: vxorpd -4(%rbx,%rcx,8), %xmm12, %xmm10 +// CHECK: encoding: [0xc5,0x19,0x57,0x54,0xcb,0xfc] + vxorpd -4(%rbx,%rcx,8), %xmm12, %xmm10 + +// CHECK: vandnps %xmm10, %xmm14, %xmm12 +// CHECK: encoding: [0xc4,0x41,0x08,0x55,0xe2] + vandnps %xmm10, %xmm14, %xmm12 + +// CHECK: vandnpd %xmm10, %xmm14, %xmm12 +// CHECK: encoding: [0xc4,0x41,0x09,0x55,0xe2] + vandnpd %xmm10, %xmm14, %xmm12 + +// CHECK: vandnps -4(%rbx,%rcx,8), %xmm12, %xmm10 +// CHECK: encoding: [0xc5,0x18,0x55,0x54,0xcb,0xfc] + vandnps -4(%rbx,%rcx,8), %xmm12, %xmm10 + +// CHECK: vandnpd -4(%rbx,%rcx,8), %xmm12, %xmm10 +// CHECK: encoding: [0xc5,0x19,0x55,0x54,0xcb,0xfc] + vandnpd -4(%rbx,%rcx,8), %xmm12, %xmm10 + +// CHECK: vmovss -4(%rbx,%rcx,8), %xmm10 +// CHECK: encoding: [0xc5,0x7a,0x10,0x54,0xcb,0xfc] + vmovss -4(%rbx,%rcx,8), %xmm10 + +// CHECK: vmovss %xmm14, %xmm10, %xmm15 +// CHECK: encoding: [0xc4,0x41,0x2a,0x10,0xfe] + vmovss %xmm14, %xmm10, %xmm15 + +// CHECK: vmovsd -4(%rbx,%rcx,8), %xmm10 +// CHECK: encoding: [0xc5,0x7b,0x10,0x54,0xcb,0xfc] + vmovsd -4(%rbx,%rcx,8), %xmm10 + +// CHECK: vmovsd %xmm14, %xmm10, %xmm15 +// CHECK: encoding: [0xc4,0x41,0x2b,0x10,0xfe] + vmovsd %xmm14, %xmm10, %xmm15 + +// rdar://7840289 +// CHECK: pshufb CPI1_0(%rip), %xmm1 +// CHECK: encoding: [0x66,0x0f,0x38,0x00,0x0d,A,A,A,A] +// CHECK: fixup A - offset: 5, value: CPI1_0-4 +pshufb CPI1_0(%rip), %xmm1 + +// CHECK: vunpckhps %xmm15, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0x15,0xef] + vunpckhps %xmm15, %xmm12, %xmm13 + +// CHECK: vunpckhpd %xmm15, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0x15,0xef] + vunpckhpd %xmm15, %xmm12, %xmm13 + +// CHECK: vunpcklps %xmm15, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0x14,0xef] + vunpcklps %xmm15, %xmm12, %xmm13 + +// CHECK: vunpcklpd %xmm15, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0x14,0xef] + vunpcklpd %xmm15, %xmm12, %xmm13 + +// CHECK: vunpckhps -4(%rbx,%rcx,8), %xmm12, %xmm15 +// CHECK: encoding: [0xc5,0x18,0x15,0x7c,0xcb,0xfc] + vunpckhps -4(%rbx,%rcx,8), %xmm12, %xmm15 + +// CHECK: vunpckhpd -4(%rbx,%rcx,8), %xmm12, %xmm15 +// CHECK: encoding: [0xc5,0x19,0x15,0x7c,0xcb,0xfc] + vunpckhpd -4(%rbx,%rcx,8), %xmm12, %xmm15 + +// CHECK: vunpcklps -4(%rbx,%rcx,8), %xmm12, %xmm15 +// CHECK: encoding: [0xc5,0x18,0x14,0x7c,0xcb,0xfc] + vunpcklps -4(%rbx,%rcx,8), %xmm12, %xmm15 + +// CHECK: vunpcklpd -4(%rbx,%rcx,8), %xmm12, %xmm15 +// CHECK: encoding: [0xc5,0x19,0x14,0x7c,0xcb,0xfc] + vunpcklpd -4(%rbx,%rcx,8), %xmm12, %xmm15 + +// CHECK: vcmpps $0, %xmm10, %xmm12, %xmm15 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xfa,0x00] + vcmpps $0, %xmm10, %xmm12, %xmm15 + +// CHECK: vcmpps $0, (%rax), %xmm12, %xmm15 +// CHECK: encoding: [0xc5,0x18,0xc2,0x38,0x00] + vcmpps $0, (%rax), %xmm12, %xmm15 + +// CHECK: vcmpps $7, %xmm10, %xmm12, %xmm15 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xfa,0x07] + vcmpps $7, %xmm10, %xmm12, %xmm15 + +// CHECK: vcmppd $0, %xmm10, %xmm12, %xmm15 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xfa,0x00] + vcmppd $0, %xmm10, %xmm12, %xmm15 + +// CHECK: vcmppd $0, (%rax), %xmm12, %xmm15 +// CHECK: encoding: [0xc5,0x19,0xc2,0x38,0x00] + vcmppd $0, (%rax), %xmm12, %xmm15 + +// CHECK: vcmppd $7, %xmm10, %xmm12, %xmm15 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xfa,0x07] + vcmppd $7, %xmm10, %xmm12, %xmm15 + +// CHECK: vshufps $8, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc6,0xeb,0x08] + vshufps $8, %xmm11, %xmm12, %xmm13 + +// CHECK: vshufps $8, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0xc6,0x6c,0xcb,0xfc,0x08] + vshufps $8, -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vshufpd $8, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc6,0xeb,0x08] + vshufpd $8, %xmm11, %xmm12, %xmm13 + +// CHECK: vshufpd $8, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc6,0x6c,0xcb,0xfc,0x08] + vshufpd $8, -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpps $0, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x00] + vcmpeqps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $2, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x02] + vcmpleps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $1, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x01] + vcmpltps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $4, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x04] + vcmpneqps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $6, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x06] + vcmpnleps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $5, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x05] + vcmpnltps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $7, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x07] + vcmpordps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $3, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x03] + vcmpunordps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $0, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x00] + vcmpeqps -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpps $2, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x02] + vcmpleps -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpps $1, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x01] + vcmpltps -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpps $4, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x04] + vcmpneqps -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpps $6, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x06] + vcmpnleps -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpps $5, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x05] + vcmpnltps -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpps $7, -4(%rbx,%rcx,8), %xmm6, %xmm2 +// CHECK: encoding: [0xc5,0xc8,0xc2,0x54,0xcb,0xfc,0x07] + vcmpordps -4(%rbx,%rcx,8), %xmm6, %xmm2 + +// CHECK: vcmpps $3, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x03] + vcmpunordps -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmppd $0, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x00] + vcmpeqpd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $2, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x02] + vcmplepd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $1, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x01] + vcmpltpd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $4, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x04] + vcmpneqpd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $6, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x06] + vcmpnlepd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $5, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x05] + vcmpnltpd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $7, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x07] + vcmpordpd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $3, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x03] + vcmpunordpd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $0, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x00] + vcmpeqpd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmppd $2, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x02] + vcmplepd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmppd $1, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x01] + vcmpltpd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmppd $4, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x04] + vcmpneqpd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmppd $6, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x06] + vcmpnlepd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmppd $5, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x05] + vcmpnltpd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmppd $7, -4(%rbx,%rcx,8), %xmm6, %xmm2 +// CHECK: encoding: [0xc5,0xc9,0xc2,0x54,0xcb,0xfc,0x07] + vcmpordpd -4(%rbx,%rcx,8), %xmm6, %xmm2 + +// CHECK: vcmppd $3, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x03] + vcmpunordpd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpss $0, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x00] + vcmpeqss %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $2, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x02] + vcmpless %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $1, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x01] + vcmpltss %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $4, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x04] + vcmpneqss %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $6, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x06] + vcmpnless %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $5, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x05] + vcmpnltss %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $7, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x07] + vcmpordss %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $3, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x03] + vcmpunordss %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $0, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x00] + vcmpeqss -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpss $2, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x02] + vcmpless -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpss $1, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x01] + vcmpltss -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpss $4, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x04] + vcmpneqss -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpss $6, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x06] + vcmpnless -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpss $5, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x05] + vcmpnltss -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpss $7, -4(%rbx,%rcx,8), %xmm6, %xmm2 +// CHECK: encoding: [0xc5,0xca,0xc2,0x54,0xcb,0xfc,0x07] + vcmpordss -4(%rbx,%rcx,8), %xmm6, %xmm2 + +// CHECK: vcmpss $3, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x03] + vcmpunordss -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpsd $0, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x00] + vcmpeqsd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $2, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x02] + vcmplesd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $1, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x01] + vcmpltsd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $4, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x04] + vcmpneqsd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $6, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x06] + vcmpnlesd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $5, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x05] + vcmpnltsd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $7, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x07] + vcmpordsd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $3, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x03] + vcmpunordsd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $0, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x00] + vcmpeqsd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpsd $2, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x02] + vcmplesd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpsd $1, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x01] + vcmpltsd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpsd $4, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x04] + vcmpneqsd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpsd $6, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x06] + vcmpnlesd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpsd $5, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x05] + vcmpnltsd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpsd $7, -4(%rbx,%rcx,8), %xmm6, %xmm2 +// CHECK: encoding: [0xc5,0xcb,0xc2,0x54,0xcb,0xfc,0x07] + vcmpordsd -4(%rbx,%rcx,8), %xmm6, %xmm2 + +// CHECK: vcmpsd $3, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x03] + vcmpunordsd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vucomiss %xmm11, %xmm12 +// CHECK: encoding: [0xc4,0x41,0x78,0x2e,0xe3] + vucomiss %xmm11, %xmm12 + +// CHECK: vucomiss (%rax), %xmm12 +// CHECK: encoding: [0xc5,0x78,0x2e,0x20] + vucomiss (%rax), %xmm12 + +// CHECK: vcomiss %xmm11, %xmm12 +// CHECK: encoding: [0xc4,0x41,0x78,0x2f,0xe3] + vcomiss %xmm11, %xmm12 + +// CHECK: vcomiss (%rax), %xmm12 +// CHECK: encoding: [0xc5,0x78,0x2f,0x20] + vcomiss (%rax), %xmm12 + +// CHECK: vucomisd %xmm11, %xmm12 +// CHECK: encoding: [0xc4,0x41,0x79,0x2e,0xe3] + vucomisd %xmm11, %xmm12 + +// CHECK: vucomisd (%rax), %xmm12 +// CHECK: encoding: [0xc5,0x79,0x2e,0x20] + vucomisd (%rax), %xmm12 + +// CHECK: vcomisd %xmm11, %xmm12 +// CHECK: encoding: [0xc4,0x41,0x79,0x2f,0xe3] + vcomisd %xmm11, %xmm12 + +// CHECK: vcomisd (%rax), %xmm12 +// CHECK: encoding: [0xc5,0x79,0x2f,0x20] + vcomisd (%rax), %xmm12 + +// CHECK: vcvttss2si (%rcx), %eax +// CHECK: encoding: [0xc5,0xfa,0x2c,0x01] + vcvttss2si (%rcx), %eax + +// CHECK: vcvtsi2ss (%rax), %xmm11, %xmm12 +// CHECK: encoding: [0xc5,0x22,0x2a,0x20] + vcvtsi2ss (%rax), %xmm11, %xmm12 + +// CHECK: vcvtsi2ss (%rax), %xmm11, %xmm12 +// CHECK: encoding: [0xc5,0x22,0x2a,0x20] + vcvtsi2ss (%rax), %xmm11, %xmm12 + +// CHECK: vcvttsd2si (%rcx), %eax +// CHECK: encoding: [0xc5,0xfb,0x2c,0x01] + vcvttsd2si (%rcx), %eax + +// CHECK: vcvtsi2sd (%rax), %xmm11, %xmm12 +// CHECK: encoding: [0xc5,0x23,0x2a,0x20] + vcvtsi2sd (%rax), %xmm11, %xmm12 + +// CHECK: vcvtsi2sd (%rax), %xmm11, %xmm12 +// CHECK: encoding: [0xc5,0x23,0x2a,0x20] + vcvtsi2sd (%rax), %xmm11, %xmm12 + +// CHECK: vmovaps (%rax), %xmm12 +// CHECK: encoding: [0xc5,0x78,0x28,0x20] + vmovaps (%rax), %xmm12 + +// CHECK: vmovaps %xmm11, %xmm12 +// CHECK: encoding: [0xc4,0x41,0x78,0x28,0xe3] + vmovaps %xmm11, %xmm12 + +// CHECK: vmovaps %xmm11, (%rax) +// CHECK: encoding: [0xc5,0x78,0x29,0x18] + vmovaps %xmm11, (%rax) + +// CHECK: vmovapd (%rax), %xmm12 +// CHECK: encoding: [0xc5,0x79,0x28,0x20] + vmovapd (%rax), %xmm12 + +// CHECK: vmovapd %xmm11, %xmm12 +// CHECK: encoding: [0xc4,0x41,0x79,0x28,0xe3] + vmovapd %xmm11, %xmm12 + +// CHECK: vmovapd %xmm11, (%rax) +// CHECK: encoding: [0xc5,0x79,0x29,0x18] + vmovapd %xmm11, (%rax) + +// CHECK: vmovups (%rax), %xmm12 +// CHECK: encoding: [0xc5,0x78,0x10,0x20] + vmovups (%rax), %xmm12 + +// CHECK: vmovups %xmm11, %xmm12 +// CHECK: encoding: [0xc4,0x41,0x78,0x10,0xe3] + vmovups %xmm11, %xmm12 + +// CHECK: vmovups %xmm11, (%rax) +// CHECK: encoding: [0xc5,0x78,0x11,0x18] + vmovups %xmm11, (%rax) + +// CHECK: vmovupd (%rax), %xmm12 +// CHECK: encoding: [0xc5,0x79,0x10,0x20] + vmovupd (%rax), %xmm12 + +// CHECK: vmovupd %xmm11, %xmm12 +// CHECK: encoding: [0xc4,0x41,0x79,0x10,0xe3] + vmovupd %xmm11, %xmm12 + +// CHECK: vmovupd %xmm11, (%rax) +// CHECK: encoding: [0xc5,0x79,0x11,0x18] + vmovupd %xmm11, (%rax) + +// CHECK: vmovlps %xmm11, (%rax) +// CHECK: encoding: [0xc5,0x78,0x13,0x18] + vmovlps %xmm11, (%rax) + +// CHECK: vmovlps (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0x12,0x28] + vmovlps (%rax), %xmm12, %xmm13 + +// CHECK: vmovlpd %xmm11, (%rax) +// CHECK: encoding: [0xc5,0x79,0x13,0x18] + vmovlpd %xmm11, (%rax) + +// CHECK: vmovlpd (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0x12,0x28] + vmovlpd (%rax), %xmm12, %xmm13 + +// CHECK: vmovhps %xmm11, (%rax) +// CHECK: encoding: [0xc5,0x78,0x17,0x18] + vmovhps %xmm11, (%rax) + +// CHECK: vmovhps (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0x16,0x28] + vmovhps (%rax), %xmm12, %xmm13 + +// CHECK: vmovhpd %xmm11, (%rax) +// CHECK: encoding: [0xc5,0x79,0x17,0x18] + vmovhpd %xmm11, (%rax) + +// CHECK: vmovhpd (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0x16,0x28] + vmovhpd (%rax), %xmm12, %xmm13 + +// CHECK: vmovlhps %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0x16,0xeb] + vmovlhps %xmm11, %xmm12, %xmm13 + +// CHECK: vmovhlps %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0x12,0xeb] + vmovhlps %xmm11, %xmm12, %xmm13 + +// CHECK: vcvtss2sil %xmm11, %eax +// CHECK: encoding: [0xc4,0xc1,0x7a,0x2d,0xc3] + vcvtss2si %xmm11, %eax + +// CHECK: vcvtss2sil (%rax), %ebx +// CHECK: encoding: [0xc5,0xfa,0x2d,0x18] + vcvtss2si (%rax), %ebx + +// CHECK: vcvtdq2ps %xmm10, %xmm12 +// CHECK: encoding: [0xc4,0x41,0x78,0x5b,0xe2] + vcvtdq2ps %xmm10, %xmm12 + +// CHECK: vcvtdq2ps (%rax), %xmm12 +// CHECK: encoding: [0xc5,0x78,0x5b,0x20] + vcvtdq2ps (%rax), %xmm12 + +// CHECK: vcvtsd2ss %xmm12, %xmm13, %xmm10 +// CHECK: encoding: [0xc4,0x41,0x13,0x5a,0xd4] + vcvtsd2ss %xmm12, %xmm13, %xmm10 + +// CHECK: vcvtsd2ss (%rax), %xmm13, %xmm10 +// CHECK: encoding: [0xc5,0x13,0x5a,0x10] + vcvtsd2ss (%rax), %xmm13, %xmm10 + +// CHECK: vcvtps2dq %xmm12, %xmm11 +// CHECK: encoding: [0xc4,0x41,0x79,0x5b,0xdc] + vcvtps2dq %xmm12, %xmm11 + +// CHECK: vcvtps2dq (%rax), %xmm11 +// CHECK: encoding: [0xc5,0x79,0x5b,0x18] + vcvtps2dq (%rax), %xmm11 + +// CHECK: vcvtss2sd %xmm12, %xmm13, %xmm10 +// CHECK: encoding: [0xc4,0x41,0x12,0x5a,0xd4] + vcvtss2sd %xmm12, %xmm13, %xmm10 + +// CHECK: vcvtss2sd (%rax), %xmm13, %xmm10 +// CHECK: encoding: [0xc5,0x12,0x5a,0x10] + vcvtss2sd (%rax), %xmm13, %xmm10 + +// CHECK: vcvtdq2ps %xmm13, %xmm10 +// CHECK: encoding: [0xc4,0x41,0x78,0x5b,0xd5] + vcvtdq2ps %xmm13, %xmm10 + +// CHECK: vcvtdq2ps (%ecx), %xmm13 +// CHECK: encoding: [0xc5,0x78,0x5b,0x29] + vcvtdq2ps (%ecx), %xmm13 + +// CHECK: vcvttps2dq %xmm12, %xmm11 +// CHECK: encoding: [0xc4,0x41,0x7a,0x5b,0xdc] + vcvttps2dq %xmm12, %xmm11 + +// CHECK: vcvttps2dq (%rax), %xmm11 +// CHECK: encoding: [0xc5,0x7a,0x5b,0x18] + vcvttps2dq (%rax), %xmm11 + +// CHECK: vcvtps2pd %xmm12, %xmm11 +// CHECK: encoding: [0xc4,0x41,0x78,0x5a,0xdc] + vcvtps2pd %xmm12, %xmm11 + +// CHECK: vcvtps2pd (%rax), %xmm11 +// CHECK: encoding: [0xc5,0x78,0x5a,0x18] + vcvtps2pd (%rax), %xmm11 + +// CHECK: vcvtpd2ps %xmm12, %xmm11 +// CHECK: encoding: [0xc4,0x41,0x79,0x5a,0xdc] + vcvtpd2ps %xmm12, %xmm11 + +// CHECK: vsqrtpd %xmm11, %xmm12 +// CHECK: encoding: [0xc4,0x41,0x79,0x51,0xe3] + vsqrtpd %xmm11, %xmm12 + +// CHECK: vsqrtpd (%rax), %xmm12 +// CHECK: encoding: [0xc5,0x79,0x51,0x20] + vsqrtpd (%rax), %xmm12 + +// CHECK: vsqrtps %xmm11, %xmm12 +// CHECK: encoding: [0xc4,0x41,0x78,0x51,0xe3] + vsqrtps %xmm11, %xmm12 + +// CHECK: vsqrtps (%rax), %xmm12 +// CHECK: encoding: [0xc5,0x78,0x51,0x20] + vsqrtps (%rax), %xmm12 + +// CHECK: vsqrtsd %xmm11, %xmm12, %xmm10 +// CHECK: encoding: [0xc4,0x41,0x1b,0x51,0xd3] + vsqrtsd %xmm11, %xmm12, %xmm10 + +// CHECK: vsqrtsd (%rax), %xmm12, %xmm10 +// CHECK: encoding: [0xc5,0x1b,0x51,0x10] + vsqrtsd (%rax), %xmm12, %xmm10 + +// CHECK: vsqrtss %xmm11, %xmm12, %xmm10 +// CHECK: encoding: [0xc4,0x41,0x1a,0x51,0xd3] + vsqrtss %xmm11, %xmm12, %xmm10 + +// CHECK: vsqrtss (%rax), %xmm12, %xmm10 +// CHECK: encoding: [0xc5,0x1a,0x51,0x10] + vsqrtss (%rax), %xmm12, %xmm10 + +// CHECK: vrsqrtps %xmm11, %xmm12 +// CHECK: encoding: [0xc4,0x41,0x78,0x52,0xe3] + vrsqrtps %xmm11, %xmm12 + +// CHECK: vrsqrtps (%rax), %xmm12 +// CHECK: encoding: [0xc5,0x78,0x52,0x20] + vrsqrtps (%rax), %xmm12 + +// CHECK: vrsqrtss %xmm11, %xmm12, %xmm10 +// CHECK: encoding: [0xc4,0x41,0x1a,0x52,0xd3] + vrsqrtss %xmm11, %xmm12, %xmm10 + +// CHECK: vrsqrtss (%rax), %xmm12, %xmm10 +// CHECK: encoding: [0xc5,0x1a,0x52,0x10] + vrsqrtss (%rax), %xmm12, %xmm10 + +// CHECK: vrcpps %xmm11, %xmm12 +// CHECK: encoding: [0xc4,0x41,0x78,0x53,0xe3] + vrcpps %xmm11, %xmm12 + +// CHECK: vrcpps (%rax), %xmm12 +// CHECK: encoding: [0xc5,0x78,0x53,0x20] + vrcpps (%rax), %xmm12 + +// CHECK: vrcpss %xmm11, %xmm12, %xmm10 +// CHECK: encoding: [0xc4,0x41,0x1a,0x53,0xd3] + vrcpss %xmm11, %xmm12, %xmm10 + +// CHECK: vrcpss (%rax), %xmm12, %xmm10 +// CHECK: encoding: [0xc5,0x1a,0x53,0x10] + vrcpss (%rax), %xmm12, %xmm10 + +// CHECK: vmovntdq %xmm11, (%rax) +// CHECK: encoding: [0xc5,0x79,0xe7,0x18] + vmovntdq %xmm11, (%rax) + +// CHECK: vmovntpd %xmm11, (%rax) +// CHECK: encoding: [0xc5,0x79,0x2b,0x18] + vmovntpd %xmm11, (%rax) + +// CHECK: vmovntps %xmm11, (%rax) +// CHECK: encoding: [0xc5,0x78,0x2b,0x18] + vmovntps %xmm11, (%rax) + +// CHECK: vldmxcsr -4(%rip) +// CHECK: encoding: [0xc5,0xf8,0xae,0x15,0xfc,0xff,0xff,0xff] + vldmxcsr -4(%rip) + +// CHECK: vstmxcsr -4(%rsp) +// CHECK: encoding: [0xc5,0xf8,0xae,0x5c,0x24,0xfc] + vstmxcsr -4(%rsp) + +// CHECK: vpsubb %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xf8,0xeb] + vpsubb %xmm11, %xmm12, %xmm13 + +// CHECK: vpsubb (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xf8,0x28] + vpsubb (%rax), %xmm12, %xmm13 + +// CHECK: vpsubw %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xf9,0xeb] + vpsubw %xmm11, %xmm12, %xmm13 + +// CHECK: vpsubw (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xf9,0x28] + vpsubw (%rax), %xmm12, %xmm13 + +// CHECK: vpsubd %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xfa,0xeb] + vpsubd %xmm11, %xmm12, %xmm13 + +// CHECK: vpsubd (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xfa,0x28] + vpsubd (%rax), %xmm12, %xmm13 + +// CHECK: vpsubq %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xfb,0xeb] + vpsubq %xmm11, %xmm12, %xmm13 + +// CHECK: vpsubq (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xfb,0x28] + vpsubq (%rax), %xmm12, %xmm13 + +// CHECK: vpsubsb %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xe8,0xeb] + vpsubsb %xmm11, %xmm12, %xmm13 + +// CHECK: vpsubsb (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xe8,0x28] + vpsubsb (%rax), %xmm12, %xmm13 + +// CHECK: vpsubsw %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xe9,0xeb] + vpsubsw %xmm11, %xmm12, %xmm13 + +// CHECK: vpsubsw (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xe9,0x28] + vpsubsw (%rax), %xmm12, %xmm13 + +// CHECK: vpsubusb %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xd8,0xeb] + vpsubusb %xmm11, %xmm12, %xmm13 + +// CHECK: vpsubusb (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xd8,0x28] + vpsubusb (%rax), %xmm12, %xmm13 + +// CHECK: vpsubusw %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xd9,0xeb] + vpsubusw %xmm11, %xmm12, %xmm13 + +// CHECK: vpsubusw (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xd9,0x28] + vpsubusw (%rax), %xmm12, %xmm13 + +// CHECK: vpaddb %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xfc,0xeb] + vpaddb %xmm11, %xmm12, %xmm13 + +// CHECK: vpaddb (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xfc,0x28] + vpaddb (%rax), %xmm12, %xmm13 + +// CHECK: vpaddw %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xfd,0xeb] + vpaddw %xmm11, %xmm12, %xmm13 + +// CHECK: vpaddw (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xfd,0x28] + vpaddw (%rax), %xmm12, %xmm13 + +// CHECK: vpaddd %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xfe,0xeb] + vpaddd %xmm11, %xmm12, %xmm13 + +// CHECK: vpaddd (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xfe,0x28] + vpaddd (%rax), %xmm12, %xmm13 + +// CHECK: vpaddq %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xd4,0xeb] + vpaddq %xmm11, %xmm12, %xmm13 + +// CHECK: vpaddq (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xd4,0x28] + vpaddq (%rax), %xmm12, %xmm13 + +// CHECK: vpaddsb %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xec,0xeb] + vpaddsb %xmm11, %xmm12, %xmm13 + +// CHECK: vpaddsb (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xec,0x28] + vpaddsb (%rax), %xmm12, %xmm13 + +// CHECK: vpaddsw %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xed,0xeb] + vpaddsw %xmm11, %xmm12, %xmm13 + +// CHECK: vpaddsw (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xed,0x28] + vpaddsw (%rax), %xmm12, %xmm13 + +// CHECK: vpaddusb %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xdc,0xeb] + vpaddusb %xmm11, %xmm12, %xmm13 + +// CHECK: vpaddusb (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xdc,0x28] + vpaddusb (%rax), %xmm12, %xmm13 + +// CHECK: vpaddusw %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xdd,0xeb] + vpaddusw %xmm11, %xmm12, %xmm13 + +// CHECK: vpaddusw (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xdd,0x28] + vpaddusw (%rax), %xmm12, %xmm13 + +// CHECK: vpmulhuw %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xe4,0xeb] + vpmulhuw %xmm11, %xmm12, %xmm13 + +// CHECK: vpmulhuw (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xe4,0x28] + vpmulhuw (%rax), %xmm12, %xmm13 + +// CHECK: vpmulhw %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xe5,0xeb] + vpmulhw %xmm11, %xmm12, %xmm13 + +// CHECK: vpmulhw (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xe5,0x28] + vpmulhw (%rax), %xmm12, %xmm13 + +// CHECK: vpmullw %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xd5,0xeb] + vpmullw %xmm11, %xmm12, %xmm13 + +// CHECK: vpmullw (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xd5,0x28] + vpmullw (%rax), %xmm12, %xmm13 + +// CHECK: vpmuludq %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xf4,0xeb] + vpmuludq %xmm11, %xmm12, %xmm13 + +// CHECK: vpmuludq (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xf4,0x28] + vpmuludq (%rax), %xmm12, %xmm13 + +// CHECK: vpavgb %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xe0,0xeb] + vpavgb %xmm11, %xmm12, %xmm13 + +// CHECK: vpavgb (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xe0,0x28] + vpavgb (%rax), %xmm12, %xmm13 + +// CHECK: vpavgw %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xe3,0xeb] + vpavgw %xmm11, %xmm12, %xmm13 + +// CHECK: vpavgw (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xe3,0x28] + vpavgw (%rax), %xmm12, %xmm13 + +// CHECK: vpminsw %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xea,0xeb] + vpminsw %xmm11, %xmm12, %xmm13 + +// CHECK: vpminsw (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xea,0x28] + vpminsw (%rax), %xmm12, %xmm13 + +// CHECK: vpminub %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xda,0xeb] + vpminub %xmm11, %xmm12, %xmm13 + +// CHECK: vpminub (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xda,0x28] + vpminub (%rax), %xmm12, %xmm13 + +// CHECK: vpmaxsw %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xee,0xeb] + vpmaxsw %xmm11, %xmm12, %xmm13 + +// CHECK: vpmaxsw (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xee,0x28] + vpmaxsw (%rax), %xmm12, %xmm13 + +// CHECK: vpmaxub %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xde,0xeb] + vpmaxub %xmm11, %xmm12, %xmm13 + +// CHECK: vpmaxub (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xde,0x28] + vpmaxub (%rax), %xmm12, %xmm13 + +// CHECK: vpsadbw %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xf6,0xeb] + vpsadbw %xmm11, %xmm12, %xmm13 + +// CHECK: vpsadbw (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xf6,0x28] + vpsadbw (%rax), %xmm12, %xmm13 + +// CHECK: vpsllw %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xf1,0xeb] + vpsllw %xmm11, %xmm12, %xmm13 + +// CHECK: vpsllw (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xf1,0x28] + vpsllw (%rax), %xmm12, %xmm13 + +// CHECK: vpslld %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xf2,0xeb] + vpslld %xmm11, %xmm12, %xmm13 + +// CHECK: vpslld (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xf2,0x28] + vpslld (%rax), %xmm12, %xmm13 + +// CHECK: vpsllq %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xf3,0xeb] + vpsllq %xmm11, %xmm12, %xmm13 + +// CHECK: vpsllq (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xf3,0x28] + vpsllq (%rax), %xmm12, %xmm13 + +// CHECK: vpsraw %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xe1,0xeb] + vpsraw %xmm11, %xmm12, %xmm13 + +// CHECK: vpsraw (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xe1,0x28] + vpsraw (%rax), %xmm12, %xmm13 + +// CHECK: vpsrad %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xe2,0xeb] + vpsrad %xmm11, %xmm12, %xmm13 + +// CHECK: vpsrad (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xe2,0x28] + vpsrad (%rax), %xmm12, %xmm13 + +// CHECK: vpsrlw %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xd1,0xeb] + vpsrlw %xmm11, %xmm12, %xmm13 + +// CHECK: vpsrlw (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xd1,0x28] + vpsrlw (%rax), %xmm12, %xmm13 + +// CHECK: vpsrld %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xd2,0xeb] + vpsrld %xmm11, %xmm12, %xmm13 + +// CHECK: vpsrld (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xd2,0x28] + vpsrld (%rax), %xmm12, %xmm13 + +// CHECK: vpsrlq %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xd3,0xeb] + vpsrlq %xmm11, %xmm12, %xmm13 + +// CHECK: vpsrlq (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xd3,0x28] + vpsrlq (%rax), %xmm12, %xmm13 + +// CHECK: vpslld $10, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0xc1,0x11,0x72,0xf4,0x0a] + vpslld $10, %xmm12, %xmm13 + +// CHECK: vpslldq $10, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0xc1,0x11,0x73,0xfc,0x0a] + vpslldq $10, %xmm12, %xmm13 + +// CHECK: vpsllq $10, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0xc1,0x11,0x73,0xf4,0x0a] + vpsllq $10, %xmm12, %xmm13 + +// CHECK: vpsllw $10, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0xc1,0x11,0x71,0xf4,0x0a] + vpsllw $10, %xmm12, %xmm13 + +// CHECK: vpsrad $10, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0xc1,0x11,0x72,0xe4,0x0a] + vpsrad $10, %xmm12, %xmm13 + +// CHECK: vpsraw $10, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0xc1,0x11,0x71,0xe4,0x0a] + vpsraw $10, %xmm12, %xmm13 + +// CHECK: vpsrld $10, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0xc1,0x11,0x72,0xd4,0x0a] + vpsrld $10, %xmm12, %xmm13 + +// CHECK: vpsrldq $10, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0xc1,0x11,0x73,0xdc,0x0a] + vpsrldq $10, %xmm12, %xmm13 + +// CHECK: vpsrlq $10, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0xc1,0x11,0x73,0xd4,0x0a] + vpsrlq $10, %xmm12, %xmm13 + +// CHECK: vpsrlw $10, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0xc1,0x11,0x71,0xd4,0x0a] + vpsrlw $10, %xmm12, %xmm13 + +// CHECK: vpslld $10, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0xc1,0x11,0x72,0xf4,0x0a] + vpslld $10, %xmm12, %xmm13 + +// CHECK: vpand %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xdb,0xeb] + vpand %xmm11, %xmm12, %xmm13 + +// CHECK: vpand (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xdb,0x28] + vpand (%rax), %xmm12, %xmm13 + +// CHECK: vpor %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xeb,0xeb] + vpor %xmm11, %xmm12, %xmm13 + +// CHECK: vpor (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xeb,0x28] + vpor (%rax), %xmm12, %xmm13 + +// CHECK: vpxor %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xef,0xeb] + vpxor %xmm11, %xmm12, %xmm13 + +// CHECK: vpxor (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xef,0x28] + vpxor (%rax), %xmm12, %xmm13 + +// CHECK: vpandn %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xdf,0xeb] + vpandn %xmm11, %xmm12, %xmm13 + +// CHECK: vpandn (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xdf,0x28] + vpandn (%rax), %xmm12, %xmm13 + +// CHECK: vpcmpeqb %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0x74,0xeb] + vpcmpeqb %xmm11, %xmm12, %xmm13 + +// CHECK: vpcmpeqb (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0x74,0x28] + vpcmpeqb (%rax), %xmm12, %xmm13 + +// CHECK: vpcmpeqw %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0x75,0xeb] + vpcmpeqw %xmm11, %xmm12, %xmm13 + +// CHECK: vpcmpeqw (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0x75,0x28] + vpcmpeqw (%rax), %xmm12, %xmm13 + +// CHECK: vpcmpeqd %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0x76,0xeb] + vpcmpeqd %xmm11, %xmm12, %xmm13 + +// CHECK: vpcmpeqd (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0x76,0x28] + vpcmpeqd (%rax), %xmm12, %xmm13 + +// CHECK: vpcmpgtb %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0x64,0xeb] + vpcmpgtb %xmm11, %xmm12, %xmm13 + +// CHECK: vpcmpgtb (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0x64,0x28] + vpcmpgtb (%rax), %xmm12, %xmm13 + +// CHECK: vpcmpgtw %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0x65,0xeb] + vpcmpgtw %xmm11, %xmm12, %xmm13 + +// CHECK: vpcmpgtw (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0x65,0x28] + vpcmpgtw (%rax), %xmm12, %xmm13 + +// CHECK: vpcmpgtd %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0x66,0xeb] + vpcmpgtd %xmm11, %xmm12, %xmm13 + +// CHECK: vpcmpgtd (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0x66,0x28] + vpcmpgtd (%rax), %xmm12, %xmm13 + +// CHECK: vpacksswb %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0x63,0xeb] + vpacksswb %xmm11, %xmm12, %xmm13 + +// CHECK: vpacksswb (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0x63,0x28] + vpacksswb (%rax), %xmm12, %xmm13 + +// CHECK: vpackssdw %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0x6b,0xeb] + vpackssdw %xmm11, %xmm12, %xmm13 + +// CHECK: vpackssdw (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0x6b,0x28] + vpackssdw (%rax), %xmm12, %xmm13 + +// CHECK: vpackuswb %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0x67,0xeb] + vpackuswb %xmm11, %xmm12, %xmm13 + +// CHECK: vpackuswb (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0x67,0x28] + vpackuswb (%rax), %xmm12, %xmm13 + +// CHECK: vpshufd $4, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x79,0x70,0xec,0x04] + vpshufd $4, %xmm12, %xmm13 + +// CHECK: vpshufd $4, (%rax), %xmm13 +// CHECK: encoding: [0xc5,0x79,0x70,0x28,0x04] + vpshufd $4, (%rax), %xmm13 + +// CHECK: vpshufhw $4, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x7a,0x70,0xec,0x04] + vpshufhw $4, %xmm12, %xmm13 + +// CHECK: vpshufhw $4, (%rax), %xmm13 +// CHECK: encoding: [0xc5,0x7a,0x70,0x28,0x04] + vpshufhw $4, (%rax), %xmm13 + +// CHECK: vpshuflw $4, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x7b,0x70,0xec,0x04] + vpshuflw $4, %xmm12, %xmm13 + +// CHECK: vpshuflw $4, (%rax), %xmm13 +// CHECK: encoding: [0xc5,0x7b,0x70,0x28,0x04] + vpshuflw $4, (%rax), %xmm13 + +// CHECK: vpunpcklbw %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0x60,0xeb] + vpunpcklbw %xmm11, %xmm12, %xmm13 + +// CHECK: vpunpcklbw (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0x60,0x28] + vpunpcklbw (%rax), %xmm12, %xmm13 + +// CHECK: vpunpcklwd %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0x61,0xeb] + vpunpcklwd %xmm11, %xmm12, %xmm13 + +// CHECK: vpunpcklwd (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0x61,0x28] + vpunpcklwd (%rax), %xmm12, %xmm13 + +// CHECK: vpunpckldq %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0x62,0xeb] + vpunpckldq %xmm11, %xmm12, %xmm13 + +// CHECK: vpunpckldq (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0x62,0x28] + vpunpckldq (%rax), %xmm12, %xmm13 + +// CHECK: vpunpcklqdq %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0x6c,0xeb] + vpunpcklqdq %xmm11, %xmm12, %xmm13 + +// CHECK: vpunpcklqdq (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0x6c,0x28] + vpunpcklqdq (%rax), %xmm12, %xmm13 + +// CHECK: vpunpckhbw %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0x68,0xeb] + vpunpckhbw %xmm11, %xmm12, %xmm13 + +// CHECK: vpunpckhbw (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0x68,0x28] + vpunpckhbw (%rax), %xmm12, %xmm13 + +// CHECK: vpunpckhwd %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0x69,0xeb] + vpunpckhwd %xmm11, %xmm12, %xmm13 + +// CHECK: vpunpckhwd (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0x69,0x28] + vpunpckhwd (%rax), %xmm12, %xmm13 + +// CHECK: vpunpckhdq %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0x6a,0xeb] + vpunpckhdq %xmm11, %xmm12, %xmm13 + +// CHECK: vpunpckhdq (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0x6a,0x28] + vpunpckhdq (%rax), %xmm12, %xmm13 + +// CHECK: vpunpckhqdq %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0x6d,0xeb] + vpunpckhqdq %xmm11, %xmm12, %xmm13 + +// CHECK: vpunpckhqdq (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0x6d,0x28] + vpunpckhqdq (%rax), %xmm12, %xmm13 + +// CHECK: vpinsrw $7, %eax, %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc4,0xe8,0x07] + vpinsrw $7, %eax, %xmm12, %xmm13 + +// CHECK: vpinsrw $7, (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc4,0x28,0x07] + vpinsrw $7, (%rax), %xmm12, %xmm13 + +// CHECK: vpextrw $7, %xmm12, %eax +// CHECK: encoding: [0xc4,0xc1,0x79,0xc5,0xc4,0x07] + vpextrw $7, %xmm12, %eax + +// CHECK: vpmovmskb %xmm12, %eax +// CHECK: encoding: [0xc4,0xc1,0x79,0xd7,0xc4] + vpmovmskb %xmm12, %eax + +// CHECK: vmaskmovdqu %xmm14, %xmm15 +// CHECK: encoding: [0xc4,0x41,0x79,0xf7,0xfe] + vmaskmovdqu %xmm14, %xmm15 + +// CHECK: vmovd %eax, %xmm14 +// CHECK: encoding: [0xc5,0x79,0x6e,0xf0] + vmovd %eax, %xmm14 + +// CHECK: vmovd (%rax), %xmm14 +// CHECK: encoding: [0xc5,0x79,0x6e,0x30] + vmovd (%rax), %xmm14 + +// CHECK: vmovd %xmm14, (%rax) +// CHECK: encoding: [0xc5,0x79,0x7e,0x30] + vmovd %xmm14, (%rax) + +// CHECK: vmovd %rax, %xmm14 +// CHECK: encoding: [0xc4,0x61,0xf9,0x6e,0xf0] + vmovd %rax, %xmm14 + +// CHECK: vmovq %xmm14, (%rax) +// CHECK: encoding: [0xc5,0x79,0xd6,0x30] + vmovq %xmm14, (%rax) + +// CHECK: vmovq %xmm14, %xmm12 +// CHECK: encoding: [0xc4,0x41,0x7a,0x7e,0xe6] + vmovq %xmm14, %xmm12 + +// CHECK: vmovq (%rax), %xmm14 +// CHECK: encoding: [0xc5,0x7a,0x7e,0x30] + vmovq (%rax), %xmm14 + +// CHECK: vmovq %rax, %xmm14 +// CHECK: encoding: [0xc4,0x61,0xf9,0x6e,0xf0] + vmovq %rax, %xmm14 + +// CHECK: vmovq %xmm14, %rax +// CHECK: encoding: [0xc4,0x61,0xf9,0x7e,0xf0] + vmovq %xmm14, %rax + +// CHECK: vcvtpd2dq %xmm11, %xmm12 +// CHECK: encoding: [0xc4,0x41,0x7b,0xe6,0xe3] + vcvtpd2dq %xmm11, %xmm12 + +// CHECK: vcvtdq2pd %xmm11, %xmm12 +// CHECK: encoding: [0xc4,0x41,0x7a,0xe6,0xe3] + vcvtdq2pd %xmm11, %xmm12 + +// CHECK: vcvtdq2pd (%rax), %xmm12 +// CHECK: encoding: [0xc5,0x7a,0xe6,0x20] + vcvtdq2pd (%rax), %xmm12 + +// CHECK: vmovshdup %xmm11, %xmm12 +// CHECK: encoding: [0xc4,0x41,0x7a,0x16,0xe3] + vmovshdup %xmm11, %xmm12 + +// CHECK: vmovshdup (%rax), %xmm12 +// CHECK: encoding: [0xc5,0x7a,0x16,0x20] + vmovshdup (%rax), %xmm12 + +// CHECK: vmovsldup %xmm11, %xmm12 +// CHECK: encoding: [0xc4,0x41,0x7a,0x12,0xe3] + vmovsldup %xmm11, %xmm12 + +// CHECK: vmovsldup (%rax), %xmm12 +// CHECK: encoding: [0xc5,0x7a,0x12,0x20] + vmovsldup (%rax), %xmm12 + +// CHECK: vmovddup %xmm11, %xmm12 +// CHECK: encoding: [0xc4,0x41,0x7b,0x12,0xe3] + vmovddup %xmm11, %xmm12 + +// CHECK: vmovddup (%rax), %xmm12 +// CHECK: encoding: [0xc5,0x7b,0x12,0x20] + vmovddup (%rax), %xmm12 + +// CHECK: vaddsubps %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xd0,0xeb] + vaddsubps %xmm11, %xmm12, %xmm13 + +// CHECK: vaddsubps (%rax), %xmm11, %xmm12 +// CHECK: encoding: [0xc5,0x23,0xd0,0x20] + vaddsubps (%rax), %xmm11, %xmm12 + +// CHECK: vaddsubpd %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xd0,0xeb] + vaddsubpd %xmm11, %xmm12, %xmm13 + +// CHECK: vaddsubpd (%rax), %xmm11, %xmm12 +// CHECK: encoding: [0xc5,0x21,0xd0,0x20] + vaddsubpd (%rax), %xmm11, %xmm12 + +// CHECK: vhaddps %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0x7c,0xeb] + vhaddps %xmm11, %xmm12, %xmm13 + +// CHECK: vhaddps (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0x7c,0x28] + vhaddps (%rax), %xmm12, %xmm13 + +// CHECK: vhaddpd %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0x7c,0xeb] + vhaddpd %xmm11, %xmm12, %xmm13 + +// CHECK: vhaddpd (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0x7c,0x28] + vhaddpd (%rax), %xmm12, %xmm13 + +// CHECK: vhsubps %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0x7d,0xeb] + vhsubps %xmm11, %xmm12, %xmm13 + +// CHECK: vhsubps (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0x7d,0x28] + vhsubps (%rax), %xmm12, %xmm13 + +// CHECK: vhsubpd %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0x7d,0xeb] + vhsubpd %xmm11, %xmm12, %xmm13 + +// CHECK: vhsubpd (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0x7d,0x28] + vhsubpd (%rax), %xmm12, %xmm13 + +// CHECK: vpabsb %xmm11, %xmm12 +// CHECK: encoding: [0xc4,0x42,0x79,0x1c,0xe3] + vpabsb %xmm11, %xmm12 + +// CHECK: vpabsb (%rax), %xmm12 +// CHECK: encoding: [0xc4,0x62,0x79,0x1c,0x20] + vpabsb (%rax), %xmm12 + +// CHECK: vpabsw %xmm11, %xmm12 +// CHECK: encoding: [0xc4,0x42,0x79,0x1d,0xe3] + vpabsw %xmm11, %xmm12 + +// CHECK: vpabsw (%rax), %xmm12 +// CHECK: encoding: [0xc4,0x62,0x79,0x1d,0x20] + vpabsw (%rax), %xmm12 + +// CHECK: vpabsd %xmm11, %xmm12 +// CHECK: encoding: [0xc4,0x42,0x79,0x1e,0xe3] + vpabsd %xmm11, %xmm12 + +// CHECK: vpabsd (%rax), %xmm12 +// CHECK: encoding: [0xc4,0x62,0x79,0x1e,0x20] + vpabsd (%rax), %xmm12 + +// CHECK: vphaddw %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x42,0x19,0x01,0xeb] + vphaddw %xmm11, %xmm12, %xmm13 + +// CHECK: vphaddw (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x62,0x19,0x01,0x28] + vphaddw (%rax), %xmm12, %xmm13 + +// CHECK: vphaddd %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x42,0x19,0x02,0xeb] + vphaddd %xmm11, %xmm12, %xmm13 + +// CHECK: vphaddd (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x62,0x19,0x02,0x28] + vphaddd (%rax), %xmm12, %xmm13 + +// CHECK: vphaddsw %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x42,0x19,0x03,0xeb] + vphaddsw %xmm11, %xmm12, %xmm13 + +// CHECK: vphaddsw (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x62,0x19,0x03,0x28] + vphaddsw (%rax), %xmm12, %xmm13 + +// CHECK: vphsubw %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x42,0x19,0x05,0xeb] + vphsubw %xmm11, %xmm12, %xmm13 + +// CHECK: vphsubw (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x62,0x19,0x05,0x28] + vphsubw (%rax), %xmm12, %xmm13 + +// CHECK: vphsubd %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x42,0x19,0x06,0xeb] + vphsubd %xmm11, %xmm12, %xmm13 + +// CHECK: vphsubd (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x62,0x19,0x06,0x28] + vphsubd (%rax), %xmm12, %xmm13 + +// CHECK: vphsubsw %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x42,0x19,0x07,0xeb] + vphsubsw %xmm11, %xmm12, %xmm13 + +// CHECK: vphsubsw (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x62,0x19,0x07,0x28] + vphsubsw (%rax), %xmm12, %xmm13 + +// CHECK: vpmaddubsw %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x42,0x19,0x04,0xeb] + vpmaddubsw %xmm11, %xmm12, %xmm13 + +// CHECK: vpmaddubsw (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x62,0x19,0x04,0x28] + vpmaddubsw (%rax), %xmm12, %xmm13 + +// CHECK: vpshufb %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x42,0x19,0x00,0xeb] + vpshufb %xmm11, %xmm12, %xmm13 + +// CHECK: vpshufb (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x62,0x19,0x00,0x28] + vpshufb (%rax), %xmm12, %xmm13 + +// CHECK: vpsignb %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x42,0x19,0x08,0xeb] + vpsignb %xmm11, %xmm12, %xmm13 + +// CHECK: vpsignb (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x62,0x19,0x08,0x28] + vpsignb (%rax), %xmm12, %xmm13 + +// CHECK: vpsignw %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x42,0x19,0x09,0xeb] + vpsignw %xmm11, %xmm12, %xmm13 + +// CHECK: vpsignw (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x62,0x19,0x09,0x28] + vpsignw (%rax), %xmm12, %xmm13 + +// CHECK: vpsignd %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x42,0x19,0x0a,0xeb] + vpsignd %xmm11, %xmm12, %xmm13 + +// CHECK: vpsignd (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x62,0x19,0x0a,0x28] + vpsignd (%rax), %xmm12, %xmm13 + +// CHECK: vpmulhrsw %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x42,0x19,0x0b,0xeb] + vpmulhrsw %xmm11, %xmm12, %xmm13 + +// CHECK: vpmulhrsw (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x62,0x19,0x0b,0x28] + vpmulhrsw (%rax), %xmm12, %xmm13 + +// CHECK: vpalignr $7, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x43,0x19,0x0f,0xeb,0x07] + vpalignr $7, %xmm11, %xmm12, %xmm13 + +// CHECK: vpalignr $7, (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x63,0x19,0x0f,0x28,0x07] + vpalignr $7, (%rax), %xmm12, %xmm13 + +// CHECK: vroundsd $7, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x43,0x19,0x0b,0xeb,0x07] + vroundsd $7, %xmm11, %xmm12, %xmm13 + +// CHECK: vroundsd $7, (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x63,0x19,0x0b,0x28,0x07] + vroundsd $7, (%rax), %xmm12, %xmm13 + +// CHECK: vroundss $7, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x43,0x19,0x0a,0xeb,0x07] + vroundss $7, %xmm11, %xmm12, %xmm13 + +// CHECK: vroundss $7, (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x63,0x19,0x0a,0x28,0x07] + vroundss $7, (%rax), %xmm12, %xmm13 + +// CHECK: vroundpd $7, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x43,0x79,0x09,0xec,0x07] + vroundpd $7, %xmm12, %xmm13 + +// CHECK: vroundpd $7, (%rax), %xmm13 +// CHECK: encoding: [0xc4,0x63,0x79,0x09,0x28,0x07] + vroundpd $7, (%rax), %xmm13 + +// CHECK: vroundps $7, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x43,0x79,0x08,0xec,0x07] + vroundps $7, %xmm12, %xmm13 + +// CHECK: vroundps $7, (%rax), %xmm13 +// CHECK: encoding: [0xc4,0x63,0x79,0x08,0x28,0x07] + vroundps $7, (%rax), %xmm13 + +// CHECK: vphminposuw %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x42,0x79,0x41,0xec] + vphminposuw %xmm12, %xmm13 + +// CHECK: vphminposuw (%rax), %xmm12 +// CHECK: encoding: [0xc4,0x62,0x79,0x41,0x20] + vphminposuw (%rax), %xmm12 + +// CHECK: vpackusdw %xmm12, %xmm13, %xmm11 +// CHECK: encoding: [0xc4,0x42,0x11,0x2b,0xdc] + vpackusdw %xmm12, %xmm13, %xmm11 + +// CHECK: vpackusdw (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x62,0x19,0x2b,0x28] + vpackusdw (%rax), %xmm12, %xmm13 + +// CHECK: vpcmpeqq %xmm12, %xmm13, %xmm11 +// CHECK: encoding: [0xc4,0x42,0x11,0x29,0xdc] + vpcmpeqq %xmm12, %xmm13, %xmm11 + +// CHECK: vpcmpeqq (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x62,0x19,0x29,0x28] + vpcmpeqq (%rax), %xmm12, %xmm13 + +// CHECK: vpminsb %xmm12, %xmm13, %xmm11 +// CHECK: encoding: [0xc4,0x42,0x11,0x38,0xdc] + vpminsb %xmm12, %xmm13, %xmm11 + +// CHECK: vpminsb (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x62,0x19,0x38,0x28] + vpminsb (%rax), %xmm12, %xmm13 + +// CHECK: vpminsd %xmm12, %xmm13, %xmm11 +// CHECK: encoding: [0xc4,0x42,0x11,0x39,0xdc] + vpminsd %xmm12, %xmm13, %xmm11 + +// CHECK: vpminsd (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x62,0x19,0x39,0x28] + vpminsd (%rax), %xmm12, %xmm13 + +// CHECK: vpminud %xmm12, %xmm13, %xmm11 +// CHECK: encoding: [0xc4,0x42,0x11,0x3b,0xdc] + vpminud %xmm12, %xmm13, %xmm11 + +// CHECK: vpminud (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x62,0x19,0x3b,0x28] + vpminud (%rax), %xmm12, %xmm13 + +// CHECK: vpminuw %xmm12, %xmm13, %xmm11 +// CHECK: encoding: [0xc4,0x42,0x11,0x3a,0xdc] + vpminuw %xmm12, %xmm13, %xmm11 + +// CHECK: vpminuw (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x62,0x19,0x3a,0x28] + vpminuw (%rax), %xmm12, %xmm13 + +// CHECK: vpmaxsb %xmm12, %xmm13, %xmm11 +// CHECK: encoding: [0xc4,0x42,0x11,0x3c,0xdc] + vpmaxsb %xmm12, %xmm13, %xmm11 + +// CHECK: vpmaxsb (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x62,0x19,0x3c,0x28] + vpmaxsb (%rax), %xmm12, %xmm13 + +// CHECK: vpmaxsd %xmm12, %xmm13, %xmm11 +// CHECK: encoding: [0xc4,0x42,0x11,0x3d,0xdc] + vpmaxsd %xmm12, %xmm13, %xmm11 + +// CHECK: vpmaxsd (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x62,0x19,0x3d,0x28] + vpmaxsd (%rax), %xmm12, %xmm13 + +// CHECK: vpmaxud %xmm12, %xmm13, %xmm11 +// CHECK: encoding: [0xc4,0x42,0x11,0x3f,0xdc] + vpmaxud %xmm12, %xmm13, %xmm11 + +// CHECK: vpmaxud (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x62,0x19,0x3f,0x28] + vpmaxud (%rax), %xmm12, %xmm13 + +// CHECK: vpmaxuw %xmm12, %xmm13, %xmm11 +// CHECK: encoding: [0xc4,0x42,0x11,0x3e,0xdc] + vpmaxuw %xmm12, %xmm13, %xmm11 + +// CHECK: vpmaxuw (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x62,0x19,0x3e,0x28] + vpmaxuw (%rax), %xmm12, %xmm13 + +// CHECK: vpmuldq %xmm12, %xmm13, %xmm11 +// CHECK: encoding: [0xc4,0x42,0x11,0x28,0xdc] + vpmuldq %xmm12, %xmm13, %xmm11 + +// CHECK: vpmuldq (%rax), %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x62,0x19,0x28,0x28] + vpmuldq (%rax), %xmm12, %xmm13 + +// CHECK: vpmulld %xmm12, %xmm5, %xmm11 +// CHECK: encoding: [0xc4,0x42,0x51,0x40,0xdc] + vpmulld %xmm12, %xmm5, %xmm11 + +// CHECK: vpmulld (%rax), %xmm5, %xmm13 +// CHECK: encoding: [0xc4,0x62,0x51,0x40,0x28] + vpmulld (%rax), %xmm5, %xmm13 + +// CHECK: vblendps $3, %xmm12, %xmm5, %xmm11 +// CHECK: encoding: [0xc4,0x43,0x51,0x0c,0xdc,0x03] + vblendps $3, %xmm12, %xmm5, %xmm11 + +// CHECK: vblendps $3, (%rax), %xmm5, %xmm11 +// CHECK: encoding: [0xc4,0x63,0x51,0x0c,0x18,0x03] + vblendps $3, (%rax), %xmm5, %xmm11 + +// CHECK: vblendpd $3, %xmm12, %xmm5, %xmm11 +// CHECK: encoding: [0xc4,0x43,0x51,0x0d,0xdc,0x03] + vblendpd $3, %xmm12, %xmm5, %xmm11 + +// CHECK: vblendpd $3, (%rax), %xmm5, %xmm11 +// CHECK: encoding: [0xc4,0x63,0x51,0x0d,0x18,0x03] + vblendpd $3, (%rax), %xmm5, %xmm11 + +// CHECK: vpblendw $3, %xmm12, %xmm5, %xmm11 +// CHECK: encoding: [0xc4,0x43,0x51,0x0e,0xdc,0x03] + vpblendw $3, %xmm12, %xmm5, %xmm11 + +// CHECK: vpblendw $3, (%rax), %xmm5, %xmm11 +// CHECK: encoding: [0xc4,0x63,0x51,0x0e,0x18,0x03] + vpblendw $3, (%rax), %xmm5, %xmm11 + +// CHECK: vmpsadbw $3, %xmm12, %xmm5, %xmm11 +// CHECK: encoding: [0xc4,0x43,0x51,0x42,0xdc,0x03] + vmpsadbw $3, %xmm12, %xmm5, %xmm11 + +// CHECK: vmpsadbw $3, (%rax), %xmm5, %xmm11 +// CHECK: encoding: [0xc4,0x63,0x51,0x42,0x18,0x03] + vmpsadbw $3, (%rax), %xmm5, %xmm11 + +// CHECK: vdpps $3, %xmm12, %xmm5, %xmm11 +// CHECK: encoding: [0xc4,0x43,0x51,0x40,0xdc,0x03] + vdpps $3, %xmm12, %xmm5, %xmm11 + +// CHECK: vdpps $3, (%rax), %xmm5, %xmm11 +// CHECK: encoding: [0xc4,0x63,0x51,0x40,0x18,0x03] + vdpps $3, (%rax), %xmm5, %xmm11 + +// CHECK: vdppd $3, %xmm12, %xmm5, %xmm11 +// CHECK: encoding: [0xc4,0x43,0x51,0x41,0xdc,0x03] + vdppd $3, %xmm12, %xmm5, %xmm11 + +// CHECK: vdppd $3, (%rax), %xmm5, %xmm11 +// CHECK: encoding: [0xc4,0x63,0x51,0x41,0x18,0x03] + vdppd $3, (%rax), %xmm5, %xmm11 + +// CHECK: vblendvpd %xmm12, %xmm5, %xmm11, %xmm13 +// CHECK: encoding: [0xc4,0x63,0x21,0x4b,0xed,0xc0] + vblendvpd %xmm12, %xmm5, %xmm11, %xmm13 + +// CHECK: vblendvpd %xmm12, (%rax), %xmm11, %xmm13 +// CHECK: encoding: [0xc4,0x63,0x21,0x4b,0x28,0xc0] + vblendvpd %xmm12, (%rax), %xmm11, %xmm13 + +// CHECK: vblendvps %xmm12, %xmm5, %xmm11, %xmm13 +// CHECK: encoding: [0xc4,0x63,0x21,0x4a,0xed,0xc0] + vblendvps %xmm12, %xmm5, %xmm11, %xmm13 + +// CHECK: vblendvps %xmm12, (%rax), %xmm11, %xmm13 +// CHECK: encoding: [0xc4,0x63,0x21,0x4a,0x28,0xc0] + vblendvps %xmm12, (%rax), %xmm11, %xmm13 + +// CHECK: vpblendvb %xmm12, %xmm5, %xmm11, %xmm13 +// CHECK: encoding: [0xc4,0x63,0x21,0x4c,0xed,0xc0] + vpblendvb %xmm12, %xmm5, %xmm11, %xmm13 + +// CHECK: vpblendvb %xmm12, (%rax), %xmm11, %xmm13 +// CHECK: encoding: [0xc4,0x63,0x21,0x4c,0x28,0xc0] + vpblendvb %xmm12, (%rax), %xmm11, %xmm13 + +// CHECK: vpmovsxbw %xmm12, %xmm10 +// CHECK: encoding: [0xc4,0x42,0x79,0x20,0xd4] + vpmovsxbw %xmm12, %xmm10 + +// CHECK: vpmovsxbw (%rax), %xmm12 +// CHECK: encoding: [0xc4,0x62,0x79,0x20,0x20] + vpmovsxbw (%rax), %xmm12 + +// CHECK: vpmovsxwd %xmm12, %xmm10 +// CHECK: encoding: [0xc4,0x42,0x79,0x23,0xd4] + vpmovsxwd %xmm12, %xmm10 + +// CHECK: vpmovsxwd (%rax), %xmm12 +// CHECK: encoding: [0xc4,0x62,0x79,0x23,0x20] + vpmovsxwd (%rax), %xmm12 + +// CHECK: vpmovsxdq %xmm12, %xmm10 +// CHECK: encoding: [0xc4,0x42,0x79,0x25,0xd4] + vpmovsxdq %xmm12, %xmm10 + +// CHECK: vpmovsxdq (%rax), %xmm12 +// CHECK: encoding: [0xc4,0x62,0x79,0x25,0x20] + vpmovsxdq (%rax), %xmm12 + +// CHECK: vpmovzxbw %xmm12, %xmm10 +// CHECK: encoding: [0xc4,0x42,0x79,0x30,0xd4] + vpmovzxbw %xmm12, %xmm10 + +// CHECK: vpmovzxbw (%rax), %xmm12 +// CHECK: encoding: [0xc4,0x62,0x79,0x30,0x20] + vpmovzxbw (%rax), %xmm12 + +// CHECK: vpmovzxwd %xmm12, %xmm10 +// CHECK: encoding: [0xc4,0x42,0x79,0x33,0xd4] + vpmovzxwd %xmm12, %xmm10 + +// CHECK: vpmovzxwd (%rax), %xmm12 +// CHECK: encoding: [0xc4,0x62,0x79,0x33,0x20] + vpmovzxwd (%rax), %xmm12 + +// CHECK: vpmovzxdq %xmm12, %xmm10 +// CHECK: encoding: [0xc4,0x42,0x79,0x35,0xd4] + vpmovzxdq %xmm12, %xmm10 + +// CHECK: vpmovzxdq (%rax), %xmm12 +// CHECK: encoding: [0xc4,0x62,0x79,0x35,0x20] + vpmovzxdq (%rax), %xmm12 + +// CHECK: vpmovsxbq %xmm12, %xmm10 +// CHECK: encoding: [0xc4,0x42,0x79,0x22,0xd4] + vpmovsxbq %xmm12, %xmm10 + +// CHECK: vpmovsxbq (%rax), %xmm12 +// CHECK: encoding: [0xc4,0x62,0x79,0x22,0x20] + vpmovsxbq (%rax), %xmm12 + +// CHECK: vpmovzxbq %xmm12, %xmm10 +// CHECK: encoding: [0xc4,0x42,0x79,0x32,0xd4] + vpmovzxbq %xmm12, %xmm10 + +// CHECK: vpmovzxbq (%rax), %xmm12 +// CHECK: encoding: [0xc4,0x62,0x79,0x32,0x20] + vpmovzxbq (%rax), %xmm12 + +// CHECK: vpmovsxbd %xmm12, %xmm10 +// CHECK: encoding: [0xc4,0x42,0x79,0x21,0xd4] + vpmovsxbd %xmm12, %xmm10 + +// CHECK: vpmovsxbd (%rax), %xmm12 +// CHECK: encoding: [0xc4,0x62,0x79,0x21,0x20] + vpmovsxbd (%rax), %xmm12 + +// CHECK: vpmovsxwq %xmm12, %xmm10 +// CHECK: encoding: [0xc4,0x42,0x79,0x24,0xd4] + vpmovsxwq %xmm12, %xmm10 + +// CHECK: vpmovsxwq (%rax), %xmm12 +// CHECK: encoding: [0xc4,0x62,0x79,0x24,0x20] + vpmovsxwq (%rax), %xmm12 + +// CHECK: vpmovzxbd %xmm12, %xmm10 +// CHECK: encoding: [0xc4,0x42,0x79,0x31,0xd4] + vpmovzxbd %xmm12, %xmm10 + +// CHECK: vpmovzxbd (%rax), %xmm12 +// CHECK: encoding: [0xc4,0x62,0x79,0x31,0x20] + vpmovzxbd (%rax), %xmm12 + +// CHECK: vpmovzxwq %xmm12, %xmm10 +// CHECK: encoding: [0xc4,0x42,0x79,0x34,0xd4] + vpmovzxwq %xmm12, %xmm10 + +// CHECK: vpmovzxwq (%rax), %xmm12 +// CHECK: encoding: [0xc4,0x62,0x79,0x34,0x20] + vpmovzxwq (%rax), %xmm12 + +// CHECK: vpextrw $7, %xmm12, %eax +// CHECK: encoding: [0xc4,0xc1,0x79,0xc5,0xc4,0x07] + vpextrw $7, %xmm12, %eax + +// CHECK: vpextrw $7, %xmm12, (%rax) +// CHECK: encoding: [0xc4,0x63,0x79,0x15,0x20,0x07] + vpextrw $7, %xmm12, (%rax) + +// CHECK: vpextrd $7, %xmm12, %eax +// CHECK: encoding: [0xc4,0x63,0x79,0x16,0xe0,0x07] + vpextrd $7, %xmm12, %eax + +// CHECK: vpextrd $7, %xmm12, (%rax) +// CHECK: encoding: [0xc4,0x63,0x79,0x16,0x20,0x07] + vpextrd $7, %xmm12, (%rax) + +// CHECK: vpextrb $7, %xmm12, %eax +// CHECK: encoding: [0xc4,0x63,0x79,0x14,0xe0,0x07] + vpextrb $7, %xmm12, %eax + +// CHECK: vpextrb $7, %xmm12, (%rax) +// CHECK: encoding: [0xc4,0x63,0x79,0x14,0x20,0x07] + vpextrb $7, %xmm12, (%rax) + +// CHECK: vpextrq $7, %xmm12, %rcx +// CHECK: encoding: [0xc4,0x63,0xf9,0x16,0xe1,0x07] + vpextrq $7, %xmm12, %rcx + +// CHECK: vpextrq $7, %xmm12, (%rcx) +// CHECK: encoding: [0xc4,0x63,0xf9,0x16,0x21,0x07] + vpextrq $7, %xmm12, (%rcx) + +// CHECK: vextractps $7, %xmm12, (%rax) +// CHECK: encoding: [0xc4,0x63,0x79,0x17,0x20,0x07] + vextractps $7, %xmm12, (%rax) + +// CHECK: vextractps $7, %xmm12, %eax +// CHECK: encoding: [0xc4,0x63,0x79,0x17,0xe0,0x07] + vextractps $7, %xmm12, %eax + +// CHECK: vpinsrw $7, %eax, %xmm12, %xmm10 +// CHECK: encoding: [0xc5,0x19,0xc4,0xd0,0x07] + vpinsrw $7, %eax, %xmm12, %xmm10 + +// CHECK: vpinsrw $7, (%rax), %xmm12, %xmm10 +// CHECK: encoding: [0xc5,0x19,0xc4,0x10,0x07] + vpinsrw $7, (%rax), %xmm12, %xmm10 + +// CHECK: vpinsrb $7, %eax, %xmm12, %xmm10 +// CHECK: encoding: [0xc4,0x63,0x19,0x20,0xd0,0x07] + vpinsrb $7, %eax, %xmm12, %xmm10 + +// CHECK: vpinsrb $7, (%rax), %xmm12, %xmm10 +// CHECK: encoding: [0xc4,0x63,0x19,0x20,0x10,0x07] + vpinsrb $7, (%rax), %xmm12, %xmm10 + +// CHECK: vpinsrd $7, %eax, %xmm12, %xmm10 +// CHECK: encoding: [0xc4,0x63,0x19,0x22,0xd0,0x07] + vpinsrd $7, %eax, %xmm12, %xmm10 + +// CHECK: vpinsrd $7, (%rax), %xmm12, %xmm10 +// CHECK: encoding: [0xc4,0x63,0x19,0x22,0x10,0x07] + vpinsrd $7, (%rax), %xmm12, %xmm10 + +// CHECK: vpinsrq $7, %rax, %xmm12, %xmm10 +// CHECK: encoding: [0xc4,0x63,0x99,0x22,0xd0,0x07] + vpinsrq $7, %rax, %xmm12, %xmm10 + +// CHECK: vpinsrq $7, (%rax), %xmm12, %xmm10 +// CHECK: encoding: [0xc4,0x63,0x99,0x22,0x10,0x07] + vpinsrq $7, (%rax), %xmm12, %xmm10 + +// CHECK: vinsertps $7, %xmm12, %xmm10, %xmm11 +// CHECK: encoding: [0xc4,0x43,0x29,0x21,0xdc,0x07] + vinsertps $7, %xmm12, %xmm10, %xmm11 + +// CHECK: vinsertps $7, (%rax), %xmm10, %xmm11 +// CHECK: encoding: [0xc4,0x63,0x29,0x21,0x18,0x07] + vinsertps $7, (%rax), %xmm10, %xmm11 + +// CHECK: vptest %xmm12, %xmm10 +// CHECK: encoding: [0xc4,0x42,0x79,0x17,0xd4] + vptest %xmm12, %xmm10 + +// CHECK: vptest (%rax), %xmm12 +// CHECK: encoding: [0xc4,0x62,0x79,0x17,0x20] + vptest (%rax), %xmm12 + +// CHECK: vmovntdqa (%rax), %xmm12 +// CHECK: encoding: [0xc4,0x62,0x79,0x2a,0x20] + vmovntdqa (%rax), %xmm12 + +// CHECK: vpcmpgtq %xmm12, %xmm10, %xmm11 +// CHECK: encoding: [0xc4,0x42,0x29,0x37,0xdc] + vpcmpgtq %xmm12, %xmm10, %xmm11 + +// CHECK: vpcmpgtq (%rax), %xmm10, %xmm13 +// CHECK: encoding: [0xc4,0x62,0x29,0x37,0x28] + vpcmpgtq (%rax), %xmm10, %xmm13 + +// CHECK: vpcmpistrm $7, %xmm12, %xmm10 +// CHECK: encoding: [0xc4,0x43,0x79,0x62,0xd4,0x07] + vpcmpistrm $7, %xmm12, %xmm10 + +// CHECK: vpcmpistrm $7, (%rax), %xmm10 +// CHECK: encoding: [0xc4,0x63,0x79,0x62,0x10,0x07] + vpcmpistrm $7, (%rax), %xmm10 + +// CHECK: vpcmpestrm $7, %xmm12, %xmm10 +// CHECK: encoding: [0xc4,0x43,0x79,0x60,0xd4,0x07] + vpcmpestrm $7, %xmm12, %xmm10 + +// CHECK: vpcmpestrm $7, (%rax), %xmm10 +// CHECK: encoding: [0xc4,0x63,0x79,0x60,0x10,0x07] + vpcmpestrm $7, (%rax), %xmm10 + +// CHECK: vpcmpistri $7, %xmm12, %xmm10 +// CHECK: encoding: [0xc4,0x43,0x79,0x63,0xd4,0x07] + vpcmpistri $7, %xmm12, %xmm10 + +// CHECK: vpcmpistri $7, (%rax), %xmm10 +// CHECK: encoding: [0xc4,0x63,0x79,0x63,0x10,0x07] + vpcmpistri $7, (%rax), %xmm10 + +// CHECK: vpcmpestri $7, %xmm12, %xmm10 +// CHECK: encoding: [0xc4,0x43,0x79,0x61,0xd4,0x07] + vpcmpestri $7, %xmm12, %xmm10 + +// CHECK: vpcmpestri $7, (%rax), %xmm10 +// CHECK: encoding: [0xc4,0x63,0x79,0x61,0x10,0x07] + vpcmpestri $7, (%rax), %xmm10 + +// CHECK: vaesimc %xmm12, %xmm10 +// CHECK: encoding: [0xc4,0x42,0x79,0xdb,0xd4] + vaesimc %xmm12, %xmm10 + +// CHECK: vaesimc (%rax), %xmm12 +// CHECK: encoding: [0xc4,0x62,0x79,0xdb,0x20] + vaesimc (%rax), %xmm12 + +// CHECK: vaesenc %xmm12, %xmm10, %xmm11 +// CHECK: encoding: [0xc4,0x42,0x29,0xdc,0xdc] + vaesenc %xmm12, %xmm10, %xmm11 + +// CHECK: vaesenc (%rax), %xmm10, %xmm13 +// CHECK: encoding: [0xc4,0x62,0x29,0xdc,0x28] + vaesenc (%rax), %xmm10, %xmm13 + +// CHECK: vaesenclast %xmm12, %xmm10, %xmm11 +// CHECK: encoding: [0xc4,0x42,0x29,0xdd,0xdc] + vaesenclast %xmm12, %xmm10, %xmm11 + +// CHECK: vaesenclast (%rax), %xmm10, %xmm13 +// CHECK: encoding: [0xc4,0x62,0x29,0xdd,0x28] + vaesenclast (%rax), %xmm10, %xmm13 + +// CHECK: vaesdec %xmm12, %xmm10, %xmm11 +// CHECK: encoding: [0xc4,0x42,0x29,0xde,0xdc] + vaesdec %xmm12, %xmm10, %xmm11 + +// CHECK: vaesdec (%rax), %xmm10, %xmm13 +// CHECK: encoding: [0xc4,0x62,0x29,0xde,0x28] + vaesdec (%rax), %xmm10, %xmm13 + +// CHECK: vaesdeclast %xmm12, %xmm10, %xmm11 +// CHECK: encoding: [0xc4,0x42,0x29,0xdf,0xdc] + vaesdeclast %xmm12, %xmm10, %xmm11 + +// CHECK: vaesdeclast (%rax), %xmm10, %xmm13 +// CHECK: encoding: [0xc4,0x62,0x29,0xdf,0x28] + vaesdeclast (%rax), %xmm10, %xmm13 + +// CHECK: vaeskeygenassist $7, %xmm12, %xmm10 +// CHECK: encoding: [0xc4,0x43,0x79,0xdf,0xd4,0x07] + vaeskeygenassist $7, %xmm12, %xmm10 + +// CHECK: vaeskeygenassist $7, (%rax), %xmm10 +// CHECK: encoding: [0xc4,0x63,0x79,0xdf,0x10,0x07] + vaeskeygenassist $7, (%rax), %xmm10 + +// CHECK: vcmpps $8, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x08] + vcmpeq_uqps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $9, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x09] + vcmpngeps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $10, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x0a] + vcmpngtps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $11, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x0b] + vcmpfalseps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $12, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x0c] + vcmpneq_oqps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $13, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x0d] + vcmpgeps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $14, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x0e] + vcmpgtps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $15, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x0f] + vcmptrueps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $16, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x10] + vcmpeq_osps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $17, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x11] + vcmplt_oqps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $18, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x12] + vcmple_oqps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $19, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x13] + vcmpunord_sps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $20, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x14] + vcmpneq_usps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $21, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x15] + vcmpnlt_uqps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $22, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x16] + vcmpnle_uqps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $23, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x17] + vcmpord_sps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $24, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x18] + vcmpeq_usps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $25, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x19] + vcmpnge_uqps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $26, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x1a] + vcmpngt_uqps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $27, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x1b] + vcmpfalse_osps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $28, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x1c] + vcmpneq_osps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $29, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x1d] + vcmpge_oqps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $30, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x1e] + vcmpgt_oqps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $31, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x1f] + vcmptrue_usps %xmm11, %xmm12, %xmm13 + +// CHECK: vmovaps (%rax), %ymm12 +// CHECK: encoding: [0xc5,0x7c,0x28,0x20] + vmovaps (%rax), %ymm12 + +// CHECK: vmovaps %ymm11, %ymm12 +// CHECK: encoding: [0xc4,0x41,0x7c,0x28,0xe3] + vmovaps %ymm11, %ymm12 + +// CHECK: vmovaps %ymm11, (%rax) +// CHECK: encoding: [0xc5,0x7c,0x29,0x18] + vmovaps %ymm11, (%rax) + +// CHECK: vmovapd (%rax), %ymm12 +// CHECK: encoding: [0xc5,0x7d,0x28,0x20] + vmovapd (%rax), %ymm12 + +// CHECK: vmovapd %ymm11, %ymm12 +// CHECK: encoding: [0xc4,0x41,0x7d,0x28,0xe3] + vmovapd %ymm11, %ymm12 + +// CHECK: vmovapd %ymm11, (%rax) +// CHECK: encoding: [0xc5,0x7d,0x29,0x18] + vmovapd %ymm11, (%rax) + +// CHECK: vmovups (%rax), %ymm12 +// CHECK: encoding: [0xc5,0x7c,0x10,0x20] + vmovups (%rax), %ymm12 + +// CHECK: vmovups %ymm11, %ymm12 +// CHECK: encoding: [0xc4,0x41,0x7c,0x10,0xe3] + vmovups %ymm11, %ymm12 + +// CHECK: vmovups %ymm11, (%rax) +// CHECK: encoding: [0xc5,0x7c,0x11,0x18] + vmovups %ymm11, (%rax) + +// CHECK: vmovupd (%rax), %ymm12 +// CHECK: encoding: [0xc5,0x7d,0x10,0x20] + vmovupd (%rax), %ymm12 + +// CHECK: vmovupd %ymm11, %ymm12 +// CHECK: encoding: [0xc4,0x41,0x7d,0x10,0xe3] + vmovupd %ymm11, %ymm12 + +// CHECK: vmovupd %ymm11, (%rax) +// CHECK: encoding: [0xc5,0x7d,0x11,0x18] + vmovupd %ymm11, (%rax) + +// CHECK: vunpckhps %ymm11, %ymm12, %ymm4 +// CHECK: encoding: [0xc4,0xc1,0x1c,0x15,0xe3] + vunpckhps %ymm11, %ymm12, %ymm4 + +// CHECK: vunpckhpd %ymm11, %ymm12, %ymm4 +// CHECK: encoding: [0xc4,0xc1,0x1d,0x15,0xe3] + vunpckhpd %ymm11, %ymm12, %ymm4 + +// CHECK: vunpcklps %ymm11, %ymm12, %ymm4 +// CHECK: encoding: [0xc4,0xc1,0x1c,0x14,0xe3] + vunpcklps %ymm11, %ymm12, %ymm4 + +// CHECK: vunpcklpd %ymm11, %ymm12, %ymm4 +// CHECK: encoding: [0xc4,0xc1,0x1d,0x14,0xe3] + vunpcklpd %ymm11, %ymm12, %ymm4 + +// CHECK: vunpckhps -4(%rbx,%rcx,8), %ymm12, %ymm10 +// CHECK: encoding: [0xc5,0x1c,0x15,0x54,0xcb,0xfc] + vunpckhps -4(%rbx,%rcx,8), %ymm12, %ymm10 + +// CHECK: vunpckhpd -4(%rbx,%rcx,8), %ymm12, %ymm10 +// CHECK: encoding: [0xc5,0x1d,0x15,0x54,0xcb,0xfc] + vunpckhpd -4(%rbx,%rcx,8), %ymm12, %ymm10 + +// CHECK: vunpcklps -4(%rbx,%rcx,8), %ymm12, %ymm10 +// CHECK: encoding: [0xc5,0x1c,0x14,0x54,0xcb,0xfc] + vunpcklps -4(%rbx,%rcx,8), %ymm12, %ymm10 + +// CHECK: vunpcklpd -4(%rbx,%rcx,8), %ymm12, %ymm10 +// CHECK: encoding: [0xc5,0x1d,0x14,0x54,0xcb,0xfc] + vunpcklpd -4(%rbx,%rcx,8), %ymm12, %ymm10 + +// CHECK: vmovntdq %ymm11, (%rax) +// CHECK: encoding: [0xc5,0x7d,0xe7,0x18] + vmovntdq %ymm11, (%rax) + +// CHECK: vmovntpd %ymm11, (%rax) +// CHECK: encoding: [0xc5,0x7d,0x2b,0x18] + vmovntpd %ymm11, (%rax) + +// CHECK: vmovntps %ymm11, (%rax) +// CHECK: encoding: [0xc5,0x7c,0x2b,0x18] + vmovntps %ymm11, (%rax) + +// CHECK: vmovmskps %xmm12, %eax +// CHECK: encoding: [0xc4,0xc1,0x78,0x50,0xc4] + vmovmskps %xmm12, %eax + +// CHECK: vmovmskpd %xmm12, %eax +// CHECK: encoding: [0xc4,0xc1,0x79,0x50,0xc4] + vmovmskpd %xmm12, %eax + +// CHECK: vmaxps %ymm12, %ymm4, %ymm6 +// CHECK: encoding: [0xc4,0xc1,0x5c,0x5f,0xf4] + vmaxps %ymm12, %ymm4, %ymm6 + +// CHECK: vmaxpd %ymm12, %ymm4, %ymm6 +// CHECK: encoding: [0xc4,0xc1,0x5d,0x5f,0xf4] + vmaxpd %ymm12, %ymm4, %ymm6 + +// CHECK: vminps %ymm12, %ymm4, %ymm6 +// CHECK: encoding: [0xc4,0xc1,0x5c,0x5d,0xf4] + vminps %ymm12, %ymm4, %ymm6 + +// CHECK: vminpd %ymm12, %ymm4, %ymm6 +// CHECK: encoding: [0xc4,0xc1,0x5d,0x5d,0xf4] + vminpd %ymm12, %ymm4, %ymm6 + +// CHECK: vsubps %ymm12, %ymm4, %ymm6 +// CHECK: encoding: [0xc4,0xc1,0x5c,0x5c,0xf4] + vsubps %ymm12, %ymm4, %ymm6 + +// CHECK: vsubpd %ymm12, %ymm4, %ymm6 +// CHECK: encoding: [0xc4,0xc1,0x5d,0x5c,0xf4] + vsubpd %ymm12, %ymm4, %ymm6 + +// CHECK: vdivps %ymm12, %ymm4, %ymm6 +// CHECK: encoding: [0xc4,0xc1,0x5c,0x5e,0xf4] + vdivps %ymm12, %ymm4, %ymm6 + +// CHECK: vdivpd %ymm12, %ymm4, %ymm6 +// CHECK: encoding: [0xc4,0xc1,0x5d,0x5e,0xf4] + vdivpd %ymm12, %ymm4, %ymm6 + +// CHECK: vaddps %ymm12, %ymm4, %ymm6 +// CHECK: encoding: [0xc4,0xc1,0x5c,0x58,0xf4] + vaddps %ymm12, %ymm4, %ymm6 + +// CHECK: vaddpd %ymm12, %ymm4, %ymm6 +// CHECK: encoding: [0xc4,0xc1,0x5d,0x58,0xf4] + vaddpd %ymm12, %ymm4, %ymm6 + +// CHECK: vmulps %ymm12, %ymm4, %ymm6 +// CHECK: encoding: [0xc4,0xc1,0x5c,0x59,0xf4] + vmulps %ymm12, %ymm4, %ymm6 + +// CHECK: vmulpd %ymm12, %ymm4, %ymm6 +// CHECK: encoding: [0xc4,0xc1,0x5d,0x59,0xf4] + vmulpd %ymm12, %ymm4, %ymm6 + +// CHECK: vmaxps (%rax), %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdc,0x5f,0x30] + vmaxps (%rax), %ymm4, %ymm6 + +// CHECK: vmaxpd (%rax), %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdd,0x5f,0x30] + vmaxpd (%rax), %ymm4, %ymm6 + +// CHECK: vminps (%rax), %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdc,0x5d,0x30] + vminps (%rax), %ymm4, %ymm6 + +// CHECK: vminpd (%rax), %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdd,0x5d,0x30] + vminpd (%rax), %ymm4, %ymm6 + +// CHECK: vsubps (%rax), %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdc,0x5c,0x30] + vsubps (%rax), %ymm4, %ymm6 + +// CHECK: vsubpd (%rax), %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdd,0x5c,0x30] + vsubpd (%rax), %ymm4, %ymm6 + +// CHECK: vdivps (%rax), %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdc,0x5e,0x30] + vdivps (%rax), %ymm4, %ymm6 + +// CHECK: vdivpd (%rax), %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdd,0x5e,0x30] + vdivpd (%rax), %ymm4, %ymm6 + +// CHECK: vaddps (%rax), %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdc,0x58,0x30] + vaddps (%rax), %ymm4, %ymm6 + +// CHECK: vaddpd (%rax), %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdd,0x58,0x30] + vaddpd (%rax), %ymm4, %ymm6 + +// CHECK: vmulps (%rax), %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdc,0x59,0x30] + vmulps (%rax), %ymm4, %ymm6 + +// CHECK: vmulpd (%rax), %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdd,0x59,0x30] + vmulpd (%rax), %ymm4, %ymm6 + +// CHECK: vsqrtpd %ymm11, %ymm12 +// CHECK: encoding: [0xc4,0x41,0x7d,0x51,0xe3] + vsqrtpd %ymm11, %ymm12 + +// CHECK: vsqrtpd (%rax), %ymm12 +// CHECK: encoding: [0xc5,0x7d,0x51,0x20] + vsqrtpd (%rax), %ymm12 + +// CHECK: vsqrtps %ymm11, %ymm12 +// CHECK: encoding: [0xc4,0x41,0x7c,0x51,0xe3] + vsqrtps %ymm11, %ymm12 + +// CHECK: vsqrtps (%rax), %ymm12 +// CHECK: encoding: [0xc5,0x7c,0x51,0x20] + vsqrtps (%rax), %ymm12 + +// CHECK: vrsqrtps %ymm11, %ymm12 +// CHECK: encoding: [0xc4,0x41,0x7c,0x52,0xe3] + vrsqrtps %ymm11, %ymm12 + +// CHECK: vrsqrtps (%rax), %ymm12 +// CHECK: encoding: [0xc5,0x7c,0x52,0x20] + vrsqrtps (%rax), %ymm12 + +// CHECK: vrcpps %ymm11, %ymm12 +// CHECK: encoding: [0xc4,0x41,0x7c,0x53,0xe3] + vrcpps %ymm11, %ymm12 + +// CHECK: vrcpps (%rax), %ymm12 +// CHECK: encoding: [0xc5,0x7c,0x53,0x20] + vrcpps (%rax), %ymm12 + +// CHECK: vandps %ymm12, %ymm14, %ymm11 +// CHECK: encoding: [0xc4,0x41,0x0c,0x54,0xdc] + vandps %ymm12, %ymm14, %ymm11 + +// CHECK: vandpd %ymm12, %ymm14, %ymm11 +// CHECK: encoding: [0xc4,0x41,0x0d,0x54,0xdc] + vandpd %ymm12, %ymm14, %ymm11 + +// CHECK: vandps -4(%rbx,%rcx,8), %ymm12, %ymm10 +// CHECK: encoding: [0xc5,0x1c,0x54,0x54,0xcb,0xfc] + vandps -4(%rbx,%rcx,8), %ymm12, %ymm10 + +// CHECK: vandpd -4(%rbx,%rcx,8), %ymm12, %ymm10 +// CHECK: encoding: [0xc5,0x1d,0x54,0x54,0xcb,0xfc] + vandpd -4(%rbx,%rcx,8), %ymm12, %ymm10 + +// CHECK: vorps %ymm12, %ymm14, %ymm11 +// CHECK: encoding: [0xc4,0x41,0x0c,0x56,0xdc] + vorps %ymm12, %ymm14, %ymm11 + +// CHECK: vorpd %ymm12, %ymm14, %ymm11 +// CHECK: encoding: [0xc4,0x41,0x0d,0x56,0xdc] + vorpd %ymm12, %ymm14, %ymm11 + +// CHECK: vorps -4(%rbx,%rcx,8), %ymm12, %ymm10 +// CHECK: encoding: [0xc5,0x1c,0x56,0x54,0xcb,0xfc] + vorps -4(%rbx,%rcx,8), %ymm12, %ymm10 + +// CHECK: vorpd -4(%rbx,%rcx,8), %ymm12, %ymm10 +// CHECK: encoding: [0xc5,0x1d,0x56,0x54,0xcb,0xfc] + vorpd -4(%rbx,%rcx,8), %ymm12, %ymm10 + +// CHECK: vxorps %ymm12, %ymm14, %ymm11 +// CHECK: encoding: [0xc4,0x41,0x0c,0x57,0xdc] + vxorps %ymm12, %ymm14, %ymm11 + +// CHECK: vxorpd %ymm12, %ymm14, %ymm11 +// CHECK: encoding: [0xc4,0x41,0x0d,0x57,0xdc] + vxorpd %ymm12, %ymm14, %ymm11 + +// CHECK: vxorps -4(%rbx,%rcx,8), %ymm12, %ymm10 +// CHECK: encoding: [0xc5,0x1c,0x57,0x54,0xcb,0xfc] + vxorps -4(%rbx,%rcx,8), %ymm12, %ymm10 + +// CHECK: vxorpd -4(%rbx,%rcx,8), %ymm12, %ymm10 +// CHECK: encoding: [0xc5,0x1d,0x57,0x54,0xcb,0xfc] + vxorpd -4(%rbx,%rcx,8), %ymm12, %ymm10 + +// CHECK: vandnps %ymm12, %ymm14, %ymm11 +// CHECK: encoding: [0xc4,0x41,0x0c,0x55,0xdc] + vandnps %ymm12, %ymm14, %ymm11 + +// CHECK: vandnpd %ymm12, %ymm14, %ymm11 +// CHECK: encoding: [0xc4,0x41,0x0d,0x55,0xdc] + vandnpd %ymm12, %ymm14, %ymm11 + +// CHECK: vandnps -4(%rbx,%rcx,8), %ymm12, %ymm10 +// CHECK: encoding: [0xc5,0x1c,0x55,0x54,0xcb,0xfc] + vandnps -4(%rbx,%rcx,8), %ymm12, %ymm10 + +// CHECK: vandnpd -4(%rbx,%rcx,8), %ymm12, %ymm10 +// CHECK: encoding: [0xc5,0x1d,0x55,0x54,0xcb,0xfc] + vandnpd -4(%rbx,%rcx,8), %ymm12, %ymm10 + diff --git a/test/MC/AsmParser/X86/x86_64-new-encoder.s b/test/MC/AsmParser/X86/x86_64-new-encoder.s index 6988110..1858441 100644 --- a/test/MC/AsmParser/X86/x86_64-new-encoder.s +++ b/test/MC/AsmParser/X86/x86_64-new-encoder.s @@ -131,3 +131,22 @@ movl 0, %eax // CHECK: movl 0, %eax # encoding: [0x8b,0x04,0x25,A,A,A,A] btq $0x01,%rdx // CHECK: btq $1, %rdx // CHECK: encoding: [0x48,0x0f,0xba,0xe2,0x01] + +//rdar://8017633 +// CHECK: movzbl %al, %esi +// CHECK: encoding: [0x0f,0xb6,0xf0] + movzx %al, %esi + +// CHECK: movzbq %al, %rsi +// CHECK: encoding: [0x48,0x0f,0xb6,0xf0] + movzx %al, %rsi + +// CHECK: movzbq (%rsp), %rsi +// CHECK: encoding: [0x48,0x0f,0xb6,0x34,0x24] + movzx 0(%rsp), %rsi + + +// rdar://7873482 +// CHECK: [0x65,0x8b,0x04,0x25,0x7c,0x00,0x00,0x00] + movl %gs:124, %eax + diff --git a/test/MC/AsmParser/X86/x86_64-operands.s b/test/MC/AsmParser/X86/x86_64-operands.s index 9e15779..88f1a64 100644 --- a/test/MC/AsmParser/X86/x86_64-operands.s +++ b/test/MC/AsmParser/X86/x86_64-operands.s @@ -1,5 +1,3 @@ -// FIXME: Actually test that we get the expected results. - // RUN: llvm-mc -triple x86_64-unknown-unknown %s | FileCheck %s # CHECK: callq a @@ -7,3 +5,11 @@ # CHECK: leaq -40(%rbp), %r15 leaq -40(%rbp), %r15 + + + +// rdar://8013734 - Alias dr6=db6 +mov %dr6, %rax +mov %db6, %rax +# CHECK: movq %dr6, %rax +# CHECK: movq %dr6, %rax diff --git a/test/MC/AsmParser/directive_desc.s b/test/MC/AsmParser/directive_desc.s index 992455c..4bc5615 100644 --- a/test/MC/AsmParser/directive_desc.s +++ b/test/MC/AsmParser/directive_desc.s @@ -1,4 +1,4 @@ -# RUN: llvm-mc -triple i386-unknown-unknown %s | FileCheck %s +# RUN: llvm-mc -triple i386-apple-darwin9 %s | FileCheck %s # CHECK: TEST0: # CHECK: .desc foo,16 diff --git a/test/MC/AsmParser/directive_subsections_via_symbols.s b/test/MC/AsmParser/directive_subsections_via_symbols.s index 38d69c9..355bf50 100644 --- a/test/MC/AsmParser/directive_subsections_via_symbols.s +++ b/test/MC/AsmParser/directive_subsections_via_symbols.s @@ -1,4 +1,4 @@ -# RUN: llvm-mc -triple i386-unknown-unknown %s | FileCheck %s +# RUN: llvm-mc -triple i386-apple-darwin9 %s | FileCheck %s # CHECK: TEST0: # CHECK: .subsections_via_symbols diff --git a/test/MC/AsmParser/directive_zerofill.s b/test/MC/AsmParser/directive_zerofill.s index 207b8a9..bd6e485 100644 --- a/test/MC/AsmParser/directive_zerofill.s +++ b/test/MC/AsmParser/directive_zerofill.s @@ -1,4 +1,4 @@ -# RUN: llvm-mc -triple i386-unknown-unknown %s | FileCheck %s +# RUN: llvm-mc -triple i386-apple-darwin9 %s | FileCheck %s # CHECK: TEST0: # CHECK: .zerofill __FOO,__bar,x,1 diff --git a/test/MC/AsmParser/exprs.s b/test/MC/AsmParser/exprs.s index d9a248c..350360c 100644 --- a/test/MC/AsmParser/exprs.s +++ b/test/MC/AsmParser/exprs.s @@ -70,5 +70,3 @@ L0: L1: jmp A .long . - L1 - - .zerofill __DATA,_bss,A,0 diff --git a/test/MC/AsmParser/hello.s b/test/MC/AsmParser/hello.s index 01e3b4d..2b62e0f 100644 --- a/test/MC/AsmParser/hello.s +++ b/test/MC/AsmParser/hello.s @@ -1,6 +1,6 @@ -// RUN: llvm-mc -triple i386-unknown-unknown %s -o - -// RUN: llvm-mc -triple i386-unknown-unknown %s -o - -output-asm-variant=1 - +// RUN: llvm-mc -triple i386-apple-darwin9 %s -o - +// RUN: llvm-mc -triple i386-apple-darwin9 %s -o - -output-asm-variant=1 + .text .align 4,0x90 .globl _main diff --git a/test/MC/Disassembler/simple-tests.txt b/test/MC/Disassembler/simple-tests.txt index 369aa9a..dcc3763 100644 --- a/test/MC/Disassembler/simple-tests.txt +++ b/test/MC/Disassembler/simple-tests.txt @@ -57,3 +57,6 @@ # CHECK: movq %cr0, %rcx 0x0f 0x20 0xc1 + +# CHECK: leal 4(%rsp), %ecx +0x8d 0x4c 0x24 0x04
\ No newline at end of file diff --git a/test/MC/MachO/jcc.s b/test/MC/MachO/jcc.s new file mode 100644 index 0000000..7640429 --- /dev/null +++ b/test/MC/MachO/jcc.s @@ -0,0 +1,106 @@ +// RUN: llvm-mc -triple i386-apple-darwin9 %s -filetype=obj -o - | macho-dump --dump-section-data | FileCheck %s + + ja 1f +1: nop + jae 1f +1: nop + jb 1f +1: nop + jbe 1f +1: nop + jc 1f +1: nop + jcxz 1f +1: nop + jecxz 1f +1: nop + je 1f +1: nop + jg 1f +1: nop + jge 1f +1: nop + jl 1f +1: nop + jle 1f +1: nop + jna 1f +1: nop + jnae 1f +1: nop + jnb 1f +1: nop + jnbe 1f +1: nop + jnc 1f +1: nop + jne 1f +1: nop + jng 1f +1: nop + jnge 1f +1: nop + jnl 1f +1: nop + jnle 1f +1: nop + jno 1f +1: nop + jnp 1f +1: nop + jns 1f +1: nop + jnz 1f +1: nop + jo 1f +1: nop + jp 1f +1: nop + jpe 1f +1: nop + jpo 1f +1: nop + js 1f +1: nop + jz 1f +1: nop + +// CHECK: ('cputype', 7) +// CHECK: ('cpusubtype', 3) +// CHECK: ('filetype', 1) +// CHECK: ('num_load_commands', 1) +// CHECK: ('load_commands_size', 124) +// CHECK: ('flag', 0) +// CHECK: ('load_commands', [ +// CHECK: # Load Command 0 +// CHECK: (('command', 1) +// CHECK: ('size', 124) +// CHECK: ('segment_name', '\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('vm_addr', 0) +// CHECK: ('vm_size', 96) +// CHECK: ('file_offset', 152) +// CHECK: ('file_size', 96) +// CHECK: ('maxprot', 7) +// CHECK: ('initprot', 7) +// CHECK: ('num_sections', 1) +// CHECK: ('flags', 0) +// CHECK: ('sections', [ +// CHECK: # Section 0 +// CHECK: (('section_name', '__text\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('address', 0) +// CHECK: ('size', 96) +// CHECK: ('offset', 152) +// CHECK: ('alignment', 0) +// CHECK: ('reloc_offset', 0) +// CHECK: ('num_reloc', 0) +// CHECK: ('flags', 0x80000400) +// CHECK: ('reserved1', 0) +// CHECK: ('reserved2', 0) +// CHECK: ), +// CHECK: ('_relocations', [ +// CHECK: ]) +// CHECK: ('_section_data', 'w\x00\x90s\x00\x90r\x00\x90v\x00\x90r\x00\x90\xe3\x00\x90\xe3\x00\x90t\x00\x90\x7f\x00\x90}\x00\x90|\x00\x90~\x00\x90v\x00\x90r\x00\x90s\x00\x90w\x00\x90s\x00\x90u\x00\x90~\x00\x90|\x00\x90}\x00\x90\x7f\x00\x90q\x00\x90{\x00\x90y\x00\x90u\x00\x90p\x00\x90z\x00\x90z\x00\x90{\x00\x90x\x00\x90t\x00\x90') +// CHECK: ]) +// CHECK: ), +// CHECK: ]) diff --git a/test/Makefile b/test/Makefile index 3750fdb..f816744 100644 --- a/test/Makefile +++ b/test/Makefile @@ -84,7 +84,8 @@ else # !SunOS ifeq ($(HOST_OS),AuroraUX) ULIMIT=ulimit -t 600 ; ulimit -d 512000 ; ulimit -v 512000 ; else # !AuroraUX -ULIMIT=ulimit -t 600 ; ulimit -d 512000 ; ulimit -m 512000 ; ulimit -v 512000 ; +# Fedora 13 x86-64 python fails with -v 51200 +ULIMIT=ulimit -t 600 ; ulimit -d 512000 ; ulimit -m 512000 ; ulimit -v 768000 ; endif # AuroraUX endif # SunOS diff --git a/test/Other/2010-05-06-Printer.ll b/test/Other/2010-05-06-Printer.ll index 17abafa..1cbe78d 100644 --- a/test/Other/2010-05-06-Printer.ll +++ b/test/Other/2010-05-06-Printer.ll @@ -1,4 +1,4 @@ -; RUN: llc -O2 -print-after-all < %s 2>&1 +; RUN: llc -O2 -print-after-all < %s 2>/dev/null define void @tester(){ ret void diff --git a/test/Other/lint.ll b/test/Other/lint.ll index 1f9efe3..dee3d11 100644 --- a/test/Other/lint.ll +++ b/test/Other/lint.ll @@ -3,6 +3,10 @@ target datalayout = "e-p:64:64:64" declare fastcc void @bar() declare void @llvm.stackrestore(i8*) +declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind +declare void @has_sret(i8* sret %p) +declare void @has_noaliases(i32* noalias %p, i32* %q) +declare void @one_arg(i32) @CG = constant i32 7 @@ -17,6 +21,10 @@ define i32 @foo() noreturn { store i32 0, i32* undef ; CHECK: Undef pointer dereference %u = load i32* undef +; CHECK: All-ones pointer dereference + store i32 0, i32* inttoptr (i64 -1 to i32*) +; CHECK: Address one pointer dereference + store i32 0, i32* inttoptr (i64 1 to i32*) ; CHECK: Memory reference address is misaligned %x = inttoptr i32 1 to i32* load i32* %x, align 4 @@ -53,6 +61,19 @@ define i32 @foo() noreturn { call void()* bitcast (i8* blockaddress(@foo, %next) to void()*)() ; CHECK: Undefined behavior: Null pointer dereference call void @llvm.stackrestore(i8* null) +; CHECK: Undefined behavior: Null pointer dereference + call void @has_sret(i8* null) +; CHECK: Unusual: noalias argument aliases another argument + call void @has_noaliases(i32* @CG, i32* @CG) +; CHECK: Call argument count mismatches callee argument count + call void (i32, i32)* bitcast (void (i32)* @one_arg to void (i32, i32)*)(i32 0, i32 0) +; CHECK: Call argument count mismatches callee argument count + call void ()* bitcast (void (i32)* @one_arg to void ()*)() +; CHECK: Call argument type mismatches callee parameter type + call void (float)* bitcast (void (i32)* @one_arg to void (float)*)(float 0.0) + +; CHECK: Write to read-only memory + call void @llvm.memcpy.p0i8.p0i8.i64(i8* bitcast (i32* @CG to i8*), i8* bitcast (i32* @CG to i8*), i64 1, i32 1, i1 0) br label %next @@ -87,13 +108,58 @@ block: unreachable } -; CHECK: Undefined behavior: Call with "tail" keyword references alloca or va_arg -; CHECK: Undefined behavior: Call with "tail" keyword references alloca or va_arg +; CHECK: Undefined behavior: Call with "tail" keyword references alloca declare void @tailcallee(i8*) define void @use_tail(i8* %valist) { %t = alloca i8 tail call void @tailcallee(i8* %t) - %s = va_arg i8* %valist, i8* - tail call void @tailcallee(i8* %s) + ret void +} + +; CHECK: Unusual: Returning alloca value +define i8* @return_local(i32 %n, i32 %m) { + %t = alloca i8, i32 %n + %s = getelementptr i8* %t, i32 %m + ret i8* %s +} + +; CHECK: Unusual: Returning alloca value +define i32* @return_obscured_local() { +entry: + %retval = alloca i32* + %x = alloca i32 + store i32* %x, i32** %retval + br label %next +next: + %t0 = load i32** %retval + %t1 = insertvalue { i32, i32, i32* } zeroinitializer, i32* %t0, 2 + %t2 = extractvalue { i32, i32, i32* } %t1, 2 + br label %exit +exit: + %t3 = phi i32* [ %t2, %next ] + %t4 = bitcast i32* %t3 to i32* + %t5 = ptrtoint i32* %t4 to i64 + %t6 = add i64 %t5, 0 + %t7 = inttoptr i64 %t6 to i32* + ret i32* %t7 +} + +; CHECK: Undefined behavior: Undef pointer dereference +define i32* @self_reference() { +entry: + unreachable +exit: + %t3 = phi i32* [ %t4, %exit ] + %t4 = bitcast i32* %t3 to i32* + %x = volatile load i32* %t3 + br label %exit +} + +; CHECK: Call return type mismatches callee return type +%struct = type { double, double } +declare i32 @nonstruct_callee() nounwind +define void @struct_caller() nounwind { +entry: + call %struct bitcast (i32 ()* @foo to %struct ()*)() ret void } diff --git a/test/Scripts/macho-dump.bat b/test/Scripts/macho-dump.bat new file mode 100644 index 0000000..81484f6 --- /dev/null +++ b/test/Scripts/macho-dump.bat @@ -0,0 +1,7 @@ +@echo off + +@rem We need to set -u to treat stdin as binary. Python 3 has support for doing +@rem this in code, but I haven't found a way to do this in 2.6 yet. + +%PYTHON_EXECUTABLE% -u %LLVM_SRC_ROOT%\test\Scripts\macho-dump %1 %2 %3 %4 %5 %6 %7 %8 %9 + diff --git a/test/TableGen/DefmInsideMultiClass.td b/test/TableGen/DefmInsideMultiClass.td new file mode 100644 index 0000000..68cc12d --- /dev/null +++ b/test/TableGen/DefmInsideMultiClass.td @@ -0,0 +1,25 @@ +// RUN: tblgen %s | grep ADDPSrr | count 1 +// XFAIL: vg_leak + +class Instruction<bits<4> opc, string Name> { + bits<4> opcode = opc; + string name = Name; +} + +multiclass basic_r<bits<4> opc> { + def rr : Instruction<opc, "rr">; + def rm : Instruction<opc, "rm">; +} + +multiclass basic_s<bits<4> opc> { + defm SS : basic_r<opc>; + defm SD : basic_r<opc>; +} + +multiclass basic_p<bits<4> opc> { + defm PS : basic_r<opc>; + defm PD : basic_r<opc>; +} + +defm ADD : basic_s<0xf>, basic_p<0xf>; +defm SUB : basic_s<0xe>, basic_p<0xe>; diff --git a/test/TableGen/LetInsideMultiClasses.td b/test/TableGen/LetInsideMultiClasses.td new file mode 100644 index 0000000..9238bf4 --- /dev/null +++ b/test/TableGen/LetInsideMultiClasses.td @@ -0,0 +1,29 @@ +// RUN: tblgen %s | grep "bit IsDouble = 1;" | count 3 +// XFAIL: vg_leak + +class Instruction<bits<4> opc, string Name> { + bits<4> opcode = opc; + string name = Name; + bit IsDouble = 0; +} + +multiclass basic_r<bits<4> opc> { + let name = "newname" in { + def rr : Instruction<opc, "rr">; + def rm : Instruction<opc, "rm">; + } + + let name = "othername" in + def rx : Instruction<opc, "rx">; +} + +multiclass basic_ss<bits<4> opc> { + let IsDouble = 0 in + defm SS : basic_r<opc>; + + let IsDouble = 1 in + defm SD : basic_r<opc>; +} + +defm ADD : basic_ss<0xf>; + diff --git a/test/TableGen/TargetInstrInfo.td b/test/TableGen/TargetInstrInfo.td index 2871eb8..146ef6f 100644 --- a/test/TableGen/TargetInstrInfo.td +++ b/test/TableGen/TargetInstrInfo.td @@ -83,8 +83,7 @@ class Inst<dag opnds, string asmstr, bits<8> opcode, // the pattern. // 6. Address expressions should become first-class entities. -// Simple copy instruction. isMoveInstr could easily be inferred from this, -// as could TargetRegisterInfo::copyRegToReg. +// Simple copy instruction. def MOV8rr : Inst<(ops R8:$dst, R8:$src), "mov $dst, $src", 0x88, MRMDestReg, [(set R8:$dst, R8:$src)]>; diff --git a/test/TableGen/defmclass.td b/test/TableGen/defmclass.td new file mode 100644 index 0000000..55482da --- /dev/null +++ b/test/TableGen/defmclass.td @@ -0,0 +1,38 @@ +// RUN: tblgen %s | FileCheck %s +// XFAIL: vg_leak + +class XD { bits<4> Prefix = 11; } +// CHECK: Prefix = { 1, 1, 0, 0 }; +class XS { bits<4> Prefix = 12; } +class VEX { bit hasVEX_4VPrefix = 1; } + +def xd : XD; + +class BaseI { + bits<4> Prefix = 0; + bit hasVEX_4VPrefix = 0; +} + +class I<bits<4> op> : BaseI { + bits<4> opcode = op; + int val = !if(!eq(Prefix, xd.Prefix), 7, 21); + int check = !if(hasVEX_4VPrefix, 0, 10); +} + +multiclass R { + def rr : I<4>; +} + +multiclass M { + def rm : I<2>; +} + +multiclass Y { + defm SS : R, M, XD; +// CHECK: Prefix = { 1, 1, 0, 0 }; +// CHECK: Prefix = { 1, 1, 0, 0 }; + defm SD : R, M, XS; +} + +// CHECK: int check = 0; +defm Instr : Y, VEX; diff --git a/test/TableGen/eqbit.td b/test/TableGen/eqbit.td new file mode 100644 index 0000000..3953252c --- /dev/null +++ b/test/TableGen/eqbit.td @@ -0,0 +1,11 @@ +// RUN: tblgen %s | FileCheck %s +// XFAIL: vg_leak +// CHECK: a = 6 +// CHECK: a = 5 + +class A<bit b = 1> { + int a = !if(!eq(b, 1), 5, 6); +} + +def X : A<0>; +def Y : A; diff --git a/test/TableGen/ifbit.td b/test/TableGen/ifbit.td new file mode 100644 index 0000000..3b0349e --- /dev/null +++ b/test/TableGen/ifbit.td @@ -0,0 +1,11 @@ +// RUN: tblgen %s | FileCheck %s +// XFAIL: vg_leak +// CHECK: a = 6 +// CHECK: a = 5 + +class A<bit b = 1> { + int a = !if(b, 5, 6); +} + +def X : A<0>; +def Y : A; diff --git a/test/TableGen/usevalname.td b/test/TableGen/usevalname.td new file mode 100644 index 0000000..1b31c8f --- /dev/null +++ b/test/TableGen/usevalname.td @@ -0,0 +1,24 @@ +// RUN: tblgen %s | FileCheck %s +// XFAIL: vg_leak + +class Instr<list<dag> pat> { + list<dag> Pattern = pat; +} + +class Reg { + int a = 3; +} + +def VR128 : Reg; +def mem_frag; +def set; +def addr; +def shufp : Reg; + +multiclass shuffle<Reg RC> { + def rri : Instr<[(set RC:$dst, (shufp:$src3 + RC:$src1, RC:$src2))]>; +} + +// CHECK: shufp:src3 +defm ADD : shuffle<VR128>; diff --git a/test/Transforms/GVN/load-pre-align.ll b/test/Transforms/GVN/load-pre-align.ll index 3a66c0b..d8ad59f 100644 --- a/test/Transforms/GVN/load-pre-align.ll +++ b/test/Transforms/GVN/load-pre-align.ll @@ -4,7 +4,7 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32- @p = external global i32 -define arm_apcscc i32 @test(i32 %n) nounwind { +define i32 @test(i32 %n) nounwind { ; CHECK: @test entry: br label %for.cond diff --git a/test/Transforms/IndVarSimplify/indirectbr.ll b/test/Transforms/IndVarSimplify/indirectbr.ll index b4ce153..a208ded 100644 --- a/test/Transforms/IndVarSimplify/indirectbr.ll +++ b/test/Transforms/IndVarSimplify/indirectbr.ll @@ -1,6 +1,6 @@ ; RUN: opt < %s -indvars -S -disable-output -; PR5758 +; PR5758 define zeroext i1 @foo() nounwind { entry: indirectbr i8* undef, [label %"202", label %"133"] @@ -20,3 +20,20 @@ entry: "202": ; preds = %entry ret i1 false } + +; PR7333 +define void @__atomvec_module__put_vrml_bonds() nounwind { +bb7.preheader: ; preds = %entry + indirectbr i8* undef, [label %bb14, label %bb16] + +bb14: ; preds = %bb14, %bb7.preheader + br label %bb16 + +bb16: ; preds = %bb16, %bb14, %bb7.preheader + %S.31.0 = phi i64 [ %3, %bb16 ], [ 1, %bb7.preheader ], [ 1, %bb14 ] ; <i64> [#uses=2] + %0 = add nsw i64 %S.31.0, -1 ; <i64> [#uses=1] + %1 = getelementptr inbounds [3 x double]* undef, i64 0, i64 %0 ; <double*> [#uses=1] + %2 = load double* %1, align 8 ; <double> [#uses=0] + %3 = add nsw i64 %S.31.0, 1 ; <i64> [#uses=1] + br label %bb16 +} diff --git a/test/Transforms/IndVarSimplify/single-element-range.ll b/test/Transforms/IndVarSimplify/single-element-range.ll index 60a9eef..4b035ee 100644 --- a/test/Transforms/IndVarSimplify/single-element-range.ll +++ b/test/Transforms/IndVarSimplify/single-element-range.ll @@ -3,7 +3,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64" target triple = "armv6-apple-darwin10" -define arm_apcscc void @sqlite3_free_table(i8** %azResult) nounwind { +define void @sqlite3_free_table(i8** %azResult) nounwind { entry: br i1 undef, label %return, label %bb diff --git a/test/Transforms/IndVarSimplify/tripcount_compute.ll b/test/Transforms/IndVarSimplify/tripcount_compute.ll index 6eaa4c5..8835b96 100644 --- a/test/Transforms/IndVarSimplify/tripcount_compute.ll +++ b/test/Transforms/IndVarSimplify/tripcount_compute.ll @@ -1,9 +1,12 @@ +; RUN: opt < %s -indvars -S | FileCheck %s + ; These tests ensure that we can compute the trip count of various forms of ; loops. If the trip count of the loop is computable, then we will know what ; the exit value of the loop will be for some value, allowing us to substitute ; it directly into users outside of the loop, making the loop dead. -; -; RUN: opt < %s -indvars -loop-deletion -simplifycfg -S | not grep br + +; CHECK: @linear_setne +; CHECK: ret i32 100 define i32 @linear_setne() { entry: @@ -19,6 +22,9 @@ loopexit: ; preds = %loop ret i32 %i } +; CHECK: @linear_setne_2 +; CHECK: ret i32 100 + define i32 @linear_setne_2() { entry: br label %loop @@ -33,6 +39,9 @@ loopexit: ; preds = %loop ret i32 %i } +; CHECK: @linear_setne_overflow +; CHECK: ret i32 0 + define i32 @linear_setne_overflow() { entry: br label %loop @@ -47,6 +56,9 @@ loopexit: ; preds = %loop ret i32 %i } +; CHECK: @linear_setlt +; CHECK: ret i32 100 + define i32 @linear_setlt() { entry: br label %loop @@ -61,6 +73,9 @@ loopexit: ; preds = %loop ret i32 %i } +; CHECK: @quadratic_setlt +; CHECK: ret i32 34 + define i32 @quadratic_setlt() { entry: br label %loop @@ -76,6 +91,9 @@ loopexit: ; preds = %loop ret i32 %i } +; CHECK: @chained +; CHECK: ret i32 200 + define i32 @chained() { entry: br label %loop @@ -98,3 +116,47 @@ loop2: ; preds = %loop2, %loopexit loopexit2: ; preds = %loop2 ret i32 %j } + +; CHECK: @chained4 +; CHECK: ret i32 400 + +define i32 @chained4() { +entry: + br label %loop + +loop: ; preds = %loop, %entry + %i = phi i32 [ 0, %entry ], [ %i.next, %loop ] ; <i32> [#uses=3] + %i.next = add i32 %i, 1 ; <i32> [#uses=1] + %c = icmp ne i32 %i.next, 100 ; <i1> [#uses=1] + br i1 %c, label %loop, label %loopexit + +loopexit: ; preds = %loop + br label %loop2 + +loop2: ; preds = %loop2, %loopexit + %j = phi i32 [ %i.next, %loopexit ], [ %j.next, %loop2 ] ; <i32> [#uses=3] + %j.next = add i32 %j, 1 ; <i32> [#uses=1] + %c2 = icmp ne i32 %j.next, 200 ; <i1> [#uses=1] + br i1 %c2, label %loop2, label %loopexit2 + +loopexit2: ; preds = %loop + br label %loop8 + +loop8: ; preds = %loop2, %loopexit + %k = phi i32 [ %j.next, %loopexit2 ], [ %k.next, %loop8 ] ; <i32> [#uses=3] + %k.next = add i32 %k, 1 ; <i32> [#uses=1] + %c8 = icmp ne i32 %k.next, 300 ; <i1> [#uses=1] + br i1 %c8, label %loop8, label %loopexit8 + +loopexit8: ; preds = %loop2 + br label %loop9 + +loop9: ; preds = %loop2, %loopexit + %l = phi i32 [ %k.next, %loopexit8 ], [ %l.next, %loop9 ] ; <i32> [#uses=3] + %l.next = add i32 %l, 1 ; <i32> [#uses=1] + %c9 = icmp ne i32 %l.next, 400 ; <i1> [#uses=1] + br i1 %c9, label %loop9, label %loopexit9 + +loopexit9: ; preds = %loop2 + ret i32 %l.next +} diff --git a/test/Transforms/Inline/2010-05-31-ByvalTailcall.ll b/test/Transforms/Inline/2010-05-31-ByvalTailcall.ll new file mode 100644 index 0000000..1ce74e6 --- /dev/null +++ b/test/Transforms/Inline/2010-05-31-ByvalTailcall.ll @@ -0,0 +1,24 @@ +; RUN: opt < %s -tailcallelim -inline -instcombine -dse -S | FileCheck %s +; PR7272 + +; When inlining through a byval call site, the inliner creates allocas which may +; be used by inlined calls, so any inlined calls need to have their 'tail' flags +; cleared. If not then you can get nastiness like with this testcase, where the +; (inlined) call to 'ext' in 'foo' was being passed an uninitialized value. + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32" +target triple = "i386-pc-linux-gnu" + +declare void @ext(i32*) + +define void @bar(i32* byval %x) { + call void @ext(i32* %x) + ret void +} + +define void @foo(i32* %x) { +; CHECK: define void @foo +; CHECK: store i32 %1, i32* %x + call void @bar(i32* byval %x) + ret void +} diff --git a/test/Transforms/InstCombine/alloca.ll b/test/Transforms/InstCombine/alloca.ll index b9add4d..e4d1367 100644 --- a/test/Transforms/InstCombine/alloca.ll +++ b/test/Transforms/InstCombine/alloca.ll @@ -1,12 +1,13 @@ -; Zero byte allocas should be deleted. target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128" -; RUN: opt < %s -instcombine -S | \ -; RUN: not grep alloca +; RUN: opt < %s -instcombine -S | FileCheck %s ; END. declare void @use(...) +; Zero byte allocas should be deleted. +; CHECK: @test +; CHECK-NOT: alloca define void @test() { %X = alloca [0 x i32] ; <[0 x i32]*> [#uses=1] call void (...)* @use( [0 x i32]* %X ) @@ -17,12 +18,18 @@ define void @test() { ret void } +; Zero byte allocas should be deleted. +; CHECK: @test2 +; CHECK-NOT: alloca define void @test2() { %A = alloca i32 ; <i32*> [#uses=1] store i32 123, i32* %A ret void } +; Zero byte allocas should be deleted. +; CHECK: @test3 +; CHECK-NOT: alloca define void @test3() { %A = alloca { i32 } ; <{ i32 }*> [#uses=1] %B = getelementptr { i32 }* %A, i32 0, i32 0 ; <i32*> [#uses=1] @@ -30,3 +37,10 @@ define void @test3() { ret void } +; CHECK: @test4 +; CHECK: = zext i32 %n to i64 +; CHECK: %A = alloca i32, i64 % +define i32* @test4(i32 %n) { + %A = alloca i32, i32 %n + ret i32* %A +} diff --git a/test/Transforms/InstCombine/badmalloc.ll b/test/Transforms/InstCombine/badmalloc.ll index cab23b5..f5a623d 100644 --- a/test/Transforms/InstCombine/badmalloc.ll +++ b/test/Transforms/InstCombine/badmalloc.ll @@ -10,6 +10,7 @@ declare void @free(i8*) define i1 @test1() { %A = call noalias i8* @malloc(i64 4) nounwind %B = icmp eq i8* %A, null + store i8 0, i8* %A call void @free(i8* %A) ret i1 %B diff --git a/test/Transforms/InstCombine/call.ll b/test/Transforms/InstCombine/call.ll index dd65b96..c256724 100644 --- a/test/Transforms/InstCombine/call.ll +++ b/test/Transforms/InstCombine/call.ll @@ -100,7 +100,7 @@ define void @test7() { declare void @test8a() define i8* @test8() { - invoke arm_apcscc void @test8a() + invoke void @test8a() to label %invoke.cont unwind label %try.handler invoke.cont: ; preds = %entry @@ -114,5 +114,5 @@ try.handler: ; preds = %entry ; calling conv, but the implementation of test8a may actually end up using the ; right calling conv. ; CHECK: @test8() { -; CHECK-NEXT: invoke arm_apcscc void @test8a() +; CHECK-NEXT: invoke void @test8a() diff --git a/test/Transforms/InstCombine/cast.ll b/test/Transforms/InstCombine/cast.ll index 77fccdf..102d2f0 100644 --- a/test/Transforms/InstCombine/cast.ll +++ b/test/Transforms/InstCombine/cast.ll @@ -638,3 +638,14 @@ define <4 x i32> @test62(<3 x float> %call4) nounwind { ; CHECK-NEXT: ret } +; PR7311 - Don't create invalid IR on scalar->vector cast. +define <2 x float> @test63(i64 %tmp8) nounwind { +entry: + %a = bitcast i64 %tmp8 to <2 x i32> + %vcvt.i = uitofp <2 x i32> %a to <2 x float> + ret <2 x float> %vcvt.i +; CHECK: @test63 +; CHECK: bitcast +; CHECK: uitofp +} + diff --git a/test/Transforms/InstCombine/crash.ll b/test/Transforms/InstCombine/crash.ll index 854bfc8..30d467e 100644 --- a/test/Transforms/InstCombine/crash.ll +++ b/test/Transforms/InstCombine/crash.ll @@ -127,11 +127,11 @@ l10: } ; PR5471 -define arm_apcscc i32 @test5a() { +define i32 @test5a() { ret i32 0 } -define arm_apcscc void @test5() { +define void @test5() { store i1 true, i1* undef %1 = invoke i32 @test5a() to label %exit unwind label %exit exit: @@ -212,7 +212,7 @@ define i8* @test10(i8* %self, i8* %tmp3) { entry: store i1 true, i1* undef store i1 true, i1* undef - invoke arm_apcscc void @test10a() + invoke void @test10a() to label %invoke.cont unwind label %try.handler ; <i8*> [#uses=0] invoke.cont: ; preds = %entry diff --git a/test/Transforms/InstCombine/getelementptr.ll b/test/Transforms/InstCombine/getelementptr.ll index f0bee4e..9e8547b 100644 --- a/test/Transforms/InstCombine/getelementptr.ll +++ b/test/Transforms/InstCombine/getelementptr.ll @@ -468,3 +468,12 @@ define i1 @test37() nounwind { getelementptr ([1 x i8]* @A37, i64 1, i64 0) ret i1 %t } + +; Test index promotion +define i32* @test38(i32* %I, i32 %n) { + %A = getelementptr i32* %I, i32 %n + ret i32* %A +; CHECK: @test38 +; CHECK: = sext i32 %n to i64 +; CHECK: %A = getelementptr i32* %I, i64 % +} diff --git a/test/Transforms/InstCombine/icmp.ll b/test/Transforms/InstCombine/icmp.ll index 29997bf..802957f 100644 --- a/test/Transforms/InstCombine/icmp.ll +++ b/test/Transforms/InstCombine/icmp.ll @@ -131,3 +131,26 @@ entry: ; CHECK: ret i1 false } +define i1 @test14(i8 %X) nounwind readnone { +entry: + %cmp = icmp slt i8 undef, -128 + ret i1 %cmp +; CHECK: @test14 +; CHECK: ret i1 false +} + +define i1 @test15() nounwind readnone { +entry: + %cmp = icmp eq i8 undef, -128 + ret i1 %cmp +; CHECK: @test15 +; CHECK: ret i1 undef +} + +define i1 @test16() nounwind readnone { +entry: + %cmp = icmp ne i8 undef, -128 + ret i1 %cmp +; CHECK: @test16 +; CHECK: ret i1 undef +} diff --git a/test/Transforms/InstCombine/load.ll b/test/Transforms/InstCombine/load.ll index 75c62a8..d11e08e 100644 --- a/test/Transforms/InstCombine/load.ll +++ b/test/Transforms/InstCombine/load.ll @@ -7,6 +7,9 @@ @Y = constant [2 x { i32, float }] [ { i32, float } { i32 12, float 1.000000e+00 }, { i32, float } { i32 37, float 0x3FF3B2FEC0000000 } ] ; <[2 x { i32, float }]*> [#uses=2] @Z = constant [2 x { i32, float }] zeroinitializer ; <[2 x { i32, float }]*> [#uses=1] +@GLOBAL = internal constant [4 x i32] zeroinitializer + + define i32 @test1() { %B = load i32* @X ; <i32> [#uses=1] ret i32 %B @@ -85,3 +88,11 @@ define i32 @test12(i32* %P) { %V = load i32* %Q ret i32 %V } + +define <16 x i8> @test13(<2 x i64> %x) { +entry: + %tmp = load <16 x i8> * bitcast ([4 x i32]* @GLOBAL to <16 x i8>*) + ret <16 x i8> %tmp +} + + diff --git a/test/Transforms/InstCombine/load2.ll b/test/Transforms/InstCombine/load2.ll deleted file mode 100644 index 611b0fb..0000000 --- a/test/Transforms/InstCombine/load2.ll +++ /dev/null @@ -1,11 +0,0 @@ -; RUN: opt < %s -instcombine -S | not grep load - -@GLOBAL = internal constant [4 x i32] zeroinitializer - - -define <16 x i8> @foo(<2 x i64> %x) { -entry: - %tmp = load <16 x i8> * bitcast ([4 x i32]* @GLOBAL to <16 x i8>*) - ret <16 x i8> %tmp -} - diff --git a/test/Transforms/InstCombine/load3.ll b/test/Transforms/InstCombine/load3.ll index 9c87316..35398e1 100644 --- a/test/Transforms/InstCombine/load3.ll +++ b/test/Transforms/InstCombine/load3.ll @@ -1,14 +1,27 @@ -; RUN: opt < %s -instcombine -S | grep load | count 1 +; RUN: opt < %s -instcombine -S | FileCheck %s +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin10.0.0" ; Instcombine should be able to do trivial CSE of loads. -declare void @use(double %n) -define void @bar(double* %p) { - %t0 = getelementptr double* %p, i32 1 - %y = load double* %t0 - %t1 = getelementptr double* %p, i32 1 - %x = load double* %t1 - call void @use(double %x) - call void @use(double %y) - ret void +define i32 @test1(i32* %p) { + %t0 = getelementptr i32* %p, i32 1 + %y = load i32* %t0 + %t1 = getelementptr i32* %p, i32 1 + %x = load i32* %t1 + %a = sub i32 %y, %x + ret i32 %a +; CHECK: @test1 +; CHECK: ret i32 0 } + + +; PR7429 +@.str = private constant [4 x i8] c"XYZ\00" +define float @test2() { + %tmp = load float* bitcast ([4 x i8]* @.str to float*), align 1 + ret float %tmp + +; CHECK: @test2 +; CHECK: ret float 0x3806965600000000 +}
\ No newline at end of file diff --git a/test/Transforms/InstCombine/malloc-free-delete.ll b/test/Transforms/InstCombine/malloc-free-delete.ll index a4b7496..317786f 100644 --- a/test/Transforms/InstCombine/malloc-free-delete.ll +++ b/test/Transforms/InstCombine/malloc-free-delete.ll @@ -1,13 +1,25 @@ -; RUN: opt < %s -instcombine -globaldce -S | FileCheck %s +; RUN: opt < %s -instcombine -S | FileCheck %s ; PR1201 define i32 @main(i32 %argc, i8** %argv) { - %c_19 = alloca i8* ; <i8**> [#uses=2] - %malloc_206 = malloc i8, i32 10 ; <i8*> [#uses=1] + %c_19 = alloca i8* + %malloc_206 = malloc i8, i32 10 ; CHECK-NOT: malloc store i8* %malloc_206, i8** %c_19 - %tmp_207 = load i8** %c_19 ; <i8*> [#uses=1] + %tmp_207 = load i8** %c_19 free i8* %tmp_207 ; CHECK-NOT: free ret i32 0 ; CHECK: ret i32 0 } + +declare i8* @malloc(i32) +declare void @free(i8*) + +define i1 @foo() { +; CHECK: @foo +; CHECK-NEXT: ret i1 false + %m = call i8* @malloc(i32 1) + %z = icmp eq i8* %m, null + call void @free(i8* %m) + ret i1 %z +} diff --git a/test/Transforms/InstCombine/select.ll b/test/Transforms/InstCombine/select.ll index 06d5338..246a7bc 100644 --- a/test/Transforms/InstCombine/select.ll +++ b/test/Transforms/InstCombine/select.ll @@ -438,3 +438,35 @@ define i32 @test34(i32 %x, i32 %y) { ; CHECK: @test34 ; CHECK: ret i32 %x } + +define i32 @test35(i32 %x) { + %cmp = icmp sge i32 %x, 0 + %cond = select i1 %cmp, i32 60, i32 100 + ret i32 %cond +; CHECK: @test35 +; CHECK: ashr i32 %x, 31 +; CHECK: and i32 {{.*}}, 40 +; CHECK: add i32 {{.*}}, 60 +; CHECK: ret +} + +define i32 @test36(i32 %x) { + %cmp = icmp slt i32 %x, 0 + %cond = select i1 %cmp, i32 60, i32 100 + ret i32 %cond +; CHECK: @test36 +; CHECK: ashr i32 %x, 31 +; CHECK: and i32 {{.*}}, -40 +; CHECK: add i32 {{.*}}, 100 +; CHECK: ret +} + +define i32 @test37(i32 %x) { + %cmp = icmp sgt i32 %x, -1 + %cond = select i1 %cmp, i32 1, i32 -1 + ret i32 %cond +; CHECK: @test37 +; CHECK: ashr i32 %x, 31 +; CHECK: or i32 {{.*}}, 1 +; CHECK: ret +} diff --git a/test/Transforms/JumpThreading/crash.ll b/test/Transforms/JumpThreading/crash.ll index 21620be..480b4a0 100644 --- a/test/Transforms/JumpThreading/crash.ll +++ b/test/Transforms/JumpThreading/crash.ll @@ -341,3 +341,49 @@ if.end12: ; preds = %if.then, %lbl_51 ret void } + + +; PR7356 +define i32 @test13(i32* %P, i8* %Ptr) { +entry: + indirectbr i8* %Ptr, [label %BrBlock, label %B2] + +B2: + store i32 4, i32 *%P + br label %BrBlock + +BrBlock: + %L = load i32* %P + %C = icmp eq i32 %L, 42 + br i1 %C, label %T, label %F + +T: + ret i32 123 +F: + ret i32 1422 +} + + +; PR7498 +define void @test14() nounwind { +entry: + %cmp33 = icmp slt i8 undef, 0 ; <i1> [#uses=1] + %tobool = icmp eq i8 undef, 0 ; <i1> [#uses=1] + br i1 %tobool, label %land.end69, label %land.rhs + +land.rhs: ; preds = %entry + br label %land.end69 + +land.end69: ; preds = %land.rhs, %entry + %0 = phi i1 [ undef, %land.rhs ], [ true, %entry ] ; <i1> [#uses=1] + %cmp71 = or i1 true, %0 ; <i1> [#uses=1] + %cmp73 = xor i1 %cmp33, %cmp71 ; <i1> [#uses=1] + br i1 %cmp73, label %if.then, label %if.end + +if.then: ; preds = %land.end69 + ret void + +if.end: ; preds = %land.end69 + ret void +} + diff --git a/test/Transforms/LoopRotate/phi-duplicate.ll b/test/Transforms/LoopRotate/phi-duplicate.ll index cac00f8..9a64e2a 100644 --- a/test/Transforms/LoopRotate/phi-duplicate.ll +++ b/test/Transforms/LoopRotate/phi-duplicate.ll @@ -30,6 +30,6 @@ for.end: ; preds = %for.cond ; Should only end up with one phi. ; CHECK: for.body: ; CHECK-NEXT: %j.02 = phi i64 -; CHECK-NOT phi +; CHECK-NOT: phi ; CHECK: ret void diff --git a/test/Transforms/LoopUnswitch/preserve-analyses.ll b/test/Transforms/LoopUnswitch/preserve-analyses.ll index 3364fb2..668f8ec 100644 --- a/test/Transforms/LoopUnswitch/preserve-analyses.ll +++ b/test/Transforms/LoopUnswitch/preserve-analyses.ll @@ -9,7 +9,7 @@ target triple = "armv6-apple-darwin9" @delim1 = external global i32 ; <i32*> [#uses=1] @delim2 = external global i32 ; <i32*> [#uses=1] -define arm_apcscc i32 @ineqn(i8* %s, i8* %p) nounwind readonly { +define i32 @ineqn(i8* %s, i8* %p) nounwind readonly { entry: %0 = load i32* @delim1, align 4 ; <i32> [#uses=1] %1 = load i32* @delim2, align 4 ; <i32> [#uses=1] diff --git a/test/Transforms/Mem2Reg/ConvertDebugInfo.ll b/test/Transforms/Mem2Reg/ConvertDebugInfo.ll index 37d27d4..2f1ccb4 100644 --- a/test/Transforms/Mem2Reg/ConvertDebugInfo.ll +++ b/test/Transforms/Mem2Reg/ConvertDebugInfo.ll @@ -9,7 +9,7 @@ entry: %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] call void @llvm.dbg.declare(metadata !{i32* %i_addr}, metadata !0), !dbg !8 ; CHECK: call void @llvm.dbg.value(metadata !{i32 %i}, i64 0, metadata !0) -; CHECK: call void @llvm.dbg.value(metadata !{double %j}, i64 0, metadata !8) +; CHECK: call void @llvm.dbg.value(metadata !{double %j}, i64 0, metadata !9) store i32 %i, i32* %i_addr call void @llvm.dbg.declare(metadata !{double* %j_addr}, metadata !9), !dbg !8 store double %j, double* %j_addr diff --git a/test/Transforms/Mem2Reg/ConvertDebugInfo2.ll b/test/Transforms/Mem2Reg/ConvertDebugInfo2.ll new file mode 100644 index 0000000..4cb621f --- /dev/null +++ b/test/Transforms/Mem2Reg/ConvertDebugInfo2.ll @@ -0,0 +1,52 @@ +; RUN: opt -mem2reg < %s | llvm-dis | grep ".dbg " | count 7 + +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + +declare void @foo(i32, i64, i8*) + +define void @baz(i32 %a) nounwind ssp { +entry: + %x_addr.i = alloca i32 ; <i32*> [#uses=2] + %y_addr.i = alloca i64 ; <i64*> [#uses=2] + %z_addr.i = alloca i8* ; <i8**> [#uses=2] + %a_addr = alloca i32 ; <i32*> [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] + call void @llvm.dbg.declare(metadata !{i32* %a_addr}, metadata !0), !dbg !7 + store i32 %a, i32* %a_addr + %0 = load i32* %a_addr, align 4, !dbg !8 ; <i32> [#uses=1] + call void @llvm.dbg.declare(metadata !{i32* %x_addr.i}, metadata !9) nounwind, !dbg !15 + store i32 %0, i32* %x_addr.i + call void @llvm.dbg.declare(metadata !{i64* %y_addr.i}, metadata !16) nounwind, !dbg !15 + store i64 55, i64* %y_addr.i + call void @llvm.dbg.declare(metadata !{i8** %z_addr.i}, metadata !17) nounwind, !dbg !15 + store i8* bitcast (void (i32)* @baz to i8*), i8** %z_addr.i + %1 = load i32* %x_addr.i, align 4, !dbg !18 ; <i32> [#uses=1] + %2 = load i64* %y_addr.i, align 8, !dbg !18 ; <i64> [#uses=1] + %3 = load i8** %z_addr.i, align 8, !dbg !18 ; <i8*> [#uses=1] + call void @foo(i32 %1, i64 %2, i8* %3) nounwind, !dbg !18 + br label %return, !dbg !19 + +return: ; preds = %entry + ret void, !dbg !19 +} + +!0 = metadata !{i32 524545, metadata !1, metadata !"a", metadata !2, i32 8, metadata !6} ; [ DW_TAG_arg_variable ] +!1 = metadata !{i32 524334, i32 0, metadata !2, metadata !"baz", metadata !"baz", metadata !"baz", metadata !2, i32 8, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false} ; [ DW_TAG_subprogram ] +!2 = metadata !{i32 524329, metadata !"bar.c", metadata !"/tmp/", metadata !3} ; [ DW_TAG_file_type ] +!3 = metadata !{i32 524305, i32 0, i32 1, metadata !"bar.c", metadata !"/tmp/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!4 = metadata !{i32 524309, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ] +!5 = metadata !{null, metadata !6} +!6 = metadata !{i32 524324, metadata !2, metadata !"int", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!7 = metadata !{i32 8, i32 0, metadata !1, null} +!8 = metadata !{i32 9, i32 0, metadata !1, null} +!9 = metadata !{i32 524545, metadata !10, metadata !"x", metadata !2, i32 4, metadata !6} ; [ DW_TAG_arg_variable ] +!10 = metadata !{i32 524334, i32 0, metadata !2, metadata !"bar", metadata !"bar", metadata !"bar", metadata !2, i32 4, metadata !11, i1 true, i1 true, i32 0, i32 0, null, i1 false, i1 false} ; [ DW_TAG_subprogram ] +!11 = metadata !{i32 524309, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_subroutine_type ] +!12 = metadata !{null, metadata !6, metadata !13, metadata !14} +!13 = metadata !{i32 524324, metadata !2, metadata !"long int", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!14 = metadata !{i32 524303, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, null} ; [ DW_TAG_pointer_type ] +!15 = metadata !{i32 4, i32 0, metadata !10, metadata !8} +!16 = metadata !{i32 524545, metadata !10, metadata !"y", metadata !2, i32 4, metadata !13} ; [ DW_TAG_arg_variable ] +!17 = metadata !{i32 524545, metadata !10, metadata !"z", metadata !2, i32 4, metadata !14} ; [ DW_TAG_arg_variable ] +!18 = metadata !{i32 5, i32 0, metadata !10, metadata !8} +!19 = metadata !{i32 10, i32 0, metadata !1, null} diff --git a/test/Transforms/PartialSpecialize/dg.exp b/test/Transforms/PartialSpecialize/dg.exp new file mode 100644 index 0000000..f200589 --- /dev/null +++ b/test/Transforms/PartialSpecialize/dg.exp @@ -0,0 +1,3 @@ +load_lib llvm.exp + +RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp}]] diff --git a/test/Transforms/PartialSpecialize/two-specializations.ll b/test/Transforms/PartialSpecialize/two-specializations.ll new file mode 100644 index 0000000..c85ddb7 --- /dev/null +++ b/test/Transforms/PartialSpecialize/two-specializations.ll @@ -0,0 +1,33 @@ +; If there are two specializations of a function, make sure each callsite +; calls the right one. +; +; RN: opt -S -partialspecialization %s | FileCheck %s +; RUN: true +declare void @callback1() +declare void @callback2() + +define internal void @UseCallback(void()* %pCallback) { + call void %pCallback() + ret void +} + +define void @foo(void()* %pNonConstCallback) +{ +Entry: +; CHECK: Entry +; CHECK-NEXT: call void @callback1() +; CHECK-NEXT: call void @callback1() +; CHECK-NEXT: call void @callback2() +; CHECK-NEXT: call void %pNonConstCallback() +; CHECK-NEXT: call void @callback1() +; CHECK-NEXT: call void @callback2() +; CHECK-NEXT: call void @callback2() + call void @UseCallback(void()* @callback1) + call void @UseCallback(void()* @callback1) + call void @UseCallback(void()* @callback2) + call void @UseCallback(void()* %pNonConstCallback) + call void @UseCallback(void()* @callback1) + call void @UseCallback(void()* @callback2) + call void @UseCallback(void()* @callback2) + ret void +} diff --git a/test/Transforms/ScalarRepl/2009-12-11-NeonTypes.ll b/test/Transforms/ScalarRepl/2009-12-11-NeonTypes.ll index 71f66d6..31d9bae 100644 --- a/test/Transforms/ScalarRepl/2009-12-11-NeonTypes.ll +++ b/test/Transforms/ScalarRepl/2009-12-11-NeonTypes.ll @@ -9,7 +9,7 @@ target triple = "thumbv7-apple-darwin10" %struct.int16x8x2_t = type { [2 x %struct.int16x8_t] } %union..0anon = type { %struct.int16x8x2_t } -define arm_apcscc void @test(<8 x i16> %tmp.0, %struct.int16x8x2_t* %dst) nounwind { +define void @test(<8 x i16> %tmp.0, %struct.int16x8x2_t* %dst) nounwind { ; CHECK: @test ; CHECK-NOT: alloca ; CHECK: "alloca point" @@ -68,7 +68,7 @@ return: ; preds = %entry ; Radar 7466574 %struct._NSRange = type { i64 } -define arm_apcscc void @test_memcpy_self() nounwind { +define void @test_memcpy_self() nounwind { ; CHECK: @test_memcpy_self ; CHECK-NOT: alloca ; CHECK: br i1 diff --git a/test/Transforms/ScalarRepl/2010-01-18-SelfCopy.ll b/test/Transforms/ScalarRepl/2010-01-18-SelfCopy.ll index 74cf251..3aee399 100644 --- a/test/Transforms/ScalarRepl/2010-01-18-SelfCopy.ll +++ b/test/Transforms/ScalarRepl/2010-01-18-SelfCopy.ll @@ -5,7 +5,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3 %struct.test = type { [3 x double ] } -define arm_apcscc void @test_memcpy_self() nounwind { +define void @test_memcpy_self() nounwind { ; CHECK: @test_memcpy_self ; CHECK-NOT: alloca ; CHECK: ret void diff --git a/test/Transforms/ScalarRepl/address-space.ll b/test/Transforms/ScalarRepl/address-space.ll new file mode 100644 index 0000000..318d4e7 --- /dev/null +++ b/test/Transforms/ScalarRepl/address-space.ll @@ -0,0 +1,35 @@ +; RUN: opt -S -scalarrepl < %s | FileCheck %s +; PR7437 - Make sure SROA preserves address space of memcpy when +; hacking on it. +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin10" + +%struct.anon = type { [1 x float] } + +; CHECK: define void @Test( +; CHECK: load float addrspace(2)* +; CHECK-NEXT: fsub float +; CHECK: store float {{.*}}, float addrspace(2)* +define void @Test(%struct.anon addrspace(2)* %pPtr) nounwind { +entry: + %s = alloca %struct.anon, align 4 ; <%struct.anon*> [#uses=3] + %arrayidx = getelementptr inbounds %struct.anon addrspace(2)* %pPtr, i64 0 ; <%struct.anon addrspace(2)*> [#uses=1] + %tmp1 = bitcast %struct.anon* %s to i8* ; <i8*> [#uses=1] + %tmp2 = bitcast %struct.anon addrspace(2)* %arrayidx to i8 addrspace(2)* ; <i8 addrspace(2)*> [#uses=1] + call void @llvm.memcpy.p0i8.p2i8.i64(i8* %tmp1, i8 addrspace(2)* %tmp2, i64 4, i32 4, i1 false) + %tmp3 = getelementptr inbounds %struct.anon* %s, i32 0, i32 0 ; <[1 x float]*> [#uses=1] + %arrayidx4 = getelementptr inbounds [1 x float]* %tmp3, i32 0, i64 0 ; <float*> [#uses=2] + %tmp5 = load float* %arrayidx4 ; <float> [#uses=1] + %sub = fsub float %tmp5, 5.000000e+00 ; <float> [#uses=1] + store float %sub, float* %arrayidx4 + %arrayidx7 = getelementptr inbounds %struct.anon addrspace(2)* %pPtr, i64 0 ; <%struct.anon addrspace(2)*> [#uses=1] + %tmp8 = bitcast %struct.anon addrspace(2)* %arrayidx7 to i8 addrspace(2)* ; <i8 addrspace(2)*> [#uses=1] + %tmp9 = bitcast %struct.anon* %s to i8* ; <i8*> [#uses=1] + call void @llvm.memcpy.p2i8.p0i8.i64(i8 addrspace(2)* %tmp8, i8* %tmp9, i64 4, i32 4, i1 false) + ret void +} + +declare void @llvm.memcpy.p0i8.p2i8.i64(i8* nocapture, i8 addrspace(2)* nocapture, i64, i32, i1) nounwind + +declare void @llvm.memcpy.p2i8.p0i8.i64(i8 addrspace(2)* nocapture, i8* nocapture, i64, i32, i1) nounwind + diff --git a/test/Transforms/ScalarRepl/memcpy-align.ll b/test/Transforms/ScalarRepl/memcpy-align.ll index 91d354d..a7af208 100644 --- a/test/Transforms/ScalarRepl/memcpy-align.ll +++ b/test/Transforms/ScalarRepl/memcpy-align.ll @@ -9,7 +9,7 @@ target triple = "arm-u-u" @c = external global %0 ; <%0*> [#uses=1] -define arm_aapcscc void @good() nounwind { +define void @good() nounwind { entry: %x0 = alloca %struct.anon, align 4 ; <%struct.anon*> [#uses=2] %tmp = bitcast %struct.anon* %x0 to i8* ; <i8*> [#uses=1] diff --git a/test/Transforms/SimplifyCFG/trapping-load-unreachable.ll b/test/Transforms/SimplifyCFG/trapping-load-unreachable.ll index 6956faa..7bca5f5 100644 --- a/test/Transforms/SimplifyCFG/trapping-load-unreachable.ll +++ b/test/Transforms/SimplifyCFG/trapping-load-unreachable.ll @@ -31,3 +31,14 @@ entry: ; CHECK: call void @llvm.trap ; CHECK: unreachable } + +; PR7369 +define void @test3() nounwind { +entry: + volatile store i32 4, i32* null + ret void + +; CHECK: @test3 +; CHECK: volatile store i32 4, i32* null +; CHECK: ret +} diff --git a/test/Transforms/SimplifyLibCalls/2010-05-30-memcpy-Struct.ll b/test/Transforms/SimplifyLibCalls/2010-05-30-memcpy-Struct.ll new file mode 100644 index 0000000..f67bae7 --- /dev/null +++ b/test/Transforms/SimplifyLibCalls/2010-05-30-memcpy-Struct.ll @@ -0,0 +1,20 @@ +; RUN: opt -simplify-libcalls %s -S -o - | FileCheck %s +; PR7265 + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-unknown-linux-gnu" + +%union.anon = type { i32, [4 x i8] } + +@.str = private constant [3 x i8] c"%s\00" ; <[3 x i8]*> [#uses=2] + +define void @CopyEventArg(%union.anon* %ev) nounwind { +entry: + %call = call i32 (i8*, i8*, ...)* @sprintf(i8* undef, i8* getelementptr inbounds ([3 x i8]* @.str, i64 0, i64 0), %union.anon* %ev) nounwind ; <i32> [#uses=0] +; CHECK: bitcast %union.anon* %ev to i8* +; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64 + ret void +} + +declare i32 @sprintf(i8*, i8*, ...) + diff --git a/test/Transforms/SimplifyLibCalls/PR7357.ll b/test/Transforms/SimplifyLibCalls/PR7357.ll new file mode 100644 index 0000000..6d5c1d5 --- /dev/null +++ b/test/Transforms/SimplifyLibCalls/PR7357.ll @@ -0,0 +1,16 @@ +; RUN: opt < %s -default-data-layout="e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32" -simplify-libcalls -S | FileCheck %s +@.str1 = private constant [11 x i8] c"(){};[]&|:\00", align 4 + +; check that simplify libcalls will not replace a call with one calling +; convention with a new call with a different calling convention. + +; CHECK: define arm_aapcscc i32 @foo(i32 %argc) +; CHECK: call arm_aapcscc i8* @strchr +define arm_aapcscc i32 @foo(i32 %argc) nounwind { +bb.nph: + call arm_aapcscc i8* @strchr(i8* getelementptr ([11 x i8]* @.str1, i32 0, +i32 0), i32 %argc) nounwind readonly + ret i32 0 +} + +declare arm_aapcscc i8* @strchr(i8*, i32) nounwind readonly diff --git a/test/Transforms/SimplifyLibCalls/StrNCmp.ll b/test/Transforms/SimplifyLibCalls/StrNCmp.ll index ba77385..8b536a5 100644 --- a/test/Transforms/SimplifyLibCalls/StrNCmp.ll +++ b/test/Transforms/SimplifyLibCalls/StrNCmp.ll @@ -2,6 +2,9 @@ ; RUN: opt < %s -simplify-libcalls -S | \ ; RUN: not grep {call.*strncmp} +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32" +target triple = "i386-apple-darwin9.0" + @hello = constant [6 x i8] c"hello\00" ; <[6 x i8]*> [#uses=1] @hell = constant [5 x i8] c"hell\00" ; <[5 x i8]*> [#uses=1] @null = constant [1 x i8] zeroinitializer ; <[1 x i8]*> [#uses=1] @@ -26,3 +29,7 @@ define i32 @main() { ret i32 %rslt4 } +define i32 @test1(i8* %P, i8* %Q) { + %cmp = call i32 @strncmp(i8* %P, i8* %Q, i32 1) + ret i32 %cmp +} diff --git a/test/Transforms/SimplifyLibCalls/StrStr.ll b/test/Transforms/SimplifyLibCalls/StrStr.ll index 2cac2d4..eefd2e8 100644 --- a/test/Transforms/SimplifyLibCalls/StrStr.ll +++ b/test/Transforms/SimplifyLibCalls/StrStr.ll @@ -46,3 +46,15 @@ entry: ; CHECK: @test4 ; CHECK: ret i8* %P } + +define i1 @test5(i8* %P, i8* %Q) nounwind readonly { +entry: + %call = tail call i8* @strstr(i8* %P, i8* %Q) nounwind ; <i8*> [#uses=1] + %cmp = icmp eq i8* %call, %P + ret i1 %cmp +; CHECK: @test5 +; CHECK: [[LEN:%[a-z]+]] = call {{i[0-9]+}} @strlen(i8* %Q) +; CHECK: [[NCMP:%[a-z]+]] = call {{i[0-9]+}} @strncmp(i8* %P, i8* %Q, {{i[0-9]+}} [[LEN]]) +; CHECK: icmp eq {{i[0-9]+}} [[NCMP]], 0 +; CHECK: ret i1 +} diff --git a/test/Transforms/StripSymbols/2010-06-30-StripDebug.ll b/test/Transforms/StripSymbols/2010-06-30-StripDebug.ll new file mode 100644 index 0000000..f5899d2 --- /dev/null +++ b/test/Transforms/StripSymbols/2010-06-30-StripDebug.ll @@ -0,0 +1,28 @@ +; RUN: opt -strip-debug < %s | llvm-dis | grep -v llvm.dbg + +@x = common global i32 0 ; <i32*> [#uses=0] + +define void @foo() nounwind readnone optsize ssp { +entry: + tail call void @llvm.dbg.value(metadata !9, i64 0, metadata !5), !dbg !10 + ret void, !dbg !11 +} + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone + +!llvm.dbg.sp = !{!0} +!llvm.dbg.lv.foo = !{!5} +!llvm.dbg.gv = !{!8} + +!0 = metadata !{i32 524334, i32 0, metadata !1, metadata !"foo", metadata !"foo", metadata !"foo", metadata !1, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, void ()* @foo} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 524329, metadata !"b.c", metadata !"/tmp", metadata !2} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 524305, i32 0, i32 1, metadata !"b.c", metadata !"/tmp", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 524309, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] +!4 = metadata !{null} +!5 = metadata !{i32 524544, metadata !6, metadata !"y", metadata !1, i32 3, metadata !7} ; [ DW_TAG_auto_variable ] +!6 = metadata !{i32 524299, metadata !0, i32 2, i32 0} ; [ DW_TAG_lexical_block ] +!7 = metadata !{i32 524324, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!8 = metadata !{i32 524340, i32 0, metadata !1, metadata !"x", metadata !"x", metadata !"", metadata !1, i32 1, metadata !7, i1 false, i1 true, i32* @x} ; [ DW_TAG_variable ] +!9 = metadata !{i32 0} +!10 = metadata !{i32 3, i32 0, metadata !6, null} +!11 = metadata !{i32 4, i32 0, metadata !6, null} diff --git a/test/Transforms/StripSymbols/2010-07-01-DeadDbgInfo.ll b/test/Transforms/StripSymbols/2010-07-01-DeadDbgInfo.ll new file mode 100644 index 0000000..1df0351 --- /dev/null +++ b/test/Transforms/StripSymbols/2010-07-01-DeadDbgInfo.ll @@ -0,0 +1,47 @@ +; RUN: opt -strip-dead-debug-info < %s | llvm-dis -o %t.ll +; RUN: grep -v bar %t.ll +; RUN: grep -v abcd %t.ll + +@xyz = global i32 2 ; <i32*> [#uses=1] + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone + +define i32 @fn() nounwind readnone ssp { +entry: + ret i32 0, !dbg !17 +} + +define i32 @foo(i32 %i) nounwind readonly ssp { +entry: + tail call void @llvm.dbg.value(metadata !{i32 %i}, i64 0, metadata !14), !dbg !19 + %.0 = load i32* @xyz, align 4 ; <i32> [#uses=1] + ret i32 %.0, !dbg !20 +} + +!llvm.dbg.sp = !{!0, !5, !9} +!llvm.dbg.lv.bar = !{!12} +!llvm.dbg.lv.foo = !{!14} +!llvm.dbg.gv = !{!15, !16} + +!0 = metadata !{i32 524334, i32 0, metadata !1, metadata !"bar", metadata !"bar", metadata !"", metadata !1, i32 5, metadata !3, i1 true, i1 true, i32 0, i32 0, null, i1 false, i1 true, null} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 524329, metadata !"g.c", metadata !"/tmp/", metadata !2} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 524305, i32 0, i32 1, metadata !"g.c", metadata !"/tmp/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 524309, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] +!4 = metadata !{null} +!5 = metadata !{i32 524334, i32 0, metadata !1, metadata !"fn", metadata !"fn", metadata !"fn", metadata !1, i32 6, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, i32 ()* @fn} ; [ DW_TAG_subprogram ] +!6 = metadata !{i32 524309, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, null} ; [ DW_TAG_subroutine_type ] +!7 = metadata !{metadata !8} +!8 = metadata !{i32 524324, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!9 = metadata !{i32 524334, i32 0, metadata !1, metadata !"foo", metadata !"foo", metadata !"foo", metadata !1, i32 7, metadata !10, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, i32 (i32)* @foo} ; [ DW_TAG_subprogram ] +!10 = metadata !{i32 524309, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !11, i32 0, null} ; [ DW_TAG_subroutine_type ] +!11 = metadata !{metadata !8, metadata !8} +!12 = metadata !{i32 524544, metadata !13, metadata !"bb", metadata !1, i32 5, metadata !8} ; [ DW_TAG_auto_variable ] +!13 = metadata !{i32 524299, metadata !0, i32 5, i32 0} ; [ DW_TAG_lexical_block ] +!14 = metadata !{i32 524545, metadata !9, metadata !"i", metadata !1, i32 7, metadata !8} ; [ DW_TAG_arg_variable ] +!15 = metadata !{i32 524340, i32 0, metadata !1, metadata !"abcd", metadata !"abcd", metadata !"", metadata !1, i32 2, metadata !8, i1 true, i1 true, null} ; [ DW_TAG_variable ] +!16 = metadata !{i32 524340, i32 0, metadata !1, metadata !"xyz", metadata !"xyz", metadata !"", metadata !1, i32 3, metadata !8, i1 false, i1 true, i32* @xyz} ; [ DW_TAG_variable ] +!17 = metadata !{i32 6, i32 0, metadata !18, null} +!18 = metadata !{i32 524299, metadata !5, i32 6, i32 0} ; [ DW_TAG_lexical_block ] +!19 = metadata !{i32 7, i32 0, metadata !9, null} +!20 = metadata !{i32 10, i32 0, metadata !21, null} +!21 = metadata !{i32 524299, metadata !9, i32 7, i32 0} ; [ DW_TAG_lexical_block ] diff --git a/test/Transforms/TailCallElim/2010-06-26-MultipleReturnValues.ll b/test/Transforms/TailCallElim/2010-06-26-MultipleReturnValues.ll new file mode 100644 index 0000000..0626592 --- /dev/null +++ b/test/Transforms/TailCallElim/2010-06-26-MultipleReturnValues.ll @@ -0,0 +1,20 @@ +; RUN: opt < %s -tailcallelim -S | FileCheck %s +; PR7328 +; PR7506 +define i32 @foo(i32 %x) { +; CHECK: define i32 @foo +; CHECK: %accumulator.tr = phi i32 [ 1, %entry ], [ 0, %body ] +entry: + %cond = icmp ugt i32 %x, 0 ; <i1> [#uses=1] + br i1 %cond, label %return, label %body + +body: ; preds = %entry + %y = add i32 %x, 1 ; <i32> [#uses=1] + %tmp = call i32 @foo(i32 %y) ; <i32> [#uses=0] +; CHECK-NOT: call + ret i32 0 +; CHECK: ret i32 %accumulator.tr + +return: ; preds = %entry + ret i32 1 +} diff --git a/test/lit.cfg b/test/lit.cfg index fd3120a..5e7e0e4 100644 --- a/test/lit.cfg +++ b/test/lit.cfg @@ -48,6 +48,13 @@ if llvm_obj_root is not None: # Propogate 'HOME' through the environment. config.environment['HOME'] = os.environ['HOME'] +# Propogate LLVM_SRC_ROOT into the environment. +config.environment['LLVM_SRC_ROOT'] = getattr(config, 'llvm_src_root', '') + +# Propogate PYTHON_EXEUTABLE into the environment +config.environment['PYTHON_EXECUTABLE'] = getattr(config, 'python_executable', + '') + ### import os diff --git a/test/lit.site.cfg.in b/test/lit.site.cfg.in index 88699e3..79b2c60 100644 --- a/test/lit.site.cfg.in +++ b/test/lit.site.cfg.in @@ -4,6 +4,7 @@ config.llvm_src_root = "@LLVM_SOURCE_DIR@" config.llvm_obj_root = "@LLVM_BINARY_DIR@" config.llvm_tools_dir = "@LLVM_TOOLS_DIR@" config.llvmgcc_dir = "@LLVMGCCDIR@" +config.python_executable = "@PYTHON_EXECUTABLE@" # Let the main config do the real work. lit.load_config(config, "@LLVM_SOURCE_DIR@/test/lit.cfg") |
