summaryrefslogtreecommitdiffstats
path: root/test/Transforms/InstCombine
diff options
context:
space:
mode:
Diffstat (limited to 'test/Transforms/InstCombine')
-rw-r--r--test/Transforms/InstCombine/2011-05-02-VectorBoolean.ll15
-rw-r--r--test/Transforms/InstCombine/2011-05-13-InBoundsGEP.ll21
-rw-r--r--test/Transforms/InstCombine/2011-05-28-swapmulsub.ll57
-rw-r--r--test/Transforms/InstCombine/call.ll8
-rw-r--r--test/Transforms/InstCombine/div.ll14
-rw-r--r--test/Transforms/InstCombine/exact.ll16
-rw-r--r--test/Transforms/InstCombine/icmp.ll11
-rw-r--r--test/Transforms/InstCombine/intrinsics.ll8
-rw-r--r--test/Transforms/InstCombine/or.ll4
-rw-r--r--test/Transforms/InstCombine/select.ll50
-rw-r--r--test/Transforms/InstCombine/shift.ll21
-rw-r--r--test/Transforms/InstCombine/vec_demanded_elts.ll16
-rw-r--r--test/Transforms/InstCombine/x86-crc32-demanded.ll17
13 files changed, 248 insertions, 10 deletions
diff --git a/test/Transforms/InstCombine/2011-05-02-VectorBoolean.ll b/test/Transforms/InstCombine/2011-05-02-VectorBoolean.ll
new file mode 100644
index 0000000..02b64e3
--- /dev/null
+++ b/test/Transforms/InstCombine/2011-05-02-VectorBoolean.ll
@@ -0,0 +1,15 @@
+; RUN: opt < %s -instcombine
+; PR9579
+
+define <2 x i16> @entry(<2 x i16> %a) nounwind {
+entry:
+ %a.addr = alloca <2 x i16>, align 4
+ %.compoundliteral = alloca <2 x i16>, align 4
+ store <2 x i16> %a, <2 x i16>* %a.addr, align 4
+ %tmp = load <2 x i16>* %a.addr, align 4
+ store <2 x i16> zeroinitializer, <2 x i16>* %.compoundliteral
+ %tmp1 = load <2 x i16>* %.compoundliteral
+ %cmp = icmp uge <2 x i16> %tmp, %tmp1
+ %sext = sext <2 x i1> %cmp to <2 x i16>
+ ret <2 x i16> %sext
+}
diff --git a/test/Transforms/InstCombine/2011-05-13-InBoundsGEP.ll b/test/Transforms/InstCombine/2011-05-13-InBoundsGEP.ll
new file mode 100644
index 0000000..fba7239
--- /dev/null
+++ b/test/Transforms/InstCombine/2011-05-13-InBoundsGEP.ll
@@ -0,0 +1,21 @@
+; RUN: opt < %s -S -instcombine | FileCheck %s
+; rdar://problem/9267970
+; ideally this test will run on a 32-bit host
+; must not discard GEPs that might overflow at runtime (aren't inbounds)
+
+define i32 @main(i32 %argc) {
+entry:
+ %tmp1 = add i32 %argc, -2
+ %tmp2 = add i32 %argc, 1879048192
+ %p = alloca i8
+; CHECK: getelementptr
+ %p1 = getelementptr i8* %p, i32 %tmp1
+; CHECK: getelementptr
+ %p2 = getelementptr i8* %p, i32 %tmp2
+ %cmp = icmp ult i8* %p1, %p2
+ br i1 %cmp, label %bbtrue, label %bbfalse
+bbtrue: ; preds = %entry
+ ret i32 -1
+bbfalse: ; preds = %entry
+ ret i32 0
+}
diff --git a/test/Transforms/InstCombine/2011-05-28-swapmulsub.ll b/test/Transforms/InstCombine/2011-05-28-swapmulsub.ll
new file mode 100644
index 0000000..b096d1f
--- /dev/null
+++ b/test/Transforms/InstCombine/2011-05-28-swapmulsub.ll
@@ -0,0 +1,57 @@
+; ModuleID = 'test1.c'
+; RUN: opt -S -instcombine < %s | FileCheck %s
+target triple = "x86_64-apple-macosx10.6.6"
+
+define zeroext i16 @foo1(i32 %on_off) nounwind uwtable ssp {
+entry:
+ %on_off.addr = alloca i32, align 4
+ %a = alloca i32, align 4
+ store i32 %on_off, i32* %on_off.addr, align 4
+ %tmp = load i32* %on_off.addr, align 4
+ %sub = sub i32 1, %tmp
+; CHECK-NOT: mul i32
+ %mul = mul i32 %sub, -2
+; CHECK: shl
+; CHECK-NEXT: add
+ store i32 %mul, i32* %a, align 4
+ %tmp1 = load i32* %a, align 4
+ %conv = trunc i32 %tmp1 to i16
+ ret i16 %conv
+}
+
+define zeroext i16 @foo2(i32 %on_off, i32 %q) nounwind uwtable ssp {
+entry:
+ %on_off.addr = alloca i32, align 4
+ %q.addr = alloca i32, align 4
+ %a = alloca i32, align 4
+ store i32 %on_off, i32* %on_off.addr, align 4
+ store i32 %q, i32* %q.addr, align 4
+ %tmp = load i32* %q.addr, align 4
+ %tmp1 = load i32* %on_off.addr, align 4
+ %sub = sub i32 %tmp, %tmp1
+; CHECK-NOT: mul i32
+ %mul = mul i32 %sub, -4
+; CHECK: sub i32
+; CHECK-NEXT: shl
+ store i32 %mul, i32* %a, align 4
+ %tmp2 = load i32* %a, align 4
+ %conv = trunc i32 %tmp2 to i16
+ ret i16 %conv
+}
+
+define zeroext i16 @foo3(i32 %on_off) nounwind uwtable ssp {
+entry:
+ %on_off.addr = alloca i32, align 4
+ %a = alloca i32, align 4
+ store i32 %on_off, i32* %on_off.addr, align 4
+ %tmp = load i32* %on_off.addr, align 4
+ %sub = sub i32 7, %tmp
+; CHECK-NOT: mul i32
+ %mul = mul i32 %sub, -4
+; CHECK: shl
+; CHECK-NEXT: add
+ store i32 %mul, i32* %a, align 4
+ %tmp1 = load i32* %a, align 4
+ %conv = trunc i32 %tmp1 to i16
+ ret i16 %conv
+}
diff --git a/test/Transforms/InstCombine/call.ll b/test/Transforms/InstCombine/call.ll
index 2ef8dc0..d084873 100644
--- a/test/Transforms/InstCombine/call.ll
+++ b/test/Transforms/InstCombine/call.ll
@@ -53,8 +53,8 @@ define i8 @test4a() {
define i32 @test4() {
%X = call i32 bitcast (i8 ()* @test4a to i32 ()*)( ) ; <i32> [#uses=1]
ret i32 %X
-; CHECK: %X1 = call i8 @test4a()
-; CHECK: %tmp = zext i8 %X1 to i32
+; CHECK: %X = call i8 @test4a()
+; CHECK: %tmp = zext i8 %X to i32
; CHECK: ret i32 %tmp
}
@@ -77,8 +77,8 @@ declare i32 @test6a(i32)
define i32 @test6() {
%X = call i32 bitcast (i32 (i32)* @test6a to i32 ()*)( )
ret i32 %X
-; CHECK: %X1 = call i32 @test6a(i32 0)
-; CHECK: ret i32 %X1
+; CHECK: %X = call i32 @test6a(i32 0)
+; CHECK: ret i32 %X
}
diff --git a/test/Transforms/InstCombine/div.ll b/test/Transforms/InstCombine/div.ll
index 2e24f19..8a0897b 100644
--- a/test/Transforms/InstCombine/div.ll
+++ b/test/Transforms/InstCombine/div.ll
@@ -118,3 +118,17 @@ define i32 @test14(i8 %x) nounwind {
; CHECK: @test14
; CHECK-NEXT: ret i32 0
}
+
+; PR9814
+define i32 @test15(i32 %a, i32 %b) nounwind {
+ %shl = shl i32 1, %b
+ %div = lshr i32 %shl, 2
+ %div2 = udiv i32 %a, %div
+ ret i32 %div2
+; CHECK: @test15
+; CHECK-NEXT: add i32 %b, -2
+; CHECK-NEXT: lshr i32 %a,
+; CHECK-NEXT: ret i32
+}
+
+
diff --git a/test/Transforms/InstCombine/exact.ll b/test/Transforms/InstCombine/exact.ll
index 58f8b5d..14741e3 100644
--- a/test/Transforms/InstCombine/exact.ll
+++ b/test/Transforms/InstCombine/exact.ll
@@ -96,6 +96,22 @@ define i1 @ashr_icmp2(i64 %X) nounwind {
ret i1 %Z
}
+; PR9998
+; Make sure we don't transform the ashr here into an sdiv
+; CHECK: @pr9998
+; CHECK: = and i32 %V, 1
+; CHECK: %Z = icmp ne
+; CHECK: ret i1 %Z
+define i1 @pr9998(i32 %V) nounwind {
+entry:
+ %W = shl i32 %V, 31
+ %X = ashr exact i32 %W, 31
+ %Y = sext i32 %X to i64
+ %Z = icmp ugt i64 %Y, 7297771788697658747
+ ret i1 %Z
+}
+
+
; CHECK: @udiv_icmp1
; CHECK: icmp ne i64 %X, 0
define i1 @udiv_icmp1(i64 %X) nounwind {
diff --git a/test/Transforms/InstCombine/icmp.ll b/test/Transforms/InstCombine/icmp.ll
index 099540a..1237ade 100644
--- a/test/Transforms/InstCombine/icmp.ll
+++ b/test/Transforms/InstCombine/icmp.ll
@@ -510,3 +510,14 @@ define i1 @test52(i32 %x1) nounwind {
ret i1 %A
}
+; PR9838
+; CHECK: @test53
+; CHECK-NEXT: ashr exact
+; CHECK-NEXT: ashr
+; CHECK-NEXT: icmp
+define i1 @test53(i32 %a, i32 %b) nounwind {
+ %x = ashr exact i32 %a, 30
+ %y = ashr i32 %b, 30
+ %z = icmp eq i32 %x, %y
+ ret i1 %z
+}
diff --git a/test/Transforms/InstCombine/intrinsics.ll b/test/Transforms/InstCombine/intrinsics.ll
index 332cd46..107f313 100644
--- a/test/Transforms/InstCombine/intrinsics.ll
+++ b/test/Transforms/InstCombine/intrinsics.ll
@@ -30,9 +30,9 @@ define i8 @uaddtest2(i8 %A, i8 %B, i1* %overflowPtr) {
; CHECK: @uaddtest2
; CHECK-NEXT: %and.A = and i8 %A, 127
; CHECK-NEXT: %and.B = and i8 %B, 127
-; CHECK-NEXT: %1 = add nuw i8 %and.A, %and.B
+; CHECK-NEXT: %x = add nuw i8 %and.A, %and.B
; CHECK-NEXT: store i1 false, i1* %overflowPtr
-; CHECK-NEXT: ret i8 %1
+; CHECK-NEXT: ret i8 %x
}
define i8 @uaddtest3(i8 %A, i8 %B, i1* %overflowPtr) {
@@ -46,9 +46,9 @@ define i8 @uaddtest3(i8 %A, i8 %B, i1* %overflowPtr) {
; CHECK: @uaddtest3
; CHECK-NEXT: %or.A = or i8 %A, -128
; CHECK-NEXT: %or.B = or i8 %B, -128
-; CHECK-NEXT: %1 = add i8 %or.A, %or.B
+; CHECK-NEXT: %x = add i8 %or.A, %or.B
; CHECK-NEXT: store i1 true, i1* %overflowPtr
-; CHECK-NEXT: ret i8 %1
+; CHECK-NEXT: ret i8 %x
}
define i8 @uaddtest4(i8 %A, i1* %overflowPtr) {
diff --git a/test/Transforms/InstCombine/or.ll b/test/Transforms/InstCombine/or.ll
index 94a5732..c0bb28d 100644
--- a/test/Transforms/InstCombine/or.ll
+++ b/test/Transforms/InstCombine/or.ll
@@ -332,8 +332,8 @@ define i64 @test31(i64 %A) nounwind readnone ssp noredzone {
%F = or i64 %D, %E
ret i64 %F
; CHECK: @test31
-; CHECK-NEXT: %E1 = and i64 %A, 4294908984
-; CHECK-NEXT: %F = or i64 %E1, 32962
+; CHECK-NEXT: %E = and i64 %A, 4294908984
+; CHECK-NEXT: %F = or i64 %E, 32962
; CHECK-NEXT: ret i64 %F
}
diff --git a/test/Transforms/InstCombine/select.ll b/test/Transforms/InstCombine/select.ll
index 3925907..4ca9bd2 100644
--- a/test/Transforms/InstCombine/select.ll
+++ b/test/Transforms/InstCombine/select.ll
@@ -749,3 +749,53 @@ define i1 @test55(i1 %X, i32 %Y, i32 %Z) {
; CHECK: icmp eq
; CHECK: ret i1
}
+
+define i32 @test56(i16 %x) nounwind {
+ %tobool = icmp eq i16 %x, 0
+ %conv = zext i16 %x to i32
+ %cond = select i1 %tobool, i32 0, i32 %conv
+ ret i32 %cond
+; CHECK: @test56
+; CHECK-NEXT: zext
+; CHECK-NEXT: ret
+}
+
+define i32 @test57(i32 %x, i32 %y) nounwind {
+ %and = and i32 %x, %y
+ %tobool = icmp eq i32 %x, 0
+ %.and = select i1 %tobool, i32 0, i32 %and
+ ret i32 %.and
+; CHECK: @test57
+; CHECK-NEXT: and i32 %x, %y
+; CHECK-NEXT: ret
+}
+
+define i32 @test58(i16 %x) nounwind {
+ %tobool = icmp ne i16 %x, 1
+ %conv = zext i16 %x to i32
+ %cond = select i1 %tobool, i32 %conv, i32 1
+ ret i32 %cond
+; CHECK: @test58
+; CHECK-NEXT: zext
+; CHECK-NEXT: ret
+}
+
+define i32 @test59(i32 %x, i32 %y) nounwind {
+ %and = and i32 %x, %y
+ %tobool = icmp ne i32 %x, %y
+ %.and = select i1 %tobool, i32 %and, i32 %y
+ ret i32 %.and
+; CHECK: @test59
+; CHECK-NEXT: and i32 %x, %y
+; CHECK-NEXT: ret
+}
+
+define i1 @test60(i32 %x, i1* %y) nounwind {
+ %cmp = icmp eq i32 %x, 0
+ %load = load i1* %y, align 1
+ %cmp1 = icmp slt i32 %x, 1
+ %sel = select i1 %cmp, i1 %load, i1 %cmp1
+ ret i1 %sel
+; CHECK: @test60
+; CHECK: select
+}
diff --git a/test/Transforms/InstCombine/shift.ll b/test/Transforms/InstCombine/shift.ll
index bded68a..d9ac9cb 100644
--- a/test/Transforms/InstCombine/shift.ll
+++ b/test/Transforms/InstCombine/shift.ll
@@ -506,3 +506,24 @@ define i32 @test41(i32 %a, i32 %b) nounwind {
; CHECK-NEXT: shl i32 8, %b
; CHECK-NEXT: ret i32
}
+
+define i32 @test42(i32 %a, i32 %b) nounwind {
+ %div = lshr i32 4096, %b ; must be exact otherwise we'd divide by zero
+ %div2 = udiv i32 %a, %div
+ ret i32 %div2
+; CHECK: @test42
+; CHECK-NEXT: lshr exact i32 4096, %b
+}
+
+define i32 @test43(i32 %a, i32 %b) nounwind {
+ %div = shl i32 4096, %b ; must be exact otherwise we'd divide by zero
+ %div2 = udiv i32 %a, %div
+ ret i32 %div2
+; CHECK: @test43
+; CHECK-NEXT: add i32 %b, 12
+; CHECK-NEXT: lshr
+; CHECK-NEXT: ret
+}
+
+
+
diff --git a/test/Transforms/InstCombine/vec_demanded_elts.ll b/test/Transforms/InstCombine/vec_demanded_elts.ll
index 9f308aa..e0188fe 100644
--- a/test/Transforms/InstCombine/vec_demanded_elts.ll
+++ b/test/Transforms/InstCombine/vec_demanded_elts.ll
@@ -136,3 +136,19 @@ declare i32 @llvm.x86.sse2.cvtsd2si(<2 x double>)
declare i64 @llvm.x86.sse2.cvtsd2si64(<2 x double>)
declare i32 @llvm.x86.sse2.cvttsd2si(<2 x double>)
declare i64 @llvm.x86.sse2.cvttsd2si64(<2 x double>)
+
+; <rdar://problem/6945110>
+define <4 x i32> @kernel3_vertical(<4 x i16> * %src, <8 x i16> * %foo) nounwind {
+entry:
+ %tmp = load <4 x i16>* %src
+ %tmp1 = load <8 x i16>* %foo
+; CHECK: %tmp2 = shufflevector
+ %tmp2 = shufflevector <4 x i16> %tmp, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
+; pmovzxwd ignores the upper 64-bits of its input; -instcombine should remove this shuffle:
+; CHECK-NOT: shufflevector
+ %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7>
+; CHECK-NEXT: pmovzxwd
+ %0 = call <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16> %tmp3)
+ ret <4 x i32> %0
+}
+declare <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16>) nounwind readnone
diff --git a/test/Transforms/InstCombine/x86-crc32-demanded.ll b/test/Transforms/InstCombine/x86-crc32-demanded.ll
new file mode 100644
index 0000000..878b97d
--- /dev/null
+++ b/test/Transforms/InstCombine/x86-crc32-demanded.ll
@@ -0,0 +1,17 @@
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+; crc32 with 64-bit destination zeros high 32-bit.
+; rdar://9467055
+
+define i64 @test() nounwind {
+entry:
+; CHECK: test
+; CHECK: tail call i64 @llvm.x86.sse42.crc32.64.64
+; CHECK-NOT: and
+; CHECK: ret
+ %0 = tail call i64 @llvm.x86.sse42.crc32.64.64(i64 0, i64 4) nounwind
+ %1 = and i64 %0, 4294967295
+ ret i64 %1
+}
+
+declare i64 @llvm.x86.sse42.crc32.64.64(i64, i64) nounwind readnone
OpenPOWER on IntegriCloud