7 files changed, 139 insertions, 2 deletions
diff --git a/test/TableGen/DefmInsideMultiClass.td b/test/TableGen/DefmInsideMultiClass.td
new file mode 100644
index 0000000..68cc12d
--- /dev/null
+++ b/test/TableGen/DefmInsideMultiClass.td
@@ -0,0 +1,25 @@
+// RUN: tblgen %s | grep ADDPSrr | count 1
+// XFAIL: vg_leak
+
+class Instruction<bits<4> opc, string Name> {
+  bits<4> opcode = opc;
+  string name = Name;
+}
+
+multiclass basic_r<bits<4> opc> {
+  def rr : Instruction<opc, "rr">;
+  def rm : Instruction<opc, "rm">;
+}
+
+multiclass basic_s<bits<4> opc> {
+  defm SS : basic_r<opc>;
+  defm SD : basic_r<opc>;
+}
+
+multiclass basic_p<bits<4> opc> {
+  defm PS : basic_r<opc>;
+  defm PD : basic_r<opc>;
+}
+
+defm ADD : basic_s<0xf>, basic_p<0xf>;
+defm SUB : basic_s<0xe>, basic_p<0xe>;
diff --git a/test/TableGen/LetInsideMultiClasses.td b/test/TableGen/LetInsideMultiClasses.td
new file mode 100644
index 0000000..9238bf4
--- /dev/null
+++ b/test/TableGen/LetInsideMultiClasses.td
@@ -0,0 +1,29 @@
+// RUN: tblgen %s | grep "bit IsDouble = 1;" | count 3
+// XFAIL: vg_leak
+
+class Instruction<bits<4> opc, string Name> {
+  bits<4> opcode = opc;
+  string name = Name;
+  bit IsDouble = 0;
+}
+
+multiclass basic_r<bits<4> opc> {
+  let name = "newname" in {
+    def rr : Instruction<opc, "rr">;
+    def rm : Instruction<opc, "rm">;
+  }
+
+  let name = "othername" in
+    def rx : Instruction<opc, "rx">;
+}
+
+multiclass basic_ss<bits<4> opc> {
+  let IsDouble = 0 in
+    defm SS : basic_r<opc>;
+
+  let IsDouble = 1 in
+    defm SD : basic_r<opc>;
+}
+
+defm ADD : basic_ss<0xf>;
+
diff --git a/test/TableGen/TargetInstrInfo.td b/test/TableGen/TargetInstrInfo.td
index 2871eb8..146ef6f 100644
--- a/test/TableGen/TargetInstrInfo.td
+++ b/test/TableGen/TargetInstrInfo.td
@@ -83,8 +83,7 @@ class Inst<dag opnds, string asmstr, bits<8> opcode,
 //     the pattern.
 //  6. Address expressions should become first-class entities.
 
-// Simple copy instruction.  isMoveInstr could easily be inferred from this,
-// as could TargetRegisterInfo::copyRegToReg.
+// Simple copy instruction.
 def MOV8rr : Inst<(ops R8:$dst, R8:$src),
                   "mov $dst, $src", 0x88, MRMDestReg,
                   [(set R8:$dst, R8:$src)]>;
diff --git a/test/TableGen/defmclass.td b/test/TableGen/defmclass.td
new file mode 100644
index 0000000..55482da
--- /dev/null
+++ b/test/TableGen/defmclass.td
@@ -0,0 +1,38 @@
+// RUN: tblgen %s | FileCheck %s
+// XFAIL: vg_leak
+
+class XD { bits<4> Prefix = 11; }
+// CHECK: Prefix = { 1, 1, 0, 0 };
+class XS { bits<4> Prefix = 12; }
+class VEX { bit hasVEX_4VPrefix = 1; }
+
+def xd : XD;
+
+class BaseI {
+  bits<4> Prefix = 0;
+  bit hasVEX_4VPrefix = 0;
+}
+
+class I<bits<4> op> : BaseI {
+  bits<4> opcode = op;
+  int val = !if(!eq(Prefix, xd.Prefix), 7, 21);
+  int check = !if(hasVEX_4VPrefix, 0, 10);
+}
+
+multiclass R {
+  def rr : I<4>;
+}
+
+multiclass M {
+  def rm : I<2>;
+}
+
+multiclass Y {
+  defm SS : R, M, XD;
+// CHECK: Prefix = { 1, 1, 0, 0 };
+// CHECK: Prefix = { 1, 1, 0, 0 };
+  defm SD : R, M, XS;
+}
+
+// CHECK: int check = 0;
+defm Instr : Y, VEX;
diff --git a/test/TableGen/eqbit.td b/test/TableGen/eqbit.td
new file mode 100644
index 0000000..3953252c
--- /dev/null
+++ b/test/TableGen/eqbit.td
@@ -0,0 +1,11 @@
+// RUN: tblgen %s | FileCheck %s
+// XFAIL: vg_leak
+// CHECK: a = 6
+// CHECK: a = 5
+
+class A<bit b = 1> {
+  int a = !if(!eq(b, 1), 5, 6);
+}
+
+def X : A<0>;
+def Y : A;
diff --git a/test/TableGen/ifbit.td b/test/TableGen/ifbit.td
new file mode 100644
index 0000000..3b0349e
--- /dev/null
+++ b/test/TableGen/ifbit.td
@@ -0,0 +1,11 @@
+// RUN: tblgen %s | FileCheck %s
+// XFAIL: vg_leak
+// CHECK: a = 6
+// CHECK: a = 5
+
+class A<bit b = 1> {
+  int a = !if(b, 5, 6);
+}
+
+def X : A<0>;
+def Y : A;
diff --git a/test/TableGen/usevalname.td b/test/TableGen/usevalname.td
new file mode 100644
index 0000000..1b31c8f
--- /dev/null
+++ b/test/TableGen/usevalname.td
@@ -0,0 +1,24 @@
+// RUN: tblgen %s | FileCheck %s
+// XFAIL: vg_leak
+
+class Instr<list<dag> pat> {
+  list<dag> Pattern = pat;
+}
+
+class Reg {
+  int a = 3;
+}
+
+def VR128 : Reg;
+def mem_frag;
+def set;
+def addr;
+def shufp : Reg;
+
+multiclass shuffle<Reg RC> {
+  def rri : Instr<[(set RC:$dst, (shufp:$src3
+                                       RC:$src1, RC:$src2))]>;
+}
+
+// CHECK: shufp:src3
+defm ADD : shuffle<VR128>;