diff options
Diffstat (limited to 'test/MC')
152 files changed, 7477 insertions, 1004 deletions
diff --git a/test/MC/ARM/arm-aliases.s b/test/MC/ARM/arm-aliases.s new file mode 100644 index 0000000..d4ea0df --- /dev/null +++ b/test/MC/ARM/arm-aliases.s @@ -0,0 +1,17 @@ +@ RUN: llvm-mc -triple=armv7-apple-darwin -show-encoding < %s | FileCheck %s + .syntax unified + +@ Shift-by-zero should canonicalize to no shift at all (lsl #0 encoding) + add r1, r2, r3, lsl #0 + sub r1, r2, r3, ror #0 + eor r1, r2, r3, lsr #0 + orr r1, r2, r3, asr #0 + and r1, r2, r3, ror #0 + bic r1, r2, r3, lsl #0 + +@ CHECK: add r1, r2, r3 @ encoding: [0x03,0x10,0x82,0xe0] +@ CHECK: sub r1, r2, r3 @ encoding: [0x03,0x10,0x42,0xe0] +@ CHECK: eor r1, r2, r3 @ encoding: [0x03,0x10,0x22,0xe0] +@ CHECK: orr r1, r2, r3 @ encoding: [0x03,0x10,0x82,0xe1] +@ CHECK: and r1, r2, r3 @ encoding: [0x03,0x10,0x02,0xe0] +@ CHECK: bic r1, r2, r3 @ encoding: [0x03,0x10,0xc2,0xe1] diff --git a/test/MC/ARM/arm-it-block.s b/test/MC/ARM/arm-it-block.s new file mode 100644 index 0000000..e5e5491 --- /dev/null +++ b/test/MC/ARM/arm-it-block.s @@ -0,0 +1,11 @@ +@ RUN: llvm-mc -triple=armv7-apple-darwin -show-encoding < %s | FileCheck %s + .syntax unified + .globl _func + +_func: +@ CHECK: _func: + it eq + moveq r2, r3 +@ 'it' is parsed but not encoded. +@ CHECK-NOT: it +@ CHECK: moveq r2, r3 @ encoding: [0x03,0x20,0xa0,0x01] diff --git a/test/MC/ARM/arm-memory-instructions.s b/test/MC/ARM/arm-memory-instructions.s index 783ac28..d8d9130 100644 --- a/test/MC/ARM/arm-memory-instructions.s +++ b/test/MC/ARM/arm-memory-instructions.s @@ -130,8 +130,13 @@ _func: @------------------------------------------------------------------------------ -@ FIXME: LDRD (label) +@ LDRD (label) @------------------------------------------------------------------------------ + ldrd r2, r3, Lbaz +Lbaz: .quad 0 + +@ CHECK: ldrd r2, r3, Lbaz @ encoding: [0xd0'A',0x20'A',0x4f'A',0xe1'A'] + @------------------------------------------------------------------------------ @ LDRD (register) diff --git a/test/MC/ARM/arm_fixups.s b/test/MC/ARM/arm_fixups.s index aba0cd8..74dfb99 100644 --- a/test/MC/ARM/arm_fixups.s +++ b/test/MC/ARM/arm_fixups.s @@ -3,7 +3,7 @@ bl _printf @ CHECK: bl _printf @ encoding: [A,A,A,0xeb] -@ CHECK: @ fixup A - offset: 0, value: _printf, kind: fixup_arm_uncondbranch +@ CHECK: @ fixup A - offset: 0, value: _printf, kind: fixup_arm_uncondbl mov r9, :lower16:(_foo) movw r9, :lower16:(_foo) diff --git a/test/MC/ARM/basic-arm-instructions.s b/test/MC/ARM/basic-arm-instructions.s index 55d9f02..4788ac7 100644 --- a/test/MC/ARM/basic-arm-instructions.s +++ b/test/MC/ARM/basic-arm-instructions.s @@ -133,9 +133,9 @@ Lforward: adr r2, #-3 @ CHECK: Lback: -@ CHECK: adr r2, Lback @ encoding: [0bAAAAAAA0,0x20'A',0x0f'A',0b1110001A] +@ CHECK: adr r2, Lback @ encoding: [A,0x20'A',0x0f'A',0xe2'A'] @ CHECK: @ fixup A - offset: 0, value: Lback, kind: fixup_arm_adr_pcrel_12 -@ CHECK: adr r3, Lforward @ encoding: [0bAAAAAAA0,0x30'A',0x0f'A',0b1110001A] +@ CHECK: adr r3, Lforward @ encoding: [A,0x30'A',0x0f'A',0xe2'A'] @ CHECK: @ fixup A - offset: 0, value: Lforward, kind: fixup_arm_adr_pcrel_12 @ CHECK: Lforward: @ CHECK: adr r2, #3 @ encoding: [0x03,0x20,0x8f,0xe2] @@ -153,6 +153,7 @@ Lforward: add r4, r5, r6, asr #5 add r4, r5, r6, ror #5 add r6, r7, r8, lsl r9 + add r4, r4, r3, asl r9 add r6, r7, r8, lsr r9 add r6, r7, r8, asr r9 add r6, r7, r8, ror r9 @@ -172,6 +173,9 @@ Lforward: add r6, r7, ror r9 add r4, r5, rrx + add r0, #-4 + add r4, r5, #-21 + @ CHECK: add r4, r5, #61440 @ encoding: [0x0f,0x4a,0x85,0xe2] @ CHECK: add r4, r5, r6 @ encoding: [0x06,0x40,0x85,0xe0] @ CHECK: add r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0x85,0xe0] @@ -180,12 +184,12 @@ Lforward: @ CHECK: add r4, r5, r6, asr #5 @ encoding: [0xc6,0x42,0x85,0xe0] @ CHECK: add r4, r5, r6, ror #5 @ encoding: [0xe6,0x42,0x85,0xe0] @ CHECK: add r6, r7, r8, lsl r9 @ encoding: [0x18,0x69,0x87,0xe0] +@ CHECK: add r4, r4, r3, lsl r9 @ encoding: [0x13,0x49,0x84,0xe0] @ CHECK: add r6, r7, r8, lsr r9 @ encoding: [0x38,0x69,0x87,0xe0] @ CHECK: add r6, r7, r8, asr r9 @ encoding: [0x58,0x69,0x87,0xe0] @ CHECK: add r6, r7, r8, ror r9 @ encoding: [0x78,0x69,0x87,0xe0] @ CHECK: add r4, r5, r6, rrx @ encoding: [0x66,0x40,0x85,0xe0] - @ CHECK: add r5, r5, #61440 @ encoding: [0x0f,0x5a,0x85,0xe2] @ CHECK: add r4, r4, r5 @ encoding: [0x05,0x40,0x84,0xe0] @ CHECK: add r4, r4, r5, lsl #5 @ encoding: [0x85,0x42,0x84,0xe0] @@ -199,6 +203,9 @@ Lforward: @ CHECK: add r6, r6, r7, ror r9 @ encoding: [0x77,0x69,0x86,0xe0] @ CHECK: add r4, r4, r5, rrx @ encoding: [0x65,0x40,0x84,0xe0] +@ CHECK: sub r0, r0, #4 @ encoding: [0x04,0x00,0x40,0xe2] +@ CHECK: sub r4, r5, #21 @ encoding: [0x15,0x40,0x45,0xe2] + @------------------------------------------------------------------------------ @ AND @@ -215,6 +222,7 @@ Lforward: and r6, r7, r8, asr r2 and r6, r7, r8, ror r2 and r10, r1, r6, rrx + and r2, r3, #0x7fffffff @ destination register is optional and r1, #0xf @@ -242,6 +250,7 @@ Lforward: @ CHECK: and r6, r7, r8, asr r2 @ encoding: [0x58,0x62,0x07,0xe0] @ CHECK: and r6, r7, r8, ror r2 @ encoding: [0x78,0x62,0x07,0xe0] @ CHECK: and r10, r1, r6, rrx @ encoding: [0x66,0xa0,0x01,0xe0] +@ CHECK: bic r2, r3, #-2147483648 @ encoding: [0x02,0x21,0xc3,0xe3] @ CHECK: and r1, r1, #15 @ encoding: [0x0f,0x10,0x01,0xe2] @ CHECK: and r10, r10, r1 @ encoding: [0x01,0xa0,0x0a,0xe0] @@ -257,8 +266,19 @@ Lforward: @ CHECK: and r10, r10, r1, rrx @ encoding: [0x61,0xa0,0x0a,0xe0] @------------------------------------------------------------------------------ -@ FIXME: ASR +@ ASR @------------------------------------------------------------------------------ + asr r2, r4, #32 + asr r2, r4, #2 + asr r2, r4, #0 + asr r4, #2 + +@ CHECK: asr r2, r4, #32 @ encoding: [0x44,0x20,0xa0,0xe1] +@ CHECK: asr r2, r4, #2 @ encoding: [0x44,0x21,0xa0,0xe1] +@ CHECK: mov r2, r4 @ encoding: [0x04,0x20,0xa0,0xe1] +@ CHECK: asr r4, r4, #2 @ encoding: [0x44,0x41,0xa0,0xe1] + + @------------------------------------------------------------------------------ @ B @------------------------------------------------------------------------------ @@ -362,15 +382,18 @@ Lforward: @------------------------------------------------------------------------------ bl _bar + bleq _bar blx _bar blls #28634268 blx #32424576 blx #16212288 @ CHECK: bl _bar @ encoding: [A,A,A,0xeb] -@ CHECK: @ fixup A - offset: 0, value: _bar, kind: fixup_arm_uncondbranch +@ CHECK: @ fixup A - offset: 0, value: _bar, kind: fixup_arm_uncondbl +@ CHECK: bleq _bar @ encoding: [A,A,A,0x0b] +@ CHECK: @ fixup A - offset: 0, value: _bar, kind: fixup_arm_condbl @ CHECK: blx _bar @ encoding: [A,A,A,0xfa] - @ fixup A - offset: 0, value: _bar, kind: fixup_arm_uncondbranch + @ fixup A - offset: 0, value: _bar, kind: fixup_arm_blx @ CHECK: blls #28634268 @ encoding: [0x27,0x3b,0x6d,0x9b] @ CHECK: blx #32424576 @ encoding: [0xa0,0xb0,0x7b,0xfa] @ CHECK: blx #16212288 @ encoding: [0x50,0xd8,0x3d,0xfa] @@ -473,6 +496,8 @@ Lforward: cmp r7, r8, asr r2 cmp r7, r8, ror r2 cmp r1, r6, rrx + cmp r0, #-2 + cmp lr, #0 @ CHECK: cmp r1, #15 @ encoding: [0x0f,0x00,0x51,0xe3] @ CHECK: cmp r1, r6 @ encoding: [0x06,0x00,0x51,0xe1] @@ -486,6 +511,8 @@ Lforward: @ CHECK: cmp r7, r8, asr r2 @ encoding: [0x58,0x02,0x57,0xe1] @ CHECK: cmp r7, r8, ror r2 @ encoding: [0x78,0x02,0x57,0xe1] @ CHECK: cmp r1, r6, rrx @ encoding: [0x66,0x00,0x51,0xe1] +@ CHECK: cmn r0, #2 @ encoding: [0x02,0x00,0x70,0xe3] +@ CHECK: cmp lr, #0 @ encoding: [0x00,0x00,0x5e,0xe3] @------------------------------------------------------------------------------ @@ -744,6 +771,10 @@ Lforward: ldmda r2!, {r1,r3-r6,sp} ldmdb r2!, {r1,r3-r6,sp} + @ system version + ldm r0, {r0, r2, lr}^ + ldm sp!, {r0-r3, pc}^ + @ CHECK: ldm r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x92,0xe8] @ CHECK: ldm r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x92,0xe8] @ CHECK: ldmib r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x92,0xe9] @@ -755,6 +786,8 @@ Lforward: @ CHECK: ldmib r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xb2,0xe9] @ CHECK: ldmda r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x32,0xe8] @ CHECK: ldmdb r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x32,0xe9] +@ CHECK: ldm r0, {lr, r0, r2} ^ @ encoding: [0x05,0x40,0xd0,0xe8] +@ CHECK: ldm sp!, {pc, r0, r1, r2, r3} ^ @ encoding: [0x0f,0x80,0xfd,0xe8] @------------------------------------------------------------------------------ @@ -780,11 +813,32 @@ Lforward: @ CHECK: ldrhthi r8, [r11], #0 @ encoding: [0xb0,0x80,0xfb,0x80] @------------------------------------------------------------------------------ -@ FIXME: LSL +@ LSL @------------------------------------------------------------------------------ + lsl r2, r4, #31 + lsl r2, r4, #1 + lsl r2, r4, #0 + lsl r4, #1 + +@ CHECK: lsl r2, r4, #31 @ encoding: [0x84,0x2f,0xa0,0xe1] +@ CHECK: lsl r2, r4, #1 @ encoding: [0x84,0x20,0xa0,0xe1] +@ CHECK: mov r2, r4 @ encoding: [0x04,0x20,0xa0,0xe1] +@ CHECK: lsl r4, r4, #1 @ encoding: [0x84,0x40,0xa0,0xe1] + + @------------------------------------------------------------------------------ -@ FIXME: LSR +@ LSR @------------------------------------------------------------------------------ + lsr r2, r4, #32 + lsr r2, r4, #2 + lsr r2, r4, #0 + lsr r4, #2 + +@ CHECK: lsr r2, r4, #32 @ encoding: [0x24,0x20,0xa0,0xe1] +@ CHECK: lsr r2, r4, #2 @ encoding: [0x24,0x21,0xa0,0xe1] +@ CHECK: mov r2, r4 @ encoding: [0x04,0x20,0xa0,0xe1] +@ CHECK: lsr r4, r4, #2 @ encoding: [0x24,0x41,0xa0,0xe1] + @------------------------------------------------------------------------------ @ MCR/MCR2 @@ -855,11 +909,28 @@ Lforward: movs r2, r3 moveq r2, r3 movseq r2, r3 + mov r12, r8, lsl #(2 - 2) + lsl r2, r3, #(2 - 2) + mov r12, r8, lsr #(2 - 2) + lsr r2, r3, #(2 - 2) + mov r12, r8, asr #(2 - 2) + asr r2, r3, #(2 - 2) + mov r12, r8, ror #(2 - 2) + ror r2, r3, #(2 - 2) @ CHECK: mov r2, r3 @ encoding: [0x03,0x20,0xa0,0xe1] @ CHECK: movs r2, r3 @ encoding: [0x03,0x20,0xb0,0xe1] @ CHECK: moveq r2, r3 @ encoding: [0x03,0x20,0xa0,0x01] @ CHECK: movseq r2, r3 @ encoding: [0x03,0x20,0xb0,0x01] +@ CHECK: mov r12, r8 @ encoding: [0x08,0xc0,0xa0,0xe1] +@ CHECK: mov r2, r3 @ encoding: [0x03,0x20,0xa0,0xe1] +@ CHECK: mov r12, r8 @ encoding: [0x08,0xc0,0xa0,0xe1] +@ CHECK: mov r2, r3 @ encoding: [0x03,0x20,0xa0,0xe1] +@ CHECK: mov r12, r8 @ encoding: [0x08,0xc0,0xa0,0xe1] +@ CHECK: mov r2, r3 @ encoding: [0x03,0x20,0xa0,0xe1] +@ CHECK: mov r12, r8 @ encoding: [0x08,0xc0,0xa0,0xe1] +@ CHECK: mov r2, r3 @ encoding: [0x03,0x20,0xa0,0xe1] + @------------------------------------------------------------------------------ @ MOVT @@ -975,6 +1046,7 @@ Lforward: muls r5, r6, r7 mulgt r5, r6, r7 mulsle r5, r6, r7 + mul r11, r5 @ CHECK: mul r5, r6, r7 @ encoding: [0x96,0x07,0x05,0xe0] @ CHECK: muls r5, r6, r7 @ encoding: [0x96,0x07,0x15,0xe0] @@ -1038,6 +1110,14 @@ Lforward: @ CHECK: mvnslt r5, r6, ror r7 @ encoding: [0x76,0x57,0xf0,0xb1] @------------------------------------------------------------------------------ +@ NEG +@------------------------------------------------------------------------------ + neg r5, r8 + +@ CHECK: rsb r5, r8, #0 @ encoding: [0x00,0x50,0x68,0xe2] + + +@------------------------------------------------------------------------------ @ NOP @------------------------------------------------------------------------------ nop @@ -1313,6 +1393,20 @@ Lforward: @------------------------------------------------------------------------------ +@ ROR +@------------------------------------------------------------------------------ + ror r2, r4, #31 + ror r2, r4, #1 + ror r2, r4, #0 + ror r4, #1 + +@ CHECK: ror r2, r4, #31 @ encoding: [0xe4,0x2f,0xa0,0xe1] +@ CHECK: ror r2, r4, #1 @ encoding: [0xe4,0x20,0xa0,0xe1] +@ CHECK: mov r2, r4 @ encoding: [0x04,0x20,0xa0,0xe1] +@ CHECK: ror r4, r4, #1 @ encoding: [0xe4,0x40,0xa0,0xe1] + + +@------------------------------------------------------------------------------ @ RSB @------------------------------------------------------------------------------ rsb r4, r5, #0xf000 diff --git a/test/MC/ARM/basic-thumb-instructions.s b/test/MC/ARM/basic-thumb-instructions.s index 0fa52b0..bc2605c 100644 --- a/test/MC/ARM/basic-thumb-instructions.s +++ b/test/MC/ARM/basic-thumb-instructions.s @@ -59,12 +59,16 @@ _func: add sp, sp, #4 add r2, sp, #8 add r2, sp, #1020 + add sp, sp, #-8 + add sp, #-8 @ CHECK: add sp, #4 @ encoding: [0x01,0xb0] @ CHECK: add sp, #508 @ encoding: [0x7f,0xb0] @ CHECK: add sp, #4 @ encoding: [0x01,0xb0] @ CHECK: add r2, sp, #8 @ encoding: [0x02,0xaa] @ CHECK: add r2, sp, #1020 @ encoding: [0xff,0xaa] +@ CHECK: sub sp, #8 @ encoding: [0x82,0xb0] +@ CHECK: sub sp, #8 @ encoding: [0x82,0xb0] @------------------------------------------------------------------------------ @@ -93,10 +97,16 @@ _func: asrs r2, r3, #32 asrs r2, r3, #5 asrs r2, r3, #1 + asrs r5, #21 + asrs r5, r5, #21 + asrs r3, r5, #21 @ CHECK: asrs r2, r3, #32 @ encoding: [0x1a,0x10] @ CHECK: asrs r2, r3, #5 @ encoding: [0x5a,0x11] @ CHECK: asrs r2, r3, #1 @ encoding: [0x5a,0x10] +@ CHECK: asrs r5, r5, #21 @ encoding: [0x6d,0x15] +@ CHECK: asrs r5, r5, #21 @ encoding: [0x6d,0x15] +@ CHECK: asrs r3, r5, #21 @ encoding: [0x6b,0x15] @------------------------------------------------------------------------------ @@ -315,9 +325,15 @@ _func: @------------------------------------------------------------------------------ lsls r4, r5, #0 lsls r4, r5, #4 + lsls r3, #12 + lsls r3, r3, #12 + lsls r1, r3, #12 @ CHECK: lsls r4, r5, #0 @ encoding: [0x2c,0x00] @ CHECK: lsls r4, r5, #4 @ encoding: [0x2c,0x01] +@ CHECK: lsls r3, r3, #12 @ encoding: [0x1b,0x03] +@ CHECK: lsls r3, r3, #12 @ encoding: [0x1b,0x03] +@ CHECK: lsls r1, r3, #12 @ encoding: [0x19,0x03] @------------------------------------------------------------------------------ @@ -333,9 +349,15 @@ _func: @------------------------------------------------------------------------------ lsrs r1, r3, #1 lsrs r1, r3, #32 + lsrs r4, #20 + lsrs r4, r4, #20 + lsrs r2, r4, #20 @ CHECK: lsrs r1, r3, #1 @ encoding: [0x59,0x08] @ CHECK: lsrs r1, r3, #32 @ encoding: [0x19,0x08] +@ CHECK: lsrs r4, r4, #20 @ encoding: [0x24,0x0d] +@ CHECK: lsrs r4, r4, #20 @ encoding: [0x24,0x0d] +@ CHECK: lsrs r2, r4, #20 @ encoding: [0x22,0x0d] @------------------------------------------------------------------------------ @@ -372,9 +394,11 @@ _func: @ MUL @------------------------------------------------------------------------------ muls r1, r2, r1 + muls r2, r2, r3 muls r3, r4 @ CHECK: muls r1, r2, r1 @ encoding: [0x51,0x43] +@ CHECK: muls r2, r3, r2 @ encoding: [0x5a,0x43] @ CHECK: muls r3, r4, r3 @ encoding: [0x63,0x43] diff --git a/test/MC/ARM/basic-thumb2-instructions.s b/test/MC/ARM/basic-thumb2-instructions.s index 68815da..d2e208b 100644 --- a/test/MC/ARM/basic-thumb2-instructions.s +++ b/test/MC/ARM/basic-thumb2-instructions.s @@ -73,6 +73,10 @@ _func: add r12, r6, #0x100 addw r12, r6, #0x100 adds r1, r2, #0x1f0 + add r2, #1 + add r0, r0, #32 + adds r2, r2, #56 + adds r2, #56 @ CHECK: itet eq @ encoding: [0x0a,0xbf] @ CHECK: addeq r1, r2, #4 @ encoding: [0x11,0x1d] @@ -85,6 +89,10 @@ _func: @ CHECK: add.w r12, r6, #256 @ encoding: [0x06,0xf5,0x80,0x7c] @ CHECK: addw r12, r6, #256 @ encoding: [0x06,0xf2,0x00,0x1c] @ CHECK: adds.w r1, r2, #496 @ encoding: [0x12,0xf5,0xf8,0x71] +@ CHECK: add.w r2, r2, #1 @ encoding: [0x02,0xf1,0x01,0x02] +@ CHECK: add.w r0, r0, #32 @ encoding: [0x00,0xf1,0x20,0x00] +@ CHECK: adds r2, #56 @ encoding: [0x38,0x32] +@ CHECK: adds r2, #56 @ encoding: [0x38,0x32] @------------------------------------------------------------------------------ @@ -95,12 +103,16 @@ _func: adds r7, r3, r1, lsl #31 adds.w r0, r3, r6, lsr #25 add.w r4, r8, r1, ror #12 + add r10, r8 + add r10, r10, r8 @ CHECK: add.w r1, r2, r8 @ encoding: [0x02,0xeb,0x08,0x01] @ CHECK: add.w r5, r9, r2, asr #32 @ encoding: [0x09,0xeb,0x22,0x05] @ CHECK: adds.w r7, r3, r1, lsl #31 @ encoding: [0x13,0xeb,0xc1,0x77] @ CHECK: adds.w r0, r3, r6, lsr #25 @ encoding: [0x13,0xeb,0x56,0x60] @ CHECK: add.w r4, r8, r1, ror #12 @ encoding: [0x08,0xeb,0x31,0x34] +@ CHECK: add r10, r8 @ encoding: [0xc2,0x44] +@ CHECK: add r10, r8 @ encoding: [0xc2,0x44] @------------------------------------------------------------------------------ @@ -360,6 +372,8 @@ _func: cmp sp, r6, lsr #1 cmp r2, r5, asr #24 cmp r1, r4, ror #15 + cmp r2, #-2 + cmp r9, #1 @ CHECK: cmp.w r5, #65280 @ encoding: [0xb5,0xf5,0x7f,0x4f] @ CHECK: cmp.w r4, r12 @ encoding: [0xb4,0xeb,0x0c,0x0f] @@ -368,6 +382,8 @@ _func: @ CHECK: cmp.w sp, r6, lsr #1 @ encoding: [0xbd,0xeb,0x56,0x0f] @ CHECK: cmp.w r2, r5, asr #24 @ encoding: [0xb2,0xeb,0x25,0x6f] @ CHECK: cmp.w r1, r4, ror #15 @ encoding: [0xb1,0xeb,0xf4,0x3f] +@ CHECK: cmn.w r2, #2 @ encoding: [0x12,0xf1,0x02,0x0f] +@ CHECK: cmp.w r9, #1 @ encoding: [0xb9,0xf1,0x01,0x0f] @------------------------------------------------------------------------------ @@ -573,6 +589,7 @@ _func: ldm r4, {r5, r6} ldm r5!, {r3, r8} ldmfd r5!, {r3, r8} + ldmia sp!, {r4-r11, pc} @ CHECK: ldm.w r4, {r4, r5, r8, r9} @ encoding: [0x94,0xe8,0x30,0x03] @ CHECK: ldm.w r4, {r5, r6} @ encoding: [0x94,0xe8,0x60,0x00] @@ -590,6 +607,7 @@ _func: @ CHECK: ldm.w r4, {r5, r6} @ encoding: [0x94,0xe8,0x60,0x00] @ CHECK: ldm.w r5!, {r3, r8} @ encoding: [0xb5,0xe8,0x08,0x01] @ CHECK: ldm.w r5!, {r3, r8} @ encoding: [0xb5,0xe8,0x08,0x01] +@ CHECK: pop.w {pc, r4, r5, r6, r7, r8, r9, r10, r11} @ encoding: [0xbd,0xe8,0xf0,0x8f] @------------------------------------------------------------------------------ @@ -599,11 +617,15 @@ _func: ldmdb r4, {r5, r6} ldmdb r5!, {r3, r8} ldmea r5!, {r3, r8} + ldmdb.w r4, {r5, r6} + ldmdb.w r5!, {r3, r8} @ CHECK: ldmdb r4, {r4, r5, r8, r9} @ encoding: [0x14,0xe9,0x30,0x03] @ CHECK: ldmdb r4, {r5, r6} @ encoding: [0x14,0xe9,0x60,0x00] @ CHECK: ldmdb r5!, {r3, r8} @ encoding: [0x35,0xe9,0x08,0x01] @ CHECK: ldmdb r5!, {r3, r8} @ encoding: [0x35,0xe9,0x08,0x01] +@ CHECK: ldmdb r4, {r5, r6} @ encoding: [0x14,0xe9,0x60,0x00] +@ CHECK: ldmdb r5!, {r3, r8} @ encoding: [0x35,0xe9,0x08,0x01] @------------------------------------------------------------------------------ @@ -638,9 +660,12 @@ _func: @ LDR(literal) @------------------------------------------------------------------------------ ldr.w r5, _foo + ldr lr, (_strcmp-4) @ CHECK: ldr.w r5, _foo @ encoding: [0x5f'A',0xf8'A',A,0x50'A'] - @ fixup A - offset: 0, value: _foo, kind: fixup_t2_ldst_pcrel_12 +@ CHECK: @ fixup A - offset: 0, value: _foo, kind: fixup_t2_ldst_pcrel_12 +@ CHECK: ldr.w lr, _strcmp-4 @ encoding: [0x5f'A',0xf8'A',A,0xe0'A'] +@ CHECK: @ fixup A - offset: 0, value: _strcmp-4, kind: fixup_t2_ldst_pcrel_12 @------------------------------------------------------------------------------ @@ -813,7 +838,7 @@ _func: @------------------------------------------------------------------------------ ldrh r5, _bar -@ CHECK: ldrh.w r5, _bar @ encoding: [0xbf'A',0xf8'A',A,0x50'A'] +@ CHECK: ldrh.w r5, _bar @ encoding: [0x3f'A',0xf8'A',A,0x50'A'] @ CHECK: @ fixup A - offset: 0, value: _bar, kind: fixup_t2_ldst_pcrel_12 @@ -882,7 +907,7 @@ _func: @------------------------------------------------------------------------------ ldrsb r5, _bar -@ CHECK: ldrsb.w r5, _bar @ encoding: [0x9f'A',0xf9'A',A,0x50'A'] +@ CHECK: ldrsb.w r5, _bar @ encoding: [0x1f'A',0xf9'A',A,0x50'A'] @ CHECK: @ fixup A - offset: 0, value: _bar, kind: fixup_t2_ldst_pcrel_12 @@ -951,7 +976,7 @@ _func: @------------------------------------------------------------------------------ ldrsh r5, _bar -@ CHECK: ldrsh.w r5, _bar @ encoding: [0xbf'A',0xf9'A',A,0x50'A'] +@ CHECK: ldrsh.w r5, _bar @ encoding: [0x3f'A',0xf9'A',A,0x50'A'] @ CHECK: @ fixup A - offset: 0, value: _bar, kind: fixup_t2_ldst_pcrel_12 @ TEMPORARILY DISABLED: @@ -1066,9 +1091,13 @@ _func: @------------------------------------------------------------------------------ mcr p7, #1, r5, c1, c1, #4 mcr2 p7, #1, r5, c1, c1, #4 + mcr p14, #0, r4, c0, c5 + mcr2 p4, #2, r2, c1, c3 @ CHECK: mcr p7, #1, r5, c1, c1, #4 @ encoding: [0x21,0xee,0x91,0x57] @ CHECK: mcr2 p7, #1, r5, c1, c1, #4 @ encoding: [0x21,0xfe,0x91,0x57] +@ CHECK: mcr p14, #0, r4, c0, c5, #0 @ encoding: [0x00,0xee,0x15,0x4e] +@ CHECK: mcr2 p4, #2, r2, c1, c3, #0 @ encoding: [0x41,0xfe,0x13,0x24] @------------------------------------------------------------------------------ @@ -1108,6 +1137,12 @@ _func: moveq r1, #12 movne.w r1, #12 mov.w r6, #450 + it lo + movlo r1, #-1 + + @ alias for mvn + mov r3, #-3 + @ CHECK: movs r1, #21 @ encoding: [0x15,0x21] @ CHECK: movs.w r1, #21 @ encoding: [0x5f,0xf0,0x15,0x01] @@ -1123,6 +1158,48 @@ _func: @ CHECK: moveq r1, #12 @ encoding: [0x0c,0x21] @ CHECK: movne.w r1, #12 @ encoding: [0x4f,0xf0,0x0c,0x01] @ CHECK: mov.w r6, #450 @ encoding: [0x4f,0xf4,0xe1,0x76] +@ CHECK: it lo @ encoding: [0x38,0xbf] +@ CHECK: movlo.w r1, #-1 @ encoding: [0x4f,0xf0,0xff,0x31] +@ CHECK: mvn r3, #2 @ encoding: [0x6f,0xf0,0x02,0x03] + +@------------------------------------------------------------------------------ +@ MOV(shifted register) +@------------------------------------------------------------------------------ + mov r6, r2, lsl #16 + mov r6, r2, lsr #16 + movs r6, r2, asr #32 + movs r6, r2, ror #5 + movs r4, r4, lsl r5 + movs r4, r4, lsr r5 + movs r4, r4, asr r5 + movs r4, r4, ror r5 + mov r4, r4, lsl r5 + movs r4, r4, ror r8 + movs r4, r5, lsr r6 + itttt eq + moveq r4, r4, lsl r5 + moveq r4, r4, lsr r5 + moveq r4, r4, asr r5 + moveq r4, r4, ror r5 + mov r4, r4, rrx + +@ CHECK: lsl.w r6, r2, #16 @ encoding: [0x4f,0xea,0x02,0x46] +@ CHECK: lsr.w r6, r2, #16 @ encoding: [0x4f,0xea,0x12,0x46] +@ CHECK: asrs r6, r2, #32 @ encoding: [0x16,0x10] +@ CHECK: rors.w r6, r2, #5 @ encoding: [0x5f,0xea,0x72,0x16] +@ CHECK: lsls r4, r5 @ encoding: [0xac,0x40] +@ CHECK: lsrs r4, r5 @ encoding: [0xec,0x40] +@ CHECK: asrs r4, r5 @ encoding: [0x2c,0x41] +@ CHECK: rors r4, r5 @ encoding: [0xec,0x41] +@ CHECK: lsl.w r4, r4, r5 @ encoding: [0x04,0xfa,0x05,0xf4] +@ CHECK: rors.w r4, r4, r8 @ encoding: [0x74,0xfa,0x08,0xf4] +@ CHECK: lsrs.w r4, r5, r6 @ encoding: [0x35,0xfa,0x06,0xf4] +@ CHECK: itttt eq @ encoding: [0x01,0xbf] +@ CHECK: lsleq r4, r5 @ encoding: [0xac,0x40] +@ CHECK: lsreq r4, r5 @ encoding: [0xec,0x40] +@ CHECK: asreq r4, r5 @ encoding: [0x2c,0x41] +@ CHECK: roreq r4, r5 @ encoding: [0xec,0x41] +@ CHECK: rrx r4, r4 @ encoding: [0x4f,0xea,0x34,0x04] @------------------------------------------------------------------------------ @@ -1143,9 +1220,13 @@ _func: @------------------------------------------------------------------------------ mrc p14, #0, r1, c1, c2, #4 mrc2 p14, #0, r1, c1, c2, #4 + mrc p11, #1, r1, c2, c2 + mrc2 p12, #3, r3, c3, c4 @ CHECK: mrc p14, #0, r1, c1, c2, #4 @ encoding: [0x11,0xee,0x92,0x1e] @ CHECK: mrc2 p14, #0, r1, c1, c2, #4 @ encoding: [0x11,0xfe,0x92,0x1e] +@ CHECK: mrc p11, #1, r1, c2, c2, #0 @ encoding: [0x32,0xee,0x12,0x1b] +@ CHECK: mrc2 p12, #3, r3, c3, c4, #0 @ encoding: [0x73,0xfe,0x14,0x3c] @------------------------------------------------------------------------------ @@ -1187,6 +1268,7 @@ _func: msr spsr_fc, r0 msr SPSR_fsxc, r5 msr cpsr_fsxc, r8 + msr cpsr, r3 @ CHECK: msr APSR_nzcvq, r1 @ encoding: [0x81,0xf3,0x00,0x88] @ CHECK: msr APSR_g, r2 @ encoding: [0x82,0xf3,0x00,0x84] @@ -1202,6 +1284,7 @@ _func: @ CHECK: msr SPSR_fc, r0 @ encoding: [0x90,0xf3,0x00,0x89] @ CHECK: msr SPSR_fsxc, r5 @ encoding: [0x95,0xf3,0x00,0x8f] @ CHECK: msr CPSR_fsxc, r8 @ encoding: [0x88,0xf3,0x00,0x8f] +@ CHECK: msr CPSR_fc, r3 @ encoding: [0x83,0xf3,0x00,0x89] @------------------------------------------------------------------------------ @@ -1212,12 +1295,18 @@ _func: mul r3, r4, r6 it eq muleq r3, r4, r5 + it le + mulle r4, r4, r8 + mul r5, r6 @ CHECK: muls r3, r4, r3 @ encoding: [0x63,0x43] @ CHECK: mul r3, r4, r3 @ encoding: [0x04,0xfb,0x03,0xf3] @ CHECK: mul r3, r4, r6 @ encoding: [0x04,0xfb,0x06,0xf3] @ CHECK: it eq @ encoding: [0x08,0xbf] @ CHECK: muleq r3, r4, r5 @ encoding: [0x04,0xfb,0x05,0xf3] +@ CHECK: it le @ encoding: [0xd8,0xbf] +@ CHECK: mulle r4, r4, r8 @ encoding: [0x04,0xfb,0x08,0xf4] +@ CHECK: mul r5, r6, r5 @ encoding: [0x06,0xfb,0x05,0xf5] @------------------------------------------------------------------------------ @@ -1228,7 +1317,7 @@ _func: mvns r0, #0x3fc0000 itte eq mvnseq r1, #12 - mvneq r1, #12 + mvneq.w r1, #12 mvnne r1, #12 @ CHECK: mvns r8, #21 @ encoding: [0x7f,0xf0,0x15,0x08] @@ -1247,7 +1336,7 @@ _func: mvns r2, r3 mvn r5, r6, lsl #19 mvn r5, r6, lsr #9 - mvn r5, r6, asr #4 + mvn.w r5, r6, asr #4 mvn r5, r6, ror #6 mvn r5, r6, rrx it eq @@ -1264,6 +1353,16 @@ _func: @ CHECK: mvneq r2, r3 @ encoding: [0xda,0x43] @------------------------------------------------------------------------------ +@ NEG +@------------------------------------------------------------------------------ + neg r5, r2 + neg r5, r8 + +@ CHECK: rsb.w r5, r2, #0 @ encoding: [0xc2,0xf1,0x00,0x05] +@ CHECK: rsb.w r5, r8, #0 @ encoding: [0xc8,0xf1,0x00,0x05] + + +@------------------------------------------------------------------------------ @ NOP @------------------------------------------------------------------------------ nop.w @@ -1343,20 +1442,24 @@ _func: pld [r6, #33] pld [r6, #257] pld [r7, #257] + pld [r1, #0] + pld [r1, #-0] @ CHECK: pld [r5, #-4] @ encoding: [0x15,0xf8,0x04,0xfc] @ CHECK: pld [r6, #32] @ encoding: [0x96,0xf8,0x20,0xf0] @ CHECK: pld [r6, #33] @ encoding: [0x96,0xf8,0x21,0xf0] @ CHECK: pld [r6, #257] @ encoding: [0x96,0xf8,0x01,0xf1] @ CHECK: pld [r7, #257] @ encoding: [0x97,0xf8,0x01,0xf1] +@ CHECK: pld [r1] @ encoding: [0x91,0xf8,0x00,0xf0] +@ CHECK: pld [r1, #-0] @ encoding: [0x11,0xf8,0x00,0xfc] @------------------------------------------------------------------------------ @ PLD(literal) @------------------------------------------------------------------------------ - pld _foo +@ pld _foo -@ CHECK: pld _foo @ encoding: [0x9f'A',0xf8'A',A,0xf0'A'] +@ FIXME: pld _foo @ encoding: [0x9f'A',0xf8'A',A,0xf0'A'] @ fixup A - offset: 0, value: _foo, kind: fixup_t2_ldst_pcrel_12 @@ -1396,10 +1499,10 @@ _func: @------------------------------------------------------------------------------ @ PLI(literal) @------------------------------------------------------------------------------ - pli _foo +@ pli _foo -@ CHECK: pli _foo @ encoding: [0x9f'A',0xf9'A',A,0xf0'A'] +@ FIXME: pli _foo @ encoding: [0x9f'A',0xf9'A',A,0xf0'A'] @ fixup A - offset: 0, value: _foo, kind: fixup_t2_ldst_pcrel_12 @@ -1420,6 +1523,21 @@ _func: @ CHECK: pli [sp, r2, lsl #1] @ encoding: [0x1d,0xf9,0x12,0xf0] @ CHECK: pli [sp, r2] @ encoding: [0x1d,0xf9,0x02,0xf0] +@------------------------------------------------------------------------------ +@ POP (alias) +@------------------------------------------------------------------------------ + pop {r2, r9} + +@ CHECK: pop.w {r2, r9} @ encoding: [0xbd,0xe8,0x04,0x02] + + +@------------------------------------------------------------------------------ +@ PUSH (alias) +@------------------------------------------------------------------------------ + push {r2, r9} + +@ CHECK: push.w {r2, r9} @ encoding: [0x2d,0xe9,0x04,0x02] + @------------------------------------------------------------------------------ @ QADD/QADD16/QADD8 @@ -1609,11 +1727,19 @@ _func: rsbs r3, r12, #0xf rsb r1, #0xff rsb r1, r1, #0xff + rsb r11, r11, #0 + rsb r9, #0 + rsbs r3, r1, #0 + rsb r3, r1, #0 @ CHECK: rsb.w r2, r5, #1044480 @ encoding: [0xc5,0xf5,0x7f,0x22] @ CHECK: rsbs.w r3, r12, #15 @ encoding: [0xdc,0xf1,0x0f,0x03] @ CHECK: rsb.w r1, r1, #255 @ encoding: [0xc1,0xf1,0xff,0x01] @ CHECK: rsb.w r1, r1, #255 @ encoding: [0xc1,0xf1,0xff,0x01] +@ CHECK: rsb.w r11, r11, #0 @ encoding: [0xcb,0xf1,0x00,0x0b] +@ CHECK: rsb.w r9, r9, #0 @ encoding: [0xc9,0xf1,0x00,0x09] +@ CHECK: rsbs r3, r1, #0 @ encoding: [0x4b,0x42] +@ CHECK: rsb.w r3, r1, #0 @ encoding: [0xc1,0xf1,0x00,0x03] @------------------------------------------------------------------------------ @@ -2287,11 +2413,13 @@ _func: stmdb r4, {r5, r6} stmdb r5!, {r3, r8} stmea r5!, {r3, r8} + stmdb.w r5, {r0, r1} @ CHECK: stmdb r4, {r4, r5, r8, r9} @ encoding: [0x04,0xe9,0x30,0x03] @ CHECK: stmdb r4, {r5, r6} @ encoding: [0x04,0xe9,0x60,0x00] @ CHECK: stmdb r5!, {r3, r8} @ encoding: [0x25,0xe9,0x08,0x01] @ CHECK: stm.w r5!, {r3, r8} @ encoding: [0xa5,0xe8,0x08,0x01] +@ CHECK: stmdb r5, {r0, r1} @ encoding: [0x05,0xe9,0x03,0x00] @------------------------------------------------------------------------------ @@ -2526,6 +2654,10 @@ _func: sub r12, r6, #0x100 subw r12, r6, #0x100 subs r1, r2, #0x1f0 + sub r2, #1 + sub r0, r0, #32 + subs r2, r2, #56 + subs r2, #56 @ CHECK: itet eq @ encoding: [0x0a,0xbf] @ CHECK: subeq r1, r2, #4 @ encoding: [0x11,0x1f] @@ -2538,6 +2670,10 @@ _func: @ CHECK: sub.w r12, r6, #256 @ encoding: [0xa6,0xf5,0x80,0x7c] @ CHECK: subw r12, r6, #256 @ encoding: [0xa6,0xf2,0x00,0x1c] @ CHECK: subs.w r1, r2, #496 @ encoding: [0xb2,0xf5,0xf8,0x71] +@ CHECK: sub.w r2, r2, #1 @ encoding: [0xa2,0xf1,0x01,0x02] +@ CHECK: sub.w r0, r0, #32 @ encoding: [0xa0,0xf1,0x20,0x00] +@ CHECK: subs r2, #56 @ encoding: [0x38,0x3a] +@ CHECK: subs r2, #56 @ encoding: [0x38,0x3a] @------------------------------------------------------------------------------ @@ -2550,6 +2686,12 @@ _func: sub r4, r5, r6, asr #5 sub r4, r5, r6, ror #5 sub.w r5, r2, r12, rrx + sub r2, sp, ip + sub sp, sp, ip + sub sp, ip + sub.w r2, sp, ip + sub.w sp, sp, ip + sub.w sp, ip @ CHECK: sub.w r4, r5, r6 @ encoding: [0xa5,0xeb,0x06,0x04] @ CHECK: sub.w r4, r5, r6, lsl #5 @ encoding: [0xa5,0xeb,0x46,0x14] @@ -2558,6 +2700,12 @@ _func: @ CHECK: sub.w r4, r5, r6, asr #5 @ encoding: [0xa5,0xeb,0x66,0x14] @ CHECK: sub.w r4, r5, r6, ror #5 @ encoding: [0xa5,0xeb,0x76,0x14] @ CHECK: sub.w r5, r2, r12, rrx @ encoding: [0xa2,0xeb,0x3c,0x05] +@ CHECK: sub.w r2, sp, r12 @ encoding: [0xad,0xeb,0x0c,0x02] +@ CHECK: sub.w sp, sp, r12 @ encoding: [0xad,0xeb,0x0c,0x0d] +@ CHECK: sub.w sp, sp, r12 @ encoding: [0xad,0xeb,0x0c,0x0d] +@ CHECK: sub.w r2, sp, r12 @ encoding: [0xad,0xeb,0x0c,0x02] +@ CHECK: sub.w sp, sp, r12 @ encoding: [0xad,0xeb,0x0c,0x0d] +@ CHECK: sub.w sp, sp, r12 @ encoding: [0xad,0xeb,0x0c,0x0d] @------------------------------------------------------------------------------ @@ -3211,3 +3359,30 @@ _func: @ CHECK: wfelt @ encoding: [0x20,0xbf] @ CHECK: wfige @ encoding: [0x30,0xbf] @ CHECK: yieldlt @ encoding: [0x10,0xbf] + + +@------------------------------------------------------------------------------ +@ Alternate syntax for LDR*(literal) encodings +@------------------------------------------------------------------------------ + ldr r11, [pc, #-22] + ldrb r11, [pc, #-22] + ldrh r11, [pc, #-22] + ldrsb r11, [pc, #-22] + ldrsh r11, [pc, #-22] + + ldr.w r11, [pc, #-22] + ldrb.w r11, [pc, #-22] + ldrh.w r11, [pc, #-22] + ldrsb.w r11, [pc, #-22] + ldrsh.w r11, [pc, #-22] + +@ CHECK: ldr.w r11, [pc, #-22] @ encoding: [0x5f,0xf8,0x16,0xb0] +@ CHECK: ldrb.w r11, [pc, #-22] @ encoding: [0x1f,0xf8,0x16,0xb0] +@ CHECK: ldrh.w r11, [pc, #-22] @ encoding: [0x3f,0xf8,0x16,0xb0] +@ CHECK: ldrsb.w r11, [pc, #-22] @ encoding: [0x1f,0xf9,0x16,0xb0] +@ CHECK: ldrsh.w r11, [pc, #-22] @ encoding: [0x3f,0xf9,0x16,0xb0] +@ CHECK: ldr.w r11, [pc, #-22] @ encoding: [0x5f,0xf8,0x16,0xb0] +@ CHECK: ldrb.w r11, [pc, #-22] @ encoding: [0x1f,0xf8,0x16,0xb0] +@ CHECK: ldrh.w r11, [pc, #-22] @ encoding: [0x3f,0xf8,0x16,0xb0] +@ CHECK: ldrsb.w r11, [pc, #-22] @ encoding: [0x1f,0xf9,0x16,0xb0] +@ CHECK: ldrsh.w r11, [pc, #-22] @ encoding: [0x3f,0xf9,0x16,0xb0] diff --git a/test/MC/ARM/cxx-global-constructor.ll b/test/MC/ARM/cxx-global-constructor.ll new file mode 100644 index 0000000..e06d2c7 --- /dev/null +++ b/test/MC/ARM/cxx-global-constructor.ll @@ -0,0 +1,12 @@ +; RUN: llc %s -mtriple=armv7-linux-gnueabi -relocation-model=pic \ +; RUN: -filetype=obj -o - | elf-dump --dump-section-data | FileCheck %s + + +@llvm.global_ctors = appending global [1 x { i32, void ()* }] [{ i32, void ()* } { i32 65535, void ()* @f }] + +define void @f() { + ret void +} + +; Check for a relocation of type R_ARM_TARGET1. +; CHECK: ('r_type', 0x26) diff --git a/test/MC/ARM/dg.exp b/test/MC/ARM/dg.exp deleted file mode 100644 index 055fa25..0000000 --- a/test/MC/ARM/dg.exp +++ /dev/null @@ -1,5 +0,0 @@ -load_lib llvm.exp - -if { [llvm_supports_target ARM] } { - RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp,s}]] -} diff --git a/test/MC/ARM/diagnostics.s b/test/MC/ARM/diagnostics.s index f722dd7..7da79c3 100644 --- a/test/MC/ARM/diagnostics.s +++ b/test/MC/ARM/diagnostics.s @@ -216,7 +216,7 @@ @ Out of order STM registers stmda sp!, {r5, r2} -@ CHECK-ERRORS: error: register list not in ascending order +@ CHECK-ERRORS: warning: register list not in ascending order @ CHECK-ERRORS: stmda sp!, {r5, r2} @ CHECK-ERRORS: ^ diff --git a/test/MC/ARM/dot-req.s b/test/MC/ARM/dot-req.s new file mode 100644 index 0000000..3b4cf5c --- /dev/null +++ b/test/MC/ARM/dot-req.s @@ -0,0 +1,11 @@ +@ RUN: llvm-mc -triple=armv7-apple-darwin -show-encoding < %s | FileCheck %s + .syntax unified +bar: +fred .req r5 + mov r11, fred +.unreq fred +fred .req r6 + mov r1, fred + +@ CHECK: mov r11, r5 @ encoding: [0x05,0xb0,0xa0,0xe1] +@ CHECK: mov r1, r6 @ encoding: [0x06,0x10,0xa0,0xe1] diff --git a/test/MC/ARM/elf-reloc-01.ll b/test/MC/ARM/elf-reloc-01.ll index e6efe7e..6899d92 100644 --- a/test/MC/ARM/elf-reloc-01.ll +++ b/test/MC/ARM/elf-reloc-01.ll @@ -42,12 +42,12 @@ entry: ] bb: ; preds = %entry - volatile store i32 11, i32* @var_tls, align 4 - volatile store double 2.200000e+01, double* @var_tls_double, align 8 - volatile store i32 33, i32* @var_static, align 4 - volatile store double 4.400000e+01, double* @var_static_double, align 8 - volatile store i32 55, i32* @var_global, align 4 - volatile store double 6.600000e+01, double* @var_global_double, align 8 + store volatile i32 11, i32* @var_tls, align 4 + store volatile double 2.200000e+01, double* @var_tls_double, align 8 + store volatile i32 33, i32* @var_static, align 4 + store volatile double 4.400000e+01, double* @var_static_double, align 8 + store volatile i32 55, i32* @var_global, align 4 + store volatile double 6.600000e+01, double* @var_global_double, align 8 br label %bb3 bb2: ; preds = %entry diff --git a/test/MC/ARM/elf-reloc-condcall.s b/test/MC/ARM/elf-reloc-condcall.s new file mode 100644 index 0000000..dcc62d3 --- /dev/null +++ b/test/MC/ARM/elf-reloc-condcall.s @@ -0,0 +1,23 @@ +// RUN: llvm-mc -triple=armv7-linux-gnueabi -filetype=obj %s -o - | \ +// RUN: elf-dump | FileCheck -check-prefix=OBJ %s + + bleq some_label + bl some_label + blx some_label +// OBJ: .rel.text + +// OBJ: 'r_offset', 0x00000000 +// OBJ-NEXT: 'r_sym', 0x000004 +// OBJ-NEXT: 'r_type', 0x1d + +// OBJ: 'r_offset', 0x00000004 +// OBJ-NEXT: 'r_sym', 0x000004 +// OBJ-NEXT: 'r_type', 0x1c + +// OBJ: 'r_offset', 0x00000008 +// OBJ-NEXT: 'r_sym', 0x000004 +// OBJ-NEXT: 'r_type', 0x1c + +// OBJ: .symtab +// OBJ: Symbol 4 +// OBJ-NEXT: some_label
\ No newline at end of file diff --git a/test/MC/ARM/elf-thumbfunc-reloc.s b/test/MC/ARM/elf-thumbfunc-reloc.s new file mode 100644 index 0000000..4a311dd --- /dev/null +++ b/test/MC/ARM/elf-thumbfunc-reloc.s @@ -0,0 +1,23 @@ +@@ test st_value bit 0 of thumb function +@ RUN: llvm-mc %s -triple=arm-freebsd-eabi -filetype=obj -o - | \ +@ RUN: elf-dump | FileCheck %s + + + .syntax unified + .text + .globl f + .align 2 + .type f,%function + .code 16 + .thumb_func +f: + push {r7, lr} + mov r7, sp + bl g + pop {r7, pc} + +@@ make sure an R_ARM_THM_CALL relocation is generated for the call to g +@CHECK: ('_relocations', [ +@CHECK: (('r_offset', 0x00000004) +@CHECK-NEXT: ('r_sym', 0x{{[0-9a-fA-F]+}}) +@CHECK-NEXT: ('r_type', 0x0a) diff --git a/test/MC/ARM/lit.local.cfg b/test/MC/ARM/lit.local.cfg new file mode 100644 index 0000000..5700913 --- /dev/null +++ b/test/MC/ARM/lit.local.cfg @@ -0,0 +1,6 @@ +config.suffixes = ['.ll', '.c', '.cpp', '.s'] + +targets = set(config.root.targets_to_build.split()) +if not 'ARM' in targets: + config.unsupported = True + diff --git a/test/MC/ARM/mode-switch.s b/test/MC/ARM/mode-switch.s index 9d49954..afcc082 100644 --- a/test/MC/ARM/mode-switch.s +++ b/test/MC/ARM/mode-switch.s @@ -13,3 +13,14 @@ .code 16 adds r0, r0, r1 @ CHECK: adds r0, r0, r1 @ encoding: [0x40,0x18] + +.arm + add r0, r0, r1 +@ CHECK: add r0, r0, r1 @ encoding: [0x01,0x00,0x80,0xe0] + +.thumb + add.w r0, r0, r1 + adds r0, r0, r1 + +@ CHECK: add.w r0, r0, r1 @ encoding: [0x00,0xeb,0x01,0x00] +@ CHECK: adds r0, r0, r1 @ encoding: [0x40,0x18] diff --git a/test/MC/ARM/neon-add-encoding.s b/test/MC/ARM/neon-add-encoding.s index e425397..1fdfa4c 100644 --- a/test/MC/ARM/neon-add-encoding.s +++ b/test/MC/ARM/neon-add-encoding.s @@ -90,39 +90,81 @@ @ CHECK: vrhadd.u32 q8, q8, q9 @ encoding: [0xe2,0x01,0x60,0xf3] vrhadd.u32 q8, q8, q9 -@ CHECK: vqadd.s8 d16, d16, d17 @ encoding: [0xb1,0x00,0x40,0xf2] vqadd.s8 d16, d16, d17 -@ CHECK: vqadd.s16 d16, d16, d17 @ encoding: [0xb1,0x00,0x50,0xf2] vqadd.s16 d16, d16, d17 -@ CHECK: vqadd.s32 d16, d16, d17 @ encoding: [0xb1,0x00,0x60,0xf2] vqadd.s32 d16, d16, d17 -@ CHECK: vqadd.s64 d16, d16, d17 @ encoding: [0xb1,0x00,0x70,0xf2] vqadd.s64 d16, d16, d17 -@ CHECK: vqadd.u8 d16, d16, d17 @ encoding: [0xb1,0x00,0x40,0xf3] vqadd.u8 d16, d16, d17 -@ CHECK: vqadd.u16 d16, d16, d17 @ encoding: [0xb1,0x00,0x50,0xf3] vqadd.u16 d16, d16, d17 -@ CHECK: vqadd.u32 d16, d16, d17 @ encoding: [0xb1,0x00,0x60,0xf3] vqadd.u32 d16, d16, d17 -@ CHECK: vqadd.u64 d16, d16, d17 @ encoding: [0xb1,0x00,0x70,0xf3] vqadd.u64 d16, d16, d17 -@ CHECK: vqadd.s8 q8, q8, q9 @ encoding: [0xf2,0x00,0x40,0xf2] + +@ CHECK: vqadd.s8 d16, d16, d17 @ encoding: [0xb1,0x00,0x40,0xf2] +@ CHECK: vqadd.s16 d16, d16, d17 @ encoding: [0xb1,0x00,0x50,0xf2] +@ CHECK: vqadd.s32 d16, d16, d17 @ encoding: [0xb1,0x00,0x60,0xf2] +@ CHECK: vqadd.s64 d16, d16, d17 @ encoding: [0xb1,0x00,0x70,0xf2] +@ CHECK: vqadd.u8 d16, d16, d17 @ encoding: [0xb1,0x00,0x40,0xf3] +@ CHECK: vqadd.u16 d16, d16, d17 @ encoding: [0xb1,0x00,0x50,0xf3] +@ CHECK: vqadd.u32 d16, d16, d17 @ encoding: [0xb1,0x00,0x60,0xf3] +@ CHECK: vqadd.u64 d16, d16, d17 @ encoding: [0xb1,0x00,0x70,0xf3] + vqadd.s8 q8, q8, q9 -@ CHECK: vqadd.s16 q8, q8, q9 @ encoding: [0xf2,0x00,0x50,0xf2] vqadd.s16 q8, q8, q9 -@ CHECK: vqadd.s32 q8, q8, q9 @ encoding: [0xf2,0x00,0x60,0xf2] vqadd.s32 q8, q8, q9 -@ CHECK: vqadd.s64 q8, q8, q9 @ encoding: [0xf2,0x00,0x70,0xf2] vqadd.s64 q8, q8, q9 -@ CHECK: vqadd.u8 q8, q8, q9 @ encoding: [0xf2,0x00,0x40,0xf3] vqadd.u8 q8, q8, q9 -@ CHECK: vqadd.u16 q8, q8, q9 @ encoding: [0xf2,0x00,0x50,0xf3] vqadd.u16 q8, q8, q9 -@ CHECK: vqadd.u32 q8, q8, q9 @ encoding: [0xf2,0x00,0x60,0xf3] vqadd.u32 q8, q8, q9 -@ CHECK: vqadd.u64 q8, q8, q9 @ encoding: [0xf2,0x00,0x70,0xf3] vqadd.u64 q8, q8, q9 +@ CHECK: vqadd.s8 q8, q8, q9 @ encoding: [0xf2,0x00,0x40,0xf2] +@ CHECK: vqadd.s16 q8, q8, q9 @ encoding: [0xf2,0x00,0x50,0xf2] +@ CHECK: vqadd.s32 q8, q8, q9 @ encoding: [0xf2,0x00,0x60,0xf2] +@ CHECK: vqadd.s64 q8, q8, q9 @ encoding: [0xf2,0x00,0x70,0xf2] +@ CHECK: vqadd.u8 q8, q8, q9 @ encoding: [0xf2,0x00,0x40,0xf3] +@ CHECK: vqadd.u16 q8, q8, q9 @ encoding: [0xf2,0x00,0x50,0xf3] +@ CHECK: vqadd.u32 q8, q8, q9 @ encoding: [0xf2,0x00,0x60,0xf3] +@ CHECK: vqadd.u64 q8, q8, q9 @ encoding: [0xf2,0x00,0x70,0xf3] + + +@ two-operand variants. + vqadd.s8 d16, d17 + vqadd.s16 d16, d17 + vqadd.s32 d16, d17 + vqadd.s64 d16, d17 + vqadd.u8 d16, d17 + vqadd.u16 d16, d17 + vqadd.u32 d16, d17 + vqadd.u64 d16, d17 + +@ CHECK: vqadd.s8 d16, d16, d17 @ encoding: [0xb1,0x00,0x40,0xf2] +@ CHECK: vqadd.s16 d16, d16, d17 @ encoding: [0xb1,0x00,0x50,0xf2] +@ CHECK: vqadd.s32 d16, d16, d17 @ encoding: [0xb1,0x00,0x60,0xf2] +@ CHECK: vqadd.s64 d16, d16, d17 @ encoding: [0xb1,0x00,0x70,0xf2] +@ CHECK: vqadd.u8 d16, d16, d17 @ encoding: [0xb1,0x00,0x40,0xf3] +@ CHECK: vqadd.u16 d16, d16, d17 @ encoding: [0xb1,0x00,0x50,0xf3] +@ CHECK: vqadd.u32 d16, d16, d17 @ encoding: [0xb1,0x00,0x60,0xf3] +@ CHECK: vqadd.u64 d16, d16, d17 @ encoding: [0xb1,0x00,0x70,0xf3] + + vqadd.s8 q8, q9 + vqadd.s16 q8, q9 + vqadd.s32 q8, q9 + vqadd.s64 q8, q9 + vqadd.u8 q8, q9 + vqadd.u16 q8, q9 + vqadd.u32 q8, q9 + vqadd.u64 q8, q9 + +@ CHECK: vqadd.s8 q8, q8, q9 @ encoding: [0xf2,0x00,0x40,0xf2] +@ CHECK: vqadd.s16 q8, q8, q9 @ encoding: [0xf2,0x00,0x50,0xf2] +@ CHECK: vqadd.s32 q8, q8, q9 @ encoding: [0xf2,0x00,0x60,0xf2] +@ CHECK: vqadd.s64 q8, q8, q9 @ encoding: [0xf2,0x00,0x70,0xf2] +@ CHECK: vqadd.u8 q8, q8, q9 @ encoding: [0xf2,0x00,0x40,0xf3] +@ CHECK: vqadd.u16 q8, q8, q9 @ encoding: [0xf2,0x00,0x50,0xf3] +@ CHECK: vqadd.u32 q8, q8, q9 @ encoding: [0xf2,0x00,0x60,0xf3] +@ CHECK: vqadd.u64 q8, q8, q9 @ encoding: [0xf2,0x00,0x70,0xf3] + + @ CHECK: vaddhn.i16 d16, q8, q9 @ encoding: [0xa2,0x04,0xc0,0xf2] vaddhn.i16 d16, q8, q9 @ CHECK: vaddhn.i32 d16, q8, q9 @ encoding: [0xa2,0x04,0xd0,0xf2] @@ -135,3 +177,43 @@ vraddhn.i32 d16, q8, q9 @ CHECK: vraddhn.i64 d16, q8, q9 @ encoding: [0xa2,0x04,0xe0,0xf3] vraddhn.i64 d16, q8, q9 + + +@ Two-operand variants + + vadd.i8 d6, d5 + vadd.i16 d7, d1 + vadd.i32 d8, d2 + vadd.i64 d9, d3 + + vadd.i8 q6, q5 + vadd.i16 q7, q1 + vadd.i32 q8, q2 + vadd.i64 q9, q3 + +@ CHECK: vadd.i8 d6, d6, d5 @ encoding: [0x05,0x68,0x06,0xf2] +@ CHECK: vadd.i16 d7, d7, d1 @ encoding: [0x01,0x78,0x17,0xf2] +@ CHECK: vadd.i32 d8, d8, d2 @ encoding: [0x02,0x88,0x28,0xf2] +@ CHECK: vadd.i64 d9, d9, d3 @ encoding: [0x03,0x98,0x39,0xf2] + +@ CHECK: vadd.i8 q6, q6, q5 @ encoding: [0x4a,0xc8,0x0c,0xf2] +@ CHECK: vadd.i16 q7, q7, q1 @ encoding: [0x42,0xe8,0x1e,0xf2] +@ CHECK: vadd.i32 q8, q8, q2 @ encoding: [0xc4,0x08,0x60,0xf2] +@ CHECK: vadd.i64 q9, q9, q3 @ encoding: [0xc6,0x28,0x72,0xf2] + + + vaddw.s8 q6, d5 + vaddw.s16 q7, d1 + vaddw.s32 q8, d2 + + vaddw.u8 q6, d5 + vaddw.u16 q7, d1 + vaddw.u32 q8, d2 + +@ CHECK: vaddw.s8 q6, q6, d5 @ encoding: [0x05,0xc1,0x8c,0xf2] +@ CHECK: vaddw.s16 q7, q7, d1 @ encoding: [0x01,0xe1,0x9e,0xf2] +@ CHECK: vaddw.s32 q8, q8, d2 @ encoding: [0x82,0x01,0xe0,0xf2] + +@ CHECK: vaddw.u8 q6, q6, d5 @ encoding: [0x05,0xc1,0x8c,0xf3] +@ CHECK: vaddw.u16 q7, q7, d1 @ encoding: [0x01,0xe1,0x9e,0xf3] +@ CHECK: vaddw.u32 q8, q8, d2 @ encoding: [0x82,0x01,0xe0,0xf3] diff --git a/test/MC/ARM/neon-bitwise-encoding.s b/test/MC/ARM/neon-bitwise-encoding.s index 81e2c4d..2ce9bcc 100644 --- a/test/MC/ARM/neon-bitwise-encoding.s +++ b/test/MC/ARM/neon-bitwise-encoding.s @@ -22,9 +22,9 @@ vorr.i32 q8, #0x1000000 vorr.i32 q8, #0x0 -@ FIXME: vorr.i32 d16, #0x1000000 @ encoding: [0x11,0x07,0xc0,0xf2] -@ FIXME: vorr.i32 q8, #0x1000000 @ encoding: [0x51,0x07,0xc0,0xf2] -@ FIXME: vorr.i32 q8, #0x0 @ encoding: [0x50,0x01,0xc0,0xf2] +@ CHECK: vorr.i32 d16, #0x1000000 @ encoding: [0x11,0x07,0xc0,0xf2] +@ CHECK: vorr.i32 q8, #0x1000000 @ encoding: [0x51,0x07,0xc0,0xf2] +@ CHECK: vorr.i32 q8, #0x0 @ encoding: [0x50,0x01,0xc0,0xf2] vbic d16, d17, d16 vbic q8, q8, q9 @@ -33,8 +33,8 @@ @ CHECK: vbic d16, d17, d16 @ encoding: [0xb0,0x01,0x51,0xf2] @ CHECK: vbic q8, q8, q9 @ encoding: [0xf2,0x01,0x50,0xf2] -@ FIXME: vbic.i32 d16, #0xFF000000 @ encoding: [0x3f,0x07,0xc7,0xf3] -@ FIXME: vbic.i32 q8, #0xFF000000 @ encoding: [0x7f,0x07,0xc7,0xf3] +@ CHECK: vbic.i32 d16, #0xff000000 @ encoding: [0x3f,0x07,0xc7,0xf3] +@ CHECK: vbic.i32 q8, #0xff000000 @ encoding: [0x7f,0x07,0xc7,0xf3] vorn d16, d17, d16 vorn q8, q8, q9 @@ -53,3 +53,211 @@ @ CHECK: vbsl d18, d17, d16 @ encoding: [0xb0,0x21,0x51,0xf3] @ CHECK: vbsl q8, q10, q9 @ encoding: [0xf2,0x01,0x54,0xf3] + + +@ Size suffices are optional. + veor q4, q7, q3 + veor.8 q4, q7, q3 + veor.16 q4, q7, q3 + veor.32 q4, q7, q3 + veor.64 q4, q7, q3 + + veor.i8 q4, q7, q3 + veor.i16 q4, q7, q3 + veor.i32 q4, q7, q3 + veor.i64 q4, q7, q3 + + veor.s8 q4, q7, q3 + veor.s16 q4, q7, q3 + veor.s32 q4, q7, q3 + veor.s64 q4, q7, q3 + + veor.u8 q4, q7, q3 + veor.u16 q4, q7, q3 + veor.u32 q4, q7, q3 + veor.u64 q4, q7, q3 + + veor.p8 q4, q7, q3 + veor.p16 q4, q7, q3 + veor.f32 q4, q7, q3 + veor.f64 q4, q7, q3 + + veor.f q4, q7, q3 + veor.d q4, q7, q3 + +@ CHECK: veor q4, q7, q3 @ encoding: [0x56,0x81,0x0e,0xf3] +@ CHECK: veor q4, q7, q3 @ encoding: [0x56,0x81,0x0e,0xf3] +@ CHECK: veor q4, q7, q3 @ encoding: [0x56,0x81,0x0e,0xf3] +@ CHECK: veor q4, q7, q3 @ encoding: [0x56,0x81,0x0e,0xf3] +@ CHECK: veor q4, q7, q3 @ encoding: [0x56,0x81,0x0e,0xf3] + +@ CHECK: veor q4, q7, q3 @ encoding: [0x56,0x81,0x0e,0xf3] +@ CHECK: veor q4, q7, q3 @ encoding: [0x56,0x81,0x0e,0xf3] +@ CHECK: veor q4, q7, q3 @ encoding: [0x56,0x81,0x0e,0xf3] +@ CHECK: veor q4, q7, q3 @ encoding: [0x56,0x81,0x0e,0xf3] + +@ CHECK: veor q4, q7, q3 @ encoding: [0x56,0x81,0x0e,0xf3] +@ CHECK: veor q4, q7, q3 @ encoding: [0x56,0x81,0x0e,0xf3] +@ CHECK: veor q4, q7, q3 @ encoding: [0x56,0x81,0x0e,0xf3] +@ CHECK: veor q4, q7, q3 @ encoding: [0x56,0x81,0x0e,0xf3] + +@ CHECK: veor q4, q7, q3 @ encoding: [0x56,0x81,0x0e,0xf3] +@ CHECK: veor q4, q7, q3 @ encoding: [0x56,0x81,0x0e,0xf3] +@ CHECK: veor q4, q7, q3 @ encoding: [0x56,0x81,0x0e,0xf3] +@ CHECK: veor q4, q7, q3 @ encoding: [0x56,0x81,0x0e,0xf3] + +@ CHECK: veor q4, q7, q3 @ encoding: [0x56,0x81,0x0e,0xf3] +@ CHECK: veor q4, q7, q3 @ encoding: [0x56,0x81,0x0e,0xf3] +@ CHECK: veor q4, q7, q3 @ encoding: [0x56,0x81,0x0e,0xf3] +@ CHECK: veor q4, q7, q3 @ encoding: [0x56,0x81,0x0e,0xf3] + +@ CHECK: veor q4, q7, q3 @ encoding: [0x56,0x81,0x0e,0xf3] +@ CHECK: veor q4, q7, q3 @ encoding: [0x56,0x81,0x0e,0xf3] + + + vand d4, d7, d3 + vand.8 d4, d7, d3 + vand.16 d4, d7, d3 + vand.32 d4, d7, d3 + vand.64 d4, d7, d3 + + vand.i8 d4, d7, d3 + vand.i16 d4, d7, d3 + vand.i32 d4, d7, d3 + vand.i64 d4, d7, d3 + + vand.s8 d4, d7, d3 + vand.s16 d4, d7, d3 + vand.s32 d4, d7, d3 + vand.s64 d4, d7, d3 + + vand.u8 d4, d7, d3 + vand.u16 d4, d7, d3 + vand.u32 d4, d7, d3 + vand.u64 d4, d7, d3 + + vand.p8 d4, d7, d3 + vand.p16 d4, d7, d3 + vand.f32 d4, d7, d3 + vand.f64 d4, d7, d3 + + vand.f d4, d7, d3 + vand.d d4, d7, d3 + +@ CHECK: vand d4, d7, d3 @ encoding: [0x13,0x41,0x07,0xf2] +@ CHECK: vand d4, d7, d3 @ encoding: [0x13,0x41,0x07,0xf2] +@ CHECK: vand d4, d7, d3 @ encoding: [0x13,0x41,0x07,0xf2] +@ CHECK: vand d4, d7, d3 @ encoding: [0x13,0x41,0x07,0xf2] +@ CHECK: vand d4, d7, d3 @ encoding: [0x13,0x41,0x07,0xf2] + +@ CHECK: vand d4, d7, d3 @ encoding: [0x13,0x41,0x07,0xf2] +@ CHECK: vand d4, d7, d3 @ encoding: [0x13,0x41,0x07,0xf2] +@ CHECK: vand d4, d7, d3 @ encoding: [0x13,0x41,0x07,0xf2] +@ CHECK: vand d4, d7, d3 @ encoding: [0x13,0x41,0x07,0xf2] + +@ CHECK: vand d4, d7, d3 @ encoding: [0x13,0x41,0x07,0xf2] +@ CHECK: vand d4, d7, d3 @ encoding: [0x13,0x41,0x07,0xf2] +@ CHECK: vand d4, d7, d3 @ encoding: [0x13,0x41,0x07,0xf2] +@ CHECK: vand d4, d7, d3 @ encoding: [0x13,0x41,0x07,0xf2] + +@ CHECK: vand d4, d7, d3 @ encoding: [0x13,0x41,0x07,0xf2] +@ CHECK: vand d4, d7, d3 @ encoding: [0x13,0x41,0x07,0xf2] +@ CHECK: vand d4, d7, d3 @ encoding: [0x13,0x41,0x07,0xf2] +@ CHECK: vand d4, d7, d3 @ encoding: [0x13,0x41,0x07,0xf2] + +@ CHECK: vand d4, d7, d3 @ encoding: [0x13,0x41,0x07,0xf2] +@ CHECK: vand d4, d7, d3 @ encoding: [0x13,0x41,0x07,0xf2] +@ CHECK: vand d4, d7, d3 @ encoding: [0x13,0x41,0x07,0xf2] +@ CHECK: vand d4, d7, d3 @ encoding: [0x13,0x41,0x07,0xf2] + +@ CHECK: vand d4, d7, d3 @ encoding: [0x13,0x41,0x07,0xf2] +@ CHECK: vand d4, d7, d3 @ encoding: [0x13,0x41,0x07,0xf2] + + vorr d4, d7, d3 + vorr.8 d4, d7, d3 + vorr.16 d4, d7, d3 + vorr.32 d4, d7, d3 + vorr.64 d4, d7, d3 + + vorr.i8 d4, d7, d3 + vorr.i16 d4, d7, d3 + vorr.i32 d4, d7, d3 + vorr.i64 d4, d7, d3 + + vorr.s8 d4, d7, d3 + vorr.s16 d4, d7, d3 + vorr.s32 q4, q7, q3 + vorr.s64 q4, q7, q3 + + vorr.u8 q4, q7, q3 + vorr.u16 q4, q7, q3 + vorr.u32 q4, q7, q3 + vorr.u64 q4, q7, q3 + + vorr.p8 q4, q7, q3 + vorr.p16 q4, q7, q3 + vorr.f32 q4, q7, q3 + vorr.f64 q4, q7, q3 + + vorr.f q4, q7, q3 + vorr.d q4, q7, q3 + +@ CHECK: vorr d4, d7, d3 @ encoding: [0x13,0x41,0x27,0xf2] +@ CHECK: vorr d4, d7, d3 @ encoding: [0x13,0x41,0x27,0xf2] +@ CHECK: vorr d4, d7, d3 @ encoding: [0x13,0x41,0x27,0xf2] +@ CHECK: vorr d4, d7, d3 @ encoding: [0x13,0x41,0x27,0xf2] +@ CHECK: vorr d4, d7, d3 @ encoding: [0x13,0x41,0x27,0xf2] + +@ CHECK: vorr d4, d7, d3 @ encoding: [0x13,0x41,0x27,0xf2] +@ CHECK: vorr d4, d7, d3 @ encoding: [0x13,0x41,0x27,0xf2] +@ CHECK: vorr d4, d7, d3 @ encoding: [0x13,0x41,0x27,0xf2] +@ CHECK: vorr d4, d7, d3 @ encoding: [0x13,0x41,0x27,0xf2] + +@ CHECK: vorr d4, d7, d3 @ encoding: [0x13,0x41,0x27,0xf2] +@ CHECK: vorr d4, d7, d3 @ encoding: [0x13,0x41,0x27,0xf2] +@ CHECK: vorr q4, q7, q3 @ encoding: [0x56,0x81,0x2e,0xf2] +@ CHECK: vorr q4, q7, q3 @ encoding: [0x56,0x81,0x2e,0xf2] + +@ CHECK: vorr q4, q7, q3 @ encoding: [0x56,0x81,0x2e,0xf2] +@ CHECK: vorr q4, q7, q3 @ encoding: [0x56,0x81,0x2e,0xf2] +@ CHECK: vorr q4, q7, q3 @ encoding: [0x56,0x81,0x2e,0xf2] +@ CHECK: vorr q4, q7, q3 @ encoding: [0x56,0x81,0x2e,0xf2] + +@ CHECK: vorr q4, q7, q3 @ encoding: [0x56,0x81,0x2e,0xf2] +@ CHECK: vorr q4, q7, q3 @ encoding: [0x56,0x81,0x2e,0xf2] +@ CHECK: vorr q4, q7, q3 @ encoding: [0x56,0x81,0x2e,0xf2] +@ CHECK: vorr q4, q7, q3 @ encoding: [0x56,0x81,0x2e,0xf2] + +@ CHECK: vorr q4, q7, q3 @ encoding: [0x56,0x81,0x2e,0xf2] +@ CHECK: vorr q4, q7, q3 @ encoding: [0x56,0x81,0x2e,0xf2] + +@ Two-operand aliases + vand.s8 q6, q5 + vand.s16 q7, q1 + vand.s32 q8, q2 + vand.f64 q8, q2 + + veor.8 q6, q5 + veor.p16 q7, q1 + veor.u32 q8, q2 + veor.d q8, q2 + + veor.i8 q6, q5 + veor.16 q7, q1 + veor.f q8, q2 + veor.i64 q8, q2 + +@ CHECK: vand q6, q6, q5 @ encoding: [0x5a,0xc1,0x0c,0xf2] +@ CHECK: vand q7, q7, q1 @ encoding: [0x52,0xe1,0x0e,0xf2] +@ CHECK: vand q8, q8, q2 @ encoding: [0xd4,0x01,0x40,0xf2] +@ CHECK: vand q8, q8, q2 @ encoding: [0xd4,0x01,0x40,0xf2] + +@ CHECK: veor q6, q6, q5 @ encoding: [0x5a,0xc1,0x0c,0xf3] +@ CHECK: veor q7, q7, q1 @ encoding: [0x52,0xe1,0x0e,0xf3] +@ CHECK: veor q8, q8, q2 @ encoding: [0xd4,0x01,0x40,0xf3] +@ CHECK: veor q8, q8, q2 @ encoding: [0xd4,0x01,0x40,0xf3] + +@ CHECK: veor q6, q6, q5 @ encoding: [0x5a,0xc1,0x0c,0xf3] +@ CHECK: veor q7, q7, q1 @ encoding: [0x52,0xe1,0x0e,0xf3] +@ CHECK: veor q8, q8, q2 @ encoding: [0xd4,0x01,0x40,0xf3] +@ CHECK: veor q8, q8, q2 @ encoding: [0xd4,0x01,0x40,0xf3] diff --git a/test/MC/ARM/neon-cmp-encoding.s b/test/MC/ARM/neon-cmp-encoding.s index d94e2f7..b3aedb8 100644 --- a/test/MC/ARM/neon-cmp-encoding.s +++ b/test/MC/ARM/neon-cmp-encoding.s @@ -111,3 +111,66 @@ @ CHECK: vcle.s8 d16, d16, #0 @ encoding: [0xa0,0x01,0xf1,0xf3] @ CHECK: vcgt.s8 d16, d16, #0 @ encoding: [0x20,0x00,0xf1,0xf3] @ CHECK: vclt.s8 d16, d16, #0 @ encoding: [0x20,0x02,0xf1,0xf3] + + + vclt.s8 q12, q13, q3 + vclt.s16 q12, q13, q3 + vclt.s32 q12, q13, q3 + vclt.u8 q12, q13, q3 + vclt.u16 q12, q13, q3 + vclt.u32 q12, q13, q3 + vclt.f32 q12, q13, q3 + + vclt.s8 d12, d13, d3 + vclt.s16 d12, d13, d3 + vclt.s32 d12, d13, d3 + vclt.u8 d12, d13, d3 + vclt.u16 d12, d13, d3 + vclt.u32 d12, d13, d3 + vclt.f32 d12, d13, d3 + +@ CHECK: vcgt.s8 q12, q3, q13 @ encoding: [0x6a,0x83,0x46,0xf2] +@ CHECK: vcgt.s16 q12, q3, q13 @ encoding: [0x6a,0x83,0x56,0xf2] +@ CHECK: vcgt.s32 q12, q3, q13 @ encoding: [0x6a,0x83,0x66,0xf2] +@ CHECK: vcgt.u8 q12, q3, q13 @ encoding: [0x6a,0x83,0x46,0xf3] +@ CHECK: vcgt.u16 q12, q3, q13 @ encoding: [0x6a,0x83,0x56,0xf3] +@ CHECK: vcgt.u32 q12, q3, q13 @ encoding: [0x6a,0x83,0x66,0xf3] +@ CHECK: vcgt.f32 q12, q3, q13 @ encoding: [0x6a,0x8e,0x66,0xf3] + +@ CHECK: vcgt.s8 d12, d3, d13 @ encoding: [0x0d,0xc3,0x03,0xf2] +@ CHECK: vcgt.s16 d12, d3, d13 @ encoding: [0x0d,0xc3,0x13,0xf2] +@ CHECK: vcgt.s32 d12, d3, d13 @ encoding: [0x0d,0xc3,0x23,0xf2] +@ CHECK: vcgt.u8 d12, d3, d13 @ encoding: [0x0d,0xc3,0x03,0xf3] +@ CHECK: vcgt.u16 d12, d3, d13 @ encoding: [0x0d,0xc3,0x13,0xf3] +@ CHECK: vcgt.u32 d12, d3, d13 @ encoding: [0x0d,0xc3,0x23,0xf3] +@ CHECK: vcgt.f32 d12, d3, d13 @ encoding: [0x0d,0xce,0x23,0xf3] + + vcle.s8 d16, d16, d17 + vcle.s16 d16, d16, d17 + vcle.s32 d16, d16, d17 + vcle.u8 d16, d16, d17 + vcle.u16 d16, d16, d17 + vcle.u32 d16, d16, d17 + vcle.f32 d16, d16, d17 + vcle.s8 q8, q8, q9 + vcle.s16 q8, q8, q9 + vcle.s32 q8, q8, q9 + vcle.u8 q8, q8, q9 + vcle.u16 q8, q8, q9 + vcle.u32 q8, q8, q9 + vcle.f32 q8, q8, q9 + +@ CHECK: vcge.s8 d16, d17, d16 @ encoding: [0xb0,0x03,0x41,0xf2] +@ CHECK: vcge.s16 d16, d17, d16 @ encoding: [0xb0,0x03,0x51,0xf2] +@ CHECK: vcge.s32 d16, d17, d16 @ encoding: [0xb0,0x03,0x61,0xf2] +@ CHECK: vcge.u8 d16, d17, d16 @ encoding: [0xb0,0x03,0x41,0xf3] +@ CHECK: vcge.u16 d16, d17, d16 @ encoding: [0xb0,0x03,0x51,0xf3] +@ CHECK: vcge.u32 d16, d17, d16 @ encoding: [0xb0,0x03,0x61,0xf3] +@ CHECK: vcge.f32 d16, d17, d16 @ encoding: [0xa0,0x0e,0x41,0xf3] +@ CHECK: vcge.s8 q8, q9, q8 @ encoding: [0xf0,0x03,0x42,0xf2] +@ CHECK: vcge.s16 q8, q9, q8 @ encoding: [0xf0,0x03,0x52,0xf2] +@ CHECK: vcge.s32 q8, q9, q8 @ encoding: [0xf0,0x03,0x62,0xf2] +@ CHECK: vcge.u8 q8, q9, q8 @ encoding: [0xf0,0x03,0x42,0xf3] +@ CHECK: vcge.u16 q8, q9, q8 @ encoding: [0xf0,0x03,0x52,0xf3] +@ CHECK: vcge.u32 q8, q9, q8 @ encoding: [0xf0,0x03,0x62,0xf3] +@ CHECK: vcge.f32 q8, q9, q8 @ encoding: [0xe0,0x0e,0x42,0xf3] diff --git a/test/MC/ARM/neon-minmax-encoding.s b/test/MC/ARM/neon-minmax-encoding.s index 2d0d8c9..b1eb258 100644 --- a/test/MC/ARM/neon-minmax-encoding.s +++ b/test/MC/ARM/neon-minmax-encoding.s @@ -1,58 +1,124 @@ @ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s -@ CHECK: vmin.s8 d16, d16, d17 @ encoding: [0xb1,0x06,0x40,0xf2] - vmin.s8 d16, d16, d17 -@ CHECK: vmin.s16 d16, d16, d17 @ encoding: [0xb1,0x06,0x50,0xf2] - vmin.s16 d16, d16, d17 -@ CHECK: vmin.s32 d16, d16, d17 @ encoding: [0xb1,0x06,0x60,0xf2] - vmin.s32 d16, d16, d17 -@ CHECK: vmin.u8 d16, d16, d17 @ encoding: [0xb1,0x06,0x40,0xf3] - vmin.u8 d16, d16, d17 -@ CHECK: vmin.u16 d16, d16, d17 @ encoding: [0xb1,0x06,0x50,0xf3] - vmin.u16 d16, d16, d17 -@ CHECK: vmin.u32 d16, d16, d17 @ encoding: [0xb1,0x06,0x60,0xf3] - vmin.u32 d16, d16, d17 -@ CHECK: vmin.f32 d16, d16, d17 @ encoding: [0xa1,0x0f,0x60,0xf2] - vmin.f32 d16, d16, d17 -@ CHECK: vmin.s8 q8, q8, q9 @ encoding: [0xf2,0x06,0x40,0xf2] - vmin.s8 q8, q8, q9 -@ CHECK: vmin.s16 q8, q8, q9 @ encoding: [0xf2,0x06,0x50,0xf2] - vmin.s16 q8, q8, q9 -@ CHECK: vmin.s32 q8, q8, q9 @ encoding: [0xf2,0x06,0x60,0xf2] - vmin.s32 q8, q8, q9 -@ CHECK: vmin.u8 q8, q8, q9 @ encoding: [0xf2,0x06,0x40,0xf3] - vmin.u8 q8, q8, q9 -@ CHECK: vmin.u16 q8, q8, q9 @ encoding: [0xf2,0x06,0x50,0xf3] - vmin.u16 q8, q8, q9 -@ CHECK: vmin.u32 q8, q8, q9 @ encoding: [0xf2,0x06,0x60,0xf3] - vmin.u32 q8, q8, q9 -@ CHECK: vmin.f32 q8, q8, q9 @ encoding: [0xe2,0x0f,0x60,0xf2] - vmin.f32 q8, q8, q9 -@ CHECK: vmax.s8 d16, d16, d17 @ encoding: [0xa1,0x06,0x40,0xf2] - vmax.s8 d16, d16, d17 -@ CHECK: vmax.s16 d16, d16, d17 @ encoding: [0xa1,0x06,0x50,0xf2] - vmax.s16 d16, d16, d17 -@ CHECK: vmax.s32 d16, d16, d17 @ encoding: [0xa1,0x06,0x60,0xf2] - vmax.s32 d16, d16, d17 -@ CHECK: vmax.u8 d16, d16, d17 @ encoding: [0xa1,0x06,0x40,0xf3] - vmax.u8 d16, d16, d17 -@ CHECK: vmax.u16 d16, d16, d17 @ encoding: [0xa1,0x06,0x50,0xf3] - vmax.u16 d16, d16, d17 -@ CHECK: vmax.u32 d16, d16, d17 @ encoding: [0xa1,0x06,0x60,0xf3] - vmax.u32 d16, d16, d17 -@ CHECK: vmax.f32 d16, d16, d17 @ encoding: [0xa1,0x0f,0x40,0xf2] - vmax.f32 d16, d16, d17 -@ CHECK: vmax.s8 q8, q8, q9 @ encoding: [0xe2,0x06,0x40,0xf2] - vmax.s8 q8, q8, q9 -@ CHECK: vmax.s16 q8, q8, q9 @ encoding: [0xe2,0x06,0x50,0xf2] - vmax.s16 q8, q8, q9 + vmax.s8 d1, d2, d3 + vmax.s16 d4, d5, d6 + vmax.s32 d7, d8, d9 + vmax.u8 d10, d11, d12 + vmax.u16 d13, d14, d15 + vmax.u32 d16, d17, d18 + vmax.f32 d19, d20, d21 + + vmax.s8 d2, d3 + vmax.s16 d5, d6 + vmax.s32 d8, d9 + vmax.u8 d11, d12 + vmax.u16 d14, d15 + vmax.u32 d17, d18 + vmax.f32 d20, d21 + + vmax.s8 q1, q2, q3 + vmax.s16 q4, q5, q6 + vmax.s32 q7, q8, q9 + vmax.u8 q10, q11, q12 + vmax.u16 q13, q14, q15 + vmax.u32 q6, q7, q8 + vmax.f32 q9, q5, q1 + + vmax.s8 q2, q3 + vmax.s16 q5, q6 + vmax.s32 q8, q9 + vmax.u8 q11, q2 + vmax.u16 q4, q5 + vmax.u32 q7, q8 + vmax.f32 q2, q1 + +@ CHECK: vmax.s8 d1, d2, d3 @ encoding: [0x03,0x16,0x02,0xf2] +@ CHECK: vmax.s16 d4, d5, d6 @ encoding: [0x06,0x46,0x15,0xf2] +@ CHECK: vmax.s32 d7, d8, d9 @ encoding: [0x09,0x76,0x28,0xf2] +@ CHECK: vmax.u8 d10, d11, d12 @ encoding: [0x0c,0xa6,0x0b,0xf3] +@ CHECK: vmax.u16 d13, d14, d15 @ encoding: [0x0f,0xd6,0x1e,0xf3] +@ CHECK: vmax.u32 d16, d17, d18 @ encoding: [0xa2,0x06,0x61,0xf3] +@ CHECK: vmax.f32 d19, d20, d21 @ encoding: [0xa5,0x3f,0x44,0xf2] +@ CHECK: vmax.s8 d2, d2, d3 @ encoding: [0x03,0x26,0x02,0xf2] +@ CHECK: vmax.s16 d5, d5, d6 @ encoding: [0x06,0x56,0x15,0xf2] +@ CHECK: vmax.s32 d8, d8, d9 @ encoding: [0x09,0x86,0x28,0xf2] +@ CHECK: vmax.u8 d11, d11, d12 @ encoding: [0x0c,0xb6,0x0b,0xf3] +@ CHECK: vmax.u16 d14, d14, d15 @ encoding: [0x0f,0xe6,0x1e,0xf3] +@ CHECK: vmax.u32 d17, d17, d18 @ encoding: [0xa2,0x16,0x61,0xf3] +@ CHECK: vmax.f32 d20, d20, d21 @ encoding: [0xa5,0x4f,0x44,0xf2] +@ CHECK: vmax.s8 q1, q2, q3 @ encoding: [0x46,0x26,0x04,0xf2] +@ CHECK: vmax.s16 q4, q5, q6 @ encoding: [0x4c,0x86,0x1a,0xf2] +@ CHECK: vmax.s32 q7, q8, q9 @ encoding: [0xe2,0xe6,0x20,0xf2] +@ CHECK: vmax.u8 q10, q11, q12 @ encoding: [0xe8,0x46,0x46,0xf3] +@ CHECK: vmax.u16 q13, q14, q15 @ encoding: [0xee,0xa6,0x5c,0xf3] +@ CHECK: vmax.u32 q6, q7, q8 @ encoding: [0x60,0xc6,0x2e,0xf3] +@ CHECK: vmax.f32 q9, q5, q1 @ encoding: [0x42,0x2f,0x4a,0xf2] +@ CHECK: vmax.s8 q2, q2, q3 @ encoding: [0x46,0x46,0x04,0xf2] +@ CHECK: vmax.s16 q5, q5, q6 @ encoding: [0x4c,0xa6,0x1a,0xf2] @ CHECK: vmax.s32 q8, q8, q9 @ encoding: [0xe2,0x06,0x60,0xf2] - vmax.s32 q8, q8, q9 -@ CHECK: vmax.u8 q8, q8, q9 @ encoding: [0xe2,0x06,0x40,0xf3] - vmax.u8 q8, q8, q9 -@ CHECK: vmax.u16 q8, q8, q9 @ encoding: [0xe2,0x06,0x50,0xf3] - vmax.u16 q8, q8, q9 -@ CHECK: vmax.u32 q8, q8, q9 @ encoding: [0xe2,0x06,0x60,0xf3] - vmax.u32 q8, q8, q9 -@ CHECK: vmax.f32 q8, q8, q9 @ encoding: [0xe2,0x0f,0x40,0xf2] - vmax.f32 q8, q8, q9 +@ CHECK: vmax.u8 q11, q11, q2 @ encoding: [0xc4,0x66,0x46,0xf3] +@ CHECK: vmax.u16 q4, q4, q5 @ encoding: [0x4a,0x86,0x18,0xf3] +@ CHECK: vmax.u32 q7, q7, q8 @ encoding: [0x60,0xe6,0x2e,0xf3] +@ CHECK: vmax.f32 q2, q2, q1 @ encoding: [0x42,0x4f,0x04,0xf2] + + + vmin.s8 d1, d2, d3 + vmin.s16 d4, d5, d6 + vmin.s32 d7, d8, d9 + vmin.u8 d10, d11, d12 + vmin.u16 d13, d14, d15 + vmin.u32 d16, d17, d18 + vmin.f32 d19, d20, d21 + + vmin.s8 d2, d3 + vmin.s16 d5, d6 + vmin.s32 d8, d9 + vmin.u8 d11, d12 + vmin.u16 d14, d15 + vmin.u32 d17, d18 + vmin.f32 d20, d21 + + vmin.s8 q1, q2, q3 + vmin.s16 q4, q5, q6 + vmin.s32 q7, q8, q9 + vmin.u8 q10, q11, q12 + vmin.u16 q13, q14, q15 + vmin.u32 q6, q7, q8 + vmin.f32 q9, q5, q1 + + vmin.s8 q2, q3 + vmin.s16 q5, q6 + vmin.s32 q8, q9 + vmin.u8 q11, q2 + vmin.u16 q4, q5 + vmin.u32 q7, q8 + vmin.f32 q2, q1 + +@ CHECK: vmin.s8 d1, d2, d3 @ encoding: [0x13,0x16,0x02,0xf2] +@ CHECK: vmin.s16 d4, d5, d6 @ encoding: [0x16,0x46,0x15,0xf2] +@ CHECK: vmin.s32 d7, d8, d9 @ encoding: [0x19,0x76,0x28,0xf2] +@ CHECK: vmin.u8 d10, d11, d12 @ encoding: [0x1c,0xa6,0x0b,0xf3] +@ CHECK: vmin.u16 d13, d14, d15 @ encoding: [0x1f,0xd6,0x1e,0xf3] +@ CHECK: vmin.u32 d16, d17, d18 @ encoding: [0xb2,0x06,0x61,0xf3] +@ CHECK: vmin.f32 d19, d20, d21 @ encoding: [0xa5,0x3f,0x64,0xf2] +@ CHECK: vmin.s8 d2, d2, d3 @ encoding: [0x13,0x26,0x02,0xf2] +@ CHECK: vmin.s16 d5, d5, d6 @ encoding: [0x16,0x56,0x15,0xf2] +@ CHECK: vmin.s32 d8, d8, d9 @ encoding: [0x19,0x86,0x28,0xf2] +@ CHECK: vmin.u8 d11, d11, d12 @ encoding: [0x1c,0xb6,0x0b,0xf3] +@ CHECK: vmin.u16 d14, d14, d15 @ encoding: [0x1f,0xe6,0x1e,0xf3] +@ CHECK: vmin.u32 d17, d17, d18 @ encoding: [0xb2,0x16,0x61,0xf3] +@ CHECK: vmin.f32 d20, d20, d21 @ encoding: [0xa5,0x4f,0x64,0xf2] +@ CHECK: vmin.s8 q1, q2, q3 @ encoding: [0x56,0x26,0x04,0xf2] +@ CHECK: vmin.s16 q4, q5, q6 @ encoding: [0x5c,0x86,0x1a,0xf2] +@ CHECK: vmin.s32 q7, q8, q9 @ encoding: [0xf2,0xe6,0x20,0xf2] +@ CHECK: vmin.u8 q10, q11, q12 @ encoding: [0xf8,0x46,0x46,0xf3] +@ CHECK: vmin.u16 q13, q14, q15 @ encoding: [0xfe,0xa6,0x5c,0xf3] +@ CHECK: vmin.u32 q6, q7, q8 @ encoding: [0x70,0xc6,0x2e,0xf3] +@ CHECK: vmin.f32 q9, q5, q1 @ encoding: [0x42,0x2f,0x6a,0xf2] +@ CHECK: vmin.s8 q2, q2, q3 @ encoding: [0x56,0x46,0x04,0xf2] +@ CHECK: vmin.s16 q5, q5, q6 @ encoding: [0x5c,0xa6,0x1a,0xf2] +@ CHECK: vmin.s32 q8, q8, q9 @ encoding: [0xf2,0x06,0x60,0xf2] +@ CHECK: vmin.u8 q11, q11, q2 @ encoding: [0xd4,0x66,0x46,0xf3] +@ CHECK: vmin.u16 q4, q4, q5 @ encoding: [0x5a,0x86,0x18,0xf3] +@ CHECK: vmin.u32 q7, q7, q8 @ encoding: [0x70,0xe6,0x2e,0xf3] +@ CHECK: vmin.f32 q2, q2, q1 @ encoding: [0x42,0x4f,0x24,0xf2] diff --git a/test/MC/ARM/neon-mov-encoding.s b/test/MC/ARM/neon-mov-encoding.s index 02eec12..6f26a13 100644 --- a/test/MC/ARM/neon-mov-encoding.s +++ b/test/MC/ARM/neon-mov-encoding.s @@ -1,5 +1,4 @@ @ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s -@ XFAIL: * vmov.i8 d16, #0x8 vmov.i16 d16, #0x10 @@ -19,9 +18,9 @@ @ CHECK: vmov.i32 d16, #0x2000 @ encoding: [0x10,0x02,0xc2,0xf2] @ CHECK: vmov.i32 d16, #0x200000 @ encoding: [0x10,0x04,0xc2,0xf2] @ CHECK: vmov.i32 d16, #0x20000000 @ encoding: [0x10,0x06,0xc2,0xf2] -@ CHECK: vmov.i32 d16, #0x20FF @ encoding: [0x10,0x0c,0xc2,0xf2] -@ CHECK: vmov.i32 d16, #0x20FFFF @ encoding: [0x10,0x0d,0xc2,0xf2] -@ CHECK: vmov.i64 d16, #0xFF0000FF0000FFFF @ encoding: [0x33,0x0e,0xc1,0xf3] +@ CHECK: vmov.i32 d16, #0x20ff @ encoding: [0x10,0x0c,0xc2,0xf2] +@ CHECK: vmov.i32 d16, #0x20ffff @ encoding: [0x10,0x0d,0xc2,0xf2] +@ CHECK: vmov.i64 d16, #0xff0000ff0000ffff @ encoding: [0x33,0x0e,0xc1,0xf3] @@ -43,9 +42,9 @@ @ CHECK: vmov.i32 q8, #0x2000 @ encoding: [0x50,0x02,0xc2,0xf2] @ CHECK: vmov.i32 q8, #0x200000 @ encoding: [0x50,0x04,0xc2,0xf2] @ CHECK: vmov.i32 q8, #0x20000000 @ encoding: [0x50,0x06,0xc2,0xf2] -@ CHECK: vmov.i32 q8, #0x20FF @ encoding: [0x50,0x0c,0xc2,0xf2] -@ CHECK: vmov.i32 q8, #0x20FFFF @ encoding: [0x50,0x0d,0xc2,0xf2] -@ CHECK: vmov.i64 q8, #0xFF0000FF0000FFFF @ encoding: [0x73,0x0e,0xc1,0xf3] +@ CHECK: vmov.i32 q8, #0x20ff @ encoding: [0x50,0x0c,0xc2,0xf2] +@ CHECK: vmov.i32 q8, #0x20ffff @ encoding: [0x50,0x0d,0xc2,0xf2] +@ CHECK: vmov.i64 q8, #0xff0000ff0000ffff @ encoding: [0x73,0x0e,0xc1,0xf3] vmvn.i16 d16, #0x10 vmvn.i16 d16, #0x1000 @@ -62,8 +61,8 @@ @ CHECK: vmvn.i32 d16, #0x2000 @ encoding: [0x30,0x02,0xc2,0xf2] @ CHECK: vmvn.i32 d16, #0x200000 @ encoding: [0x30,0x04,0xc2,0xf2] @ CHECK: vmvn.i32 d16, #0x20000000 @ encoding: [0x30,0x06,0xc2,0xf2] -@ CHECK: vmvn.i32 d16, #0x20FF @ encoding: [0x30,0x0c,0xc2,0xf2] -@ CHECK: vmvn.i32 d16, #0x20FFFF @ encoding: [0x30,0x0d,0xc2,0xf2] +@ CHECK: vmvn.i32 d16, #0x20ff @ encoding: [0x30,0x0c,0xc2,0xf2] +@ CHECK: vmvn.i32 d16, #0x20ffff @ encoding: [0x30,0x0d,0xc2,0xf2] vmovl.s8 q8, d16 vmovl.s16 q8, d16 diff --git a/test/MC/ARM/neon-mul-accum-encoding.s b/test/MC/ARM/neon-mul-accum-encoding.s index ed9ceb3..e71ad71 100644 --- a/test/MC/ARM/neon-mul-accum-encoding.s +++ b/test/MC/ARM/neon-mul-accum-encoding.s @@ -1,66 +1,94 @@ @ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s -@ CHECK: vmla.i8 d16, d18, d17 @ encoding: [0xa1,0x09,0x42,0xf2] vmla.i8 d16, d18, d17 -@ CHECK: vmla.i16 d16, d18, d17 @ encoding: [0xa1,0x09,0x52,0xf2] vmla.i16 d16, d18, d17 -@ CHECK: vmla.i32 d16, d18, d17 @ encoding: [0xa1,0x09,0x62,0xf2] vmla.i32 d16, d18, d17 -@ CHECK: vmla.f32 d16, d18, d17 @ encoding: [0xb1,0x0d,0x42,0xf2] vmla.f32 d16, d18, d17 -@ CHECK: vmla.i8 q9, q8, q10 @ encoding: [0xe4,0x29,0x40,0xf2] vmla.i8 q9, q8, q10 -@ CHECK: vmla.i16 q9, q8, q10 @ encoding: [0xe4,0x29,0x50,0xf2] vmla.i16 q9, q8, q10 -@ CHECK: vmla.i32 q9, q8, q10 @ encoding: [0xe4,0x29,0x60,0xf2] vmla.i32 q9, q8, q10 -@ CHECK: vmla.f32 q9, q8, q10 @ encoding: [0xf4,0x2d,0x40,0xf2] vmla.f32 q9, q8, q10 -@ CHECK: vmlal.s8 q8, d19, d18 @ encoding: [0xa2,0x08,0xc3,0xf2] + vmla.i32 q12, q8, d3[0] + +@ CHECK: vmla.i8 d16, d18, d17 @ encoding: [0xa1,0x09,0x42,0xf2] +@ CHECK: vmla.i16 d16, d18, d17 @ encoding: [0xa1,0x09,0x52,0xf2] +@ CHECK: vmla.i32 d16, d18, d17 @ encoding: [0xa1,0x09,0x62,0xf2] +@ CHECK: vmla.f32 d16, d18, d17 @ encoding: [0xb1,0x0d,0x42,0xf2] +@ CHECK: vmla.i8 q9, q8, q10 @ encoding: [0xe4,0x29,0x40,0xf2] +@ CHECK: vmla.i16 q9, q8, q10 @ encoding: [0xe4,0x29,0x50,0xf2] +@ CHECK: vmla.i32 q9, q8, q10 @ encoding: [0xe4,0x29,0x60,0xf2] +@ CHECK: vmla.f32 q9, q8, q10 @ encoding: [0xf4,0x2d,0x40,0xf2] +@ CHECK: vmla.i32 q12, q8, d3[0] @ encoding: [0xc3,0x80,0xe0,0xf3] + + vmlal.s8 q8, d19, d18 -@ CHECK: vmlal.s16 q8, d19, d18 @ encoding: [0xa2,0x08,0xd3,0xf2] vmlal.s16 q8, d19, d18 -@ CHECK: vmlal.s32 q8, d19, d18 @ encoding: [0xa2,0x08,0xe3,0xf2] vmlal.s32 q8, d19, d18 -@ CHECK: vmlal.u8 q8, d19, d18 @ encoding: [0xa2,0x08,0xc3,0xf3] vmlal.u8 q8, d19, d18 -@ CHECK: vmlal.u16 q8, d19, d18 @ encoding: [0xa2,0x08,0xd3,0xf3] vmlal.u16 q8, d19, d18 -@ CHECK: vmlal.u32 q8, d19, d18 @ encoding: [0xa2,0x08,0xe3,0xf3] vmlal.u32 q8, d19, d18 -@ CHECK: vqdmlal.s16 q8, d19, d18 @ encoding: [0xa2,0x09,0xd3,0xf2] + +@ CHECK: vmlal.s8 q8, d19, d18 @ encoding: [0xa2,0x08,0xc3,0xf2] +@ CHECK: vmlal.s16 q8, d19, d18 @ encoding: [0xa2,0x08,0xd3,0xf2] +@ CHECK: vmlal.s32 q8, d19, d18 @ encoding: [0xa2,0x08,0xe3,0xf2] +@ CHECK: vmlal.u8 q8, d19, d18 @ encoding: [0xa2,0x08,0xc3,0xf3] +@ CHECK: vmlal.u16 q8, d19, d18 @ encoding: [0xa2,0x08,0xd3,0xf3] +@ CHECK: vmlal.u32 q8, d19, d18 @ encoding: [0xa2,0x08,0xe3,0xf3] + + vqdmlal.s16 q8, d19, d18 -@ CHECK: vqdmlal.s32 q8, d19, d18 @ encoding: [0xa2,0x09,0xe3,0xf2] vqdmlal.s32 q8, d19, d18 -@ CHECK: vmls.i8 d16, d18, d17 @ encoding: [0xa1,0x09,0x42,0xf3] + vqdmlal.s16 q11, d11, d7[0] + vqdmlal.s16 q11, d11, d7[1] + vqdmlal.s16 q11, d11, d7[2] + vqdmlal.s16 q11, d11, d7[3] + +@ CHECK: vqdmlal.s16 q8, d19, d18 @ encoding: [0xa2,0x09,0xd3,0xf2] +@ CHECK: vqdmlal.s32 q8, d19, d18 @ encoding: [0xa2,0x09,0xe3,0xf2] +@ CHECK: vqdmlal.s16 q11, d11, d7[0] @ encoding: [0x47,0x63,0xdb,0xf2] +@ CHECK: vqdmlal.s16 q11, d11, d7[1] @ encoding: [0x4f,0x63,0xdb,0xf2] +@ CHECK: vqdmlal.s16 q11, d11, d7[2] @ encoding: [0x67,0x63,0xdb,0xf2] +@ CHECK: vqdmlal.s16 q11, d11, d7[3] @ encoding: [0x6f,0x63,0xdb,0xf2] + + vmls.i8 d16, d18, d17 -@ CHECK: vmls.i16 d16, d18, d17 @ encoding: [0xa1,0x09,0x52,0xf3] vmls.i16 d16, d18, d17 -@ CHECK: vmls.i32 d16, d18, d17 @ encoding: [0xa1,0x09,0x62,0xf3] vmls.i32 d16, d18, d17 -@ CHECK: vmls.f32 d16, d18, d17 @ encoding: [0xb1,0x0d,0x62,0xf2] vmls.f32 d16, d18, d17 -@ CHECK: vmls.i8 q9, q8, q10 @ encoding: [0xe4,0x29,0x40,0xf3] vmls.i8 q9, q8, q10 -@ CHECK: vmls.i16 q9, q8, q10 @ encoding: [0xe4,0x29,0x50,0xf3] vmls.i16 q9, q8, q10 -@ CHECK: vmls.i32 q9, q8, q10 @ encoding: [0xe4,0x29,0x60,0xf3] vmls.i32 q9, q8, q10 -@ CHECK: vmls.f32 q9, q8, q10 @ encoding: [0xf4,0x2d,0x60,0xf2] vmls.f32 q9, q8, q10 -@ CHECK: vmlsl.s8 q8, d19, d18 @ encoding: [0xa2,0x0a,0xc3,0xf2] + vmls.i16 q4, q12, d6[2] + +@ CHECK: vmls.i8 d16, d18, d17 @ encoding: [0xa1,0x09,0x42,0xf3] +@ CHECK: vmls.i16 d16, d18, d17 @ encoding: [0xa1,0x09,0x52,0xf3] +@ CHECK: vmls.i32 d16, d18, d17 @ encoding: [0xa1,0x09,0x62,0xf3] +@ CHECK: vmls.f32 d16, d18, d17 @ encoding: [0xb1,0x0d,0x62,0xf2] +@ CHECK: vmls.i8 q9, q8, q10 @ encoding: [0xe4,0x29,0x40,0xf3] +@ CHECK: vmls.i16 q9, q8, q10 @ encoding: [0xe4,0x29,0x50,0xf3] +@ CHECK: vmls.i32 q9, q8, q10 @ encoding: [0xe4,0x29,0x60,0xf3] +@ CHECK: vmls.f32 q9, q8, q10 @ encoding: [0xf4,0x2d,0x60,0xf2] +@ CHECK: vmls.i16 q4, q12, d6[2] @ encoding: [0xe6,0x84,0x98,0xf3] + + vmlsl.s8 q8, d19, d18 -@ CHECK: vmlsl.s16 q8, d19, d18 @ encoding: [0xa2,0x0a,0xd3,0xf2] vmlsl.s16 q8, d19, d18 -@ CHECK: vmlsl.s32 q8, d19, d18 @ encoding: [0xa2,0x0a,0xe3,0xf2] vmlsl.s32 q8, d19, d18 -@ CHECK: vmlsl.u8 q8, d19, d18 @ encoding: [0xa2,0x0a,0xc3,0xf3] vmlsl.u8 q8, d19, d18 -@ CHECK: vmlsl.u16 q8, d19, d18 @ encoding: [0xa2,0x0a,0xd3,0xf3] vmlsl.u16 q8, d19, d18 -@ CHECK: vmlsl.u32 q8, d19, d18 @ encoding: [0xa2,0x0a,0xe3,0xf3] vmlsl.u32 q8, d19, d18 -@ CHECK: vqdmlsl.s16 q8, d19, d18 @ encoding: [0xa2,0x0b,0xd3,0xf2] + +@ CHECK: vmlsl.s8 q8, d19, d18 @ encoding: [0xa2,0x0a,0xc3,0xf2] +@ CHECK: vmlsl.s16 q8, d19, d18 @ encoding: [0xa2,0x0a,0xd3,0xf2] +@ CHECK: vmlsl.s32 q8, d19, d18 @ encoding: [0xa2,0x0a,0xe3,0xf2] +@ CHECK: vmlsl.u8 q8, d19, d18 @ encoding: [0xa2,0x0a,0xc3,0xf3] +@ CHECK: vmlsl.u16 q8, d19, d18 @ encoding: [0xa2,0x0a,0xd3,0xf3] +@ CHECK: vmlsl.u32 q8, d19, d18 @ encoding: [0xa2,0x0a,0xe3,0xf3] + + vqdmlsl.s16 q8, d19, d18 -@ CHECK: vqdmlsl.s32 q8, d19, d18 @ encoding: [0xa2,0x0b,0xe3,0xf2] vqdmlsl.s32 q8, d19, d18 + +@ CHECK: vqdmlsl.s16 q8, d19, d18 @ encoding: [0xa2,0x0b,0xd3,0xf2] +@ CHECK: vqdmlsl.s32 q8, d19, d18 @ encoding: [0xa2,0x0b,0xe3,0xf2] diff --git a/test/MC/ARM/neon-mul-encoding.s b/test/MC/ARM/neon-mul-encoding.s index 4dc7803..d6bc1f3 100644 --- a/test/MC/ARM/neon-mul-encoding.s +++ b/test/MC/ARM/neon-mul-encoding.s @@ -1,82 +1,168 @@ @ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s - vmla.i8 d16, d18, d17 - vmla.i16 d16, d18, d17 - vmla.i32 d16, d18, d17 - vmla.f32 d16, d18, d17 - vmla.i8 q9, q8, q10 - vmla.i16 q9, q8, q10 - vmla.i32 q9, q8, q10 - vmla.f32 q9, q8, q10 - -@ CHECK: vmla.i8 d16, d18, d17 @ encoding: [0xa1,0x09,0x42,0xf2] -@ CHECK: vmla.i16 d16, d18, d17 @ encoding: [0xa1,0x09,0x52,0xf2] -@ CHECK: vmla.i32 d16, d18, d17 @ encoding: [0xa1,0x09,0x62,0xf2] -@ CHECK: vmla.f32 d16, d18, d17 @ encoding: [0xb1,0x0d,0x42,0xf2] -@ CHECK: vmla.i8 q9, q8, q10 @ encoding: [0xe4,0x29,0x40,0xf2] -@ CHECK: vmla.i16 q9, q8, q10 @ encoding: [0xe4,0x29,0x50,0xf2] -@ CHECK: vmla.i32 q9, q8, q10 @ encoding: [0xe4,0x29,0x60,0xf2] -@ CHECK: vmla.f32 q9, q8, q10 @ encoding: [0xf4,0x2d,0x40,0xf2] - - - vmlal.s8 q8, d19, d18 - vmlal.s16 q8, d19, d18 - vmlal.s32 q8, d19, d18 - vmlal.u8 q8, d19, d18 - vmlal.u16 q8, d19, d18 - vmlal.u32 q8, d19, d18 - -@ CHECK: vmlal.s8 q8, d19, d18 @ encoding: [0xa2,0x08,0xc3,0xf2] -@ CHECK: vmlal.s16 q8, d19, d18 @ encoding: [0xa2,0x08,0xd3,0xf2] -@ CHECK: vmlal.s32 q8, d19, d18 @ encoding: [0xa2,0x08,0xe3,0xf2] -@ CHECK: vmlal.u8 q8, d19, d18 @ encoding: [0xa2,0x08,0xc3,0xf3] -@ CHECK: vmlal.u16 q8, d19, d18 @ encoding: [0xa2,0x08,0xd3,0xf3] -@ CHECK: vmlal.u32 q8, d19, d18 @ encoding: [0xa2,0x08,0xe3,0xf3] - - - vqdmlal.s16 q8, d19, d18 - vqdmlal.s32 q8, d19, d18 - -@ CHECK: vqdmlal.s16 q8, d19, d18 @ encoding: [0xa2,0x09,0xd3,0xf2] -@ CHECK: vqdmlal.s32 q8, d19, d18 @ encoding: [0xa2,0x09,0xe3,0xf2] - - - vmls.i8 d16, d18, d17 - vmls.i16 d16, d18, d17 - vmls.i32 d16, d18, d17 - vmls.f32 d16, d18, d17 - vmls.i8 q9, q8, q10 - vmls.i16 q9, q8, q10 - vmls.i32 q9, q8, q10 - vmls.f32 q9, q8, q10 - -@ CHECK: vmls.i8 d16, d18, d17 @ encoding: [0xa1,0x09,0x42,0xf3] -@ CHECK: vmls.i16 d16, d18, d17 @ encoding: [0xa1,0x09,0x52,0xf3] -@ CHECK: vmls.i32 d16, d18, d17 @ encoding: [0xa1,0x09,0x62,0xf3] -@ CHECK: vmls.f32 d16, d18, d17 @ encoding: [0xb1,0x0d,0x62,0xf2] -@ CHECK: vmls.i8 q9, q8, q10 @ encoding: [0xe4,0x29,0x40,0xf3] -@ CHECK: vmls.i16 q9, q8, q10 @ encoding: [0xe4,0x29,0x50,0xf3] -@ CHECK: vmls.i32 q9, q8, q10 @ encoding: [0xe4,0x29,0x60,0xf3] -@ CHECK: vmls.f32 q9, q8, q10 @ encoding: [0xf4,0x2d,0x60,0xf2] - - - vmlsl.s8 q8, d19, d18 - vmlsl.s16 q8, d19, d18 - vmlsl.s32 q8, d19, d18 - vmlsl.u8 q8, d19, d18 - vmlsl.u16 q8, d19, d18 - vmlsl.u32 q8, d19, d18 - -@ CHECK: vmlsl.s8 q8, d19, d18 @ encoding: [0xa2,0x0a,0xc3,0xf2] -@ CHECK: vmlsl.s16 q8, d19, d18 @ encoding: [0xa2,0x0a,0xd3,0xf2] -@ CHECK: vmlsl.s32 q8, d19, d18 @ encoding: [0xa2,0x0a,0xe3,0xf2] -@ CHECK: vmlsl.u8 q8, d19, d18 @ encoding: [0xa2,0x0a,0xc3,0xf3] -@ CHECK: vmlsl.u16 q8, d19, d18 @ encoding: [0xa2,0x0a,0xd3,0xf3] -@ CHECK: vmlsl.u32 q8, d19, d18 @ encoding: [0xa2,0x0a,0xe3,0xf3] - - - vqdmlsl.s16 q8, d19, d18 - vqdmlsl.s32 q8, d19, d18 - -@ CHECK: vqdmlsl.s16 q8, d19, d18 @ encoding: [0xa2,0x0b,0xd3,0xf2] -@ CHECK: vqdmlsl.s32 q8, d19, d18 @ encoding: [0xa2,0x0b,0xe3,0xf2] + vmul.i8 d16, d16, d17 + vmul.i16 d16, d16, d17 + vmul.i32 d16, d16, d17 + vmul.f32 d16, d16, d17 + vmul.i8 q8, q8, q9 + vmul.i16 q8, q8, q9 + vmul.i32 q8, q8, q9 + vmul.f32 q8, q8, q9 + vmul.p8 d16, d16, d17 + vmul.p8 q8, q8, q9 + vmul.i16 d18, d8, d0[3] + + vmul.i8 d16, d17 + vmul.i16 d16, d17 + vmul.i32 d16, d17 + vmul.f32 d16, d17 + vmul.i8 q8, q9 + vmul.i16 q8, q9 + vmul.i32 q8, q9 + vmul.f32 q8, q9 + vmul.p8 d16, d17 + vmul.p8 q8, q9 + +@ CHECK: vmul.i8 d16, d16, d17 @ encoding: [0xb1,0x09,0x40,0xf2] +@ CHECK: vmul.i16 d16, d16, d17 @ encoding: [0xb1,0x09,0x50,0xf2] +@ CHECK: vmul.i32 d16, d16, d17 @ encoding: [0xb1,0x09,0x60,0xf2] +@ CHECK: vmul.f32 d16, d16, d17 @ encoding: [0xb1,0x0d,0x40,0xf3] +@ CHECK: vmul.i8 q8, q8, q9 @ encoding: [0xf2,0x09,0x40,0xf2] +@ CHECK: vmul.i16 q8, q8, q9 @ encoding: [0xf2,0x09,0x50,0xf2] +@ CHECK: vmul.i32 q8, q8, q9 @ encoding: [0xf2,0x09,0x60,0xf2] +@ CHECK: vmul.f32 q8, q8, q9 @ encoding: [0xf2,0x0d,0x40,0xf3] +@ CHECK: vmul.p8 d16, d16, d17 @ encoding: [0xb1,0x09,0x40,0xf3] +@ CHECK: vmul.p8 q8, q8, q9 @ encoding: [0xf2,0x09,0x40,0xf3] +@ CHECK: vmul.i16 d18, d8, d0[3] @ encoding: [0x68,0x28,0xd8,0xf2] + +@ CHECK: vmul.i8 d16, d16, d17 @ encoding: [0xb1,0x09,0x40,0xf2] +@ CHECK: vmul.i16 d16, d16, d17 @ encoding: [0xb1,0x09,0x50,0xf2] +@ CHECK: vmul.i32 d16, d16, d17 @ encoding: [0xb1,0x09,0x60,0xf2] +@ CHECK: vmul.f32 d16, d16, d17 @ encoding: [0xb1,0x0d,0x40,0xf3] +@ CHECK: vmul.i8 q8, q8, q9 @ encoding: [0xf2,0x09,0x40,0xf2] +@ CHECK: vmul.i16 q8, q8, q9 @ encoding: [0xf2,0x09,0x50,0xf2] +@ CHECK: vmul.i32 q8, q8, q9 @ encoding: [0xf2,0x09,0x60,0xf2] +@ CHECK: vmul.f32 q8, q8, q9 @ encoding: [0xf2,0x0d,0x40,0xf3] +@ CHECK: vmul.p8 d16, d16, d17 @ encoding: [0xb1,0x09,0x40,0xf3] +@ CHECK: vmul.p8 q8, q8, q9 @ encoding: [0xf2,0x09,0x40,0xf3] + + + vqdmulh.s16 d16, d16, d17 + vqdmulh.s32 d16, d16, d17 + vqdmulh.s16 q8, q8, q9 + vqdmulh.s32 q8, q8, q9 + vqdmulh.s16 d16, d17 + vqdmulh.s32 d16, d17 + vqdmulh.s16 q8, q9 + vqdmulh.s32 q8, q9 + vqdmulh.s16 d11, d2, d3[0] + +@ CHECK: vqdmulh.s16 d16, d16, d17 @ encoding: [0xa1,0x0b,0x50,0xf2] +@ CHECK: vqdmulh.s32 d16, d16, d17 @ encoding: [0xa1,0x0b,0x60,0xf2] +@ CHECK: vqdmulh.s16 q8, q8, q9 @ encoding: [0xe2,0x0b,0x50,0xf2] +@ CHECK: vqdmulh.s32 q8, q8, q9 @ encoding: [0xe2,0x0b,0x60,0xf2] +@ CHECK: vqdmulh.s16 d16, d16, d17 @ encoding: [0xa1,0x0b,0x50,0xf2] +@ CHECK: vqdmulh.s32 d16, d16, d17 @ encoding: [0xa1,0x0b,0x60,0xf2] +@ CHECK: vqdmulh.s16 q8, q8, q9 @ encoding: [0xe2,0x0b,0x50,0xf2] +@ CHECK: vqdmulh.s32 q8, q8, q9 @ encoding: [0xe2,0x0b,0x60,0xf2] +@ CHECK: vqdmulh.s16 d11, d2, d3[0] @ encoding: [0x43,0xbc,0x92,0xf2] + + + vqrdmulh.s16 d16, d16, d17 + vqrdmulh.s32 d16, d16, d17 + vqrdmulh.s16 q8, q8, q9 + vqrdmulh.s32 q8, q8, q9 + +@ CHECK: vqrdmulh.s16 d16, d16, d17 @ encoding: [0xa1,0x0b,0x50,0xf3] +@ CHECK: vqrdmulh.s32 d16, d16, d17 @ encoding: [0xa1,0x0b,0x60,0xf3] +@ CHECK: vqrdmulh.s16 q8, q8, q9 @ encoding: [0xe2,0x0b,0x50,0xf3] +@ CHECK: vqrdmulh.s32 q8, q8, q9 @ encoding: [0xe2,0x0b,0x60,0xf3] + + + vmull.s8 q8, d16, d17 + vmull.s16 q8, d16, d17 + vmull.s32 q8, d16, d17 + vmull.u8 q8, d16, d17 + vmull.u16 q8, d16, d17 + vmull.u32 q8, d16, d17 + vmull.p8 q8, d16, d17 + +@ CHECK: vmull.s8 q8, d16, d17 @ encoding: [0xa1,0x0c,0xc0,0xf2] +@ CHECK: vmull.s16 q8, d16, d17 @ encoding: [0xa1,0x0c,0xd0,0xf2] +@ CHECK: vmull.s32 q8, d16, d17 @ encoding: [0xa1,0x0c,0xe0,0xf2] +@ CHECK: vmull.u8 q8, d16, d17 @ encoding: [0xa1,0x0c,0xc0,0xf3] +@ CHECK: vmull.u16 q8, d16, d17 @ encoding: [0xa1,0x0c,0xd0,0xf3] +@ CHECK: vmull.u32 q8, d16, d17 @ encoding: [0xa1,0x0c,0xe0,0xf3] +@ CHECK: vmull.p8 q8, d16, d17 @ encoding: [0xa1,0x0e,0xc0,0xf2] + + + vqdmull.s16 q8, d16, d17 + vqdmull.s32 q8, d16, d17 + +@ CHECK: vqdmull.s16 q8, d16, d17 @ encoding: [0xa1,0x0d,0xd0,0xf2] +@ CHECK: vqdmull.s32 q8, d16, d17 @ encoding: [0xa1,0x0d,0xe0,0xf2] + + + vmul.i16 d0, d4[2] + vmul.s16 d1, d7[3] + vmul.u16 d2, d1[1] + vmul.i32 d3, d2[0] + vmul.s32 d4, d3[1] + vmul.u32 d5, d4[0] + vmul.f32 d6, d5[1] + + vmul.i16 q0, d4[2] + vmul.s16 q1, d7[3] + vmul.u16 q2, d1[1] + vmul.i32 q3, d2[0] + vmul.s32 q4, d3[1] + vmul.u32 q5, d4[0] + vmul.f32 q6, d5[1] + + vmul.i16 d9, d0, d4[2] + vmul.s16 d8, d1, d7[3] + vmul.u16 d7, d2, d1[1] + vmul.i32 d6, d3, d2[0] + vmul.s32 d5, d4, d3[1] + vmul.u32 d4, d5, d4[0] + vmul.f32 d3, d6, d5[1] + + vmul.i16 q9, q0, d4[2] + vmul.s16 q8, q1, d7[3] + vmul.u16 q7, q2, d1[1] + vmul.i32 q6, q3, d2[0] + vmul.s32 q5, q4, d3[1] + vmul.u32 q4, q5, d4[0] + vmul.f32 q3, q6, d5[1] + +@ CHECK: vmul.i16 d0, d0, d4[2] @ encoding: [0x64,0x08,0x90,0xf2] +@ CHECK: vmul.i16 d1, d1, d7[3] @ encoding: [0x6f,0x18,0x91,0xf2] +@ CHECK: vmul.i16 d2, d2, d1[1] @ encoding: [0x49,0x28,0x92,0xf2] +@ CHECK: vmul.i32 d3, d3, d2[0] @ encoding: [0x42,0x38,0xa3,0xf2] +@ CHECK: vmul.i32 d4, d4, d3[1] @ encoding: [0x63,0x48,0xa4,0xf2] +@ CHECK: vmul.i32 d5, d5, d4[0] @ encoding: [0x44,0x58,0xa5,0xf2] +@ CHECK: vmul.f32 d6, d6, d5[1] @ encoding: [0x65,0x69,0xa6,0xf2] + +@ CHECK: vmul.i16 q0, q0, d4[2] @ encoding: [0x64,0x08,0x90,0xf3] +@ CHECK: vmul.i16 q1, q1, d7[3] @ encoding: [0x6f,0x28,0x92,0xf3] +@ CHECK: vmul.i16 q2, q2, d1[1] @ encoding: [0x49,0x48,0x94,0xf3] +@ CHECK: vmul.i32 q3, q3, d2[0] @ encoding: [0x42,0x68,0xa6,0xf3] +@ CHECK: vmul.i32 q4, q4, d3[1] @ encoding: [0x63,0x88,0xa8,0xf3] +@ CHECK: vmul.i32 q5, q5, d4[0] @ encoding: [0x44,0xa8,0xaa,0xf3] +@ CHECK: vmul.f32 q6, q6, d5[1] @ encoding: [0x65,0xc9,0xac,0xf3] + +@ CHECK: vmul.i16 d9, d0, d4[2] @ encoding: [0x64,0x98,0x90,0xf2] +@ CHECK: vmul.i16 d8, d1, d7[3] @ encoding: [0x6f,0x88,0x91,0xf2] +@ CHECK: vmul.i16 d7, d2, d1[1] @ encoding: [0x49,0x78,0x92,0xf2] +@ CHECK: vmul.i32 d6, d3, d2[0] @ encoding: [0x42,0x68,0xa3,0xf2] +@ CHECK: vmul.i32 d5, d4, d3[1] @ encoding: [0x63,0x58,0xa4,0xf2] +@ CHECK: vmul.i32 d4, d5, d4[0] @ encoding: [0x44,0x48,0xa5,0xf2] +@ CHECK: vmul.f32 d3, d6, d5[1] @ encoding: [0x65,0x39,0xa6,0xf2] + +@ CHECK: vmul.i16 q9, q0, d4[2] @ encoding: [0x64,0x28,0xd0,0xf3] +@ CHECK: vmul.i16 q8, q1, d7[3] @ encoding: [0x6f,0x08,0xd2,0xf3] +@ CHECK: vmul.i16 q7, q2, d1[1] @ encoding: [0x49,0xe8,0x94,0xf3] +@ CHECK: vmul.i32 q6, q3, d2[0] @ encoding: [0x42,0xc8,0xa6,0xf3] +@ CHECK: vmul.i32 q5, q4, d3[1] @ encoding: [0x63,0xa8,0xa8,0xf3] +@ CHECK: vmul.i32 q4, q5, d4[0] @ encoding: [0x44,0x88,0xaa,0xf3] +@ CHECK: vmul.f32 q3, q6, d5[1] @ encoding: [0x65,0x69,0xac,0xf3] diff --git a/test/MC/ARM/neon-pairwise-encoding.s b/test/MC/ARM/neon-pairwise-encoding.s index 65c47bd..b1e86aa 100644 --- a/test/MC/ARM/neon-pairwise-encoding.s +++ b/test/MC/ARM/neon-pairwise-encoding.s @@ -8,6 +8,16 @@ vpadd.i32 d16, d17, d16 @ CHECK: vpadd.f32 d16, d16, d17 @ encoding: [0xa1,0x0d,0x40,0xf3] vpadd.f32 d16, d16, d17 + +@ CHECK: vpadd.i8 d17, d17, d16 @ encoding: [0xb0,0x1b,0x41,0xf2] + vpadd.i8 d17, d16 +@ CHECK: vpadd.i16 d17, d17, d16 @ encoding: [0xb0,0x1b,0x51,0xf2] + vpadd.i16 d17, d16 +@ CHECK: vpadd.i32 d17, d17, d16 @ encoding: [0xb0,0x1b,0x61,0xf2] + vpadd.i32 d17, d16 +@ CHECK: vpadd.f32 d16, d16, d17 @ encoding: [0xa1,0x0d,0x40,0xf3] + vpadd.f32 d16, d17 + @ CHECK: vpaddl.s8 d16, d16 @ encoding: [0x20,0x02,0xf0,0xf3] vpaddl.s8 d16, d16 @ CHECK: vpaddl.s16 d16, d16 @ encoding: [0x20,0x02,0xf4,0xf3] diff --git a/test/MC/ARM/neon-shift-encoding.s b/test/MC/ARM/neon-shift-encoding.s index a7a1b83..54ed173 100644 --- a/test/MC/ARM/neon-shift-encoding.s +++ b/test/MC/ARM/neon-shift-encoding.s @@ -1,134 +1,255 @@ @ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s _foo: -@ CHECK: vshl.u8 d16, d17, d16 @ encoding: [0xa1,0x04,0x40,0xf3] vshl.u8 d16, d17, d16 -@ CHECK: vshl.u16 d16, d17, d16 @ encoding: [0xa1,0x04,0x50,0xf3] vshl.u16 d16, d17, d16 -@ CHECK: vshl.u32 d16, d17, d16 @ encoding: [0xa1,0x04,0x60,0xf3] vshl.u32 d16, d17, d16 -@ CHECK: vshl.u64 d16, d17, d16 @ encoding: [0xa1,0x04,0x70,0xf3] vshl.u64 d16, d17, d16 -@ CHECK: vshl.i8 d16, d16, #7 @ encoding: [0x30,0x05,0xcf,0xf2] vshl.i8 d16, d16, #7 -@ CHECK: vshl.i16 d16, d16, #15 @ encoding: [0x30,0x05,0xdf,0xf2] vshl.i16 d16, d16, #15 -@ CHECK: vshl.i32 d16, d16, #31 @ encoding: [0x30,0x05,0xff,0xf2] vshl.i32 d16, d16, #31 -@ CHECK: vshl.i64 d16, d16, #63 @ encoding: [0xb0,0x05,0xff,0xf2] vshl.i64 d16, d16, #63 -@ CHECK: vshl.u8 q8, q9, q8 @ encoding: [0xe2,0x04,0x40,0xf3] vshl.u8 q8, q9, q8 -@ CHECK: vshl.u16 q8, q9, q8 @ encoding: [0xe2,0x04,0x50,0xf3] vshl.u16 q8, q9, q8 -@ CHECK: vshl.u32 q8, q9, q8 @ encoding: [0xe2,0x04,0x60,0xf3] vshl.u32 q8, q9, q8 -@ CHECK: vshl.u64 q8, q9, q8 @ encoding: [0xe2,0x04,0x70,0xf3] vshl.u64 q8, q9, q8 -@ CHECK: vshl.i8 q8, q8, #7 @ encoding: [0x70,0x05,0xcf,0xf2] vshl.i8 q8, q8, #7 -@ CHECK: vshl.i16 q8, q8, #15 @ encoding: [0x70,0x05,0xdf,0xf2] vshl.i16 q8, q8, #15 -@ CHECK: vshl.i32 q8, q8, #31 @ encoding: [0x70,0x05,0xff,0xf2] vshl.i32 q8, q8, #31 -@ CHECK: vshl.i64 q8, q8, #63 @ encoding: [0xf0,0x05,0xff,0xf2] vshl.i64 q8, q8, #63 -@ CHECK: vshr.u8 d16, d16, #7 @ encoding: [0x30,0x00,0xc9,0xf3] + +@ CHECK: vshl.u8 d16, d17, d16 @ encoding: [0xa1,0x04,0x40,0xf3] +@ CHECK: vshl.u16 d16, d17, d16 @ encoding: [0xa1,0x04,0x50,0xf3] +@ CHECK: vshl.u32 d16, d17, d16 @ encoding: [0xa1,0x04,0x60,0xf3] +@ CHECK: vshl.u64 d16, d17, d16 @ encoding: [0xa1,0x04,0x70,0xf3] +@ CHECK: vshl.i8 d16, d16, #7 @ encoding: [0x30,0x05,0xcf,0xf2] +@ CHECK: vshl.i16 d16, d16, #15 @ encoding: [0x30,0x05,0xdf,0xf2] +@ CHECK: vshl.i32 d16, d16, #31 @ encoding: [0x30,0x05,0xff,0xf2] +@ CHECK: vshl.i64 d16, d16, #63 @ encoding: [0xb0,0x05,0xff,0xf2] +@ CHECK: vshl.u8 q8, q9, q8 @ encoding: [0xe2,0x04,0x40,0xf3] +@ CHECK: vshl.u16 q8, q9, q8 @ encoding: [0xe2,0x04,0x50,0xf3] +@ CHECK: vshl.u32 q8, q9, q8 @ encoding: [0xe2,0x04,0x60,0xf3] +@ CHECK: vshl.u64 q8, q9, q8 @ encoding: [0xe2,0x04,0x70,0xf3] +@ CHECK: vshl.i8 q8, q8, #7 @ encoding: [0x70,0x05,0xcf,0xf2] +@ CHECK: vshl.i16 q8, q8, #15 @ encoding: [0x70,0x05,0xdf,0xf2] +@ CHECK: vshl.i32 q8, q8, #31 @ encoding: [0x70,0x05,0xff,0xf2] +@ CHECK: vshl.i64 q8, q8, #63 @ encoding: [0xf0,0x05,0xff,0xf2] + + vshr.u8 d16, d16, #7 -@ CHECK: vshr.u16 d16, d16, #15 @ encoding: [0x30,0x00,0xd1,0xf3] vshr.u16 d16, d16, #15 -@ CHECK: vshr.u32 d16, d16, #31 @ encoding: [0x30,0x00,0xe1,0xf3] vshr.u32 d16, d16, #31 -@ CHECK: vshr.u64 d16, d16, #63 @ encoding: [0xb0,0x00,0xc1,0xf3] vshr.u64 d16, d16, #63 -@ CHECK: vshr.u8 q8, q8, #7 @ encoding: [0x70,0x00,0xc9,0xf3] vshr.u8 q8, q8, #7 -@ CHECK: vshr.u16 q8, q8, #15 @ encoding: [0x70,0x00,0xd1,0xf3] vshr.u16 q8, q8, #15 -@ CHECK: vshr.u32 q8, q8, #31 @ encoding: [0x70,0x00,0xe1,0xf3] vshr.u32 q8, q8, #31 -@ CHECK: vshr.u64 q8, q8, #63 @ encoding: [0xf0,0x00,0xc1,0xf3] vshr.u64 q8, q8, #63 -@ CHECK: vshr.s8 d16, d16, #7 @ encoding: [0x30,0x00,0xc9,0xf2] vshr.s8 d16, d16, #7 -@ CHECK: vshr.s16 d16, d16, #15 @ encoding: [0x30,0x00,0xd1,0xf2] vshr.s16 d16, d16, #15 -@ CHECK: vshr.s32 d16, d16, #31 @ encoding: [0x30,0x00,0xe1,0xf2] vshr.s32 d16, d16, #31 -@ CHECK: vshr.s64 d16, d16, #63 @ encoding: [0xb0,0x00,0xc1,0xf2] vshr.s64 d16, d16, #63 -@ CHECK: vshr.s8 q8, q8, #7 @ encoding: [0x70,0x00,0xc9,0xf2] vshr.s8 q8, q8, #7 -@ CHECK: vshr.s16 q8, q8, #15 @ encoding: [0x70,0x00,0xd1,0xf2] vshr.s16 q8, q8, #15 -@ CHECK: vshr.s32 q8, q8, #31 @ encoding: [0x70,0x00,0xe1,0xf2] vshr.s32 q8, q8, #31 -@ CHECK: vshr.s64 q8, q8, #63 @ encoding: [0xf0,0x00,0xc1,0xf2] vshr.s64 q8, q8, #63 -@ CHECK: vsra.u8 d16, d16, #7 @ encoding: [0x30,0x01,0xc9,0xf3] - vsra.u8 d16, d16, #7 -@ CHECK: vsra.u16 d16, d16, #15 @ encoding: [0x30,0x01,0xd1,0xf3] - vsra.u16 d16, d16, #15 -@ CHECK: vsra.u32 d16, d16, #31 @ encoding: [0x30,0x01,0xe1,0xf3] - vsra.u32 d16, d16, #31 -@ CHECK: vsra.u64 d16, d16, #63 @ encoding: [0xb0,0x01,0xc1,0xf3] - vsra.u64 d16, d16, #63 -@ CHECK: vsra.u8 q8, q8, #7 @ encoding: [0x70,0x01,0xc9,0xf3] - vsra.u8 q8, q8, #7 -@ CHECK: vsra.u16 q8, q8, #15 @ encoding: [0x70,0x01,0xd1,0xf3] - vsra.u16 q8, q8, #15 -@ CHECK: vsra.u32 q8, q8, #31 @ encoding: [0x70,0x01,0xe1,0xf3] - vsra.u32 q8, q8, #31 -@ CHECK: vsra.u64 q8, q8, #63 @ encoding: [0xf0,0x01,0xc1,0xf3] - vsra.u64 q8, q8, #63 -@ CHECK: vsra.s8 d16, d16, #7 @ encoding: [0x30,0x01,0xc9,0xf2] - vsra.s8 d16, d16, #7 -@ CHECK: vsra.s16 d16, d16, #15 @ encoding: [0x30,0x01,0xd1,0xf2] - vsra.s16 d16, d16, #15 -@ CHECK: vsra.s32 d16, d16, #31 @ encoding: [0x30,0x01,0xe1,0xf2] - vsra.s32 d16, d16, #31 -@ CHECK: vsra.s64 d16, d16, #63 @ encoding: [0xb0,0x01,0xc1,0xf2] - vsra.s64 d16, d16, #63 -@ CHECK: vsra.s8 q8, q8, #7 @ encoding: [0x70,0x01,0xc9,0xf2] - vsra.s8 q8, q8, #7 -@ CHECK: vsra.s16 q8, q8, #15 @ encoding: [0x70,0x01,0xd1,0xf2] - vsra.s16 q8, q8, #15 -@ CHECK: vsra.s32 q8, q8, #31 @ encoding: [0x70,0x01,0xe1,0xf2] - vsra.s32 q8, q8, #31 -@ CHECK: vsra.s64 q8, q8, #63 @ encoding: [0xf0,0x01,0xc1,0xf2] - vsra.s64 q8, q8, #63 -@ CHECK: vsri.8 d16, d16, #7 @ encoding: [0x30,0x04,0xc9,0xf3] - vsri.8 d16, d16, #7 -@ CHECK: vsri.16 d16, d16, #15 @ encoding: [0x30,0x04,0xd1,0xf3] - vsri.16 d16, d16, #15 -@ CHECK: vsri.32 d16, d16, #31 @ encoding: [0x30,0x04,0xe1,0xf3] - vsri.32 d16, d16, #31 -@ CHECK: vsri.64 d16, d16, #63 @ encoding: [0xb0,0x04,0xc1,0xf3] - vsri.64 d16, d16, #63 -@ CHECK: vsri.8 q8, q8, #7 @ encoding: [0x70,0x04,0xc9,0xf3] - vsri.8 q8, q8, #7 -@ CHECK: vsri.16 q8, q8, #15 @ encoding: [0x70,0x04,0xd1,0xf3] - vsri.16 q8, q8, #15 -@ CHECK: vsri.32 q8, q8, #31 @ encoding: [0x70,0x04,0xe1,0xf3] - vsri.32 q8, q8, #31 -@ CHECK: vsri.64 q8, q8, #63 @ encoding: [0xf0,0x04,0xc1,0xf3] - vsri.64 q8, q8, #63 -@ CHECK: vsli.8 d16, d16, #7 @ encoding: [0x30,0x05,0xcf,0xf3] - vsli.8 d16, d16, #7 -@ CHECK: vsli.16 d16, d16, #15 @ encoding: [0x30,0x05,0xdf,0xf3] - vsli.16 d16, d16, #15 -@ CHECK: vsli.32 d16, d16, #31 @ encoding: [0x30,0x05,0xff,0xf3] - vsli.32 d16, d16, #31 -@ CHECK: vsli.64 d16, d16, #63 @ encoding: [0xb0,0x05,0xff,0xf3] - vsli.64 d16, d16, #63 -@ CHECK: vsli.8 q8, q8, #7 @ encoding: [0x70,0x05,0xcf,0xf3] - vsli.8 q8, q8, #7 -@ CHECK: vsli.16 q8, q8, #15 @ encoding: [0x70,0x05,0xdf,0xf3] - vsli.16 q8, q8, #15 -@ CHECK: vsli.32 q8, q8, #31 @ encoding: [0x70,0x05,0xff,0xf3] - vsli.32 q8, q8, #31 -@ CHECK: vsli.64 q8, q8, #63 @ encoding: [0xf0,0x05,0xff,0xf3] - vsli.64 q8, q8, #63 + +@ CHECK: vshr.u8 d16, d16, #7 @ encoding: [0x30,0x00,0xc9,0xf3] +@ CHECK: vshr.u16 d16, d16, #15 @ encoding: [0x30,0x00,0xd1,0xf3] +@ CHECK: vshr.u32 d16, d16, #31 @ encoding: [0x30,0x00,0xe1,0xf3] +@ CHECK: vshr.u64 d16, d16, #63 @ encoding: [0xb0,0x00,0xc1,0xf3] +@ CHECK: vshr.u8 q8, q8, #7 @ encoding: [0x70,0x00,0xc9,0xf3] +@ CHECK: vshr.u16 q8, q8, #15 @ encoding: [0x70,0x00,0xd1,0xf3] +@ CHECK: vshr.u32 q8, q8, #31 @ encoding: [0x70,0x00,0xe1,0xf3] +@ CHECK: vshr.u64 q8, q8, #63 @ encoding: [0xf0,0x00,0xc1,0xf3] +@ CHECK: vshr.s8 d16, d16, #7 @ encoding: [0x30,0x00,0xc9,0xf2] +@ CHECK: vshr.s16 d16, d16, #15 @ encoding: [0x30,0x00,0xd1,0xf2] +@ CHECK: vshr.s32 d16, d16, #31 @ encoding: [0x30,0x00,0xe1,0xf2] +@ CHECK: vshr.s64 d16, d16, #63 @ encoding: [0xb0,0x00,0xc1,0xf2] +@ CHECK: vshr.s8 q8, q8, #7 @ encoding: [0x70,0x00,0xc9,0xf2] +@ CHECK: vshr.s16 q8, q8, #15 @ encoding: [0x70,0x00,0xd1,0xf2] +@ CHECK: vshr.s32 q8, q8, #31 @ encoding: [0x70,0x00,0xe1,0xf2] +@ CHECK: vshr.s64 q8, q8, #63 @ encoding: [0xf0,0x00,0xc1,0xf2] + +@ implied destination operand variants. + vshr.u8 d16, #7 + vshr.u16 d16, #15 + vshr.u32 d16, #31 + vshr.u64 d16, #63 + vshr.u8 q8, #7 + vshr.u16 q8, #15 + vshr.u32 q8, #31 + vshr.u64 q8, #63 + vshr.s8 d16, #7 + vshr.s16 d16, #15 + vshr.s32 d16, #31 + vshr.s64 d16, #63 + vshr.s8 q8, #7 + vshr.s16 q8, #15 + vshr.s32 q8, #31 + vshr.s64 q8, #63 + +@ CHECK: vshr.u8 d16, d16, #7 @ encoding: [0x30,0x00,0xc9,0xf3] +@ CHECK: vshr.u16 d16, d16, #15 @ encoding: [0x30,0x00,0xd1,0xf3] +@ CHECK: vshr.u32 d16, d16, #31 @ encoding: [0x30,0x00,0xe1,0xf3] +@ CHECK: vshr.u64 d16, d16, #63 @ encoding: [0xb0,0x00,0xc1,0xf3] +@ CHECK: vshr.u8 q8, q8, #7 @ encoding: [0x70,0x00,0xc9,0xf3] +@ CHECK: vshr.u16 q8, q8, #15 @ encoding: [0x70,0x00,0xd1,0xf3] +@ CHECK: vshr.u32 q8, q8, #31 @ encoding: [0x70,0x00,0xe1,0xf3] +@ CHECK: vshr.u64 q8, q8, #63 @ encoding: [0xf0,0x00,0xc1,0xf3] +@ CHECK: vshr.s8 d16, d16, #7 @ encoding: [0x30,0x00,0xc9,0xf2] +@ CHECK: vshr.s16 d16, d16, #15 @ encoding: [0x30,0x00,0xd1,0xf2] +@ CHECK: vshr.s32 d16, d16, #31 @ encoding: [0x30,0x00,0xe1,0xf2] +@ CHECK: vshr.s64 d16, d16, #63 @ encoding: [0xb0,0x00,0xc1,0xf2] +@ CHECK: vshr.s8 q8, q8, #7 @ encoding: [0x70,0x00,0xc9,0xf2] +@ CHECK: vshr.s16 q8, q8, #15 @ encoding: [0x70,0x00,0xd1,0xf2] +@ CHECK: vshr.s32 q8, q8, #31 @ encoding: [0x70,0x00,0xe1,0xf2] +@ CHECK: vshr.s64 q8, q8, #63 @ encoding: [0xf0,0x00,0xc1,0xf2] + + + vsra.s8 d16, d6, #7 + vsra.s16 d26, d18, #15 + vsra.s32 d11, d10, #31 + vsra.s64 d12, d19, #63 + vsra.s8 q1, q8, #7 + vsra.s16 q2, q7, #15 + vsra.s32 q3, q6, #31 + vsra.s64 q4, q5, #63 + + vsra.s8 d16, #7 + vsra.s16 d15, #15 + vsra.s32 d14, #31 + vsra.s64 d13, #63 + vsra.s8 q4, #7 + vsra.s16 q5, #15 + vsra.s32 q6, #31 + vsra.s64 q7, #63 + +@ CHECK: vsra.s8 d16, d6, #7 @ encoding: [0x16,0x01,0xc9,0xf2] +@ CHECK: vsra.s16 d26, d18, #15 @ encoding: [0x32,0xa1,0xd1,0xf2] +@ CHECK: vsra.s32 d11, d10, #31 @ encoding: [0x1a,0xb1,0xa1,0xf2] +@ CHECK: vsra.s64 d12, d19, #63 @ encoding: [0xb3,0xc1,0x81,0xf2] +@ CHECK: vsra.s8 q1, q8, #7 @ encoding: [0x70,0x21,0x89,0xf2] +@ CHECK: vsra.s16 q2, q7, #15 @ encoding: [0x5e,0x41,0x91,0xf2] +@ CHECK: vsra.s32 q3, q6, #31 @ encoding: [0x5c,0x61,0xa1,0xf2] +@ CHECK: vsra.s64 q4, q5, #63 @ encoding: [0xda,0x81,0x81,0xf2] +@ CHECK: vsra.s8 d16, d16, #7 @ encoding: [0x30,0x01,0xc9,0xf2] +@ CHECK: vsra.s16 d15, d15, #15 @ encoding: [0x1f,0xf1,0x91,0xf2] +@ CHECK: vsra.s32 d14, d14, #31 @ encoding: [0x1e,0xe1,0xa1,0xf2] +@ CHECK: vsra.s64 d13, d13, #63 @ encoding: [0x9d,0xd1,0x81,0xf2] +@ CHECK: vsra.s8 q4, q4, #7 @ encoding: [0x58,0x81,0x89,0xf2] +@ CHECK: vsra.s16 q5, q5, #15 @ encoding: [0x5a,0xa1,0x91,0xf2] +@ CHECK: vsra.s32 q6, q6, #31 @ encoding: [0x5c,0xc1,0xa1,0xf2] +@ CHECK: vsra.s64 q7, q7, #63 @ encoding: [0xde,0xe1,0x81,0xf2] + + + vsra.u8 d16, d6, #7 + vsra.u16 d26, d18, #15 + vsra.u32 d11, d10, #31 + vsra.u64 d12, d19, #63 + vsra.u8 q1, q8, #7 + vsra.u16 q2, q7, #15 + vsra.u32 q3, q6, #31 + vsra.u64 q4, q5, #63 + + vsra.u8 d16, #7 + vsra.u16 d15, #15 + vsra.u32 d14, #31 + vsra.u64 d13, #63 + vsra.u8 q4, #7 + vsra.u16 q5, #15 + vsra.u32 q6, #31 + vsra.u64 q7, #63 + +@ CHECK: vsra.u8 d16, d6, #7 @ encoding: [0x16,0x01,0xc9,0xf3] +@ CHECK: vsra.u16 d26, d18, #15 @ encoding: [0x32,0xa1,0xd1,0xf3] +@ CHECK: vsra.u32 d11, d10, #31 @ encoding: [0x1a,0xb1,0xa1,0xf3] +@ CHECK: vsra.u64 d12, d19, #63 @ encoding: [0xb3,0xc1,0x81,0xf3] +@ CHECK: vsra.u8 q1, q8, #7 @ encoding: [0x70,0x21,0x89,0xf3] +@ CHECK: vsra.u16 q2, q7, #15 @ encoding: [0x5e,0x41,0x91,0xf3] +@ CHECK: vsra.u32 q3, q6, #31 @ encoding: [0x5c,0x61,0xa1,0xf3] +@ CHECK: vsra.u64 q4, q5, #63 @ encoding: [0xda,0x81,0x81,0xf3] +@ CHECK: vsra.u8 d16, d16, #7 @ encoding: [0x30,0x01,0xc9,0xf3] +@ CHECK: vsra.u16 d15, d15, #15 @ encoding: [0x1f,0xf1,0x91,0xf3] +@ CHECK: vsra.u32 d14, d14, #31 @ encoding: [0x1e,0xe1,0xa1,0xf3] +@ CHECK: vsra.u64 d13, d13, #63 @ encoding: [0x9d,0xd1,0x81,0xf3] +@ CHECK: vsra.u8 q4, q4, #7 @ encoding: [0x58,0x81,0x89,0xf3] +@ CHECK: vsra.u16 q5, q5, #15 @ encoding: [0x5a,0xa1,0x91,0xf3] +@ CHECK: vsra.u32 q6, q6, #31 @ encoding: [0x5c,0xc1,0xa1,0xf3] +@ CHECK: vsra.u64 q7, q7, #63 @ encoding: [0xde,0xe1,0x81,0xf3] + + + vsri.8 d16, d6, #7 + vsri.16 d26, d18, #15 + vsri.32 d11, d10, #31 + vsri.64 d12, d19, #63 + vsri.8 q1, q8, #7 + vsri.16 q2, q7, #15 + vsri.32 q3, q6, #31 + vsri.64 q4, q5, #63 + + vsri.8 d16, #7 + vsri.16 d15, #15 + vsri.32 d14, #31 + vsri.64 d13, #63 + vsri.8 q4, #7 + vsri.16 q5, #15 + vsri.32 q6, #31 + vsri.64 q7, #63 + +@ CHECK: vsri.8 d16, d6, #7 @ encoding: [0x16,0x04,0xc9,0xf3] +@ CHECK: vsri.16 d26, d18, #15 @ encoding: [0x32,0xa4,0xd1,0xf3] +@ CHECK: vsri.32 d11, d10, #31 @ encoding: [0x1a,0xb4,0xa1,0xf3] +@ CHECK: vsri.64 d12, d19, #63 @ encoding: [0xb3,0xc4,0x81,0xf3] +@ CHECK: vsri.8 q1, q8, #7 @ encoding: [0x70,0x24,0x89,0xf3] +@ CHECK: vsri.16 q2, q7, #15 @ encoding: [0x5e,0x44,0x91,0xf3] +@ CHECK: vsri.32 q3, q6, #31 @ encoding: [0x5c,0x64,0xa1,0xf3] +@ CHECK: vsri.64 q4, q5, #63 @ encoding: [0xda,0x84,0x81,0xf3] +@ CHECK: vsri.8 d16, d16, #7 @ encoding: [0x30,0x04,0xc9,0xf3] +@ CHECK: vsri.16 d15, d15, #15 @ encoding: [0x1f,0xf4,0x91,0xf3] +@ CHECK: vsri.32 d14, d14, #31 @ encoding: [0x1e,0xe4,0xa1,0xf3] +@ CHECK: vsri.64 d13, d13, #63 @ encoding: [0x9d,0xd4,0x81,0xf3] +@ CHECK: vsri.8 q4, q4, #7 @ encoding: [0x58,0x84,0x89,0xf3] +@ CHECK: vsri.16 q5, q5, #15 @ encoding: [0x5a,0xa4,0x91,0xf3] +@ CHECK: vsri.32 q6, q6, #31 @ encoding: [0x5c,0xc4,0xa1,0xf3] +@ CHECK: vsri.64 q7, q7, #63 @ encoding: [0xde,0xe4,0x81,0xf3] + + + vsli.8 d16, d6, #7 + vsli.16 d26, d18, #15 + vsli.32 d11, d10, #31 + vsli.64 d12, d19, #63 + vsli.8 q1, q8, #7 + vsli.16 q2, q7, #15 + vsli.32 q3, q6, #31 + vsli.64 q4, q5, #63 + + vsli.8 d16, #7 + vsli.16 d15, #15 + vsli.32 d14, #31 + vsli.64 d13, #63 + vsli.8 q4, #7 + vsli.16 q5, #15 + vsli.32 q6, #31 + vsli.64 q7, #63 + +@ CHECK: vsli.8 d16, d6, #7 @ encoding: [0x16,0x05,0xcf,0xf3] +@ CHECK: vsli.16 d26, d18, #15 @ encoding: [0x32,0xa5,0xdf,0xf3] +@ CHECK: vsli.32 d11, d10, #31 @ encoding: [0x1a,0xb5,0xbf,0xf3] +@ CHECK: vsli.64 d12, d19, #63 @ encoding: [0xb3,0xc5,0xbf,0xf3] +@ CHECK: vsli.8 q1, q8, #7 @ encoding: [0x70,0x25,0x8f,0xf3] +@ CHECK: vsli.16 q2, q7, #15 @ encoding: [0x5e,0x45,0x9f,0xf3] +@ CHECK: vsli.32 q3, q6, #31 @ encoding: [0x5c,0x65,0xbf,0xf3] +@ CHECK: vsli.64 q4, q5, #63 @ encoding: [0xda,0x85,0xbf,0xf3] +@ CHECK: vsli.8 d16, d16, #7 @ encoding: [0x30,0x05,0xcf,0xf3] +@ CHECK: vsli.16 d15, d15, #15 @ encoding: [0x1f,0xf5,0x9f,0xf3] +@ CHECK: vsli.32 d14, d14, #31 @ encoding: [0x1e,0xe5,0xbf,0xf3] +@ CHECK: vsli.64 d13, d13, #63 @ encoding: [0x9d,0xd5,0xbf,0xf3] +@ CHECK: vsli.8 q4, q4, #7 @ encoding: [0x58,0x85,0x8f,0xf3] +@ CHECK: vsli.16 q5, q5, #15 @ encoding: [0x5a,0xa5,0x9f,0xf3] +@ CHECK: vsli.32 q6, q6, #31 @ encoding: [0x5c,0xc5,0xbf,0xf3] +@ CHECK: vsli.64 q7, q7, #63 @ encoding: [0xde,0xe5,0xbf,0xf3] + + @ CHECK: vshll.s8 q8, d16, #7 @ encoding: [0x30,0x0a,0xcf,0xf2] vshll.s8 q8, d16, #7 @ CHECK: vshll.s16 q8, d16, #15 @ encoding: [0x30,0x0a,0xdf,0xf2] @@ -235,3 +356,134 @@ _foo: vqrshrn.u32 d16, q8, #13 @ CHECK: vqrshrn.u64 d16, q8, #13 @ encoding: [0x70,0x09,0xf3,0xf3] vqrshrn.u64 d16, q8, #13 + +@ Optional destination operand variants. + vshl.s8 q4, q5 + vshl.s16 q4, q5 + vshl.s32 q4, q5 + vshl.s64 q4, q5 + + vshl.u8 q4, q5 + vshl.u16 q4, q5 + vshl.u32 q4, q5 + vshl.u64 q4, q5 + + vshl.s8 d4, d5 + vshl.s16 d4, d5 + vshl.s32 d4, d5 + vshl.s64 d4, d5 + + vshl.u8 d4, d5 + vshl.u16 d4, d5 + vshl.u32 d4, d5 + vshl.u64 d4, d5 + +@ CHECK: vshl.s8 q4, q4, q5 @ encoding: [0x48,0x84,0x0a,0xf2] +@ CHECK: vshl.s16 q4, q4, q5 @ encoding: [0x48,0x84,0x1a,0xf2] +@ CHECK: vshl.s32 q4, q4, q5 @ encoding: [0x48,0x84,0x2a,0xf2] +@ CHECK: vshl.s64 q4, q4, q5 @ encoding: [0x48,0x84,0x3a,0xf2] + +@ CHECK: vshl.u8 q4, q4, q5 @ encoding: [0x48,0x84,0x0a,0xf3] +@ CHECK: vshl.u16 q4, q4, q5 @ encoding: [0x48,0x84,0x1a,0xf3] +@ CHECK: vshl.u32 q4, q4, q5 @ encoding: [0x48,0x84,0x2a,0xf3] +@ CHECK: vshl.u64 q4, q4, q5 @ encoding: [0x48,0x84,0x3a,0xf3] + +@ CHECK: vshl.s8 d4, d4, d5 @ encoding: [0x04,0x44,0x05,0xf2] +@ CHECK: vshl.s16 d4, d4, d5 @ encoding: [0x04,0x44,0x15,0xf2] +@ CHECK: vshl.s32 d4, d4, d5 @ encoding: [0x04,0x44,0x25,0xf2] +@ CHECK: vshl.s64 d4, d4, d5 @ encoding: [0x04,0x44,0x35,0xf2] + +@ CHECK: vshl.u8 d4, d4, d5 @ encoding: [0x04,0x44,0x05,0xf3] +@ CHECK: vshl.u16 d4, d4, d5 @ encoding: [0x04,0x44,0x15,0xf3] +@ CHECK: vshl.u32 d4, d4, d5 @ encoding: [0x04,0x44,0x25,0xf3] +@ CHECK: vshl.u64 d4, d4, d5 @ encoding: [0x04,0x44,0x35,0xf3] + + vshl.s8 q4, #2 + vshl.s16 q4, #14 + vshl.s32 q4, #27 + vshl.s64 q4, #35 + + vshl.s8 d4, #6 + vshl.u16 d4, #10 + vshl.s32 d4, #17 + vshl.u64 d4, #43 + +@ CHECK: vshl.i8 q4, q4, #2 @ encoding: [0x58,0x85,0x8a,0xf2] +@ CHECK: vshl.i16 q4, q4, #14 @ encoding: [0x58,0x85,0x9e,0xf2] +@ CHECK: vshl.i32 q4, q4, #27 @ encoding: [0x58,0x85,0xbb,0xf2] +@ CHECK: vshl.i64 q4, q4, #35 @ encoding: [0xd8,0x85,0xa3,0xf2] + +@ CHECK: vshl.i8 d4, d4, #6 @ encoding: [0x14,0x45,0x8e,0xf2] +@ CHECK: vshl.i16 d4, d4, #10 @ encoding: [0x14,0x45,0x9a,0xf2] +@ CHECK: vshl.i32 d4, d4, #17 @ encoding: [0x14,0x45,0xb1,0xf2] +@ CHECK: vshl.i64 d4, d4, #43 @ encoding: [0x94,0x45,0xab,0xf2] + + +@ Two-operand forms. + vshr.s8 d15, #8 + vshr.s16 d12, #16 + vshr.s32 d13, #32 + vshr.s64 d14, #64 + vshr.u8 d16, #8 + vshr.u16 d17, #16 + vshr.u32 d6, #32 + vshr.u64 d10, #64 + vshr.s8 q1, #8 + vshr.s16 q2, #16 + vshr.s32 q3, #32 + vshr.s64 q4, #64 + vshr.u8 q5, #8 + vshr.u16 q6, #16 + vshr.u32 q7, #32 + vshr.u64 q8, #64 + +@ CHECK: vshr.s8 d15, d15, #8 @ encoding: [0x1f,0xf0,0x88,0xf2] +@ CHECK: vshr.s16 d12, d12, #16 @ encoding: [0x1c,0xc0,0x90,0xf2] +@ CHECK: vshr.s32 d13, d13, #32 @ encoding: [0x1d,0xd0,0xa0,0xf2] +@ CHECK: vshr.s64 d14, d14, #64 @ encoding: [0x9e,0xe0,0x80,0xf2] +@ CHECK: vshr.u8 d16, d16, #8 @ encoding: [0x30,0x00,0xc8,0xf3] +@ CHECK: vshr.u16 d17, d17, #16 @ encoding: [0x31,0x10,0xd0,0xf3] +@ CHECK: vshr.u32 d6, d6, #32 @ encoding: [0x16,0x60,0xa0,0xf3] +@ CHECK: vshr.u64 d10, d10, #64 @ encoding: [0x9a,0xa0,0x80,0xf3] +@ CHECK: vshr.s8 q1, q1, #8 @ encoding: [0x52,0x20,0x88,0xf2] +@ CHECK: vshr.s16 q2, q2, #16 @ encoding: [0x54,0x40,0x90,0xf2] +@ CHECK: vshr.s32 q3, q3, #32 @ encoding: [0x56,0x60,0xa0,0xf2] +@ CHECK: vshr.s64 q4, q4, #64 @ encoding: [0xd8,0x80,0x80,0xf2] +@ CHECK: vshr.u8 q5, q5, #8 @ encoding: [0x5a,0xa0,0x88,0xf3] +@ CHECK: vshr.u16 q6, q6, #16 @ encoding: [0x5c,0xc0,0x90,0xf3] +@ CHECK: vshr.u32 q7, q7, #32 @ encoding: [0x5e,0xe0,0xa0,0xf3] +@ CHECK: vshr.u64 q8, q8, #64 @ encoding: [0xf0,0x00,0xc0,0xf3] + + vrshr.s8 d15, #8 + vrshr.s16 d12, #16 + vrshr.s32 d13, #32 + vrshr.s64 d14, #64 + vrshr.u8 d16, #8 + vrshr.u16 d17, #16 + vrshr.u32 d6, #32 + vrshr.u64 d10, #64 + vrshr.s8 q1, #8 + vrshr.s16 q2, #16 + vrshr.s32 q3, #32 + vrshr.s64 q4, #64 + vrshr.u8 q5, #8 + vrshr.u16 q6, #16 + vrshr.u32 q7, #32 + vrshr.u64 q8, #64 + +@ CHECK: vrshr.s8 d15, d15, #8 @ encoding: [0x1f,0xf2,0x88,0xf2] +@ CHECK: vrshr.s16 d12, d12, #16 @ encoding: [0x1c,0xc2,0x90,0xf2] +@ CHECK: vrshr.s32 d13, d13, #32 @ encoding: [0x1d,0xd2,0xa0,0xf2] +@ CHECK: vrshr.s64 d14, d14, #64 @ encoding: [0x9e,0xe2,0x80,0xf2] +@ CHECK: vrshr.u8 d16, d16, #8 @ encoding: [0x30,0x02,0xc8,0xf3] +@ CHECK: vrshr.u16 d17, d17, #16 @ encoding: [0x31,0x12,0xd0,0xf3] +@ CHECK: vrshr.u32 d6, d6, #32 @ encoding: [0x16,0x62,0xa0,0xf3] +@ CHECK: vrshr.u64 d10, d10, #64 @ encoding: [0x9a,0xa2,0x80,0xf3] +@ CHECK: vrshr.s8 q1, q1, #8 @ encoding: [0x52,0x22,0x88,0xf2] +@ CHECK: vrshr.s16 q2, q2, #16 @ encoding: [0x54,0x42,0x90,0xf2] +@ CHECK: vrshr.s32 q3, q3, #32 @ encoding: [0x56,0x62,0xa0,0xf2] +@ CHECK: vrshr.s64 q4, q4, #64 @ encoding: [0xd8,0x82,0x80,0xf2] +@ CHECK: vrshr.u8 q5, q5, #8 @ encoding: [0x5a,0xa2,0x88,0xf3] +@ CHECK: vrshr.u16 q6, q6, #16 @ encoding: [0x5c,0xc2,0x90,0xf3] +@ CHECK: vrshr.u32 q7, q7, #32 @ encoding: [0x5e,0xe2,0xa0,0xf3] +@ CHECK: vrshr.u64 q8, q8, #64 @ encoding: [0xf0,0x02,0xc0,0xf3] diff --git a/test/MC/ARM/neon-shiftaccum-encoding.s b/test/MC/ARM/neon-shiftaccum-encoding.s deleted file mode 100644 index 0dc630d..0000000 --- a/test/MC/ARM/neon-shiftaccum-encoding.s +++ /dev/null @@ -1,98 +0,0 @@ -@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s - -@ CHECK: vsra.s8 d17, d16, #8 @ encoding: [0x30,0x11,0xc8,0xf2] - vsra.s8 d17, d16, #8 -@ CHECK: vsra.s16 d17, d16, #16 @ encoding: [0x30,0x11,0xd0,0xf2] - vsra.s16 d17, d16, #16 -@ CHECK: vsra.s32 d17, d16, #32 @ encoding: [0x30,0x11,0xe0,0xf2] - vsra.s32 d17, d16, #32 -@ CHECK: vsra.s64 d17, d16, #64 @ encoding: [0xb0,0x11,0xc0,0xf2] - vsra.s64 d17, d16, #64 -@ CHECK: vsra.s8 q8, q9, #8 @ encoding: [0x72,0x01,0xc8,0xf2] - vsra.s8 q8, q9, #8 -@ CHECK: vsra.s16 q8, q9, #16 @ encoding: [0x72,0x01,0xd0,0xf2] - vsra.s16 q8, q9, #16 -@ CHECK: vsra.s32 q8, q9, #32 @ encoding: [0x72,0x01,0xe0,0xf2] - vsra.s32 q8, q9, #32 -@ CHECK: vsra.s64 q8, q9, #64 @ encoding: [0xf2,0x01,0xc0,0xf2] - vsra.s64 q8, q9, #64 -@ CHECK: vsra.u8 d17, d16, #8 @ encoding: [0x30,0x11,0xc8,0xf3] - vsra.u8 d17, d16, #8 -@ CHECK: vsra.u16 d17, d16, #16 @ encoding: [0x30,0x11,0xd0,0xf3] - vsra.u16 d17, d16, #16 -@ CHECK: vsra.u32 d17, d16, #32 @ encoding: [0x30,0x11,0xe0,0xf3] - vsra.u32 d17, d16, #32 -@ CHECK: vsra.u64 d17, d16, #64 @ encoding: [0xb0,0x11,0xc0,0xf3] - vsra.u64 d17, d16, #64 -@ CHECK: vsra.u8 q8, q9, #8 @ encoding: [0x72,0x01,0xc8,0xf3] - vsra.u8 q8, q9, #8 -@ CHECK: vsra.u16 q8, q9, #16 @ encoding: [0x72,0x01,0xd0,0xf3] - vsra.u16 q8, q9, #16 -@ CHECK: vsra.u32 q8, q9, #32 @ encoding: [0x72,0x01,0xe0,0xf3] - vsra.u32 q8, q9, #32 -@ CHECK: vsra.u64 q8, q9, #64 @ encoding: [0xf2,0x01,0xc0,0xf3] - vsra.u64 q8, q9, #64 -@ CHECK: vrsra.s8 d17, d16, #8 @ encoding: [0x30,0x13,0xc8,0xf2] - vrsra.s8 d17, d16, #8 -@ CHECK: vrsra.s16 d17, d16, #16 @ encoding: [0x30,0x13,0xd0,0xf2] - vrsra.s16 d17, d16, #16 -@ CHECK: vrsra.s32 d17, d16, #32 @ encoding: [0x30,0x13,0xe0,0xf2] - vrsra.s32 d17, d16, #32 -@ CHECK: vrsra.s64 d17, d16, #64 @ encoding: [0xb0,0x13,0xc0,0xf2] - vrsra.s64 d17, d16, #64 -@ CHECK: vrsra.u8 d17, d16, #8 @ encoding: [0x30,0x13,0xc8,0xf3] - vrsra.u8 d17, d16, #8 -@ CHECK: vrsra.u16 d17, d16, #16 @ encoding: [0x30,0x13,0xd0,0xf3] - vrsra.u16 d17, d16, #16 -@ CHECK: vrsra.u32 d17, d16, #32 @ encoding: [0x30,0x13,0xe0,0xf3] - vrsra.u32 d17, d16, #32 -@ CHECK: vrsra.u64 d17, d16, #64 @ encoding: [0xb0,0x13,0xc0,0xf3] - vrsra.u64 d17, d16, #64 -@ CHECK: vrsra.s8 q8, q9, #8 @ encoding: [0x72,0x03,0xc8,0xf2] - vrsra.s8 q8, q9, #8 -@ CHECK: vrsra.s16 q8, q9, #16 @ encoding: [0x72,0x03,0xd0,0xf2] - vrsra.s16 q8, q9, #16 -@ CHECK: vrsra.s32 q8, q9, #32 @ encoding: [0x72,0x03,0xe0,0xf2] - vrsra.s32 q8, q9, #32 -@ CHECK: vrsra.s64 q8, q9, #64 @ encoding: [0xf2,0x03,0xc0,0xf2] - vrsra.s64 q8, q9, #64 -@ CHECK: vrsra.u8 q8, q9, #8 @ encoding: [0x72,0x03,0xc8,0xf3] - vrsra.u8 q8, q9, #8 -@ CHECK: vrsra.u16 q8, q9, #16 @ encoding: [0x72,0x03,0xd0,0xf3] - vrsra.u16 q8, q9, #16 -@ CHECK: vrsra.u32 q8, q9, #32 @ encoding: [0x72,0x03,0xe0,0xf3] - vrsra.u32 q8, q9, #32 -@ CHECK: vrsra.u64 q8, q9, #64 @ encoding: [0xf2,0x03,0xc0,0xf3] - vrsra.u64 q8, q9, #64 -@ CHECK: vsli.8 d17, d16, #7 @ encoding: [0x30,0x15,0xcf,0xf3] - vsli.8 d17, d16, #7 -@ CHECK: vsli.16 d17, d16, #15 @ encoding: [0x30,0x15,0xdf,0xf3] - vsli.16 d17, d16, #15 -@ CHECK: vsli.32 d17, d16, #31 @ encoding: [0x30,0x15,0xff,0xf3] - vsli.32 d17, d16, #31 -@ CHECK: vsli.64 d17, d16, #63 @ encoding: [0xb0,0x15,0xff,0xf3] - vsli.64 d17, d16, #63 -@ CHECK: vsli.8 q9, q8, #7 @ encoding: [0x70,0x25,0xcf,0xf3] - vsli.8 q9, q8, #7 -@ CHECK: vsli.16 q9, q8, #15 @ encoding: [0x70,0x25,0xdf,0xf3] - vsli.16 q9, q8, #15 -@ CHECK: vsli.32 q9, q8, #31 @ encoding: [0x70,0x25,0xff,0xf3] - vsli.32 q9, q8, #31 -@ CHECK: vsli.64 q9, q8, #63 @ encoding: [0xf0,0x25,0xff,0xf3] - vsli.64 q9, q8, #63 -@ CHECK: vsri.8 d17, d16, #8 @ encoding: [0x30,0x14,0xc8,0xf3] - vsri.8 d17, d16, #8 -@ CHECK: vsri.16 d17, d16, #16 @ encoding: [0x30,0x14,0xd0,0xf3] - vsri.16 d17, d16, #16 -@ CHECK: vsri.32 d17, d16, #32 @ encoding: [0x30,0x14,0xe0,0xf3] - vsri.32 d17, d16, #32 -@ CHECK: vsri.64 d17, d16, #64 @ encoding: [0xb0,0x14,0xc0,0xf3] - vsri.64 d17, d16, #64 -@ CHECK: vsri.8 q9, q8, #8 @ encoding: [0x70,0x24,0xc8,0xf3] - vsri.8 q9, q8, #8 -@ CHECK: vsri.16 q9, q8, #16 @ encoding: [0x70,0x24,0xd0,0xf3] - vsri.16 q9, q8, #16 -@ CHECK: vsri.32 q9, q8, #32 @ encoding: [0x70,0x24,0xe0,0xf3] - vsri.32 q9, q8, #32 -@ CHECK: vsri.64 q9, q8, #64 @ encoding: [0xf0,0x24,0xc0,0xf3] - vsri.64 q9, q8, #64 diff --git a/test/MC/ARM/neon-shuffle-encoding.s b/test/MC/ARM/neon-shuffle-encoding.s index ce7eb66..0f07d9f 100644 --- a/test/MC/ARM/neon-shuffle-encoding.s +++ b/test/MC/ARM/neon-shuffle-encoding.s @@ -1,46 +1,136 @@ @ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s -@ CHECK: vext.8 d16, d17, d16, #3 @ encoding: [0xa0,0x03,0xf1,0xf2] vext.8 d16, d17, d16, #3 -@ CHECK: vext.8 d16, d17, d16, #5 @ encoding: [0xa0,0x05,0xf1,0xf2] vext.8 d16, d17, d16, #5 -@ CHECK: vext.8 q8, q9, q8, #3 @ encoding: [0xe0,0x03,0xf2,0xf2] vext.8 q8, q9, q8, #3 -@ CHECK: vext.8 q8, q9, q8, #7 @ encoding: [0xe0,0x07,0xf2,0xf2] vext.8 q8, q9, q8, #7 -@ CHECK: vext.16 d16, d17, d16, #3 @ encoding: [0xa0,0x06,0xf1,0xf2] vext.16 d16, d17, d16, #3 -@ CHECK: vext.32 q8, q9, q8, #3 @ encoding: [0xe0,0x0c,0xf2,0xf2] vext.32 q8, q9, q8, #3 -@ CHECK: vtrn.8 d17, d16 @ encoding: [0xa0,0x10,0xf2,0xf3] + vext.64 q8, q9, q8, #1 + + vext.8 d17, d16, #3 + vext.8 d7, d11, #5 + vext.8 q3, q8, #3 + vext.8 q9, q4, #7 + vext.16 d1, d26, #3 + vext.32 q5, q8, #3 + vext.64 q5, q8, #1 + + +@ CHECK: vext.8 d16, d17, d16, #3 @ encoding: [0xa0,0x03,0xf1,0xf2] +@ CHECK: vext.8 d16, d17, d16, #5 @ encoding: [0xa0,0x05,0xf1,0xf2] +@ CHECK: vext.8 q8, q9, q8, #3 @ encoding: [0xe0,0x03,0xf2,0xf2] +@ CHECK: vext.8 q8, q9, q8, #7 @ encoding: [0xe0,0x07,0xf2,0xf2] +@ CHECK: vext.16 d16, d17, d16, #3 @ encoding: [0xa0,0x06,0xf1,0xf2] +@ CHECK: vext.32 q8, q9, q8, #3 @ encoding: [0xe0,0x0c,0xf2,0xf2] +@ CHECK: vext.64 q8, q9, q8, #1 @ encoding: [0xe0,0x08,0xf2,0xf2] + +@ CHECK: vext.8 d17, d17, d16, #3 @ encoding: [0xa0,0x13,0xf1,0xf2] +@ CHECK: vext.8 d7, d7, d11, #5 @ encoding: [0x0b,0x75,0xb7,0xf2] +@ CHECK: vext.8 q3, q3, q8, #3 @ encoding: [0x60,0x63,0xb6,0xf2] +@ CHECK: vext.8 q9, q9, q4, #7 @ encoding: [0xc8,0x27,0xf2,0xf2] +@ CHECK: vext.16 d1, d1, d26, #3 @ encoding: [0x2a,0x16,0xb1,0xf2] +@ CHECK: vext.32 q5, q5, q8, #3 @ encoding: [0x60,0xac,0xba,0xf2] +@ CHECK: vext.64 q5, q5, q8, #1 @ encoding: [0x60,0xa8,0xba,0xf2] + + vtrn.8 d17, d16 -@ CHECK: vtrn.16 d17, d16 @ encoding: [0xa0,0x10,0xf6,0xf3] vtrn.16 d17, d16 -@ CHECK: vtrn.32 d17, d16 @ encoding: [0xa0,0x10,0xfa,0xf3] vtrn.32 d17, d16 -@ CHECK: vtrn.8 q9, q8 @ encoding: [0xe0,0x20,0xf2,0xf3] vtrn.8 q9, q8 -@ CHECK: vtrn.16 q9, q8 @ encoding: [0xe0,0x20,0xf6,0xf3] vtrn.16 q9, q8 -@ CHECK: vtrn.32 q9, q8 @ encoding: [0xe0,0x20,0xfa,0xf3] vtrn.32 q9, q8 -@ CHECK: vuzp.8 d17, d16 @ encoding: [0x20,0x11,0xf2,0xf3] + +@ CHECK: vtrn.8 d17, d16 @ encoding: [0xa0,0x10,0xf2,0xf3] +@ CHECK: vtrn.16 d17, d16 @ encoding: [0xa0,0x10,0xf6,0xf3] +@ CHECK: vtrn.32 d17, d16 @ encoding: [0xa0,0x10,0xfa,0xf3] +@ CHECK: vtrn.8 q9, q8 @ encoding: [0xe0,0x20,0xf2,0xf3] +@ CHECK: vtrn.16 q9, q8 @ encoding: [0xe0,0x20,0xf6,0xf3] +@ CHECK: vtrn.32 q9, q8 @ encoding: [0xe0,0x20,0xfa,0xf3] + + vuzp.8 d17, d16 -@ CHECK: vuzp.16 d17, d16 @ encoding: [0x20,0x11,0xf6,0xf3] vuzp.16 d17, d16 -@ CHECK: vuzp.8 q9, q8 @ encoding: [0x60,0x21,0xf2,0xf3] vuzp.8 q9, q8 -@ CHECK: vuzp.16 q9, q8 @ encoding: [0x60,0x21,0xf6,0xf3] vuzp.16 q9, q8 -@ CHECK: vuzp.32 q9, q8 @ encoding: [0x60,0x21,0xfa,0xf3] vuzp.32 q9, q8 -@ CHECK: vzip.8 d17, d16 @ encoding: [0xa0,0x11,0xf2,0xf3] vzip.8 d17, d16 -@ CHECK: vzip.16 d17, d16 @ encoding: [0xa0,0x11,0xf6,0xf3] vzip.16 d17, d16 -@ CHECK: vzip.8 q9, q8 @ encoding: [0xe0,0x21,0xf2,0xf3] vzip.8 q9, q8 -@ CHECK: vzip.16 q9, q8 @ encoding: [0xe0,0x21,0xf6,0xf3] vzip.16 q9, q8 -@ CHECK: vzip.32 q9, q8 @ encoding: [0xe0,0x21,0xfa,0xf3] vzip.32 q9, q8 + vzip.32 d2, d3 + vuzp.32 d2, d3 + +@ CHECK: vuzp.8 d17, d16 @ encoding: [0x20,0x11,0xf2,0xf3] +@ CHECK: vuzp.16 d17, d16 @ encoding: [0x20,0x11,0xf6,0xf3] +@ CHECK: vuzp.8 q9, q8 @ encoding: [0x60,0x21,0xf2,0xf3] +@ CHECK: vuzp.16 q9, q8 @ encoding: [0x60,0x21,0xf6,0xf3] +@ CHECK: vuzp.32 q9, q8 @ encoding: [0x60,0x21,0xfa,0xf3] +@ CHECK: vzip.8 d17, d16 @ encoding: [0xa0,0x11,0xf2,0xf3] +@ CHECK: vzip.16 d17, d16 @ encoding: [0xa0,0x11,0xf6,0xf3] +@ CHECK: vzip.8 q9, q8 @ encoding: [0xe0,0x21,0xf2,0xf3] +@ CHECK: vzip.16 q9, q8 @ encoding: [0xe0,0x21,0xf6,0xf3] +@ CHECK: vzip.32 q9, q8 @ encoding: [0xe0,0x21,0xfa,0xf3] +@ CHECK: vtrn.32 d2, d3 @ encoding: [0x83,0x20,0xba,0xf3] +@ CHECK: vtrn.32 d2, d3 @ encoding: [0x83,0x20,0xba,0xf3] + + +@ VTRN alternate size suffices + + vtrn.8 d3, d9 + vtrn.i8 d3, d9 + vtrn.u8 d3, d9 + vtrn.p8 d3, d9 + vtrn.16 d3, d9 + vtrn.i16 d3, d9 + vtrn.u16 d3, d9 + vtrn.p16 d3, d9 + vtrn.32 d3, d9 + vtrn.i32 d3, d9 + vtrn.u32 d3, d9 + vtrn.f32 d3, d9 + vtrn.f d3, d9 + + vtrn.8 q14, q6 + vtrn.i8 q14, q6 + vtrn.u8 q14, q6 + vtrn.p8 q14, q6 + vtrn.16 q14, q6 + vtrn.i16 q14, q6 + vtrn.u16 q14, q6 + vtrn.p16 q14, q6 + vtrn.32 q14, q6 + vtrn.i32 q14, q6 + vtrn.u32 q14, q6 + vtrn.f32 q14, q6 + vtrn.f q14, q6 + +@ CHECK: vtrn.8 d3, d9 @ encoding: [0x89,0x30,0xb2,0xf3] +@ CHECK: vtrn.8 d3, d9 @ encoding: [0x89,0x30,0xb2,0xf3] +@ CHECK: vtrn.8 d3, d9 @ encoding: [0x89,0x30,0xb2,0xf3] +@ CHECK: vtrn.8 d3, d9 @ encoding: [0x89,0x30,0xb2,0xf3] +@ CHECK: vtrn.16 d3, d9 @ encoding: [0x89,0x30,0xb6,0xf3] +@ CHECK: vtrn.16 d3, d9 @ encoding: [0x89,0x30,0xb6,0xf3] +@ CHECK: vtrn.16 d3, d9 @ encoding: [0x89,0x30,0xb6,0xf3] +@ CHECK: vtrn.16 d3, d9 @ encoding: [0x89,0x30,0xb6,0xf3] +@ CHECK: vtrn.32 d3, d9 @ encoding: [0x89,0x30,0xba,0xf3] +@ CHECK: vtrn.32 d3, d9 @ encoding: [0x89,0x30,0xba,0xf3] +@ CHECK: vtrn.32 d3, d9 @ encoding: [0x89,0x30,0xba,0xf3] +@ CHECK: vtrn.32 d3, d9 @ encoding: [0x89,0x30,0xba,0xf3] +@ CHECK: vtrn.32 d3, d9 @ encoding: [0x89,0x30,0xba,0xf3] + +@ CHECK: vtrn.8 q14, q6 @ encoding: [0xcc,0xc0,0xf2,0xf3] +@ CHECK: vtrn.8 q14, q6 @ encoding: [0xcc,0xc0,0xf2,0xf3] +@ CHECK: vtrn.8 q14, q6 @ encoding: [0xcc,0xc0,0xf2,0xf3] +@ CHECK: vtrn.8 q14, q6 @ encoding: [0xcc,0xc0,0xf2,0xf3] +@ CHECK: vtrn.16 q14, q6 @ encoding: [0xcc,0xc0,0xf6,0xf3] +@ CHECK: vtrn.16 q14, q6 @ encoding: [0xcc,0xc0,0xf6,0xf3] +@ CHECK: vtrn.16 q14, q6 @ encoding: [0xcc,0xc0,0xf6,0xf3] +@ CHECK: vtrn.16 q14, q6 @ encoding: [0xcc,0xc0,0xf6,0xf3] +@ CHECK: vtrn.32 q14, q6 @ encoding: [0xcc,0xc0,0xfa,0xf3] +@ CHECK: vtrn.32 q14, q6 @ encoding: [0xcc,0xc0,0xfa,0xf3] +@ CHECK: vtrn.32 q14, q6 @ encoding: [0xcc,0xc0,0xfa,0xf3] +@ CHECK: vtrn.32 q14, q6 @ encoding: [0xcc,0xc0,0xfa,0xf3] +@ CHECK: vtrn.32 q14, q6 @ encoding: [0xcc,0xc0,0xfa,0xf3] + diff --git a/test/MC/ARM/neon-sub-encoding.s b/test/MC/ARM/neon-sub-encoding.s index 241a01f..0622e19 100644 --- a/test/MC/ARM/neon-sub-encoding.s +++ b/test/MC/ARM/neon-sub-encoding.s @@ -1,25 +1,51 @@ @ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s -@ CHECK: vsub.i8 d16, d17, d16 @ encoding: [0xa0,0x08,0x41,0xf3] vsub.i8 d16, d17, d16 -@ CHECK: vsub.i16 d16, d17, d16 @ encoding: [0xa0,0x08,0x51,0xf3] vsub.i16 d16, d17, d16 -@ CHECK: vsub.i32 d16, d17, d16 @ encoding: [0xa0,0x08,0x61,0xf3] vsub.i32 d16, d17, d16 -@ CHECK: vsub.i64 d16, d17, d16 @ encoding: [0xa0,0x08,0x71,0xf3] vsub.i64 d16, d17, d16 -@ CHECK: vsub.f32 d16, d16, d17 @ encoding: [0xa1,0x0d,0x60,0xf2] vsub.f32 d16, d16, d17 -@ CHECK: vsub.i8 q8, q8, q9 @ encoding: [0xe2,0x08,0x40,0xf3] vsub.i8 q8, q8, q9 -@ CHECK: vsub.i16 q8, q8, q9 @ encoding: [0xe2,0x08,0x50,0xf3] vsub.i16 q8, q8, q9 -@ CHECK: vsub.i32 q8, q8, q9 @ encoding: [0xe2,0x08,0x60,0xf3] vsub.i32 q8, q8, q9 -@ CHECK: vsub.i64 q8, q8, q9 @ encoding: [0xe2,0x08,0x70,0xf3] vsub.i64 q8, q8, q9 -@ CHECK: vsub.f32 q8, q8, q9 @ encoding: [0xe2,0x0d,0x60,0xf2] vsub.f32 q8, q8, q9 + + vsub.i8 d13, d21 + vsub.i16 d14, d22 + vsub.i32 d15, d23 + vsub.i64 d16, d24 + vsub.f32 d17, d25 + vsub.i8 q1, q10 + vsub.i16 q2, q9 + vsub.i32 q3, q8 + vsub.i64 q4, q7 + vsub.f32 q5, q6 + +@ CHECK: vsub.i8 d16, d17, d16 @ encoding: [0xa0,0x08,0x41,0xf3] +@ CHECK: vsub.i16 d16, d17, d16 @ encoding: [0xa0,0x08,0x51,0xf3] +@ CHECK: vsub.i32 d16, d17, d16 @ encoding: [0xa0,0x08,0x61,0xf3] +@ CHECK: vsub.i64 d16, d17, d16 @ encoding: [0xa0,0x08,0x71,0xf3] +@ CHECK: vsub.f32 d16, d16, d17 @ encoding: [0xa1,0x0d,0x60,0xf2] +@ CHECK: vsub.i8 q8, q8, q9 @ encoding: [0xe2,0x08,0x40,0xf3] +@ CHECK: vsub.i16 q8, q8, q9 @ encoding: [0xe2,0x08,0x50,0xf3] +@ CHECK: vsub.i32 q8, q8, q9 @ encoding: [0xe2,0x08,0x60,0xf3] +@ CHECK: vsub.i64 q8, q8, q9 @ encoding: [0xe2,0x08,0x70,0xf3] +@ CHECK: vsub.f32 q8, q8, q9 @ encoding: [0xe2,0x0d,0x60,0xf2] + +@ CHECK: vsub.i8 d13, d13, d21 @ encoding: [0x25,0xd8,0x0d,0xf3] +@ CHECK: vsub.i16 d14, d14, d22 @ encoding: [0x26,0xe8,0x1e,0xf3] +@ CHECK: vsub.i32 d15, d15, d23 @ encoding: [0x27,0xf8,0x2f,0xf3] +@ CHECK: vsub.i64 d16, d16, d24 @ encoding: [0xa8,0x08,0x70,0xf3] +@ CHECK: vsub.f32 d17, d17, d25 @ encoding: [0xa9,0x1d,0x61,0xf2] +@ CHECK: vsub.i8 q1, q1, q10 @ encoding: [0x64,0x28,0x02,0xf3] +@ CHECK: vsub.i16 q2, q2, q9 @ encoding: [0x62,0x48,0x14,0xf3] +@ CHECK: vsub.i32 q3, q3, q8 @ encoding: [0x60,0x68,0x26,0xf3] +@ CHECK: vsub.i64 q4, q4, q7 @ encoding: [0x4e,0x88,0x38,0xf3] +@ CHECK: vsub.f32 q5, q5, q6 @ encoding: [0x4c,0xad,0x2a,0xf2] + + + @ CHECK: vsubl.s8 q8, d17, d16 @ encoding: [0xa0,0x02,0xc1,0xf2] vsubl.s8 q8, d17, d16 @ CHECK: vsubl.s16 q8, d17, d16 @ encoding: [0xa0,0x02,0xd1,0xf2] diff --git a/test/MC/ARM/neon-table-encoding.s b/test/MC/ARM/neon-table-encoding.s index 7bf47c7..343ae83 100644 --- a/test/MC/ARM/neon-table-encoding.s +++ b/test/MC/ARM/neon-table-encoding.s @@ -1,19 +1,22 @@ @ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s -@ XFAIL: * -@ CHECK: vtbl.8 d16, {d17}, d16 @ encoding: [0xa0,0x08,0xf1,0xf3] vtbl.8 d16, {d17}, d16 -@ CHECK: vtbl.8 d16, {d16, d17}, d18 @ encoding: [0xa2,0x09,0xf0,0xf3] vtbl.8 d16, {d16, d17}, d18 -@ CHECK: vtbl.8 d16, {d16, d17, d18}, d20 @ encoding: [0xa4,0x0a,0xf0,0xf3] vtbl.8 d16, {d16, d17, d18}, d20 -@ CHECK: vtbl.8 d16, {d16, d17, d18, d19}, d20 @ encoding: [0xa4,0x0b,0xf0,0xf3] vtbl.8 d16, {d16, d17, d18, d19}, d20 -@ CHECK: vtbx.8 d18, {d16}, d17 @ encoding: [0xe1,0x28,0xf0,0xf3] + +@ CHECK: vtbl.8 d16, {d17}, d16 @ encoding: [0xa0,0x08,0xf1,0xf3] +@ CHECK: vtbl.8 d16, {d16, d17}, d18 @ encoding: [0xa2,0x09,0xf0,0xf3] +@ CHECK: vtbl.8 d16, {d16, d17, d18}, d20 @ encoding: [0xa4,0x0a,0xf0,0xf3] +@ CHECK: vtbl.8 d16, {d16, d17, d18, d19}, d20 @ encoding: [0xa4,0x0b,0xf0,0xf3] + + vtbx.8 d18, {d16}, d17 -@ CHECK: vtbx.8 d19, {d16, d17}, d18 @ encoding: [0xe2,0x39,0xf0,0xf3] vtbx.8 d19, {d16, d17}, d18 -@ CHECK: vtbx.8 d20, {d16, d17, d18}, d21 @ encoding: [0xe5,0x4a,0xf0,0xf3] vtbx.8 d20, {d16, d17, d18}, d21 -@ CHECK: vtbx.8 d20, {d16, d17, d18, d19}, d21 @ encoding: [0xe5,0x4b,0xf0,0xf3] vtbx.8 d20, {d16, d17, d18, d19}, d21 + +@ CHECK: vtbx.8 d18, {d16}, d17 @ encoding: [0xe1,0x28,0xf0,0xf3] +@ CHECK: vtbx.8 d19, {d16, d17}, d18 @ encoding: [0xe2,0x39,0xf0,0xf3] +@ CHECK: vtbx.8 d20, {d16, d17, d18}, d21 @ encoding: [0xe5,0x4a,0xf0,0xf3] +@ CHECK: vtbx.8 d20, {d16, d17, d18, d19}, d21 @ encoding: [0xe5,0x4b,0xf0,0xf3] diff --git a/test/MC/ARM/neon-vld-encoding.s b/test/MC/ARM/neon-vld-encoding.s index 55c8868..3cc6bf1 100644 --- a/test/MC/ARM/neon-vld-encoding.s +++ b/test/MC/ARM/neon-vld-encoding.s @@ -1,5 +1,4 @@ @ RUN: llvm-mc -mcpu=cortex-a8 -triple armv7-apple-darwin -show-encoding < %s | FileCheck %s -@ XFAIL: * vld1.8 {d16}, [r0, :64] vld1.16 {d16}, [r0] @@ -9,15 +8,107 @@ vld1.16 {d16, d17}, [r0, :128] vld1.32 {d16, d17}, [r0] vld1.64 {d16, d17}, [r0] + vld1.8 {d1, d2, d3}, [r3] + vld1.16 {d4, d5, d6}, [r3, :64] + vld1.32 {d5, d6, d7}, [r3] + vld1.64 {d6, d7, d8}, [r3, :64] + vld1.8 {d1, d2, d3, d4}, [r3] + vld1.16 {d4, d5, d6, d7}, [r3, :64] + vld1.32 {d5, d6, d7, d8}, [r3] + vld1.64 {d6, d7, d8, d9}, [r3, :64] -@ CHECK: vld1.8 {d16}, [r0, :64] @ encoding: [0x1f,0x07,0x60,0xf4] -@ CHECK: vld1.16 {d16}, [r0] @ encoding: [0x4f,0x07,0x60,0xf4] -@ CHECK: vld1.32 {d16}, [r0] @ encoding: [0x8f,0x07,0x60,0xf4] -@ CHECK: vld1.64 {d16}, [r0] @ encoding: [0xcf,0x07,0x60,0xf4] -@ CHECK: vld1.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x0a,0x60,0xf4] -@ CHECK: vld1.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x0a,0x60,0xf4] -@ CHECK: vld1.32 {d16, d17}, [r0]@ encoding: [0x8f,0x0a,0x60,0xf4] -@ CHECK: vld1.64 {d16, d17}, [r0]@ encoding: [0xcf,0x0a,0x60,0xf4] + vld1.8 {d16}, [r0, :64]! + vld1.16 {d16}, [r0]! + vld1.32 {d16}, [r0]! + vld1.64 {d16}, [r0]! + vld1.8 {d16, d17}, [r0, :64]! + vld1.16 {d16, d17}, [r0, :128]! + vld1.32 {d16, d17}, [r0]! + vld1.64 {d16, d17}, [r0]! + + vld1.8 {d16}, [r0, :64], r5 + vld1.16 {d16}, [r0], r5 + vld1.32 {d16}, [r0], r5 + vld1.64 {d16}, [r0], r5 + vld1.8 {d16, d17}, [r0, :64], r5 + vld1.16 {d16, d17}, [r0, :128], r5 + vld1.32 {d16, d17}, [r0], r5 + vld1.64 {d16, d17}, [r0], r5 + + vld1.8 {d1, d2, d3}, [r3]! + vld1.16 {d4, d5, d6}, [r3, :64]! + vld1.32 {d5, d6, d7}, [r3]! + vld1.64 {d6, d7, d8}, [r3, :64]! + + vld1.8 {d1, d2, d3}, [r3], r6 + vld1.16 {d4, d5, d6}, [r3, :64], r6 + vld1.32 {d5, d6, d7}, [r3], r6 + vld1.64 {d6, d7, d8}, [r3, :64], r6 + + vld1.8 {d1, d2, d3, d4}, [r3]! + vld1.16 {d4, d5, d6, d7}, [r3, :64]! + vld1.32 {d5, d6, d7, d8}, [r3]! + vld1.64 {d6, d7, d8, d9}, [r3, :64]! + + vld1.8 {d1, d2, d3, d4}, [r3], r8 + vld1.16 {d4, d5, d6, d7}, [r3, :64], r8 + vld1.32 {d5, d6, d7, d8}, [r3], r8 + vld1.64 {d6, d7, d8, d9}, [r3, :64], r8 + +@ CHECK: vld1.8 {d16}, [r0, :64] @ encoding: [0x1f,0x07,0x60,0xf4] +@ CHECK: vld1.16 {d16}, [r0] @ encoding: [0x4f,0x07,0x60,0xf4] +@ CHECK: vld1.32 {d16}, [r0] @ encoding: [0x8f,0x07,0x60,0xf4] +@ CHECK: vld1.64 {d16}, [r0] @ encoding: [0xcf,0x07,0x60,0xf4] +@ CHECK: vld1.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x0a,0x60,0xf4] +@ CHECK: vld1.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x0a,0x60,0xf4] +@ CHECK: vld1.32 {d16, d17}, [r0] @ encoding: [0x8f,0x0a,0x60,0xf4] +@ CHECK: vld1.64 {d16, d17}, [r0] @ encoding: [0xcf,0x0a,0x60,0xf4] +@ CHECK: vld1.8 {d1, d2, d3}, [r3] @ encoding: [0x0f,0x16,0x23,0xf4] +@ CHECK: vld1.16 {d4, d5, d6}, [r3, :64] @ encoding: [0x5f,0x46,0x23,0xf4] +@ CHECK: vld1.32 {d5, d6, d7}, [r3] @ encoding: [0x8f,0x56,0x23,0xf4] +@ CHECK: vld1.64 {d6, d7, d8}, [r3, :64] @ encoding: [0xdf,0x66,0x23,0xf4] +@ CHECK: vld1.8 {d1, d2, d3, d4}, [r3] @ encoding: [0x0f,0x12,0x23,0xf4] +@ CHECK: vld1.16 {d4, d5, d6, d7}, [r3, :64] @ encoding: [0x5f,0x42,0x23,0xf4] +@ CHECK: vld1.32 {d5, d6, d7, d8}, [r3] @ encoding: [0x8f,0x52,0x23,0xf4] +@ CHECK: vld1.64 {d6, d7, d8, d9}, [r3, :64] @ encoding: [0xdf,0x62,0x23,0xf4] +@ CHECK: vld1.8 {d16}, [r0, :64]! @ encoding: [0x1d,0x07,0x60,0xf4] + +@ CHECK: vld1.16 {d16}, [r0]! @ encoding: [0x4d,0x07,0x60,0xf4] +@ CHECK: vld1.32 {d16}, [r0]! @ encoding: [0x8d,0x07,0x60,0xf4] +@ CHECK: vld1.64 {d16}, [r0]! @ encoding: [0xcd,0x07,0x60,0xf4] +@ CHECK: vld1.8 {d16, d17}, [r0, :64]! @ encoding: [0x1d,0x0a,0x60,0xf4] +@ CHECK: vld1.16 {d16, d17}, [r0, :128]! @ encoding: [0x6d,0x0a,0x60,0xf4] +@ CHECK: vld1.32 {d16, d17}, [r0]! @ encoding: [0x8d,0x0a,0x60,0xf4] +@ CHECK: vld1.64 {d16, d17}, [r0]! @ encoding: [0xcd,0x0a,0x60,0xf4] + +@ CHECK: vld1.8 {d16}, [r0, :64], r5 @ encoding: [0x15,0x07,0x60,0xf4] +@ CHECK: vld1.16 {d16}, [r0], r5 @ encoding: [0x45,0x07,0x60,0xf4] +@ CHECK: vld1.32 {d16}, [r0], r5 @ encoding: [0x85,0x07,0x60,0xf4] +@ CHECK: vld1.64 {d16}, [r0], r5 @ encoding: [0xc5,0x07,0x60,0xf4] +@ CHECK: vld1.8 {d16, d17}, [r0, :64], r5 @ encoding: [0x15,0x0a,0x60,0xf4] +@ CHECK: vld1.16 {d16, d17}, [r0, :128], r5 @ encoding: [0x65,0x0a,0x60,0xf4] +@ CHECK: vld1.32 {d16, d17}, [r0], r5 @ encoding: [0x85,0x0a,0x60,0xf4] +@ CHECK: vld1.64 {d16, d17}, [r0], r5 @ encoding: [0xc5,0x0a,0x60,0xf4] + +@ CHECK: vld1.8 {d1, d2, d3}, [r3]! @ encoding: [0x0d,0x16,0x23,0xf4] +@ CHECK: vld1.16 {d4, d5, d6}, [r3, :64]! @ encoding: [0x5d,0x46,0x23,0xf4] +@ CHECK: vld1.32 {d5, d6, d7}, [r3]! @ encoding: [0x8d,0x56,0x23,0xf4] +@ CHECK: vld1.64 {d6, d7, d8}, [r3, :64]! @ encoding: [0xdd,0x66,0x23,0xf4] + +@ CHECK: vld1.8 {d1, d2, d3}, [r3], r6 @ encoding: [0x06,0x16,0x23,0xf4] +@ CHECK: vld1.16 {d4, d5, d6}, [r3, :64], r6 @ encoding: [0x56,0x46,0x23,0xf4] +@ CHECK: vld1.32 {d5, d6, d7}, [r3], r6 @ encoding: [0x86,0x56,0x23,0xf4] +@ CHECK: vld1.64 {d6, d7, d8}, [r3, :64], r6 @ encoding: [0xd6,0x66,0x23,0xf4] + +@ CHECK: vld1.8 {d1, d2, d3, d4}, [r3]! @ encoding: [0x0d,0x12,0x23,0xf4] +@ CHECK: vld1.16 {d4, d5, d6, d7}, [r3, :64]! @ encoding: [0x5d,0x42,0x23,0xf4] +@ CHECK: vld1.32 {d5, d6, d7, d8}, [r3]! @ encoding: [0x8d,0x52,0x23,0xf4] +@ CHECK: vld1.64 {d6, d7, d8, d9}, [r3, :64]! @ encoding: [0xdd,0x62,0x23,0xf4] + +@ CHECK: vld1.8 {d1, d2, d3, d4}, [r3], r8 @ encoding: [0x08,0x12,0x23,0xf4] +@ CHECK: vld1.16 {d4, d5, d6, d7}, [r3, :64], r8 @ encoding: [0x58,0x42,0x23,0xf4] +@ CHECK: vld1.32 {d5, d6, d7, d8}, [r3], r8 @ encoding: [0x88,0x52,0x23,0xf4] +@ CHECK: vld1.64 {d6, d7, d8, d9}, [r3, :64], r8 @ encoding: [0xd8,0x62,0x23,0xf4] vld2.8 {d16, d17}, [r0, :64] @@ -27,63 +118,154 @@ vld2.16 {d16, d17, d18, d19}, [r0, :128] vld2.32 {d16, d17, d18, d19}, [r0, :256] + vld2.8 {d19, d20}, [r0, :64]! + vld2.16 {d16, d17}, [r0, :128]! + vld2.32 {q10}, [r0]! + vld2.8 {d4-d7}, [r0, :64]! + vld2.16 {d1, d2, d3, d4}, [r0, :128]! + vld2.32 {q7, q8}, [r0, :256]! + + vld2.8 {d19, d20}, [r0, :64], r6 + vld2.16 {d16, d17}, [r0, :128], r6 + vld2.32 {q10}, [r0], r6 + vld2.8 {d4-d7}, [r0, :64], r6 + vld2.16 {d1, d2, d3, d4}, [r0, :128], r6 + vld2.32 {q7, q8}, [r0, :256], r6 + @ CHECK: vld2.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x08,0x60,0xf4] @ CHECK: vld2.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x08,0x60,0xf4] -@ CHECK: vld2.32 {d16, d17}, [r0]@ encoding: [0x8f,0x08,0x60,0xf4] -@ CHECK: vld2.8 {d16, d17, d18, d19}, [r0, :64]@ encoding: [0x1f,0x03,0x60,0xf4] +@ CHECK: vld2.32 {d16, d17}, [r0] @ encoding: [0x8f,0x08,0x60,0xf4] +@ CHECK: vld2.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x03,0x60,0xf4] @ CHECK: vld2.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x03,0x60,0xf4] @ CHECK: vld2.32 {d16, d17, d18, d19}, [r0, :256] @ encoding: [0xbf,0x03,0x60,0xf4] +@ CHECK: vld2.8 {d19, d20}, [r0, :64]! @ encoding: [0x1d,0x38,0x60,0xf4] +@ CHECK: vld2.16 {d16, d17}, [r0, :128]! @ encoding: [0x6d,0x08,0x60,0xf4] +@ CHECK: vld2.32 {d20, d21}, [r0]! @ encoding: [0x8d,0x48,0x60,0xf4] +@ CHECK: vld2.8 {d4, d5, d6, d7}, [r0, :64]! @ encoding: [0x1d,0x43,0x20,0xf4] +@ CHECK: vld2.16 {d1, d2, d3, d4}, [r0, :128]! @ encoding: [0x6d,0x13,0x20,0xf4] +@ CHECK: vld2.32 {d14, d15, d16, d17}, [r0, :256]! @ encoding: [0xbd,0xe3,0x20,0xf4] + +@ CHECK: vld2.8 {d19, d20}, [r0, :64], r6 @ encoding: [0x16,0x38,0x60,0xf4] +@ CHECK: vld2.16 {d16, d17}, [r0, :128], r6 @ encoding: [0x66,0x08,0x60,0xf4] +@ CHECK: vld2.32 {d20, d21}, [r0], r6 @ encoding: [0x86,0x48,0x60,0xf4] +@ CHECK: vld2.8 {d4, d5, d6, d7}, [r0, :64], r6 @ encoding: [0x16,0x43,0x20,0xf4] +@ CHECK: vld2.16 {d1, d2, d3, d4}, [r0, :128], r6 @ encoding: [0x66,0x13,0x20,0xf4] +@ CHECK: vld2.32 {d14, d15, d16, d17}, [r0, :256], r6 @ encoding: [0xb6,0xe3,0x20,0xf4] + + + vld3.8 {d16, d17, d18}, [r1] + vld3.16 {d6, d7, d8}, [r2] + vld3.32 {d1, d2, d3}, [r3] + vld3.8 {d16, d18, d20}, [r0, :64] + vld3.u16 {d27, d29, d31}, [r4] + vld3.i32 {d6, d8, d10}, [r5] - vld3.8 {d16, d17, d18}, [r0, :64] - vld3.16 {d16, d17, d18}, [r0] - vld3.32 {d16, d17, d18}, [r0] - vld3.8 {d16, d18, d20}, [r0, :64]! - vld3.8 {d17, d19, d21}, [r0, :64]! - vld3.16 {d16, d18, d20}, [r0]! - vld3.16 {d17, d19, d21}, [r0]! - vld3.32 {d16, d18, d20}, [r0]! - vld3.32 {d17, d19, d21}, [r0]! + vld3.i8 {d12, d13, d14}, [r6], r1 + vld3.i16 {d11, d12, d13}, [r7], r2 + vld3.u32 {d2, d3, d4}, [r8], r3 + vld3.8 {d4, d6, d8}, [r9], r4 + vld3.u16 {d14, d16, d18}, [r9], r4 + vld3.i32 {d16, d18, d20}, [r10], r5 -@ CHECK: vld3.8 {d16, d17, d18}, [r0, :64] @ encoding: [0x1f,0x04,0x60,0xf4] -@ CHECK: vld3.16 {d16, d17, d18}, [r0] @ encoding: [0x4f,0x04,0x60,0xf4] -@ CHECK: vld3.32 {d16, d17, d18}, [r0] @ encoding: [0x8f,0x04,0x60,0xf4] + vld3.p8 {d6, d7, d8}, [r8]! + vld3.16 {d9, d10, d11}, [r7]! + vld3.f32 {d1, d2, d3}, [r6]! + vld3.8 {d16, d18, d20}, [r0, :64]! + vld3.p16 {d20, d22, d24}, [r5]! + vld3.32 {d5, d7, d9}, [r4]! + + +@ CHECK: vld3.8 {d16, d17, d18}, [r1] @ encoding: [0x0f,0x04,0x61,0xf4] +@ CHECK: vld3.16 {d6, d7, d8}, [r2] @ encoding: [0x4f,0x64,0x22,0xf4] +@ CHECK: vld3.32 {d1, d2, d3}, [r3] @ encoding: [0x8f,0x14,0x23,0xf4] +@ CHECK: vld3.8 {d16, d18, d20}, [r0, :64] @ encoding: [0x1f,0x05,0x60,0xf4] +@ CHECK: vld3.16 {d27, d29, d31}, [r4] @ encoding: [0x4f,0xb5,0x64,0xf4] +@ CHECK: vld3.32 {d6, d8, d10}, [r5] @ encoding: [0x8f,0x65,0x25,0xf4] +@ CHECK: vld3.8 {d12, d13, d14}, [r6], r1 @ encoding: [0x01,0xc4,0x26,0xf4] +@ CHECK: vld3.16 {d11, d12, d13}, [r7], r2 @ encoding: [0x42,0xb4,0x27,0xf4] +@ CHECK: vld3.32 {d2, d3, d4}, [r8], r3 @ encoding: [0x83,0x24,0x28,0xf4] +@ CHECK: vld3.8 {d4, d6, d8}, [r9], r4 @ encoding: [0x04,0x45,0x29,0xf4] +@ CHECK: vld3.16 {d14, d16, d18}, [r9], r4 @ encoding: [0x44,0xe5,0x29,0xf4] +@ CHECK: vld3.32 {d16, d18, d20}, [r10], r5 @ encoding: [0x85,0x05,0x6a,0xf4] +@ CHECK: vld3.8 {d6, d7, d8}, [r8]! @ encoding: [0x0d,0x64,0x28,0xf4] +@ CHECK: vld3.16 {d9, d10, d11}, [r7]! @ encoding: [0x4d,0x94,0x27,0xf4] +@ CHECK: vld3.32 {d1, d2, d3}, [r6]! @ encoding: [0x8d,0x14,0x26,0xf4] @ CHECK: vld3.8 {d16, d18, d20}, [r0, :64]! @ encoding: [0x1d,0x05,0x60,0xf4] -@ CHECK: vld3.8 {d17, d19, d21}, [r0, :64]! @ encoding: [0x1d,0x15,0x60,0xf4] -@ CHECK: vld3.16 {d16, d18, d20}, [r0]! @ encoding: [0x4d,0x05,0x60,0xf4] -@ CHECK: vld3.16 {d17, d19, d21}, [r0]! @ encoding: [0x4d,0x15,0x60,0xf4] -@ CHECK: vld3.32 {d16, d18, d20}, [r0]! @ encoding: [0x8d,0x05,0x60,0xf4] -@ CHECK: vld3.32 {d17, d19, d21}, [r0]! @ encoding: [0x8d,0x15,0x60,0xf4] - - - vld4.8 {d16, d17, d18, d19}, [r0, :64] - vld4.16 {d16, d17, d18, d19}, [r0, :128] - vld4.32 {d16, d17, d18, d19}, [r0, :256] - vld4.8 {d16, d18, d20, d22}, [r0, :256]! - vld4.8 {d17, d19, d21, d23}, [r0, :256]! - vld4.16 {d16, d18, d20, d22}, [r0]! - vld4.16 {d17, d19, d21, d23}, [r0]! - vld4.32 {d16, d18, d20, d22}, [r0]! - vld4.32 {d17, d19, d21, d23}, [r0]! - -@ CHECK: vld4.8 {d16, d17, d18, d19}, [r0, :64]@ encoding: [0x1f,0x00,0x60,0xf4] -@ CHECK: vld4.16 {d16, d17, d18, d19}, [r0,:128]@ encoding:[0x6f,0x00,0x60,0xf4] -@ CHECK: vld4.32 {d16, d17, d18, d19}, [r0,:256]@ encoding:[0xbf,0x00,0x60,0xf4] -@ CHECK: vld4.8 {d16, d18, d20, d22}, [r0,:256]!@ encoding:[0x3d,0x01,0x60,0xf4] -@ CHECK: vld4.8 {d17, d19, d21, d23}, [r0,:256]!@ encoding:[0x3d,0x11,0x60,0xf4] -@ CHECK: vld4.16 {d16, d18, d20, d22}, [r0]! @ encoding: [0x4d,0x01,0x60,0xf4] -@ CHECK: vld4.16 {d17, d19, d21, d23}, [r0]! @ encoding: [0x4d,0x11,0x60,0xf4] -@ CHECK: vld4.32 {d16, d18, d20, d22}, [r0]! @ encoding: [0x8d,0x01,0x60,0xf4] -@ CHECK: vld4.32 {d17, d19, d21, d23}, [r0]! @ encoding: [0x8d,0x11,0x60,0xf4] +@ CHECK: vld3.16 {d20, d22, d24}, [r5]! @ encoding: [0x4d,0x45,0x65,0xf4] +@ CHECK: vld3.32 {d5, d7, d9}, [r4]! @ encoding: [0x8d,0x55,0x24,0xf4] + + + vld4.8 {d16, d17, d18, d19}, [r1, :64] + vld4.16 {d16, d17, d18, d19}, [r2, :128] + vld4.32 {d16, d17, d18, d19}, [r3, :256] + vld4.8 {d17, d19, d21, d23}, [r5, :256] + vld4.16 {d17, d19, d21, d23}, [r7] + vld4.32 {d16, d18, d20, d22}, [r8] + + vld4.s8 {d16, d17, d18, d19}, [r1, :64]! + vld4.s16 {d16, d17, d18, d19}, [r2, :128]! + vld4.s32 {d16, d17, d18, d19}, [r3, :256]! + vld4.u8 {d17, d19, d21, d23}, [r5, :256]! + vld4.u16 {d17, d19, d21, d23}, [r7]! + vld4.u32 {d16, d18, d20, d22}, [r8]! + + vld4.p8 {d16, d17, d18, d19}, [r1, :64], r8 + vld4.p16 {d16, d17, d18, d19}, [r2], r7 + vld4.f32 {d16, d17, d18, d19}, [r3, :64], r5 + vld4.i8 {d16, d18, d20, d22}, [r4, :256], r2 + vld4.i16 {d16, d18, d20, d22}, [r6], r3 + vld4.i32 {d17, d19, d21, d23}, [r9], r4 + +@ CHECK: vld4.8 {d16, d17, d18, d19}, [r1, :64] @ encoding: [0x1f,0x00,0x61,0xf4] +@ CHECK: vld4.16 {d16, d17, d18, d19}, [r2, :128] @ encoding: [0x6f,0x00,0x62,0xf4] +@ CHECK: vld4.32 {d16, d17, d18, d19}, [r3, :256] @ encoding: [0xbf,0x00,0x63,0xf4] +@ CHECK: vld4.8 {d17, d19, d21, d23}, [r5, :256] @ encoding: [0x3f,0x11,0x65,0xf4] +@ CHECK: vld4.16 {d17, d19, d21, d23}, [r7] @ encoding: [0x4f,0x11,0x67,0xf4] +@ CHECK: vld4.32 {d16, d18, d20, d22}, [r8] @ encoding: [0x8f,0x01,0x68,0xf4] +@ CHECK: vld4.8 {d16, d17, d18, d19}, [r1, :64]! @ encoding: [0x1d,0x00,0x61,0xf4] +@ CHECK: vld4.16 {d16, d17, d18, d19}, [r2, :128]! @ encoding: [0x6d,0x00,0x62,0xf4] +@ CHECK: vld4.32 {d16, d17, d18, d19}, [r3, :256]! @ encoding: [0xbd,0x00,0x63,0xf4] +@ CHECK: vld4.8 {d17, d19, d21, d23}, [r5, :256]! @ encoding: [0x3d,0x11,0x65,0xf4] +@ CHECK: vld4.16 {d17, d19, d21, d23}, [r7]! @ encoding: [0x4d,0x11,0x67,0xf4] +@ CHECK: vld4.32 {d16, d18, d20, d22}, [r8]! @ encoding: [0x8d,0x01,0x68,0xf4] +@ CHECK: vld4.8 {d16, d17, d18, d19}, [r1, :64], r8 @ encoding: [0x18,0x00,0x61,0xf4] +@ CHECK: vld4.16 {d16, d17, d18, d19}, [r2], r7 @ encoding: [0x47,0x00,0x62,0xf4] +@ CHECK: vld4.32 {d16, d17, d18, d19}, [r3, :64], r5 @ encoding: [0x95,0x00,0x63,0xf4] +@ CHECK: vld4.8 {d16, d18, d20, d22}, [r4, :256], r2 @ encoding: [0x32,0x01,0x64,0xf4] +@ CHECK: vld4.16 {d16, d18, d20, d22}, [r6], r3 @ encoding: [0x43,0x01,0x66,0xf4] +@ CHECK: vld4.32 {d17, d19, d21, d23}, [r9], r4 @ encoding: [0x84,0x11,0x69,0xf4] + + + vld1.8 {d4[]}, [r1] + vld1.8 {d4[]}, [r1]! + vld1.8 {d4[]}, [r1], r3 + vld1.8 {d4[], d5[]}, [r1] + vld1.8 {d4[], d5[]}, [r1]! + vld1.8 {d4[], d5[]}, [r1], r3 +@ CHECK: vld1.8 {d4[]}, [r1] @ encoding: [0x0f,0x4c,0xa1,0xf4] +@ CHECK: vld1.8 {d4[]}, [r1]! @ encoding: [0x0d,0x4c,0xa1,0xf4] +@ CHECK: vld1.8 {d4[]}, [r1], r3 @ encoding: [0x03,0x4c,0xa1,0xf4] +@ CHECK: vld1.8 {d4[], d5[]}, [r1] @ encoding: [0x2f,0x4c,0xa1,0xf4] +@ CHECK: vld1.8 {d4[], d5[]}, [r1]! @ encoding: [0x2d,0x4c,0xa1,0xf4] +@ CHECK: vld1.8 {d4[], d5[]}, [r1], r3 @ encoding: [0x23,0x4c,0xa1,0xf4] vld1.8 {d16[3]}, [r0] vld1.16 {d16[2]}, [r0, :16] vld1.32 {d16[1]}, [r0, :32] + vld1.p8 d12[6], [r2]! + vld1.i8 d12[6], [r2], r2 + vld1.u16 d12[3], [r2]! + vld1.16 d12[2], [r2], r2 @ CHECK: vld1.8 {d16[3]}, [r0] @ encoding: [0x6f,0x00,0xe0,0xf4] @ CHECK: vld1.16 {d16[2]}, [r0, :16] @ encoding: [0x9f,0x04,0xe0,0xf4] @ CHECK: vld1.32 {d16[1]}, [r0, :32] @ encoding: [0xbf,0x08,0xe0,0xf4] +@ CHECK: vld1.8 {d12[6]}, [r2]! @ encoding: [0xcd,0xc0,0xa2,0xf4] +@ CHECK: vld1.8 {d12[6]}, [r2], r2 @ encoding: [0xc2,0xc0,0xa2,0xf4] +@ CHECK: vld1.16 {d12[3]}, [r2]! @ encoding: [0xcd,0xc4,0xa2,0xf4] +@ CHECK: vld1.16 {d12[2]}, [r2], r2 @ encoding: [0x82,0xc4,0xa2,0xf4] vld2.8 {d16[1], d17[1]}, [r0, :16] @@ -91,35 +273,225 @@ vld2.32 {d16[1], d17[1]}, [r0] vld2.16 {d17[1], d19[1]}, [r0] vld2.32 {d17[0], d19[0]}, [r0, :64] + vld2.32 {d17[0], d19[0]}, [r0, :64]! + vld2.8 {d2[4], d3[4]}, [r2], r3 + vld2.8 {d2[4], d3[4]}, [r2]! + vld2.8 {d2[4], d3[4]}, [r2] + vld2.32 {d22[], d23[]}, [r1] + vld2.32 {d22[], d24[]}, [r1] + vld2.32 {d10[ ],d11[ ]}, [r3]! + vld2.32 {d14[ ],d16[ ]}, [r4]! + vld2.32 {d22[ ],d23[ ]}, [r5], r4 + vld2.32 {d22[ ],d24[ ]}, [r6], r4 @ CHECK: vld2.8 {d16[1], d17[1]}, [r0, :16] @ encoding: [0x3f,0x01,0xe0,0xf4] @ CHECK: vld2.16 {d16[1], d17[1]}, [r0, :32] @ encoding: [0x5f,0x05,0xe0,0xf4] @ CHECK: vld2.32 {d16[1], d17[1]}, [r0] @ encoding: [0x8f,0x09,0xe0,0xf4] @ CHECK: vld2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xe0,0xf4] @ CHECK: vld2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xe0,0xf4] +@ CHECK: vld2.32 {d17[0], d19[0]}, [r0, :64]! @ encoding: [0x5d,0x19,0xe0,0xf4] +@ CHECK: vld2.8 {d2[4], d3[4]}, [r2], r3 @ encoding: [0x83,0x21,0xa2,0xf4] +@ CHECK: vld2.8 {d2[4], d3[4]}, [r2]! @ encoding: [0x8d,0x21,0xa2,0xf4] +@ CHECK: vld2.8 {d2[4], d3[4]}, [r2] @ encoding: [0x8f,0x21,0xa2,0xf4] +@ CHECK: vld2.32 {d22[], d23[]}, [r1] @ encoding: [0x8f,0x6d,0xe1,0xf4] +@ CHECK: vld2.32 {d22[], d24[]}, [r1] @ encoding: [0xaf,0x6d,0xe1,0xf4] +@ CHECK: vld2.32 {d10[], d11[]}, [r3]! @ encoding: [0x8d,0xad,0xa3,0xf4] +@ CHECK: vld2.32 {d14[], d16[]}, [r4]! @ encoding: [0xad,0xed,0xa4,0xf4] +@ CHECK: vld2.32 {d22[], d23[]}, [r5], r4 @ encoding: [0x84,0x6d,0xe5,0xf4] +@ CHECK: vld2.32 {d22[], d24[]}, [r6], r4 @ encoding: [0xa4,0x6d,0xe6,0xf4] + + + vld3.8 {d16[1], d17[1], d18[1]}, [r1] + vld3.16 {d6[1], d7[1], d8[1]}, [r2] + vld3.32 {d1[1], d2[1], d3[1]}, [r3] + vld3.u16 {d27[2], d29[2], d31[2]}, [r4] + vld3.i32 {d6[0], d8[0], d10[0]}, [r5] + + vld3.i8 {d12[3], d13[3], d14[3]}, [r6], r1 + vld3.i16 {d11[2], d12[2], d13[2]}, [r7], r2 + vld3.u32 {d2[1], d3[1], d4[1]}, [r8], r3 + vld3.u16 {d14[2], d16[2], d18[2]}, [r9], r4 + vld3.i32 {d16[0], d18[0], d20[0]}, [r10], r5 + + vld3.p8 {d6[6], d7[6], d8[6]}, [r8]! + vld3.16 {d9[2], d10[2], d11[2]}, [r7]! + vld3.f32 {d1[1], d2[1], d3[1]}, [r6]! + vld3.p16 {d20[2], d22[2], d24[2]}, [r5]! + vld3.32 {d5[0], d7[0], d9[0]}, [r4]! + +@ CHECK: vld3.8 {d16[1], d17[1], d18[1]}, [r1] @ encoding: [0x2f,0x02,0xe1,0xf4] +@ CHECK: vld3.16 {d6[1], d7[1], d8[1]}, [r2] @ encoding: [0x4f,0x66,0xa2,0xf4] +@ CHECK: vld3.32 {d1[1], d2[1], d3[1]}, [r3] @ encoding: [0x8f,0x1a,0xa3,0xf4] +@ CHECK: vld3.16 {d27[2], d29[2], d31[2]}, [r4] @ encoding: [0xaf,0xb6,0xe4,0xf4] +@ CHECK: vld3.32 {d6[0], d8[0], d10[0]}, [r5] @ encoding: [0x4f,0x6a,0xa5,0xf4] +@ CHECK: vld3.8 {d12[3], d13[3], d14[3]}, [r6], r1 @ encoding: [0x61,0xc2,0xa6,0xf4] +@ CHECK: vld3.16 {d11[2], d12[2], d13[2]}, [r7], r2 @ encoding: [0x82,0xb6,0xa7,0xf4] +@ CHECK: vld3.32 {d2[1], d3[1], d4[1]}, [r8], r3 @ encoding: [0x83,0x2a,0xa8,0xf4] +@ CHECK: vld3.16 {d14[2], d16[2], d18[2]}, [r9], r4 @ encoding: [0xa4,0xe6,0xa9,0xf4] +@ CHECK: vld3.32 {d16[0], d18[0], d20[0]}, [r10], r5 @ encoding: [0x45,0x0a,0xea,0xf4] +@ CHECK: vld3.8 {d6[6], d7[6], d8[6]}, [r8]! @ encoding: [0xcd,0x62,0xa8,0xf4] +@ CHECK: vld3.16 {d9[2], d10[2], d11[2]}, [r7]! @ encoding: [0x8d,0x96,0xa7,0xf4] +@ CHECK: vld3.32 {d1[1], d2[1], d3[1]}, [r6]! @ encoding: [0x8d,0x1a,0xa6,0xf4] +@ CHECK: vld3.16 {d20[2], d21[2], d22[2]}, [r5]! @ encoding: [0xad,0x46,0xe5,0xf4] +@ CHECK: vld3.32 {d5[0], d7[0], d9[0]}, [r4]! @ encoding: [0x4d,0x5a,0xa4,0xf4] + + + vld3.8 {d16[], d17[], d18[]}, [r1] + vld3.16 {d16[], d17[], d18[]}, [r2] + vld3.32 {d16[], d17[], d18[]}, [r3] + vld3.8 {d17[], d19[], d21[]}, [r7] + vld3.16 {d17[], d19[], d21[]}, [r7] + vld3.32 {d16[], d18[], d20[]}, [r8] + + vld3.s8 {d16[], d17[], d18[]}, [r1]! + vld3.s16 {d16[], d17[], d18[]}, [r2]! + vld3.s32 {d16[], d17[], d18[]}, [r3]! + vld3.u8 {d17[], d19[], d21[]}, [r7]! + vld3.u16 {d17[], d19[], d21[]}, [r7]! + vld3.u32 {d16[], d18[], d20[]}, [r8]! + + vld3.p8 {d16[], d17[], d18[]}, [r1], r8 + vld3.p16 {d16[], d17[], d18[]}, [r2], r7 + vld3.f32 {d16[], d17[], d18[]}, [r3], r5 + vld3.i8 {d16[], d18[], d20[]}, [r6], r3 + vld3.i16 {d16[], d18[], d20[]}, [r6], r3 + vld3.i32 {d17[], d19[], d21[]}, [r9], r4 + +@ CHECK: vld3.8 {d16[], d17[], d18[]}, [r1] @ encoding: [0x0f,0x0e,0xe1,0xf4] +@ CHECK: vld3.16 {d16[], d17[], d18[]}, [r2] @ encoding: [0x4f,0x0e,0xe2,0xf4] +@ CHECK: vld3.32 {d16[], d17[], d18[]}, [r3] @ encoding: [0x8f,0x0e,0xe3,0xf4] +@ CHECK: vld3.8 {d17[], d19[], d21[]}, [r7] @ encoding: [0x2f,0x1e,0xe7,0xf4] +@ CHECK: vld3.16 {d17[], d19[], d21[]}, [r7] @ encoding: [0x6f,0x1e,0xe7,0xf4] +@ CHECK: vld3.32 {d16[], d18[], d20[]}, [r8] @ encoding: [0xaf,0x0e,0xe8,0xf4] +@ CHECK: vld3.8 {d16[], d17[], d18[]}, [r1]! @ encoding: [0x0d,0x0e,0xe1,0xf4] +@ CHECK: vld3.16 {d16[], d17[], d18[]}, [r2]! @ encoding: [0x4d,0x0e,0xe2,0xf4] +@ CHECK: vld3.32 {d16[], d17[], d18[]}, [r3]! @ encoding: [0x8d,0x0e,0xe3,0xf4] +@ CHECK: vld3.8 {d17[], d18[], d19[]}, [r7]! @ encoding: [0x2d,0x1e,0xe7,0xf4] +@ CHECK: vld3.16 {d17[], d18[], d19[]}, [r7]! @ encoding: [0x6d,0x1e,0xe7,0xf4] +@ CHECK: vld3.32 {d16[], d18[], d20[]}, [r8]! @ encoding: [0xad,0x0e,0xe8,0xf4] +@ CHECK: vld3.8 {d16[], d17[], d18[]}, [r1], r8 @ encoding: [0x08,0x0e,0xe1,0xf4] +@ CHECK: vld3.16 {d16[], d17[], d18[]}, [r2], r7 @ encoding: [0x47,0x0e,0xe2,0xf4] +@ CHECK: vld3.32 {d16[], d17[], d18[]}, [r3], r5 @ encoding: [0x85,0x0e,0xe3,0xf4] +@ CHECK: vld3.8 {d16[], d18[], d20[]}, [r6], r3 @ encoding: [0x23,0x0e,0xe6,0xf4] +@ CHECK: vld3.16 {d16[], d18[], d20[]}, [r6], r3 @ encoding: [0x63,0x0e,0xe6,0xf4] +@ CHECK: vld3.32 {d17[], d19[], d21[]}, [r9], r4 @ encoding: [0xa4,0x1e,0xe9,0xf4] + + + vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1] + vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2] + vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3] + vld4.16 {d17[1], d19[1], d21[1], d23[1]}, [r7] + vld4.32 {d16[1], d18[1], d20[1], d22[1]}, [r8] + + vld4.s8 {d16[1], d17[1], d18[1], d19[1]}, [r1, :32]! + vld4.s16 {d16[1], d17[1], d18[1], d19[1]}, [r2, :64]! + vld4.s32 {d16[1], d17[1], d18[1], d19[1]}, [r3, :128]! + vld4.u16 {d17[1], d19[1], d21[1], d23[1]}, [r7]! + vld4.u32 {d16[1], d18[1], d20[1], d22[1]}, [r8]! + + vld4.p8 {d16[1], d17[1], d18[1], d19[1]}, [r1, :32], r8 + vld4.p16 {d16[1], d17[1], d18[1], d19[1]}, [r2], r7 + vld4.f32 {d16[1], d17[1], d18[1], d19[1]}, [r3, :64], r5 + vld4.i16 {d16[1], d18[1], d20[1], d22[1]}, [r6], r3 + vld4.i32 {d17[1], d19[1], d21[1], d23[1]}, [r9], r4 + +@ CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1] @ encoding: [0x2f,0x03,0xe1,0xf4] +@ CHECK: vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2] @ encoding: [0x4f,0x07,0xe2,0xf4] +@ CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3] @ encoding: [0x8f,0x0b,0xe3,0xf4] +@ CHECK: vld4.16 {d17[1], d19[1], d21[1], d23[1]}, [r7] @ encoding: [0x6f,0x17,0xe7,0xf4] +@ CHECK: vld4.32 {d16[1], d18[1], d20[1], d22[1]}, [r8] @ encoding: [0xcf,0x0b,0xe8,0xf4] +@ CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1, :32]! @ encoding: [0x3d,0x03,0xe1,0xf4] +@ CHECK: vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2, :64]! @ encoding: [0x5d,0x07,0xe2,0xf4] +@ CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3, :128]! @ encoding: [0xad,0x0b,0xe3,0xf4] +@ CHECK: vld4.16 {d17[1], d18[1], d19[1], d20[1]}, [r7]! @ encoding: [0x6d,0x17,0xe7,0xf4] +@ CHECK: vld4.32 {d16[1], d18[1], d20[1], d22[1]}, [r8]! @ encoding: [0xcd,0x0b,0xe8,0xf4] +@ CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1, :32], r8 @ encoding: [0x38,0x03,0xe1,0xf4] +@ CHECK: vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2], r7 @ encoding: [0x47,0x07,0xe2,0xf4] +@ CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3, :64], r5 @ encoding: [0x95,0x0b,0xe3,0xf4] +@ CHECK: vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r6], r3 @ encoding: [0x63,0x07,0xe6,0xf4] +@ CHECK: vld4.32 {d17[1], d19[1], d21[1], d23[1]}, [r9], r4 @ encoding: [0xc4,0x1b,0xe9,0xf4] + + + vld4.8 {d16[], d17[], d18[], d19[]}, [r1] + vld4.16 {d16[], d17[], d18[], d19[]}, [r2] + vld4.32 {d16[], d17[], d18[], d19[]}, [r3] + vld4.8 {d17[], d19[], d21[], d23[]}, [r7] + vld4.16 {d17[], d19[], d21[], d23[]}, [r7] + vld4.32 {d16[], d18[], d20[], d22[]}, [r8] + + vld4.s8 {d16[], d17[], d18[], d19[]}, [r1]! + vld4.s16 {d16[], d17[], d18[], d19[]}, [r2]! + vld4.s32 {d16[], d17[], d18[], d19[]}, [r3]! + vld4.u8 {d17[], d19[], d21[], d23[]}, [r7]! + vld4.u16 {d17[], d19[], d21[], d23[]}, [r7]! + vld4.u32 {d16[], d18[], d20[], d22[]}, [r8]! + + vld4.p8 {d16[], d17[], d18[], d19[]}, [r1], r8 + vld4.p16 {d16[], d17[], d18[], d19[]}, [r2], r7 + vld4.f32 {d16[], d17[], d18[], d19[]}, [r3], r5 + vld4.i8 {d16[], d18[], d20[], d22[]}, [r6], r3 + vld4.i16 {d16[], d18[], d20[], d22[]}, [r6], r3 + vld4.i32 {d17[], d19[], d21[], d23[]}, [r9], r4 + +@ CHECK: vld4.8 {d16[], d17[], d18[], d19[]}, [r1] @ encoding: [0x0f,0x0f,0xe1,0xf4] +@ CHECK: vld4.16 {d16[], d17[], d18[], d19[]}, [r2] @ encoding: [0x4f,0x0f,0xe2,0xf4] +@ CHECK: vld4.32 {d16[], d17[], d18[], d19[]}, [r3] @ encoding: [0x8f,0x0f,0xe3,0xf4] +@ CHECK: vld4.8 {d17[], d19[], d21[], d23[]}, [r7] @ encoding: [0x2f,0x1f,0xe7,0xf4] +@ CHECK: vld4.16 {d17[], d19[], d21[], d23[]}, [r7] @ encoding: [0x6f,0x1f,0xe7,0xf4] +@ CHECK: vld4.32 {d16[], d18[], d20[], d22[]}, [r8] @ encoding: [0xaf,0x0f,0xe8,0xf4] +@ CHECK: vld4.8 {d16[], d17[], d18[], d19[]}, [r1]! @ encoding: [0x0d,0x0f,0xe1,0xf4] +@ CHECK: vld4.16 {d16[], d17[], d18[], d19[]}, [r2]! @ encoding: [0x4d,0x0f,0xe2,0xf4] +@ CHECK: vld4.32 {d16[], d17[], d18[], d19[]}, [r3]! @ encoding: [0x8d,0x0f,0xe3,0xf4] +@ CHECK: vld4.8 {d17[], d18[], d19[], d20[]}, [r7]! @ encoding: [0x2d,0x1f,0xe7,0xf4] +@ CHECK: vld4.16 {d17[], d18[], d19[], d20[]}, [r7]! @ encoding: [0x6d,0x1f,0xe7,0xf4] +@ CHECK: vld4.32 {d16[], d18[], d20[], d22[]}, [r8]! @ encoding: [0xad,0x0f,0xe8,0xf4] +@ CHECK: vld4.8 {d16[], d17[], d18[], d19[]}, [r1], r8 @ encoding: [0x08,0x0f,0xe1,0xf4] +@ CHECK: vld4.16 {d16[], d17[], d18[], d19[]}, [r2], r7 @ encoding: [0x47,0x0f,0xe2,0xf4] +@ CHECK: vld4.32 {d16[], d17[], d18[], d19[]}, [r3], r5 @ encoding: [0x85,0x0f,0xe3,0xf4] +@ CHECK: vld4.8 {d16[], d18[], d20[], d22[]}, [r6], r3 @ encoding: [0x23,0x0f,0xe6,0xf4] +@ CHECK: vld4.16 {d16[], d18[], d20[], d22[]}, [r6], r3 @ encoding: [0x63,0x0f,0xe6,0xf4] +@ CHECK: vld4.32 {d17[], d19[], d21[], d23[]}, [r9], r4 @ encoding: [0xa4,0x1f,0xe9,0xf4] + +@ Handle 'Q' registers in register lists as if the sub-reg D regs were +@ specified instead. + vld1.8 {q3}, [r9] + vld1.8 {q3, q4}, [r9] + +@ CHECK: vld1.8 {d6, d7}, [r9] @ encoding: [0x0f,0x6a,0x29,0xf4] +@ CHECK: vld1.8 {d6, d7, d8, d9}, [r9] @ encoding: [0x0f,0x62,0x29,0xf4] + + +@ Spot-check additional size-suffix aliases. + vld1.8 {d2}, [r2] + vld1.p8 {d2}, [r2] + vld1.u8 {d2}, [r2] + + vld1.8 {q2}, [r2] + vld1.p8 {q2}, [r2] + vld1.u8 {q2}, [r2] + vld1.f32 {q2}, [r2] + + vld1.u8 {d2, d3, d4}, [r2] + vld1.i32 {d2, d3, d4}, [r2] + vld1.f64 {d2, d3, d4}, [r2] +@ CHECK: vld1.8 {d2}, [r2] @ encoding: [0x0f,0x27,0x22,0xf4] +@ CHECK: vld1.8 {d2}, [r2] @ encoding: [0x0f,0x27,0x22,0xf4] +@ CHECK: vld1.8 {d2}, [r2] @ encoding: [0x0f,0x27,0x22,0xf4] - vld3.8 {d16[1], d17[1], d18[1]}, [r0] - vld3.16 {d16[1], d17[1], d18[1]}, [r0] - vld3.32 {d16[1], d17[1], d18[1]}, [r0] - vld3.16 {d16[1], d18[1], d20[1]}, [r0] - vld3.32 {d17[1], d19[1], d21[1]}, [r0] +@ CHECK: vld1.8 {d4, d5}, [r2] @ encoding: [0x0f,0x4a,0x22,0xf4] +@ CHECK: vld1.8 {d4, d5}, [r2] @ encoding: [0x0f,0x4a,0x22,0xf4] +@ CHECK: vld1.8 {d4, d5}, [r2] @ encoding: [0x0f,0x4a,0x22,0xf4] +@ CHECK: vld1.32 {d4, d5}, [r2] @ encoding: [0x8f,0x4a,0x22,0xf4] -@ CHECK: vld3.8 {d16[1], d17[1], d18[1]}, [r0] @ encoding: [0x2f,0x02,0xe0,0xf4] -@ CHECK: vld3.16 {d16[1], d17[1], d18[1]}, [r0]@ encoding: [0x4f,0x06,0xe0,0xf4] -@ CHECK: vld3.32 {d16[1], d17[1], d18[1]}, [r0]@ encoding: [0x8f,0x0a,0xe0,0xf4] -@ CHECK: vld3.16 {d16[1], d18[1], d20[1]}, [r0]@ encoding: [0x6f,0x06,0xe0,0xf4] -@ CHECK: vld3.32 {d17[1], d19[1], d21[1]}, [r0]@ encoding: [0xcf,0x1a,0xe0,0xf4] +@ CHECK: vld1.8 {d2, d3, d4}, [r2] @ encoding: [0x0f,0x26,0x22,0xf4] +@ CHECK: vld1.32 {d2, d3, d4}, [r2] @ encoding: [0x8f,0x26,0x22,0xf4] +@ CHECK: vld1.64 {d2, d3, d4}, [r2] @ encoding: [0xcf,0x26,0x22,0xf4] - vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] - vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] - vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128] - vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r0, :64] - vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] +@ Register lists can use the range syntax, just like VLDM + vld1.f64 {d2-d5}, [r2,:128]! + vld1.f64 {d2,d3,d4,d5}, [r2,:128]! -@ CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] @ encoding: [0x3f,0x03,0xe0,0xf4] -@ CHECK: vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] @ encoding: [0x4f,0x07,0xe0,0xf4] -@ CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128] @ encoding: [0xaf,0x0b,0xe0,0xf4] -@ CHECK: vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r0, :64] @ encoding: [0x7f,0x07,0xe0,0xf4] -@ CHECK: vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] @ encoding: [0x4f,0x1b,0xe0,0xf4] +@ CHECK: vld1.64 {d2, d3, d4, d5}, [r2, :128]! @ encoding: [0xed,0x22,0x22,0xf4] +@ CHECK: vld1.64 {d2, d3, d4, d5}, [r2, :128]! @ encoding: [0xed,0x22,0x22,0xf4] diff --git a/test/MC/ARM/neon-vst-encoding.s b/test/MC/ARM/neon-vst-encoding.s index c595aa2..f5feca4 100644 --- a/test/MC/ARM/neon-vst-encoding.s +++ b/test/MC/ARM/neon-vst-encoding.s @@ -1,101 +1,278 @@ @ RUN: llvm-mc -mcpu=cortex-a8 -triple armv7-apple-darwin -show-encoding < %s | FileCheck %s -@ XFAIL: * + + vst1.8 {d16}, [r0, :64] + vst1.16 {d16}, [r0] + vst1.32 {d16}, [r0] + vst1.64 {d16}, [r0] + vst1.8 {d16, d17}, [r0, :64] + vst1.16 {d16, d17}, [r0, :128] + vst1.32 {d16, d17}, [r0] + vst1.64 {d16, d17}, [r0] + vst1.8 {d16, d17, d18}, [r0, :64] + vst1.8 {d16, d17, d18}, [r0, :64]! + vst1.8 {d16, d17, d18}, [r0], r3 + vst1.8 {d16, d17, d18, d19}, [r0, :64] + vst1.16 {d16, d17, d18, d19}, [r1, :64]! + vst1.64 {d16, d17, d18, d19}, [r3], r2 @ CHECK: vst1.8 {d16}, [r0, :64] @ encoding: [0x1f,0x07,0x40,0xf4] - vst1.8 {d16}, [r0, :64] -@ CHECK: vst1.16 {d16}, [r0] @ encoding: [0x4f,0x07,0x40,0xf4] - vst1.16 {d16}, [r0] -@ CHECK: vst1.32 {d16}, [r0] @ encoding: [0x8f,0x07,0x40,0xf4] - vst1.32 {d16}, [r0] -@ CHECK: vst1.64 {d16}, [r0] @ encoding: [0xcf,0x07,0x40,0xf4] - vst1.64 {d16}, [r0] +@ CHECK: vst1.16 {d16}, [r0] @ encoding: [0x4f,0x07,0x40,0xf4] +@ CHECK: vst1.32 {d16}, [r0] @ encoding: [0x8f,0x07,0x40,0xf4] +@ CHECK: vst1.64 {d16}, [r0] @ encoding: [0xcf,0x07,0x40,0xf4] @ CHECK: vst1.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x0a,0x40,0xf4] - vst1.8 {d16, d17}, [r0, :64] -@ CHECK: vst1.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x0a,0x40,0xf4] - vst1.16 {d16, d17}, [r0, :128] -@ CHECK: vst1.32 {d16, d17}, [r0] @ encoding: [0x8f,0x0a,0x40,0xf4] - vst1.32 {d16, d17}, [r0] -@ CHECK: vst1.64 {d16, d17}, [r0] @ encoding: [0xcf,0x0a,0x40,0xf4] - vst1.64 {d16, d17}, [r0] +@ CHECK: vst1.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x0a,0x40,0xf4] +@ CHECK: vst1.32 {d16, d17}, [r0] @ encoding: [0x8f,0x0a,0x40,0xf4] +@ CHECK: vst1.64 {d16, d17}, [r0] @ encoding: [0xcf,0x0a,0x40,0xf4] +@ CHECK: vst1.8 {d16, d17, d18}, [r0, :64] @ encoding: [0x1f,0x06,0x40,0xf4] +@ CHECK: vst1.8 {d16, d17, d18}, [r0, :64]! @ encoding: [0x1d,0x06,0x40,0xf4] +@ CHECK: vst1.8 {d16, d17, d18}, [r0], r3 @ encoding: [0x03,0x06,0x40,0xf4] +@ CHECK: vst1.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x02,0x40,0xf4] +@ CHECK: vst1.16 {d16, d17, d18, d19}, [r1, :64]! @ encoding: [0x5d,0x02,0x41,0xf4] +@ CHECK: vst1.64 {d16, d17, d18, d19}, [r3], r2 @ encoding: [0xc2,0x02,0x43,0xf4] + + + vst2.8 {d16, d17}, [r0, :64] + vst2.16 {d16, d17}, [r0, :128] + vst2.32 {d16, d17}, [r0] + vst2.8 {d16, d17, d18, d19}, [r0, :64] + vst2.16 {d16, d17, d18, d19}, [r0, :128] + vst2.32 {d16, d17, d18, d19}, [r0, :256] + vst2.8 {d16, d17}, [r0, :64]! + vst2.16 {q15}, [r0, :128]! + vst2.32 {d14, d15}, [r0]! + vst2.8 {d16, d17, d18, d19}, [r0, :64]! + vst2.16 {d18-d21}, [r0, :128]! + vst2.32 {q4, q5}, [r0, :256]! @ CHECK: vst2.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x08,0x40,0xf4] - vst2.8 {d16, d17}, [r0, :64] -@ CHECK: vst2.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x08,0x40,0xf4] - vst2.16 {d16, d17}, [r0, :128] -@ CHECK: vst2.32 {d16, d17}, [r0] @ encoding: [0x8f,0x08,0x40,0xf4] - vst2.32 {d16, d17}, [r0] +@ CHECK: vst2.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x08,0x40,0xf4] +@ CHECK: vst2.32 {d16, d17}, [r0] @ encoding: [0x8f,0x08,0x40,0xf4] @ CHECK: vst2.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x03,0x40,0xf4] - vst2.8 {d16, d17, d18, d19}, [r0, :64] -@ CHECK: vst2.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x03,0x40,0xf4] - vst2.16 {d16, d17, d18, d19}, [r0, :128] -@ CHECK: vst2.32 {d16, d17, d18, d19}, [r0, :256] @ encoding: [0xbf,0x03,0x40,0xf4] - vst2.32 {d16, d17, d18, d19}, [r0, :256] - -@ CHECK: vst3.8 {d16, d17, d18}, [r0, :64] @ encoding: [0x1f,0x04,0x40,0xf4] - vst3.8 {d16, d17, d18}, [r0, :64] -@ CHECK: vst3.16 {d16, d17, d18}, [r0] @ encoding: [0x4f,0x04,0x40,0xf4] - vst3.16 {d16, d17, d18}, [r0] -@ CHECK: vst3.32 {d16, d17, d18}, [r0] @ encoding: [0x8f,0x04,0x40,0xf4] - vst3.32 {d16, d17, d18}, [r0] +@ CHECK: vst2.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x03,0x40,0xf4] +@ CHECK: vst2.32 {d16, d17, d18, d19}, [r0, :256] @ encoding: [0xbf,0x03,0x40,0xf4] +@ CHECK: vst2.8 {d16, d17}, [r0, :64]! @ encoding: [0x1d,0x08,0x40,0xf4] +@ CHECK: vst2.16 {d30, d31}, [r0, :128]! @ encoding: [0x6d,0xe8,0x40,0xf4] +@ CHECK: vst2.32 {d14, d15}, [r0]! @ encoding: [0x8d,0xe8,0x00,0xf4] +@ CHECK: vst2.8 {d16, d17, d18, d19}, [r0, :64]! @ encoding: [0x1d,0x03,0x40,0xf4] +@ CHECK: vst2.16 {d18, d19, d20, d21}, [r0, :128]! @ encoding: [0x6d,0x23,0x40,0xf4] +@ CHECK: vst2.32 {d8, d9, d10, d11}, [r0, :256]! @ encoding: [0xbd,0x83,0x00,0xf4] + + + vst3.8 {d16, d17, d18}, [r1] + vst3.16 {d6, d7, d8}, [r2] + vst3.32 {d1, d2, d3}, [r3] + vst3.8 {d16, d18, d20}, [r0, :64] + vst3.u16 {d27, d29, d31}, [r4] + vst3.i32 {d6, d8, d10}, [r5] + + vst3.i8 {d12, d13, d14}, [r6], r1 + vst3.i16 {d11, d12, d13}, [r7], r2 + vst3.u32 {d2, d3, d4}, [r8], r3 + vst3.8 {d4, d6, d8}, [r9], r4 + vst3.u16 {d14, d16, d18}, [r9], r4 + vst3.i32 {d16, d18, d20}, [r10], r5 + + vst3.p8 {d6, d7, d8}, [r8]! + vst3.16 {d9, d10, d11}, [r7]! + vst3.f32 {d1, d2, d3}, [r6]! + vst3.8 {d16, d18, d20}, [r0, :64]! + vst3.p16 {d20, d22, d24}, [r5]! + vst3.32 {d5, d7, d9}, [r4]! + +@ CHECK: vst3.8 {d16, d17, d18}, [r1] @ encoding: [0x0f,0x04,0x41,0xf4] +@ CHECK: vst3.16 {d6, d7, d8}, [r2] @ encoding: [0x4f,0x64,0x02,0xf4] +@ CHECK: vst3.32 {d1, d2, d3}, [r3] @ encoding: [0x8f,0x14,0x03,0xf4] +@ CHECK: vst3.8 {d16, d18, d20}, [r0, :64] @ encoding: [0x1f,0x05,0x40,0xf4] +@ CHECK: vst3.16 {d27, d29, d31}, [r4] @ encoding: [0x4f,0xb5,0x44,0xf4] +@ CHECK: vst3.32 {d6, d8, d10}, [r5] @ encoding: [0x8f,0x65,0x05,0xf4] +@ CHECK: vst3.8 {d12, d13, d14}, [r6], r1 @ encoding: [0x01,0xc4,0x06,0xf4] +@ CHECK: vst3.16 {d11, d12, d13}, [r7], r2 @ encoding: [0x42,0xb4,0x07,0xf4] +@ CHECK: vst3.32 {d2, d3, d4}, [r8], r3 @ encoding: [0x83,0x24,0x08,0xf4] +@ CHECK: vst3.8 {d4, d6, d8}, [r9], r4 @ encoding: [0x04,0x45,0x09,0xf4] +@ CHECK: vst3.16 {d14, d16, d18}, [r9], r4 @ encoding: [0x44,0xe5,0x09,0xf4] +@ CHECK: vst3.32 {d16, d18, d20}, [r10], r5 @ encoding: [0x85,0x05,0x4a,0xf4] +@ CHECK: vst3.8 {d6, d7, d8}, [r8]! @ encoding: [0x0d,0x64,0x08,0xf4] +@ CHECK: vst3.16 {d9, d10, d11}, [r7]! @ encoding: [0x4d,0x94,0x07,0xf4] +@ CHECK: vst3.32 {d1, d2, d3}, [r6]! @ encoding: [0x8d,0x14,0x06,0xf4] @ CHECK: vst3.8 {d16, d18, d20}, [r0, :64]! @ encoding: [0x1d,0x05,0x40,0xf4] - vst3.8 {d16, d18, d20}, [r0, :64]! -@ CHECK: vst3.8 {d17, d19, d21}, [r0, :64]! @ encoding: [0x1d,0x15,0x40,0xf4] - vst3.8 {d17, d19, d21}, [r0, :64]! -@ CHECK: vst3.16 {d16, d18, d20}, [r0]! @ encoding: [0x4d,0x05,0x40,0xf4] - vst3.16 {d16, d18, d20}, [r0]! -@ CHECK: vst3.16 {d17, d19, d21}, [r0]! @ encoding: [0x4d,0x15,0x40,0xf4] - vst3.16 {d17, d19, d21}, [r0]! -@ CHECK: vst3.32 {d16, d18, d20}, [r0]! @ encoding: [0x8d,0x05,0x40,0xf4] - vst3.32 {d16, d18, d20}, [r0]! -@ CHECK: vst3.32 {d17, d19, d21}, [r0]! @ encoding: [0x8d,0x15,0x40,0xf4] - vst3.32 {d17, d19, d21}, [r0]! - -@ CHECK: vst4.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x00,0x40,0xf4] - vst4.8 {d16, d17, d18, d19}, [r0, :64] -@ CHECK: vst4.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x00,0x40,0xf4] - vst4.16 {d16, d17, d18, d19}, [r0, :128] -@ CHECK: vst4.8 {d16, d18, d20, d22}, [r0, :256]! @ encoding: [0x3d,0x01,0x40,0xf4] - vst4.8 {d16, d18, d20, d22}, [r0, :256]! -@ CHECK: vst4.8 {d17, d19, d21, d23}, [r0, :256]! @ encoding: [0x3d,0x11,0x40,0xf4] - vst4.8 {d17, d19, d21, d23}, [r0, :256]! -@ CHECK: vst4.16 {d16, d18, d20, d22}, [r0]! @ encoding: [0x4d,0x01,0x40,0xf4] - vst4.16 {d16, d18, d20, d22}, [r0]! -@ CHECK: vst4.16 {d17, d19, d21, d23}, [r0]! @ encoding: [0x4d,0x11,0x40,0xf4] - vst4.16 {d17, d19, d21, d23}, [r0]! -@ CHECK: vst4.32 {d16, d18, d20, d22}, [r0]! @ encoding: [0x8d,0x01,0x40,0xf4] - vst4.32 {d16, d18, d20, d22}, [r0]! -@ CHECK: vst4.32 {d17, d19, d21, d23}, [r0]! @ encoding: [0x8d,0x11,0x40,0xf4] - vst4.32 {d17, d19, d21, d23}, [r0]! +@ CHECK: vst3.16 {d20, d22, d24}, [r5]! @ encoding: [0x4d,0x45,0x45,0xf4] +@ CHECK: vst3.32 {d5, d7, d9}, [r4]! @ encoding: [0x8d,0x55,0x04,0xf4] + + + vst4.8 {d16, d17, d18, d19}, [r1, :64] + vst4.16 {d16, d17, d18, d19}, [r2, :128] + vst4.32 {d16, d17, d18, d19}, [r3, :256] + vst4.8 {d17, d19, d21, d23}, [r5, :256] + vst4.16 {d17, d19, d21, d23}, [r7] + vst4.32 {d16, d18, d20, d22}, [r8] + + vst4.s8 {d16, d17, d18, d19}, [r1, :64]! + vst4.s16 {d16, d17, d18, d19}, [r2, :128]! + vst4.s32 {d16, d17, d18, d19}, [r3, :256]! + vst4.u8 {d17, d19, d21, d23}, [r5, :256]! + vst4.u16 {d17, d19, d21, d23}, [r7]! + vst4.u32 {d16, d18, d20, d22}, [r8]! + + vst4.p8 {d16, d17, d18, d19}, [r1, :64], r8 + vst4.p16 {d16, d17, d18, d19}, [r2], r7 + vst4.f32 {d16, d17, d18, d19}, [r3, :64], r5 + vst4.i8 {d16, d18, d20, d22}, [r4, :256], r2 + vst4.i16 {d16, d18, d20, d22}, [r6], r3 + vst4.i32 {d17, d19, d21, d23}, [r9], r4 + +@ CHECK: vst4.8 {d16, d17, d18, d19}, [r1, :64] @ encoding: [0x1f,0x00,0x41,0xf4] +@ CHECK: vst4.16 {d16, d17, d18, d19}, [r2, :128] @ encoding: [0x6f,0x00,0x42,0xf4] +@ CHECK: vst4.32 {d16, d17, d18, d19}, [r3, :256] @ encoding: [0xbf,0x00,0x43,0xf4] +@ CHECK: vst4.8 {d17, d19, d21, d23}, [r5, :256] @ encoding: [0x3f,0x11,0x45,0xf4] +@ CHECK: vst4.16 {d17, d19, d21, d23}, [r7] @ encoding: [0x4f,0x11,0x47,0xf4] +@ CHECK: vst4.32 {d16, d18, d20, d22}, [r8] @ encoding: [0x8f,0x01,0x48,0xf4] +@ CHECK: vst4.8 {d16, d17, d18, d19}, [r1, :64]! @ encoding: [0x1d,0x00,0x41,0xf4] +@ CHECK: vst4.16 {d16, d17, d18, d19}, [r2, :128]! @ encoding: [0x6d,0x00,0x42,0xf4] +@ CHECK: vst4.32 {d16, d17, d18, d19}, [r3, :256]! @ encoding: [0xbd,0x00,0x43,0xf4] +@ CHECK: vst4.8 {d17, d19, d21, d23}, [r5, :256]! @ encoding: [0x3d,0x11,0x45,0xf4] +@ CHECK: vst4.16 {d17, d19, d21, d23}, [r7]! @ encoding: [0x4d,0x11,0x47,0xf4] +@ CHECK: vst4.32 {d16, d18, d20, d22}, [r8]! @ encoding: [0x8d,0x01,0x48,0xf4] +@ CHECK: vst4.8 {d16, d17, d18, d19}, [r1, :64], r8 @ encoding: [0x18,0x00,0x41,0xf4] +@ CHECK: vst4.16 {d16, d17, d18, d19}, [r2], r7 @ encoding: [0x47,0x00,0x42,0xf4] +@ CHECK: vst4.32 {d16, d17, d18, d19}, [r3, :64], r5 @ encoding: [0x95,0x00,0x43,0xf4] +@ CHECK: vst4.8 {d16, d18, d20, d22}, [r4, :256], r2 @ encoding: [0x32,0x01,0x44,0xf4] +@ CHECK: vst4.16 {d16, d18, d20, d22}, [r6], r3 @ encoding: [0x43,0x01,0x46,0xf4] +@ CHECK: vst4.32 {d17, d19, d21, d23}, [r9], r4 @ encoding: [0x84,0x11,0x49,0xf4] + + + vst2.8 {d16[1], d17[1]}, [r0, :16] + vst2.p16 {d16[1], d17[1]}, [r0, :32] + vst2.i32 {d16[1], d17[1]}, [r0] + vst2.u16 {d17[1], d19[1]}, [r0] + vst2.f32 {d17[0], d19[0]}, [r0, :64] + + vst2.8 {d2[4], d3[4]}, [r2], r3 + vst2.u8 {d2[4], d3[4]}, [r2]! + vst2.p8 {d2[4], d3[4]}, [r2] + + vst2.16 {d17[1], d19[1]}, [r0] + vst2.32 {d17[0], d19[0]}, [r0, :64] + vst2.i16 {d7[1], d9[1]}, [r1]! + vst2.32 {d6[0], d8[0]}, [r2, :64]! + vst2.16 {d2[1], d4[1]}, [r3], r5 + vst2.u32 {d5[0], d7[0]}, [r4, :64], r7 @ CHECK: vst2.8 {d16[1], d17[1]}, [r0, :16] @ encoding: [0x3f,0x01,0xc0,0xf4] - vst2.8 {d16[1], d17[1]}, [r0, :16] -@ CHECK: vst2.16 {d16[1], d17[1]}, [r0, :32] @ encoding: [0x5f,0x05,0xc0,0xf4] - vst2.16 {d16[1], d17[1]}, [r0, :32] -@ CHECK: vst2.32 {d16[1], d17[1]}, [r0] @ encoding: [0x8f,0x09,0xc0,0xf4] - vst2.32 {d16[1], d17[1]}, [r0] -@ CHECK: vst2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xc0,0xf4] - vst2.16 {d17[1], d19[1]}, [r0] -@ CHECK: vst2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xc0,0xf4] - vst2.32 {d17[0], d19[0]}, [r0, :64] - -@ CHECK: vst3.8 {d16[1], d17[1], d18[1]}, [r0] @ encoding: [0x2f,0x02,0xc0,0xf4] - vst3.8 {d16[1], d17[1], d18[1]}, [r0] -@ CHECK: vst3.16 {d16[1], d17[1], d18[1]}, [r0] @ encoding: [0x4f,0x06,0xc0,0xf4] - vst3.16 {d16[1], d17[1], d18[1]}, [r0] -@ CHECK: vst3.32 {d16[1], d17[1], d18[1]}, [r0] @ encoding: [0x8f,0x0a,0xc0,0xf4] - vst3.32 {d16[1], d17[1], d18[1]}, [r0] -@ CHECK: vst3.16 {d17[2], d19[2], d21[2]}, [r0] @ encoding: [0xaf,0x16,0xc0,0xf4] - vst3.16 {d17[2], d19[2], d21[2]}, [r0] -@ CHECK: vst3.32 {d16[0], d18[0], d20[0]}, [r0] @ encoding: [0x4f,0x0a,0xc0,0xf4] - vst3.32 {d16[0], d18[0], d20[0]}, [r0] - -@ CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] @ encoding: [0x3f,0x03,0xc0,0xf4] - vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] -@ CHECK: vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] @ encoding: [0x4f,0x07,0xc0,0xf4] - vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] -@ CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128] @ encoding: [0xaf,0x0b,0xc0,0xf4] - vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128] -@ CHECK: vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0, :64] @ encoding: [0xff,0x17,0xc0,0xf4] - vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0, :64] -@ CHECK: vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] @ encoding: [0x4f,0x1b,0xc0,0xf4] - vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] +@ CHECK: vst2.16 {d16[1], d17[1]}, [r0, :32] @ encoding: [0x5f,0x05,0xc0,0xf4] +@ CHECK: vst2.32 {d16[1], d17[1]}, [r0] @ encoding: [0x8f,0x09,0xc0,0xf4] +@ CHECK: vst2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xc0,0xf4] +@ CHECK: vst2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xc0,0xf4] + +@ CHECK: vst2.8 {d2[4], d3[4]}, [r2], r3 @ encoding: [0x83,0x21,0x82,0xf4] +@ CHECK: vst2.8 {d2[4], d3[4]}, [r2]! @ encoding: [0x8d,0x21,0x82,0xf4] +@ CHECK: vst2.8 {d2[4], d3[4]}, [r2] @ encoding: [0x8f,0x21,0x82,0xf4] + +@ CHECK: vst2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xc0,0xf4] +@ CHECK: vst2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xc0,0xf4] +@ CHECK: vst2.16 {d7[1], d9[1]}, [r1]! @ encoding: [0x6d,0x75,0x81,0xf4] +@ CHECK: vst2.32 {d6[0], d8[0]}, [r2, :64]! @ encoding: [0x5d,0x69,0x82,0xf4] +@ CHECK: vst2.16 {d2[1], d4[1]}, [r3], r5 @ encoding: [0x65,0x25,0x83,0xf4] +@ CHECK: vst2.32 {d5[0], d7[0]}, [r4, :64], r7 @ encoding: [0x57,0x59,0x84,0xf4] + + + vst3.8 {d16[1], d17[1], d18[1]}, [r1] + vst3.16 {d6[1], d7[1], d8[1]}, [r2] + vst3.32 {d1[1], d2[1], d3[1]}, [r3] + vst3.u16 {d27[1], d29[1], d31[1]}, [r4] + vst3.i32 {d6[1], d8[1], d10[1]}, [r5] + + vst3.i8 {d12[1], d13[1], d14[1]}, [r6], r1 + vst3.i16 {d11[1], d12[1], d13[1]}, [r7], r2 + vst3.u32 {d2[1], d3[1], d4[1]}, [r8], r3 + vst3.u16 {d14[1], d16[1], d18[1]}, [r9], r4 + vst3.i32 {d16[1], d18[1], d20[1]}, [r10], r5 + + vst3.p8 {d6[1], d7[1], d8[1]}, [r8]! + vst3.16 {d9[1], d10[1], d11[1]}, [r7]! + vst3.f32 {d1[1], d2[1], d3[1]}, [r6]! + vst3.p16 {d20[1], d22[1], d24[1]}, [r5]! + vst3.32 {d5[1], d7[1], d9[1]}, [r4]! + +@ CHECK: vst3.8 {d16[1], d17[1], d18[1]}, [r1] @ encoding: [0x2f,0x02,0xc1,0xf4] +@ CHECK: vst3.16 {d6[1], d7[1], d8[1]}, [r2] @ encoding: [0x4f,0x66,0x82,0xf4] +@ CHECK: vst3.32 {d1[1], d2[1], d3[1]}, [r3] @ encoding: [0x8f,0x1a,0x83,0xf4] +@ CHECK: vst3.16 {d27[1], d29[1], d31[1]}, [r4] @ encoding: [0x6f,0xb6,0xc4,0xf4] +@ CHECK: vst3.32 {d6[1], d8[1], d10[1]}, [r5] @ encoding: [0xcf,0x6a,0x85,0xf4] +@ CHECK: vst3.8 {d12[1], d13[1], d14[1]}, [r6], r1 @ encoding: [0x21,0xc2,0x86,0xf4] +@ CHECK: vst3.16 {d11[1], d12[1], d13[1]}, [r7], r2 @ encoding: [0x42,0xb6,0x87,0xf4] +@ CHECK: vst3.32 {d2[1], d3[1], d4[1]}, [r8], r3 @ encoding: [0x83,0x2a,0x88,0xf4] +@ CHECK: vst3.16 {d14[1], d16[1], d18[1]}, [r9], r4 @ encoding: [0x64,0xe6,0x89,0xf4] +@ CHECK: vst3.32 {d16[1], d18[1], d20[1]}, [r10], r5 @ encoding: [0xc5,0x0a,0xca,0xf4] +@ CHECK: vst3.8 {d6[1], d7[1], d8[1]}, [r8]! @ encoding: [0x2d,0x62,0x88,0xf4] +@ CHECK: vst3.16 {d9[1], d10[1], d11[1]}, [r7]! @ encoding: [0x4d,0x96,0x87,0xf4] +@ CHECK: vst3.32 {d1[1], d2[1], d3[1]}, [r6]! @ encoding: [0x8d,0x1a,0x86,0xf4] +@ CHECK: vst3.16 {d20[1], d21[1], d22[1]}, [r5]! @ encoding: [0x6d,0x46,0xc5,0xf4] +@ CHECK: vst3.32 {d5[1], d7[1], d9[1]}, [r4]! @ encoding: [0xcd,0x5a,0x84,0xf4] + + + vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1] + vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2] + vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3] + vst4.16 {d17[1], d19[1], d21[1], d23[1]}, [r7] + vst4.32 {d16[1], d18[1], d20[1], d22[1]}, [r8] + + vst4.s8 {d16[1], d17[1], d18[1], d19[1]}, [r1, :32]! + vst4.s16 {d16[1], d17[1], d18[1], d19[1]}, [r2, :64]! + vst4.s32 {d16[1], d17[1], d18[1], d19[1]}, [r3, :128]! + vst4.u16 {d17[1], d19[1], d21[1], d23[1]}, [r7]! + vst4.u32 {d16[1], d18[1], d20[1], d22[1]}, [r8]! + + vst4.p8 {d16[1], d17[1], d18[1], d19[1]}, [r1, :32], r8 + vst4.p16 {d16[1], d17[1], d18[1], d19[1]}, [r2], r7 + vst4.f32 {d16[1], d17[1], d18[1], d19[1]}, [r3, :64], r5 + vst4.i16 {d16[1], d18[1], d20[1], d22[1]}, [r6], r3 + vst4.i32 {d17[1], d19[1], d21[1], d23[1]}, [r9], r4 + +@ CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1] @ encoding: [0x2f,0x03,0xc1,0xf4] +@ CHECK: vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2] @ encoding: [0x4f,0x07,0xc2,0xf4] +@ CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3] @ encoding: [0x8f,0x0b,0xc3,0xf4] +@ CHECK: vst4.16 {d17[1], d19[1], d21[1], d23[1]}, [r7] @ encoding: [0x6f,0x17,0xc7,0xf4] +@ CHECK: vst4.32 {d16[1], d18[1], d20[1], d22[1]}, [r8] @ encoding: [0xcf,0x0b,0xc8,0xf4] +@ CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1, :32]! @ encoding: [0x3d,0x03,0xc1,0xf4] +@ CHECK: vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2, :64]! @ encoding: [0x5d,0x07,0xc2,0xf4] +@ CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3, :128]! @ encoding: [0xad,0x0b,0xc3,0xf4] +@ CHECK: vst4.16 {d17[1], d18[1], d19[1], d20[1]}, [r7]! @ encoding: [0x6d,0x17,0xc7,0xf4] +@ CHECK: vst4.32 {d16[1], d18[1], d20[1], d22[1]}, [r8]! @ encoding: [0xcd,0x0b,0xc8,0xf4] +@ CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1, :32], r8 @ encoding: [0x38,0x03,0xc1,0xf4] +@ CHECK: vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2], r7 @ encoding: [0x47,0x07,0xc2,0xf4] +@ CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3, :64], r5 @ encoding: [0x95,0x0b,0xc3,0xf4] +@ CHECK: vst4.16 {d16[1], d18[1], d20[1], d22[1]}, [r6], r3 @ encoding: [0x63,0x07,0xc6,0xf4] +@ CHECK: vst4.32 {d17[1], d19[1], d21[1], d23[1]}, [r9], r4 @ encoding: [0xc4,0x1b,0xc9,0xf4] + + +@ Spot-check additional size-suffix aliases. + + vst1.8 {d2}, [r2] + vst1.p8 {d2}, [r2] + vst1.u8 {d2}, [r2] + + vst1.8 {q2}, [r2] + vst1.p8 {q2}, [r2] + vst1.u8 {q2}, [r2] + vst1.f32 {q2}, [r2] + +@ CHECK: vst1.8 {d2}, [r2] @ encoding: [0x0f,0x27,0x02,0xf4] +@ CHECK: vst1.8 {d2}, [r2] @ encoding: [0x0f,0x27,0x02,0xf4] +@ CHECK: vst1.8 {d2}, [r2] @ encoding: [0x0f,0x27,0x02,0xf4] + +@ CHECK: vst1.8 {d4, d5}, [r2] @ encoding: [0x0f,0x4a,0x02,0xf4] +@ CHECK: vst1.8 {d4, d5}, [r2] @ encoding: [0x0f,0x4a,0x02,0xf4] +@ CHECK: vst1.8 {d4, d5}, [r2] @ encoding: [0x0f,0x4a,0x02,0xf4] +@ CHECK: vst1.32 {d4, d5}, [r2] @ encoding: [0x8f,0x4a,0x02,0xf4] + +@ rdar://11082188 + vst2.8 {d8, d10}, [r4] +@ CHECK: vst2.8 {d8, d10}, [r4] @ encoding: [0x0f,0x89,0x04,0xf4] + + vst1.32 {d9[1]}, [r3, :32] + vst1.32 {d27[1]}, [r9, :32]! + vst1.32 {d27[1]}, [r3, :32], r5 +@ CHECK: vst1.32 {d9[1]}, [r3, :32] @ encoding: [0xbf,0x98,0x83,0xf4] +@ CHECK: vst1.32 {d27[1]}, [r9, :32]! @ encoding: [0xbd,0xb8,0xc9,0xf4] +@ CHECK: vst1.32 {d27[1]}, [r3, :32], r5 @ encoding: [0xb5,0xb8,0xc3,0xf4] + diff --git a/test/MC/ARM/neon-vswp.s b/test/MC/ARM/neon-vswp.s new file mode 100644 index 0000000..2138eed --- /dev/null +++ b/test/MC/ARM/neon-vswp.s @@ -0,0 +1,7 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple armv7-apple-darwin -show-encoding < %s | FileCheck %s + +vswp d1, d2 +vswp q1, q2 + +@ CHECK: vswp d1, d2 @ encoding: [0x02,0x10,0xb2,0xf3] +@ CHECK: vswp q1, q2 @ encoding: [0x44,0x20,0xb2,0xf3] diff --git a/test/MC/ARM/neont2-minmax-encoding.s b/test/MC/ARM/neont2-minmax-encoding.s index 7e86d45..9ecadce 100644 --- a/test/MC/ARM/neont2-minmax-encoding.s +++ b/test/MC/ARM/neont2-minmax-encoding.s @@ -2,59 +2,125 @@ .code 16 -@ CHECK: vmin.s8 d16, d16, d17 @ encoding: [0x40,0xef,0xb1,0x06] - vmin.s8 d16, d16, d17 -@ CHECK: vmin.s16 d16, d16, d17 @ encoding: [0x50,0xef,0xb1,0x06] - vmin.s16 d16, d16, d17 -@ CHECK: vmin.s32 d16, d16, d17 @ encoding: [0x60,0xef,0xb1,0x06] - vmin.s32 d16, d16, d17 -@ CHECK: vmin.u8 d16, d16, d17 @ encoding: [0x40,0xff,0xb1,0x06] - vmin.u8 d16, d16, d17 -@ CHECK: vmin.u16 d16, d16, d17 @ encoding: [0x50,0xff,0xb1,0x06] - vmin.u16 d16, d16, d17 -@ CHECK: vmin.u32 d16, d16, d17 @ encoding: [0x60,0xff,0xb1,0x06] - vmin.u32 d16, d16, d17 -@ CHECK: vmin.f32 d16, d16, d17 @ encoding: [0x60,0xef,0xa1,0x0f] - vmin.f32 d16, d16, d17 -@ CHECK: vmin.s8 q8, q8, q9 @ encoding: [0x40,0xef,0xf2,0x06] - vmin.s8 q8, q8, q9 -@ CHECK: vmin.s16 q8, q8, q9 @ encoding: [0x50,0xef,0xf2,0x06] - vmin.s16 q8, q8, q9 -@ CHECK: vmin.s32 q8, q8, q9 @ encoding: [0x60,0xef,0xf2,0x06] - vmin.s32 q8, q8, q9 -@ CHECK: vmin.u8 q8, q8, q9 @ encoding: [0x40,0xff,0xf2,0x06] - vmin.u8 q8, q8, q9 -@ CHECK: vmin.u16 q8, q8, q9 @ encoding: [0x50,0xff,0xf2,0x06] - vmin.u16 q8, q8, q9 -@ CHECK: vmin.u32 q8, q8, q9 @ encoding: [0x60,0xff,0xf2,0x06] - vmin.u32 q8, q8, q9 -@ CHECK: vmin.f32 q8, q8, q9 @ encoding: [0x60,0xef,0xe2,0x0f] - vmin.f32 q8, q8, q9 -@ CHECK: vmax.s8 d16, d16, d17 @ encoding: [0x40,0xef,0xa1,0x06] - vmax.s8 d16, d16, d17 -@ CHECK: vmax.s16 d16, d16, d17 @ encoding: [0x50,0xef,0xa1,0x06] - vmax.s16 d16, d16, d17 -@ CHECK: vmax.s32 d16, d16, d17 @ encoding: [0x60,0xef,0xa1,0x06] - vmax.s32 d16, d16, d17 -@ CHECK: vmax.u8 d16, d16, d17 @ encoding: [0x40,0xff,0xa1,0x06] - vmax.u8 d16, d16, d17 -@ CHECK: vmax.u16 d16, d16, d17 @ encoding: [0x50,0xff,0xa1,0x06] - vmax.u16 d16, d16, d17 -@ CHECK: vmax.u32 d16, d16, d17 @ encoding: [0x60,0xff,0xa1,0x06] - vmax.u32 d16, d16, d17 -@ CHECK: vmax.f32 d16, d16, d17 @ encoding: [0x40,0xef,0xa1,0x0f] - vmax.f32 d16, d16, d17 -@ CHECK: vmax.s8 q8, q8, q9 @ encoding: [0x40,0xef,0xe2,0x06] - vmax.s8 q8, q8, q9 -@ CHECK: vmax.s16 q8, q8, q9 @ encoding: [0x50,0xef,0xe2,0x06] - vmax.s16 q8, q8, q9 + vmax.s8 d1, d2, d3 + vmax.s16 d4, d5, d6 + vmax.s32 d7, d8, d9 + vmax.u8 d10, d11, d12 + vmax.u16 d13, d14, d15 + vmax.u32 d16, d17, d18 + vmax.f32 d19, d20, d21 + + vmax.s8 d2, d3 + vmax.s16 d5, d6 + vmax.s32 d8, d9 + vmax.u8 d11, d12 + vmax.u16 d14, d15 + vmax.u32 d17, d18 + vmax.f32 d20, d21 + + vmax.s8 q1, q2, q3 + vmax.s16 q4, q5, q6 + vmax.s32 q7, q8, q9 + vmax.u8 q10, q11, q12 + vmax.u16 q13, q14, q15 + vmax.u32 q6, q7, q8 + vmax.f32 q9, q5, q1 + + vmax.s8 q2, q3 + vmax.s16 q5, q6 + vmax.s32 q8, q9 + vmax.u8 q11, q2 + vmax.u16 q4, q5 + vmax.u32 q7, q8 + vmax.f32 q2, q1 + +@ CHECK: vmax.s8 d1, d2, d3 @ encoding: [0x02,0xef,0x03,0x16] +@ CHECK: vmax.s16 d4, d5, d6 @ encoding: [0x15,0xef,0x06,0x46] +@ CHECK: vmax.s32 d7, d8, d9 @ encoding: [0x28,0xef,0x09,0x76] +@ CHECK: vmax.u8 d10, d11, d12 @ encoding: [0x0b,0xff,0x0c,0xa6] +@ CHECK: vmax.u16 d13, d14, d15 @ encoding: [0x1e,0xff,0x0f,0xd6] +@ CHECK: vmax.u32 d16, d17, d18 @ encoding: [0x61,0xff,0xa2,0x06] +@ CHECK: vmax.f32 d19, d20, d21 @ encoding: [0x44,0xef,0xa5,0x3f] +@ CHECK: vmax.s8 d2, d2, d3 @ encoding: [0x02,0xef,0x03,0x26] +@ CHECK: vmax.s16 d5, d5, d6 @ encoding: [0x15,0xef,0x06,0x56] +@ CHECK: vmax.s32 d8, d8, d9 @ encoding: [0x28,0xef,0x09,0x86] +@ CHECK: vmax.u8 d11, d11, d12 @ encoding: [0x0b,0xff,0x0c,0xb6] +@ CHECK: vmax.u16 d14, d14, d15 @ encoding: [0x1e,0xff,0x0f,0xe6] +@ CHECK: vmax.u32 d17, d17, d18 @ encoding: [0x61,0xff,0xa2,0x16] +@ CHECK: vmax.f32 d20, d20, d21 @ encoding: [0x44,0xef,0xa5,0x4f] +@ CHECK: vmax.s8 q1, q2, q3 @ encoding: [0x04,0xef,0x46,0x26] +@ CHECK: vmax.s16 q4, q5, q6 @ encoding: [0x1a,0xef,0x4c,0x86] +@ CHECK: vmax.s32 q7, q8, q9 @ encoding: [0x20,0xef,0xe2,0xe6] +@ CHECK: vmax.u8 q10, q11, q12 @ encoding: [0x46,0xff,0xe8,0x46] +@ CHECK: vmax.u16 q13, q14, q15 @ encoding: [0x5c,0xff,0xee,0xa6] +@ CHECK: vmax.u32 q6, q7, q8 @ encoding: [0x2e,0xff,0x60,0xc6] +@ CHECK: vmax.f32 q9, q5, q1 @ encoding: [0x4a,0xef,0x42,0x2f] +@ CHECK: vmax.s8 q2, q2, q3 @ encoding: [0x04,0xef,0x46,0x46] +@ CHECK: vmax.s16 q5, q5, q6 @ encoding: [0x1a,0xef,0x4c,0xa6] @ CHECK: vmax.s32 q8, q8, q9 @ encoding: [0x60,0xef,0xe2,0x06] - vmax.s32 q8, q8, q9 -@ CHECK: vmax.u8 q8, q8, q9 @ encoding: [0x40,0xff,0xe2,0x06] - vmax.u8 q8, q8, q9 -@ CHECK: vmax.u16 q8, q8, q9 @ encoding: [0x50,0xff,0xe2,0x06] - vmax.u16 q8, q8, q9 -@ CHECK: vmax.u32 q8, q8, q9 @ encoding: [0x60,0xff,0xe2,0x06] - vmax.u32 q8, q8, q9 -@ CHECK: vmax.f32 q8, q8, q9 @ encoding: [0x40,0xef,0xe2,0x0f] - vmax.f32 q8, q8, q9 +@ CHECK: vmax.u8 q11, q11, q2 @ encoding: [0x46,0xff,0xc4,0x66] +@ CHECK: vmax.u16 q4, q4, q5 @ encoding: [0x18,0xff,0x4a,0x86] +@ CHECK: vmax.u32 q7, q7, q8 @ encoding: [0x2e,0xff,0x60,0xe6] +@ CHECK: vmax.f32 q2, q2, q1 @ encoding: [0x04,0xef,0x42,0x4f] + + + vmin.s8 d1, d2, d3 + vmin.s16 d4, d5, d6 + vmin.s32 d7, d8, d9 + vmin.u8 d10, d11, d12 + vmin.u16 d13, d14, d15 + vmin.u32 d16, d17, d18 + vmin.f32 d19, d20, d21 + + vmin.s8 d2, d3 + vmin.s16 d5, d6 + vmin.s32 d8, d9 + vmin.u8 d11, d12 + vmin.u16 d14, d15 + vmin.u32 d17, d18 + vmin.f32 d20, d21 + + vmin.s8 q1, q2, q3 + vmin.s16 q4, q5, q6 + vmin.s32 q7, q8, q9 + vmin.u8 q10, q11, q12 + vmin.u16 q13, q14, q15 + vmin.u32 q6, q7, q8 + vmin.f32 q9, q5, q1 + + vmin.s8 q2, q3 + vmin.s16 q5, q6 + vmin.s32 q8, q9 + vmin.u8 q11, q2 + vmin.u16 q4, q5 + vmin.u32 q7, q8 + vmin.f32 q2, q1 + +@ CHECK: vmin.s8 d1, d2, d3 @ encoding: [0x02,0xef,0x13,0x16] +@ CHECK: vmin.s16 d4, d5, d6 @ encoding: [0x15,0xef,0x16,0x46] +@ CHECK: vmin.s32 d7, d8, d9 @ encoding: [0x28,0xef,0x19,0x76] +@ CHECK: vmin.u8 d10, d11, d12 @ encoding: [0x0b,0xff,0x1c,0xa6] +@ CHECK: vmin.u16 d13, d14, d15 @ encoding: [0x1e,0xff,0x1f,0xd6] +@ CHECK: vmin.u32 d16, d17, d18 @ encoding: [0x61,0xff,0xb2,0x06] +@ CHECK: vmin.f32 d19, d20, d21 @ encoding: [0x64,0xef,0xa5,0x3f] +@ CHECK: vmin.s8 d2, d2, d3 @ encoding: [0x02,0xef,0x13,0x26] +@ CHECK: vmin.s16 d5, d5, d6 @ encoding: [0x15,0xef,0x16,0x56] +@ CHECK: vmin.s32 d8, d8, d9 @ encoding: [0x28,0xef,0x19,0x86] +@ CHECK: vmin.u8 d11, d11, d12 @ encoding: [0x0b,0xff,0x1c,0xb6] +@ CHECK: vmin.u16 d14, d14, d15 @ encoding: [0x1e,0xff,0x1f,0xe6] +@ CHECK: vmin.u32 d17, d17, d18 @ encoding: [0x61,0xff,0xb2,0x16] +@ CHECK: vmin.f32 d20, d20, d21 @ encoding: [0x64,0xef,0xa5,0x4f] +@ CHECK: vmin.s8 q1, q2, q3 @ encoding: [0x04,0xef,0x56,0x26] +@ CHECK: vmin.s16 q4, q5, q6 @ encoding: [0x1a,0xef,0x5c,0x86] +@ CHECK: vmin.s32 q7, q8, q9 @ encoding: [0x20,0xef,0xf2,0xe6] +@ CHECK: vmin.u8 q10, q11, q12 @ encoding: [0x46,0xff,0xf8,0x46] +@ CHECK: vmin.u16 q13, q14, q15 @ encoding: [0x5c,0xff,0xfe,0xa6] +@ CHECK: vmin.u32 q6, q7, q8 @ encoding: [0x2e,0xff,0x70,0xc6] +@ CHECK: vmin.f32 q9, q5, q1 @ encoding: [0x6a,0xef,0x42,0x2f] +@ CHECK: vmin.s8 q2, q2, q3 @ encoding: [0x04,0xef,0x56,0x46] +@ CHECK: vmin.s16 q5, q5, q6 @ encoding: [0x1a,0xef,0x5c,0xa6] +@ CHECK: vmin.s32 q8, q8, q9 @ encoding: [0x60,0xef,0xf2,0x06] +@ CHECK: vmin.u8 q11, q11, q2 @ encoding: [0x46,0xff,0xd4,0x66] +@ CHECK: vmin.u16 q4, q4, q5 @ encoding: [0x18,0xff,0x5a,0x86] +@ CHECK: vmin.u32 q7, q7, q8 @ encoding: [0x2e,0xff,0x70,0xe6] +@ CHECK: vmin.f32 q2, q2, q1 @ encoding: [0x24,0xef,0x42,0x4f] diff --git a/test/MC/ARM/neont2-mov-encoding.s b/test/MC/ARM/neont2-mov-encoding.s index ababbb7..43df349 100644 --- a/test/MC/ARM/neont2-mov-encoding.s +++ b/test/MC/ARM/neont2-mov-encoding.s @@ -1,119 +1,131 @@ @ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s -@ XFAIL: * .code 16 -@ CHECK: vmov.i8 d16, #0x8 @ encoding: [0x18,0x0e,0xc0,0xef] vmov.i8 d16, #0x8 -@ CHECK: vmov.i16 d16, #0x10 @ encoding: [0x10,0x08,0xc1,0xef] vmov.i16 d16, #0x10 -@ CHECK: vmov.i16 d16, #0x1000 @ encoding: [0x10,0x0a,0xc1,0xef] vmov.i16 d16, #0x1000 -@ CHECK: vmov.i32 d16, #0x20 @ encoding: [0x10,0x00,0xc2,0xef] vmov.i32 d16, #0x20 -@ CHECK: vmov.i32 d16, #0x2000 @ encoding: [0x10,0x02,0xc2,0xef] vmov.i32 d16, #0x2000 -@ CHECK: vmov.i32 d16, #0x200000 @ encoding: [0x10,0x04,0xc2,0xef] vmov.i32 d16, #0x200000 -@ CHECK: vmov.i32 d16, #0x20000000 @ encoding: [0x10,0x06,0xc2,0xef] vmov.i32 d16, #0x20000000 -@ CHECK: vmov.i32 d16, #0x20FF @ encoding: [0x10,0x0c,0xc2,0xef] vmov.i32 d16, #0x20FF -@ CHECK: vmov.i32 d16, #0x20FFFF @ encoding: [0x10,0x0d,0xc2,0xef] vmov.i32 d16, #0x20FFFF -@ CHECK: vmov.i64 d16, #0xFF0000FF0000FFFF @ encoding: [0x33,0x0e,0xc1,0xff] vmov.i64 d16, #0xFF0000FF0000FFFF -@ CHECK: vmov.i8 q8, #0x8 @ encoding: [0x58,0x0e,0xc0,0xef] + +@ CHECK: vmov.i8 d16, #0x8 @ encoding: [0xc0,0xef,0x18,0x0e] +@ CHECK: vmov.i16 d16, #0x10 @ encoding: [0xc1,0xef,0x10,0x08] +@ CHECK: vmov.i16 d16, #0x1000 @ encoding: [0xc1,0xef,0x10,0x0a] +@ CHECK: vmov.i32 d16, #0x20 @ encoding: [0xc2,0xef,0x10,0x00] +@ CHECK: vmov.i32 d16, #0x2000 @ encoding: [0xc2,0xef,0x10,0x02] +@ CHECK: vmov.i32 d16, #0x200000 @ encoding: [0xc2,0xef,0x10,0x04] +@ CHECK: vmov.i32 d16, #0x20000000 @ encoding: [0xc2,0xef,0x10,0x06] +@ CHECK: vmov.i32 d16, #0x20ff @ encoding: [0xc2,0xef,0x10,0x0c] +@ CHECK: vmov.i32 d16, #0x20ffff @ encoding: [0xc2,0xef,0x10,0x0d] +@ CHECK: vmov.i64 d16, #0xff0000ff0000ffff @ encoding: [0xc1,0xff,0x33,0x0e] + + vmov.i8 q8, #0x8 -@ CHECK: vmov.i16 q8, #0x10 @ encoding: [0x50,0x08,0xc1,0xef] vmov.i16 q8, #0x10 -@ CHECK: vmov.i16 q8, #0x1000 @ encoding: [0x50,0x0a,0xc1,0xef] vmov.i16 q8, #0x1000 -@ CHECK: vmov.i32 q8, #0x20 @ encoding: [0x50,0x00,0xc2,0xef] vmov.i32 q8, #0x20 -@ CHECK: vmov.i32 q8, #0x2000 @ encoding: [0x50,0x02,0xc2,0xef] vmov.i32 q8, #0x2000 -@ CHECK: vmov.i32 q8, #0x200000 @ encoding: [0x50,0x04,0xc2,0xef] vmov.i32 q8, #0x200000 -@ CHECK: vmov.i32 q8, #0x20000000 @ encoding: [0x50,0x06,0xc2,0xef] vmov.i32 q8, #0x20000000 -@ CHECK: vmov.i32 q8, #0x20FF @ encoding: [0x50,0x0c,0xc2,0xef] vmov.i32 q8, #0x20FF -@ CHECK: vmov.i32 q8, #0x20FFFF @ encoding: [0x50,0x0d,0xc2,0xef] vmov.i32 q8, #0x20FFFF -@ CHECK: vmov.i64 q8, #0xFF0000FF0000FFFF @ encoding: [0x73,0x0e,0xc1,0xff] vmov.i64 q8, #0xFF0000FF0000FFFF -@ CHECK: vmvn.i16 d16, #0x10 @ encoding: [0x30,0x08,0xc1,0xef] + +@ CHECK: vmov.i8 q8, #0x8 @ encoding: [0xc0,0xef,0x58,0x0e] +@ CHECK: vmov.i16 q8, #0x10 @ encoding: [0xc1,0xef,0x50,0x08] +@ CHECK: vmov.i16 q8, #0x1000 @ encoding: [0xc1,0xef,0x50,0x0a] +@ CHECK: vmov.i32 q8, #0x20 @ encoding: [0xc2,0xef,0x50,0x00] +@ CHECK: vmov.i32 q8, #0x2000 @ encoding: [0xc2,0xef,0x50,0x02] +@ CHECK: vmov.i32 q8, #0x200000 @ encoding: [0xc2,0xef,0x50,0x04] +@ CHECK: vmov.i32 q8, #0x20000000 @ encoding: [0xc2,0xef,0x50,0x06] +@ CHECK: vmov.i32 q8, #0x20ff @ encoding: [0xc2,0xef,0x50,0x0c] +@ CHECK: vmov.i32 q8, #0x20ffff @ encoding: [0xc2,0xef,0x50,0x0d] +@ CHECK: vmov.i64 q8, #0xff0000ff0000ffff @ encoding: [0xc1,0xff,0x73,0x0e] + + vmvn.i16 d16, #0x10 -@ CHECK: vmvn.i16 d16, #0x1000 @ encoding: [0x30,0x0a,0xc1,0xef] vmvn.i16 d16, #0x1000 -@ CHECK: vmvn.i32 d16, #0x20 @ encoding: [0x30,0x00,0xc2,0xef] vmvn.i32 d16, #0x20 -@ CHECK: vmvn.i32 d16, #0x2000 @ encoding: [0x30,0x02,0xc2,0xef] vmvn.i32 d16, #0x2000 -@ CHECK: vmvn.i32 d16, #0x200000 @ encoding: [0x30,0x04,0xc2,0xef] vmvn.i32 d16, #0x200000 -@ CHECK: vmvn.i32 d16, #0x20000000 @ encoding: [0x30,0x06,0xc2,0xef] vmvn.i32 d16, #0x20000000 -@ CHECK: vmvn.i32 d16, #0x20FF @ encoding: [0x30,0x0c,0xc2,0xef] vmvn.i32 d16, #0x20FF -@ CHECK: vmvn.i32 d16, #0x20FFFF @ encoding: [0x30,0x0d,0xc2,0xef] vmvn.i32 d16, #0x20FFFF -@ CHECK: vmovl.s8 q8, d16 @ encoding: [0x30,0x0a,0xc8,0xef] + +@ CHECK: vmvn.i16 d16, #0x10 @ encoding: [0xc1,0xef,0x30,0x08] +@ CHECK: vmvn.i16 d16, #0x1000 @ encoding: [0xc1,0xef,0x30,0x0a] +@ CHECK: vmvn.i32 d16, #0x20 @ encoding: [0xc2,0xef,0x30,0x00] +@ CHECK: vmvn.i32 d16, #0x2000 @ encoding: [0xc2,0xef,0x30,0x02] +@ CHECK: vmvn.i32 d16, #0x200000 @ encoding: [0xc2,0xef,0x30,0x04] +@ CHECK: vmvn.i32 d16, #0x20000000 @ encoding: [0xc2,0xef,0x30,0x06] +@ CHECK: vmvn.i32 d16, #0x20ff @ encoding: [0xc2,0xef,0x30,0x0c] +@ CHECK: vmvn.i32 d16, #0x20ffff @ encoding: [0xc2,0xef,0x30,0x0d] + + vmovl.s8 q8, d16 -@ CHECK: vmovl.s16 q8, d16 @ encoding: [0x30,0x0a,0xd0,0xef] vmovl.s16 q8, d16 -@ CHECK: vmovl.s32 q8, d16 @ encoding: [0x30,0x0a,0xe0,0xef] vmovl.s32 q8, d16 -@ CHECK: vmovl.u8 q8, d16 @ encoding: [0x30,0x0a,0xc8,0xff] vmovl.u8 q8, d16 -@ CHECK: vmovl.u16 q8, d16 @ encoding: [0x30,0x0a,0xd0,0xff] vmovl.u16 q8, d16 -@ CHECK: vmovl.u32 q8, d16 @ encoding: [0x30,0x0a,0xe0,0xff] vmovl.u32 q8, d16 -@ CHECK: vmovn.i16 d16, q8 @ encoding: [0x20,0x02,0xf2,0xff] vmovn.i16 d16, q8 -@ CHECK: vmovn.i32 d16, q8 @ encoding: [0x20,0x02,0xf6,0xff] vmovn.i32 d16, q8 -@ CHECK: vmovn.i64 d16, q8 @ encoding: [0x20,0x02,0xfa,0xff] vmovn.i64 d16, q8 -@ CHECK: vqmovn.s16 d16, q8 @ encoding: [0xa0,0x02,0xf2,0xff] vqmovn.s16 d16, q8 -@ CHECK: vqmovn.s32 d16, q8 @ encoding: [0xa0,0x02,0xf6,0xff] vqmovn.s32 d16, q8 -@ CHECK: vqmovn.s64 d16, q8 @ encoding: [0xa0,0x02,0xfa,0xff] vqmovn.s64 d16, q8 -@ CHECK: vqmovn.u16 d16, q8 @ encoding: [0xe0,0x02,0xf2,0xff] vqmovn.u16 d16, q8 -@ CHECK: vqmovn.u32 d16, q8 @ encoding: [0xe0,0x02,0xf6,0xff] vqmovn.u32 d16, q8 -@ CHECK: vqmovn.u64 d16, q8 @ encoding: [0xe0,0x02,0xfa,0xff] vqmovn.u64 d16, q8 -@ CHECK: vqmovun.s16 d16, q8 @ encoding: [0x60,0x02,0xf2,0xff] vqmovun.s16 d16, q8 -@ CHECK: vqmovun.s32 d16, q8 @ encoding: [0x60,0x02,0xf6,0xff] vqmovun.s32 d16, q8 -@ CHECK: vqmovun.s64 d16, q8 @ encoding: [0x60,0x02,0xfa,0xff] vqmovun.s64 d16, q8 -@ CHECK: vmov.s8 r0, d16[1] @ encoding: [0xb0,0x0b,0x50,0xee] + +@ CHECK: vmovl.s8 q8, d16 @ encoding: [0xc8,0xef,0x30,0x0a] +@ CHECK: vmovl.s16 q8, d16 @ encoding: [0xd0,0xef,0x30,0x0a] +@ CHECK: vmovl.s32 q8, d16 @ encoding: [0xe0,0xef,0x30,0x0a] +@ CHECK: vmovl.u8 q8, d16 @ encoding: [0xc8,0xff,0x30,0x0a] +@ CHECK: vmovl.u16 q8, d16 @ encoding: [0xd0,0xff,0x30,0x0a] +@ CHECK: vmovl.u32 q8, d16 @ encoding: [0xe0,0xff,0x30,0x0a] +@ CHECK: vmovn.i16 d16, q8 @ encoding: [0xf2,0xff,0x20,0x02] +@ CHECK: vmovn.i32 d16, q8 @ encoding: [0xf6,0xff,0x20,0x02] +@ CHECK: vmovn.i64 d16, q8 @ encoding: [0xfa,0xff,0x20,0x02] +@ CHECK: vqmovn.s16 d16, q8 @ encoding: [0xf2,0xff,0xa0,0x02] +@ CHECK: vqmovn.s32 d16, q8 @ encoding: [0xf6,0xff,0xa0,0x02] +@ CHECK: vqmovn.s64 d16, q8 @ encoding: [0xfa,0xff,0xa0,0x02] +@ CHECK: vqmovn.u16 d16, q8 @ encoding: [0xf2,0xff,0xe0,0x02] +@ CHECK: vqmovn.u32 d16, q8 @ encoding: [0xf6,0xff,0xe0,0x02] +@ CHECK: vqmovn.u64 d16, q8 @ encoding: [0xfa,0xff,0xe0,0x02] +@ CHECK: vqmovun.s16 d16, q8 @ encoding: [0xf2,0xff,0x60,0x02] +@ CHECK: vqmovun.s32 d16, q8 @ encoding: [0xf6,0xff,0x60,0x02] +@ CHECK: vqmovun.s64 d16, q8 @ encoding: [0xfa,0xff,0x60,0x02] + + vmov.s8 r0, d16[1] -@ CHECK: vmov.s16 r0, d16[1] @ encoding: [0xf0,0x0b,0x10,0xee] vmov.s16 r0, d16[1] -@ CHECK: vmov.u8 r0, d16[1] @ encoding: [0xb0,0x0b,0xd0,0xee] vmov.u8 r0, d16[1] -@ CHECK: vmov.u16 r0, d16[1] @ encoding: [0xf0,0x0b,0x90,0xee] vmov.u16 r0, d16[1] -@ CHECK: vmov.32 r0, d16[1] @ encoding: [0x90,0x0b,0x30,0xee] vmov.32 r0, d16[1] -@ CHECK: vmov.8 d16[1], r1 @ encoding: [0xb0,0x1b,0x40,0xee] vmov.8 d16[1], r1 -@ CHECK: vmov.16 d16[1], r1 @ encoding: [0xf0,0x1b,0x00,0xee] vmov.16 d16[1], r1 -@ CHECK: vmov.32 d16[1], r1 @ encoding: [0x90,0x1b,0x20,0xee] vmov.32 d16[1], r1 -@ CHECK: vmov.8 d18[1], r1 @ encoding: [0xb0,0x1b,0x42,0xee] vmov.8 d18[1], r1 -@ CHECK: vmov.16 d18[1], r1 @ encoding: [0xf0,0x1b,0x02,0xee] vmov.16 d18[1], r1 -@ CHECK: vmov.32 d18[1], r1 @ encoding: [0x90,0x1b,0x22,0xee] vmov.32 d18[1], r1 + +@ CHECK: vmov.s8 r0, d16[1] @ encoding: [0x50,0xee,0xb0,0x0b] +@ CHECK: vmov.s16 r0, d16[1] @ encoding: [0x10,0xee,0xf0,0x0b] +@ CHECK: vmov.u8 r0, d16[1] @ encoding: [0xd0,0xee,0xb0,0x0b] +@ CHECK: vmov.u16 r0, d16[1] @ encoding: [0x90,0xee,0xf0,0x0b] +@ CHECK: vmov.32 r0, d16[1] @ encoding: [0x30,0xee,0x90,0x0b] +@ CHECK: vmov.8 d16[1], r1 @ encoding: [0x40,0xee,0xb0,0x1b] +@ CHECK: vmov.16 d16[1], r1 @ encoding: [0x00,0xee,0xf0,0x1b] +@ CHECK: vmov.32 d16[1], r1 @ encoding: [0x20,0xee,0x90,0x1b] +@ CHECK: vmov.8 d18[1], r1 @ encoding: [0x42,0xee,0xb0,0x1b] +@ CHECK: vmov.16 d18[1], r1 @ encoding: [0x02,0xee,0xf0,0x1b] +@ CHECK: vmov.32 d18[1], r1 @ encoding: [0x22,0xee,0x90,0x1b] diff --git a/test/MC/ARM/neont2-mul-accum-encoding.s b/test/MC/ARM/neont2-mul-accum-encoding.s index be4bf79..bc6a4d4 100644 --- a/test/MC/ARM/neont2-mul-accum-encoding.s +++ b/test/MC/ARM/neont2-mul-accum-encoding.s @@ -10,6 +10,7 @@ vmla.i16 q9, q8, q10 vmla.i32 q9, q8, q10 vmla.f32 q9, q8, q10 + vmla.i32 q12, q8, d3[0] @ CHECK: vmla.i8 d16, d18, d17 @ encoding: [0x42,0xef,0xa1,0x09] @ CHECK: vmla.i16 d16, d18, d17 @ encoding: [0x52,0xef,0xa1,0x09] @@ -19,6 +20,7 @@ @ CHECK: vmla.i16 q9, q8, q10 @ encoding: [0x50,0xef,0xe4,0x29] @ CHECK: vmla.i32 q9, q8, q10 @ encoding: [0x60,0xef,0xe4,0x29] @ CHECK: vmla.f32 q9, q8, q10 @ encoding: [0x40,0xef,0xf4,0x2d] +@ CHECK: vmla.i32 q12, q8, d3[0] @ encoding: [0xe0,0xff,0xc3,0x80] vmlal.s8 q8, d19, d18 @@ -27,6 +29,7 @@ vmlal.u8 q8, d19, d18 vmlal.u16 q8, d19, d18 vmlal.u32 q8, d19, d18 + vmlal.s32 q0, d5, d10[0] @ CHECK: vmlal.s8 q8, d19, d18 @ encoding: [0xc3,0xef,0xa2,0x08] @ CHECK: vmlal.s16 q8, d19, d18 @ encoding: [0xd3,0xef,0xa2,0x08] @@ -34,13 +37,22 @@ @ CHECK: vmlal.u8 q8, d19, d18 @ encoding: [0xc3,0xff,0xa2,0x08] @ CHECK: vmlal.u16 q8, d19, d18 @ encoding: [0xd3,0xff,0xa2,0x08] @ CHECK: vmlal.u32 q8, d19, d18 @ encoding: [0xe3,0xff,0xa2,0x08] +@ CHECK: vmlal.s32 q0, d5, d10[0] @ encoding: [0xa5,0xef,0x4a,0x02] vqdmlal.s16 q8, d19, d18 vqdmlal.s32 q8, d19, d18 + vqdmlal.s16 q11, d11, d7[0] + vqdmlal.s16 q11, d11, d7[1] + vqdmlal.s16 q11, d11, d7[2] + vqdmlal.s16 q11, d11, d7[3] @ CHECK: vqdmlal.s16 q8, d19, d18 @ encoding: [0xd3,0xef,0xa2,0x09] @ CHECK: vqdmlal.s32 q8, d19, d18 @ encoding: [0xe3,0xef,0xa2,0x09] +@ CHECK: vqdmlal.s16 q11, d11, d7[0] @ encoding: [0xdb,0xef,0x47,0x63] +@ CHECK: vqdmlal.s16 q11, d11, d7[1] @ encoding: [0xdb,0xef,0x4f,0x63] +@ CHECK: vqdmlal.s16 q11, d11, d7[2] @ encoding: [0xdb,0xef,0x67,0x63] +@ CHECK: vqdmlal.s16 q11, d11, d7[3] @ encoding: [0xdb,0xef,0x6f,0x63] vmls.i8 d16, d18, d17 @@ -51,6 +63,7 @@ vmls.i16 q9, q8, q10 vmls.i32 q9, q8, q10 vmls.f32 q9, q8, q10 + vmls.i16 q4, q12, d6[2] @ CHECK: vmls.i8 d16, d18, d17 @ encoding: [0x42,0xff,0xa1,0x09] @ CHECK: vmls.i16 d16, d18, d17 @ encoding: [0x52,0xff,0xa1,0x09] @@ -60,6 +73,7 @@ @ CHECK: vmls.i16 q9, q8, q10 @ encoding: [0x50,0xff,0xe4,0x29] @ CHECK: vmls.i32 q9, q8, q10 @ encoding: [0x60,0xff,0xe4,0x29] @ CHECK: vmls.f32 q9, q8, q10 @ encoding: [0x60,0xef,0xf4,0x2d] +@ CHECK: vmls.i16 q4, q12, d6[2] @ encoding: [0x98,0xff,0xe6,0x84] vmlsl.s8 q8, d19, d18 @@ -68,6 +82,7 @@ vmlsl.u8 q8, d19, d18 vmlsl.u16 q8, d19, d18 vmlsl.u32 q8, d19, d18 + vmlsl.u16 q11, d25, d1[3] @ CHECK: vmlsl.s8 q8, d19, d18 @ encoding: [0xc3,0xef,0xa2,0x0a] @ CHECK: vmlsl.s16 q8, d19, d18 @ encoding: [0xd3,0xef,0xa2,0x0a] @@ -75,6 +90,7 @@ @ CHECK: vmlsl.u8 q8, d19, d18 @ encoding: [0xc3,0xff,0xa2,0x0a] @ CHECK: vmlsl.u16 q8, d19, d18 @ encoding: [0xd3,0xff,0xa2,0x0a] @ CHECK: vmlsl.u32 q8, d19, d18 @ encoding: [0xe3,0xff,0xa2,0x0a] +@ CHECK: vmlsl.u16 q11, d25, d1[3] @ encoding: [0xd9,0xff,0xe9,0x66] vqdmlsl.s16 q8, d19, d18 diff --git a/test/MC/ARM/neont2-mul-encoding.s b/test/MC/ARM/neont2-mul-encoding.s index 93ecabb..dfbb667 100644 --- a/test/MC/ARM/neont2-mul-encoding.s +++ b/test/MC/ARM/neont2-mul-encoding.s @@ -2,57 +2,77 @@ .code 16 -@ CHECK: vmul.i8 d16, d16, d17 @ encoding: [0x40,0xef,0xb1,0x09] vmul.i8 d16, d16, d17 -@ CHECK: vmul.i16 d16, d16, d17 @ encoding: [0x50,0xef,0xb1,0x09] vmul.i16 d16, d16, d17 -@ CHECK: vmul.i32 d16, d16, d17 @ encoding: [0x60,0xef,0xb1,0x09] vmul.i32 d16, d16, d17 -@ CHECK: vmul.f32 d16, d16, d17 @ encoding: [0x40,0xff,0xb1,0x0d] vmul.f32 d16, d16, d17 -@ CHECK: vmul.i8 q8, q8, q9 @ encoding: [0x40,0xef,0xf2,0x09] vmul.i8 q8, q8, q9 -@ CHECK: vmul.i16 q8, q8, q9 @ encoding: [0x50,0xef,0xf2,0x09] vmul.i16 q8, q8, q9 -@ CHECK: vmul.i32 q8, q8, q9 @ encoding: [0x60,0xef,0xf2,0x09] vmul.i32 q8, q8, q9 -@ CHECK: vmul.f32 q8, q8, q9 @ encoding: [0x40,0xff,0xf2,0x0d] vmul.f32 q8, q8, q9 -@ CHECK: vmul.p8 d16, d16, d17 @ encoding: [0x40,0xff,0xb1,0x09] vmul.p8 d16, d16, d17 -@ CHECK: vmul.p8 q8, q8, q9 @ encoding: [0x40,0xff,0xf2,0x09] vmul.p8 q8, q8, q9 -@ CHECK: vqdmulh.s16 d16, d16, d17 @ encoding: [0x50,0xef,0xa1,0x0b] + vmul.i16 d18, d8, d0[3] + +@ CHECK: vmul.i8 d16, d16, d17 @ encoding: [0x40,0xef,0xb1,0x09] +@ CHECK: vmul.i16 d16, d16, d17 @ encoding: [0x50,0xef,0xb1,0x09] +@ CHECK: vmul.i32 d16, d16, d17 @ encoding: [0x60,0xef,0xb1,0x09] +@ CHECK: vmul.f32 d16, d16, d17 @ encoding: [0x40,0xff,0xb1,0x0d] +@ CHECK: vmul.i8 q8, q8, q9 @ encoding: [0x40,0xef,0xf2,0x09] +@ CHECK: vmul.i16 q8, q8, q9 @ encoding: [0x50,0xef,0xf2,0x09] +@ CHECK: vmul.i32 q8, q8, q9 @ encoding: [0x60,0xef,0xf2,0x09] +@ CHECK: vmul.f32 q8, q8, q9 @ encoding: [0x40,0xff,0xf2,0x0d] +@ CHECK: vmul.p8 d16, d16, d17 @ encoding: [0x40,0xff,0xb1,0x09] +@ CHECK: vmul.p8 q8, q8, q9 @ encoding: [0x40,0xff,0xf2,0x09] +@ CHECK: vmul.i16 d18, d8, d0[3] @ encoding: [0xd8,0xef,0x68,0x28] + + vqdmulh.s16 d16, d16, d17 -@ CHECK: vqdmulh.s32 d16, d16, d17 @ encoding: [0x60,0xef,0xa1,0x0b] vqdmulh.s32 d16, d16, d17 -@ CHECK: vqdmulh.s16 q8, q8, q9 @ encoding: [0x50,0xef,0xe2,0x0b] vqdmulh.s16 q8, q8, q9 -@ CHECK: vqdmulh.s32 q8, q8, q9 @ encoding: [0x60,0xef,0xe2,0x0b] vqdmulh.s32 q8, q8, q9 -@ CHECK: vqrdmulh.s16 d16, d16, d17 @ encoding: [0x50,0xff,0xa1,0x0b] + vqdmulh.s16 d11, d2, d3[0] + +@ CHECK: vqdmulh.s16 d16, d16, d17 @ encoding: [0x50,0xef,0xa1,0x0b] +@ CHECK: vqdmulh.s32 d16, d16, d17 @ encoding: [0x60,0xef,0xa1,0x0b] +@ CHECK: vqdmulh.s16 q8, q8, q9 @ encoding: [0x50,0xef,0xe2,0x0b] +@ CHECK: vqdmulh.s32 q8, q8, q9 @ encoding: [0x60,0xef,0xe2,0x0b] +@ CHECK: vqdmulh.s16 d11, d2, d3[0] @ encoding: [0x92,0xef,0x43,0xbc] + + vqrdmulh.s16 d16, d16, d17 -@ CHECK: vqrdmulh.s32 d16, d16, d17 @ encoding: [0x60,0xff,0xa1,0x0b] vqrdmulh.s32 d16, d16, d17 -@ CHECK: vqrdmulh.s16 q8, q8, q9 @ encoding: [0x50,0xff,0xe2,0x0b] vqrdmulh.s16 q8, q8, q9 -@ CHECK: vqrdmulh.s32 q8, q8, q9 @ encoding: [0x60,0xff,0xe2,0x0b] vqrdmulh.s32 q8, q8, q9 -@ CHECK: vmull.s8 q8, d16, d17 @ encoding: [0xc0,0xef,0xa1,0x0c] + +@ CHECK: vqrdmulh.s16 d16, d16, d17 @ encoding: [0x50,0xff,0xa1,0x0b] +@ CHECK: vqrdmulh.s32 d16, d16, d17 @ encoding: [0x60,0xff,0xa1,0x0b] +@ CHECK: vqrdmulh.s16 q8, q8, q9 @ encoding: [0x50,0xff,0xe2,0x0b] +@ CHECK: vqrdmulh.s32 q8, q8, q9 @ encoding: [0x60,0xff,0xe2,0x0b] + + vmull.s8 q8, d16, d17 -@ CHECK: vmull.s16 q8, d16, d17 @ encoding: [0xd0,0xef,0xa1,0x0c] vmull.s16 q8, d16, d17 -@ CHECK: vmull.s32 q8, d16, d17 @ encoding: [0xe0,0xef,0xa1,0x0c] vmull.s32 q8, d16, d17 -@ CHECK: vmull.u8 q8, d16, d17 @ encoding: [0xc0,0xff,0xa1,0x0c] vmull.u8 q8, d16, d17 -@ CHECK: vmull.u16 q8, d16, d17 @ encoding: [0xd0,0xff,0xa1,0x0c] vmull.u16 q8, d16, d17 -@ CHECK: vmull.u32 q8, d16, d17 @ encoding: [0xe0,0xff,0xa1,0x0c] vmull.u32 q8, d16, d17 -@ CHECK: vmull.p8 q8, d16, d17 @ encoding: [0xc0,0xef,0xa1,0x0e] vmull.p8 q8, d16, d17 -@ CHECK: vqdmull.s16 q8, d16, d17 @ encoding: [0xd0,0xef,0xa1,0x0d] + +@ CHECK: vmull.s8 q8, d16, d17 @ encoding: [0xc0,0xef,0xa1,0x0c] +@ CHECK: vmull.s16 q8, d16, d17 @ encoding: [0xd0,0xef,0xa1,0x0c] +@ CHECK: vmull.s32 q8, d16, d17 @ encoding: [0xe0,0xef,0xa1,0x0c] +@ CHECK: vmull.u8 q8, d16, d17 @ encoding: [0xc0,0xff,0xa1,0x0c] +@ CHECK: vmull.u16 q8, d16, d17 @ encoding: [0xd0,0xff,0xa1,0x0c] +@ CHECK: vmull.u32 q8, d16, d17 @ encoding: [0xe0,0xff,0xa1,0x0c] +@ CHECK: vmull.p8 q8, d16, d17 @ encoding: [0xc0,0xef,0xa1,0x0e] + + vqdmull.s16 q8, d16, d17 -@ CHECK: vqdmull.s32 q8, d16, d17 @ encoding: [0xe0,0xef,0xa1,0x0d] vqdmull.s32 q8, d16, d17 + vqdmull.s16 q1, d7, d1[1] + +@ CHECK: vqdmull.s16 q8, d16, d17 @ encoding: [0xd0,0xef,0xa1,0x0d] +@ CHECK: vqdmull.s32 q8, d16, d17 @ encoding: [0xe0,0xef,0xa1,0x0d] +@ CHECK: vqdmull.s16 q1, d7, d1[1] @ encoding: [0x97,0xef,0x49,0x2b] + diff --git a/test/MC/ARM/neont2-table-encoding.s b/test/MC/ARM/neont2-table-encoding.s index 46fb934..9bfcc74 100644 --- a/test/MC/ARM/neont2-table-encoding.s +++ b/test/MC/ARM/neont2-table-encoding.s @@ -1,21 +1,24 @@ @ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s -@ XFAIL: * .code 16 -@ CHECK: vtbl.8 d16, {d17}, d16 @ encoding: [0xa0,0x08,0xf1,0xff] vtbl.8 d16, {d17}, d16 -@ CHECK: vtbl.8 d16, {d16, d17}, d18 @ encoding: [0xa2,0x09,0xf0,0xff] vtbl.8 d16, {d16, d17}, d18 -@ CHECK: vtbl.8 d16, {d16, d17, d18}, d20 @ encoding: [0xa4,0x0a,0xf0,0xff] vtbl.8 d16, {d16, d17, d18}, d20 -@ CHECK: vtbl.8 d16, {d16, d17, d18, d19}, d20 @ encoding: [0xa4,0x0b,0xf0,0xff] vtbl.8 d16, {d16, d17, d18, d19}, d20 -@ CHECK: vtbx.8 d18, {d16}, d17 @ encoding: [0xe1,0x28,0xf0,0xff] + +@ CHECK: vtbl.8 d16, {d17}, d16 @ encoding: [0xf1,0xff,0xa0,0x08] +@ CHECK: vtbl.8 d16, {d16, d17}, d18 @ encoding: [0xf0,0xff,0xa2,0x09] +@ CHECK: vtbl.8 d16, {d16, d17, d18}, d20 @ encoding: [0xf0,0xff,0xa4,0x0a] +@ CHECK: vtbl.8 d16, {d16, d17, d18, d19}, d20 @ encoding: [0xf0,0xff,0xa4,0x0b] + + vtbx.8 d18, {d16}, d17 -@ CHECK: vtbx.8 d19, {d16, d17}, d18 @ encoding: [0xe2,0x39,0xf0,0xff] vtbx.8 d19, {d16, d17}, d18 -@ CHECK: vtbx.8 d20, {d16, d17, d18}, d21 @ encoding: [0xe5,0x4a,0xf0,0xff] vtbx.8 d20, {d16, d17, d18}, d21 -@ CHECK: vtbx.8 d20, {d16, d17, d18, d19}, d21 @ encoding: [0xe5,0x4b,0xf0,0xff] vtbx.8 d20, {d16, d17, d18, d19}, d21 + +@ CHECK: vtbx.8 d18, {d16}, d17 @ encoding: [0xf0,0xff,0xe1,0x28] +@ CHECK: vtbx.8 d19, {d16, d17}, d18 @ encoding: [0xf0,0xff,0xe2,0x39] +@ CHECK: vtbx.8 d20, {d16, d17, d18}, d21 @ encoding: [0xf0,0xff,0xe5,0x4a] +@ CHECK: vtbx.8 d20, {d16, d17, d18, d19}, d21 @ encoding: [0xf0,0xff,0xe5,0x4b] diff --git a/test/MC/ARM/neont2-vst-encoding.s b/test/MC/ARM/neont2-vst-encoding.s index 1722f12..b50d8b6 100644 --- a/test/MC/ARM/neont2-vst-encoding.s +++ b/test/MC/ARM/neont2-vst-encoding.s @@ -101,3 +101,7 @@ vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0, :64] @ CHECK: vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] @ encoding: [0x4f,0x1b,0xc0,0xf9] vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] + +@ rdar://11082188 + vst2.8 {d8, d10}, [r4] +@ CHECK: vst2.8 {d8, d10}, [r4] @ encoding: [0x04,0xf9,0x0f,0x89] diff --git a/test/MC/ARM/pr11877.s b/test/MC/ARM/pr11877.s new file mode 100644 index 0000000..da3f6ad --- /dev/null +++ b/test/MC/ARM/pr11877.s @@ -0,0 +1,6 @@ +// RUN: llvm-mc -triple arm-unknown-unknown %s + +i: + .long g +g = h +h = i diff --git a/test/MC/ARM/prefetch.ll b/test/MC/ARM/prefetch.ll deleted file mode 100644 index e77fdb1..0000000 --- a/test/MC/ARM/prefetch.ll +++ /dev/null @@ -1,58 +0,0 @@ -; RUN: llc < %s -mtriple=armv7-apple-darwin -mattr=+v7,+mp -show-mc-encoding | FileCheck %s -check-prefix=ARM -; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+v7 -show-mc-encoding | FileCheck %s -check-prefix=T2 -; rdar://8924681 - -define void @t1(i8* %ptr) nounwind { -entry: -; ARM: t1: -; ARM: pldw [r0] @ encoding: [0x00,0xf0,0x90,0xf5] -; ARM: pld [r0] @ encoding: [0x00,0xf0,0xd0,0xf5] - -; T2: t1: -; T2: pld [r0] @ encoding: [0x90,0xf8,0x00,0xf0] - tail call void @llvm.prefetch( i8* %ptr, i32 1, i32 3 ) - tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3 ) - ret void -} - -define void @t2(i8* %ptr) nounwind { -entry: -; ARM: t2: -; ARM: pld [r0, #1023] @ encoding: [0xff,0xf3,0xd0,0xf5] - -; T2: t2: -; T2: pld [r0, #1023] @ encoding: [0x90,0xf8,0xff,0xf3] - %tmp = getelementptr i8* %ptr, i32 1023 - tail call void @llvm.prefetch( i8* %tmp, i32 0, i32 3 ) - ret void -} - -define void @t3(i32 %base, i32 %offset) nounwind { -entry: -; ARM: t3: -; ARM: pld [r0, r1, lsr #2] @ encoding: [0x21,0xf1,0xd0,0xf7] - -; T2: t3: -; T2: pld [r0, r1] @ encoding: [0x10,0xf8,0x01,0xf0] - %tmp1 = lshr i32 %offset, 2 - %tmp2 = add i32 %base, %tmp1 - %tmp3 = inttoptr i32 %tmp2 to i8* - tail call void @llvm.prefetch( i8* %tmp3, i32 0, i32 3 ) - ret void -} - -define void @t4(i32 %base, i32 %offset) nounwind { -entry: -; ARM: t4: -; ARM: pld [r0, r1, lsl #2] @ encoding: [0x01,0xf1,0xd0,0xf7] - -; T2: t4: -; T2: pld [r0, r1, lsl #2] @ encoding: [0x10,0xf8,0x21,0xf0] - %tmp1 = shl i32 %offset, 2 - %tmp2 = add i32 %base, %tmp1 - %tmp3 = inttoptr i32 %tmp2 to i8* - tail call void @llvm.prefetch( i8* %tmp3, i32 0, i32 3 ) - ret void -} - -declare void @llvm.prefetch(i8*, i32, i32) nounwind diff --git a/test/MC/ARM/simple-fp-encoding.s b/test/MC/ARM/simple-fp-encoding.s index e7d452a..b592f1e 100644 --- a/test/MC/ARM/simple-fp-encoding.s +++ b/test/MC/ARM/simple-fp-encoding.s @@ -21,9 +21,15 @@ @ CHECK: vmul.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x61,0xee] vmul.f64 d16, d17, d16 +@ CHECK: vmul.f64 d20, d20, d17 @ encoding: [0xa1,0x4b,0x64,0xee] + vmul.f64 d20, d17 + @ CHECK: vmul.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x20,0xee] vmul.f32 s0, s1, s0 +@ CHECK: vmul.f32 s11, s11, s21 @ encoding: [0xaa,0x5a,0x65,0xee] + vmul.f32 s11, s21 + @ CHECK: vnmul.f64 d16, d17, d16 @ encoding: [0xe0,0x0b,0x61,0xee] vnmul.f64 d16, d17, d16 @@ -114,10 +120,21 @@ @ CHECK: vnmls.f32 s1, s2, s0 @ encoding: [0x00,0x0a,0x51,0xee] vnmls.f32 s1, s2, s0 -@ CHECK: vmrs apsr_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee] -@ CHECK: vmrs apsr_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee] + vmrs APSR_nzcv, fpscr vmrs apsr_nzcv, fpscr fmstat + vmrs r2, fpsid + vmrs r3, FPSID + vmrs r4, mvfr0 + vmrs r5, MVFR1 + +@ CHECK: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee] +@ CHECK: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee] +@ CHECK: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee] +@ CHECK: vmrs r2, fpsid @ encoding: [0x10,0x2a,0xf0,0xee] +@ CHECK: vmrs r3, fpsid @ encoding: [0x10,0x3a,0xf0,0xee] +@ CHECK: vmrs r4, mvfr0 @ encoding: [0x10,0x4a,0xf7,0xee] +@ CHECK: vmrs r5, mvfr1 @ encoding: [0x10,0x5a,0xf6,0xee] @ CHECK: vnegne.f64 d16, d16 @ encoding: [0x60,0x0b,0xf1,0x1e] vnegne.f64 d16, d16 @@ -127,6 +144,16 @@ vmovne s0, r0 vmoveq s0, r1 + vmov.f32 r1, s2 + vmov.f32 s4, r3 + vmov.f64 r1, r5, d2 + vmov.f64 d4, r3, r9 + +@ CHECK: vmov r1, s2 @ encoding: [0x10,0x1a,0x11,0xee] +@ CHECK: vmov s4, r3 @ encoding: [0x10,0x3a,0x02,0xee] +@ CHECK: vmov r1, r5, d2 @ encoding: [0x12,0x1b,0x55,0xec] +@ CHECK: vmov d4, r3, r9 @ encoding: [0x14,0x3b,0x49,0xec] + @ CHECK: vmrs r0, fpscr @ encoding: [0x10,0x0a,0xf1,0xee] vmrs r0, fpscr @ CHECK: vmrs r0, fpexc @ encoding: [0x10,0x0a,0xf8,0xee] @@ -172,52 +199,62 @@ @ CHECK: vmov r0, r1, d16 @ encoding: [0x30,0x0b,0x51,0xec] vmov r0, r1, d16 -@ CHECK: vldr.64 d17, [r0] @ encoding: [0x00,0x1b,0xd0,0xed] +@ CHECK: vldr d17, [r0] @ encoding: [0x00,0x1b,0xd0,0xed] +@ CHECK: vldr s0, [lr] @ encoding: [0x00,0x0a,0x9e,0xed] +@ CHECK: vldr d0, [lr] @ encoding: [0x00,0x0b,0x9e,0xed] + vldr.64 d17, [r0] + vldr.i32 s0, [lr] + vldr.d d0, [lr] -@ CHECK: vldr.64 d1, [r2, #32] @ encoding: [0x08,0x1b,0x92,0xed] -@ CHECK: vldr.64 d1, [r2, #-32] @ encoding: [0x08,0x1b,0x12,0xed] +@ CHECK: vldr d1, [r2, #32] @ encoding: [0x08,0x1b,0x92,0xed] +@ CHECK: vldr d1, [r2, #-32] @ encoding: [0x08,0x1b,0x12,0xed] vldr.64 d1, [r2, #32] - vldr.64 d1, [r2, #-32] + vldr.f64 d1, [r2, #-32] -@ CHECK: vldr.64 d2, [r3] @ encoding: [0x00,0x2b,0x93,0xed] +@ CHECK: vldr d2, [r3] @ encoding: [0x00,0x2b,0x93,0xed] vldr.64 d2, [r3] -@ CHECK: vldr.64 d3, [pc] @ encoding: [0x00,0x3b,0x9f,0xed] -@ CHECK: vldr.64 d3, [pc] @ encoding: [0x00,0x3b,0x9f,0xed] -@ CHECK: vldr.64 d3, [pc, #-0] @ encoding: [0x00,0x3b,0x1f,0xed] +@ CHECK: vldr d3, [pc] @ encoding: [0x00,0x3b,0x9f,0xed] +@ CHECK: vldr d3, [pc] @ encoding: [0x00,0x3b,0x9f,0xed] +@ CHECK: vldr d3, [pc, #-0] @ encoding: [0x00,0x3b,0x1f,0xed] vldr.64 d3, [pc] vldr.64 d3, [pc,#0] vldr.64 d3, [pc,#-0] -@ CHECK: vldr.32 s13, [r0] @ encoding: [0x00,0x6a,0xd0,0xed] +@ CHECK: vldr s13, [r0] @ encoding: [0x00,0x6a,0xd0,0xed] vldr.32 s13, [r0] -@ CHECK: vldr.32 s1, [r2, #32] @ encoding: [0x08,0x0a,0xd2,0xed] -@ CHECK: vldr.32 s1, [r2, #-32] @ encoding: [0x08,0x0a,0x52,0xed] +@ CHECK: vldr s1, [r2, #32] @ encoding: [0x08,0x0a,0xd2,0xed] +@ CHECK: vldr s1, [r2, #-32] @ encoding: [0x08,0x0a,0x52,0xed] vldr.32 s1, [r2, #32] vldr.32 s1, [r2, #-32] -@ CHECK: vldr.32 s2, [r3] @ encoding: [0x00,0x1a,0x93,0xed] +@ CHECK: vldr s2, [r3] @ encoding: [0x00,0x1a,0x93,0xed] vldr.32 s2, [r3] -@ CHECK: vldr.32 s5, [pc] @ encoding: [0x00,0x2a,0xdf,0xed] -@ CHECK: vldr.32 s5, [pc] @ encoding: [0x00,0x2a,0xdf,0xed] -@ CHECK: vldr.32 s5, [pc, #-0] @ encoding: [0x00,0x2a,0x5f,0xed] +@ CHECK: vldr s5, [pc] @ encoding: [0x00,0x2a,0xdf,0xed] +@ CHECK: vldr s5, [pc] @ encoding: [0x00,0x2a,0xdf,0xed] +@ CHECK: vldr s5, [pc, #-0] @ encoding: [0x00,0x2a,0x5f,0xed] vldr.32 s5, [pc] vldr.32 s5, [pc,#0] vldr.32 s5, [pc,#-0] -@ CHECK: vstr.64 d4, [r1] @ encoding: [0x00,0x4b,0x81,0xed] -@ CHECK: vstr.64 d4, [r1, #24] @ encoding: [0x06,0x4b,0x81,0xed] -@ CHECK: vstr.64 d4, [r1, #-24] @ encoding: [0x06,0x4b,0x01,0xed] +@ CHECK: vstr d4, [r1] @ encoding: [0x00,0x4b,0x81,0xed] +@ CHECK: vstr d4, [r1, #24] @ encoding: [0x06,0x4b,0x81,0xed] +@ CHECK: vstr d4, [r1, #-24] @ encoding: [0x06,0x4b,0x01,0xed] +@ CHECK: vstr s0, [lr] @ encoding: [0x00,0x0a,0x8e,0xed] +@ CHECK: vstr d0, [lr] @ encoding: [0x00,0x0b,0x8e,0xed] + vstr.64 d4, [r1] vstr.64 d4, [r1, #24] vstr.64 d4, [r1, #-24] + vstr s0, [lr] + vstr d0, [lr] -@ CHECK: vstr.32 s4, [r1] @ encoding: [0x00,0x2a,0x81,0xed] -@ CHECK: vstr.32 s4, [r1, #24] @ encoding: [0x06,0x2a,0x81,0xed] -@ CHECK: vstr.32 s4, [r1, #-24] @ encoding: [0x06,0x2a,0x01,0xed] +@ CHECK: vstr s4, [r1] @ encoding: [0x00,0x2a,0x81,0xed] +@ CHECK: vstr s4, [r1, #24] @ encoding: [0x06,0x2a,0x81,0xed] +@ CHECK: vstr s4, [r1, #-24] @ encoding: [0x06,0x2a,0x01,0xed] vstr.32 s4, [r1] vstr.32 s4, [r1, #24] vstr.32 s4, [r1, #-24] @@ -229,8 +266,10 @@ @ CHECK: vstmia r1, {d2, d3, d4, d5, d6, d7} @ encoding: [0x0c,0x2b,0x81,0xec] @ CHECK: vstmia r1, {s2, s3, s4, s5, s6, s7} @ encoding: [0x06,0x1a,0x81,0xec] +@ CHECK: vpush {d8, d9, d10, d11, d12, d13, d14, d15} @ encoding: [0x10,0x8b,0x2d,0xed] vstmia r1, {d2,d3-d6,d7} vstmia r1, {s2,s3-s6,s7} + vstmdb sp!, {q4-q7} @ CHECK: vcvtr.s32.f64 s0, d0 @ encoding: [0x40,0x0b,0xbd,0xee] @ CHECK: vcvtr.s32.f32 s0, s1 @ encoding: [0x60,0x0a,0xbd,0xee] @@ -243,3 +282,76 @@ @ CHECK: vmovne s25, s26, r2, r5 vmovne s25, s26, r2, r5 @ encoding: [0x39,0x2a,0x45,0x1c] + +@ VMOV w/ optional data type suffix. + vmov.32 s1, r8 + vmov.s16 s2, r4 + vmov.16 s3, r6 + vmov.u32 s4, r1 + vmov.p8 s5, r2 + vmov.8 s6, r3 + + vmov.32 r1, s8 + vmov.s16 r2, s4 + vmov.16 r3, s6 + vmov.u32 r4, s1 + vmov.p8 r5, s2 + vmov.8 r6, s3 + +@ CHECK: vmov s1, r8 @ encoding: [0x90,0x8a,0x00,0xee] +@ CHECK: vmov s2, r4 @ encoding: [0x10,0x4a,0x01,0xee] +@ CHECK: vmov s3, r6 @ encoding: [0x90,0x6a,0x01,0xee] +@ CHECK: vmov s4, r1 @ encoding: [0x10,0x1a,0x02,0xee] +@ CHECK: vmov s5, r2 @ encoding: [0x90,0x2a,0x02,0xee] +@ CHECK: vmov s6, r3 @ encoding: [0x10,0x3a,0x03,0xee] +@ CHECK: vmov r1, s8 @ encoding: [0x10,0x1a,0x14,0xee] +@ CHECK: vmov r2, s4 @ encoding: [0x10,0x2a,0x12,0xee] +@ CHECK: vmov r3, s6 @ encoding: [0x10,0x3a,0x13,0xee] +@ CHECK: vmov r4, s1 @ encoding: [0x90,0x4a,0x10,0xee] +@ CHECK: vmov r5, s2 @ encoding: [0x10,0x5a,0x11,0xee] +@ CHECK: vmov r6, s3 @ encoding: [0x90,0x6a,0x11,0xee] + + +@ VCVT (between floating-point and fixed-point) + vcvt.f32.u32 s0, s0, #20 + vcvt.f64.s32 d0, d0, #32 + vcvt.f32.u16 s0, s0, #1 + vcvt.f64.s16 d0, d0, #16 + vcvt.f32.s32 s1, s1, #20 + vcvt.f64.u32 d20, d20, #32 + vcvt.f32.s16 s17, s17, #1 + vcvt.f64.u16 d23, d23, #16 + vcvt.u32.f32 s12, s12, #20 + vcvt.s32.f64 d2, d2, #32 + vcvt.u16.f32 s28, s28, #1 + vcvt.s16.f64 d15, d15, #16 + vcvt.s32.f32 s1, s1, #20 + vcvt.u32.f64 d20, d20, #32 + vcvt.s16.f32 s17, s17, #1 + vcvt.u16.f64 d23, d23, #16 + +@ CHECK: vcvt.f32.u32 s0, s0, #20 @ encoding: [0xc6,0x0a,0xbb,0xee] +@ CHECK: vcvt.f64.s32 d0, d0, #32 @ encoding: [0xc0,0x0b,0xba,0xee] +@ CHECK: vcvt.f32.u16 s0, s0, #1 @ encoding: [0x67,0x0a,0xbb,0xee] +@ CHECK: vcvt.f64.s16 d0, d0, #16 @ encoding: [0x40,0x0b,0xba,0xee] +@ CHECK: vcvt.f32.s32 s1, s1, #20 @ encoding: [0xc6,0x0a,0xfa,0xee] +@ CHECK: vcvt.f64.u32 d20, d20, #32 @ encoding: [0xc0,0x4b,0xfb,0xee] +@ CHECK: vcvt.f32.s16 s17, s17, #1 @ encoding: [0x67,0x8a,0xfa,0xee] +@ CHECK: vcvt.f64.u16 d23, d23, #16 @ encoding: [0x40,0x7b,0xfb,0xee] + +@ CHECK: vcvt.u32.f32 s12, s12, #20 @ encoding: [0xc6,0x6a,0xbf,0xee] +@ CHECK: vcvt.s32.f64 d2, d2, #32 @ encoding: [0xc0,0x2b,0xbe,0xee] +@ CHECK: vcvt.u16.f32 s28, s28, #1 @ encoding: [0x67,0xea,0xbf,0xee] +@ CHECK: vcvt.s16.f64 d15, d15, #16 @ encoding: [0x40,0xfb,0xbe,0xee] +@ CHECK: vcvt.s32.f32 s1, s1, #20 @ encoding: [0xc6,0x0a,0xfe,0xee] +@ CHECK: vcvt.u32.f64 d20, d20, #32 @ encoding: [0xc0,0x4b,0xff,0xee] +@ CHECK: vcvt.s16.f32 s17, s17, #1 @ encoding: [0x67,0x8a,0xfe,0xee] +@ CHECK: vcvt.u16.f64 d23, d23, #16 @ encoding: [0x40,0x7b,0xff,0xee] + + +@ Use NEON to load some f32 immediates that don't fit the f8 representation. + vmov.f32 d4, #0.0 + vmov.f32 d4, #32.0 + +@ CHECK: vmov.i32 d4, #0x0 @ encoding: [0x10,0x40,0x80,0xf2] +@ CHECK: vmov.i32 d4, #0x42000000 @ encoding: [0x12,0x46,0x84,0xf2] diff --git a/test/MC/ARM/thumb-diagnostics.s b/test/MC/ARM/thumb-diagnostics.s index d02c27e..99d7e38 100644 --- a/test/MC/ARM/thumb-diagnostics.s +++ b/test/MC/ARM/thumb-diagnostics.s @@ -24,13 +24,9 @@ @ Out of range immediates for ASR instruction. asrs r2, r3, #33 - asrs r2, r3, #0 @ CHECK-ERRORS: error: invalid operand for instruction @ CHECK-ERRORS: asrs r2, r3, #33 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: error: invalid operand for instruction -@ CHECK-ERRORS: asrs r2, r3, #0 -@ CHECK-ERRORS: ^ @ Out of range immediates for BKPT instruction. bkpt #256 @@ -125,10 +121,10 @@ error: invalid operand for instruction add sp, #3 add sp, sp, #512 add r2, sp, #1024 -@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled @ CHECK-ERRORS: add sp, #-1 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled @ CHECK-ERRORS: add sp, #3 @ CHECK-ERRORS: ^ @ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/ARM/vfp4.s b/test/MC/ARM/vfp4.s new file mode 100644 index 0000000..cc87a38 --- /dev/null +++ b/test/MC/ARM/vfp4.s @@ -0,0 +1,50 @@ +@ RUN: llvm-mc < %s -triple armv7-unknown-unknown -show-encoding -mattr=+neon,+vfp4 | FileCheck %s --check-prefix=ARM +@ RUN: llvm-mc < %s -triple thumbv7-unknown-unknown -show-encoding -mattr=+neon,+vfp4 | FileCheck %s --check-prefix=THUMB + +@ ARM: vfma.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0xe2,0xee] +@ THUMB: vfma.f64 d16, d18, d17 @ encoding: [0xe2,0xee,0xa1,0x0b] +vfma.f64 d16, d18, d17 + +@ ARM: vfma.f32 s2, s4, s0 @ encoding: [0x00,0x1a,0xa2,0xee] +@ THUMB: vfma.f32 s2, s4, s0 @ encoding: [0xa2,0xee,0x00,0x1a] +vfma.f32 s2, s4, s0 + +@ ARM: vfma.f32 d16, d18, d17 @ encoding: [0xb1,0x0c,0x42,0xf2] +@ THUMB: vfma.f32 d16, d18, d17 @ encoding: [0x42,0xef,0xb1,0x0c] +vfma.f32 d16, d18, d17 + +@ ARM: vfma.f32 q2, q4, q0 @ encoding: [0x50,0x4c,0x08,0xf2] +@ THUMB: vfma.f32 q2, q4, q0 @ encoding: [0x08,0xef,0x50,0x4c] +vfma.f32 q2, q4, q0 + +@ ARM: vfnma.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0xd2,0xee] +@ THUMB: vfnma.f64 d16, d18, d17 @ encoding: [0xd2,0xee,0xe1,0x0b] +vfnma.f64 d16, d18, d17 + +@ ARM: vfnma.f32 s2, s4, s0 @ encoding: [0x40,0x1a,0x92,0xee] +@ THUMB: vfnma.f32 s2, s4, s0 @ encoding: [0x92,0xee,0x40,0x1a] +vfnma.f32 s2, s4, s0 + +@ ARM: vfms.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0xe2,0xee] +@ THUMB: vfms.f64 d16, d18, d17 @ encoding: [0xe2,0xee,0xe1,0x0b] +vfms.f64 d16, d18, d17 + +@ ARM: vfms.f32 s2, s4, s0 @ encoding: [0x40,0x1a,0xa2,0xee] +@ THUMB: vfms.f32 s2, s4, s0 @ encoding: [0xa2,0xee,0x40,0x1a] +vfms.f32 s2, s4, s0 + +@ ARM: vfms.f32 d16, d18, d17 @ encoding: [0xb1,0x0c,0x62,0xf2] +@ THUMB: vfms.f32 d16, d18, d17 @ encoding: [0x62,0xef,0xb1,0x0c] +vfms.f32 d16, d18, d17 + +@ ARM: vfms.f32 q2, q4, q0 @ encoding: [0x50,0x4c,0x28,0xf2] +@ THUMB: vfms.f32 q2, q4, q0 @ encoding: [0x28,0xef,0x50,0x4c] +vfms.f32 q2, q4, q0 + +@ ARM: vfnms.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0xd2,0xee] +@ THUMB: vfnms.f64 d16, d18, d17 @ encoding: [0xd2,0xee,0xa1,0x0b] +vfnms.f64 d16, d18, d17 + +@ ARM: vfnms.f32 s2, s4, s0 @ encoding: [0x00,0x1a,0x92,0xee] +@ THUMB: vfnms.f32 s2, s4, s0 @ encoding: [0x92,0xee,0x00,0x1a] +vfnms.f32 s2, s4, s0 diff --git a/test/MC/ARM/vpush-vpop.s b/test/MC/ARM/vpush-vpop.s index 1212c83..4fb4dec 100644 --- a/test/MC/ARM/vpush-vpop.s +++ b/test/MC/ARM/vpush-vpop.s @@ -7,6 +7,21 @@ foo: vpush {s8, s9, s10, s11, s12} vpop {d8, d9, d10, d11, d12} vpop {s8, s9, s10, s11, s12} +@ optional size suffix + vpush.s8 {d8, d9, d10, d11, d12} + vpush.16 {s8, s9, s10, s11, s12} + vpop.f32 {d8, d9, d10, d11, d12} + vpop.64 {s8, s9, s10, s11, s12} + +@ CHECK-THUMB: vpush {d8, d9, d10, d11, d12} @ encoding: [0x2d,0xed,0x0a,0x8b] +@ CHECK-THUMB: vpush {s8, s9, s10, s11, s12} @ encoding: [0x2d,0xed,0x05,0x4a] +@ CHECK-THUMB: vpop {d8, d9, d10, d11, d12} @ encoding: [0xbd,0xec,0x0a,0x8b] +@ CHECK-THUMB: vpop {s8, s9, s10, s11, s12} @ encoding: [0xbd,0xec,0x05,0x4a] + +@ CHECK-ARM: vpush {d8, d9, d10, d11, d12} @ encoding: [0x0a,0x8b,0x2d,0xed] +@ CHECK-ARM: vpush {s8, s9, s10, s11, s12} @ encoding: [0x05,0x4a,0x2d,0xed] +@ CHECK-ARM: vpop {d8, d9, d10, d11, d12} @ encoding: [0x0a,0x8b,0xbd,0xec] +@ CHECK-ARM: vpop {s8, s9, s10, s11, s12} @ encoding: [0x05,0x4a,0xbd,0xec] @ CHECK-THUMB: vpush {d8, d9, d10, d11, d12} @ encoding: [0x2d,0xed,0x0a,0x8b] @ CHECK-THUMB: vpush {s8, s9, s10, s11, s12} @ encoding: [0x2d,0xed,0x05,0x4a] diff --git a/test/MC/AsmParser/2011-09-06-NoNewline.s b/test/MC/AsmParser/2011-09-06-NoNewline.s deleted file mode 100644 index 33e1dbb..0000000 --- a/test/MC/AsmParser/2011-09-06-NoNewline.s +++ /dev/null @@ -1,7 +0,0 @@ -// RUN: llvm-mc -triple i386-unknown-unknown %s -movl %gs:8, %eax -// RUN: llvm-mc -triple i386-unknown-unknown %s -movl %gs:8, %eax -// RUN: llvm-mc -triple i386-unknown-unknown %s -movl %gs:8, %eax -
\ No newline at end of file diff --git a/test/MC/AsmParser/cfi-unfinished-frame.s b/test/MC/AsmParser/cfi-unfinished-frame.s new file mode 100644 index 0000000..1182d52 --- /dev/null +++ b/test/MC/AsmParser/cfi-unfinished-frame.s @@ -0,0 +1,5 @@ +// RUN: not llvm-mc -filetype=asm -triple x86_64-pc-linux-gnu %s -o %t 2>%t.out +// RUN: FileCheck -input-file=%t.out %s + +.cfi_startproc +// CHECK: Unfinished frame diff --git a/test/MC/AsmParser/dg.exp b/test/MC/AsmParser/dg.exp deleted file mode 100644 index a6d81da..0000000 --- a/test/MC/AsmParser/dg.exp +++ /dev/null @@ -1,5 +0,0 @@ -load_lib llvm.exp - -if { [llvm_supports_target X86] } { - RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{s}]] -} diff --git a/test/MC/AsmParser/directive_file-errors.s b/test/MC/AsmParser/directive_file-errors.s new file mode 100644 index 0000000..5ae2bbe --- /dev/null +++ b/test/MC/AsmParser/directive_file-errors.s @@ -0,0 +1,9 @@ +// RUN: not llvm-mc -g -triple i386-unknown-unknown %s 2> %t.err | FileCheck %s +// RUN: FileCheck --check-prefix=CHECK-ERRORS %s < %t.err +// Test for Bug 11740 + + .file "hello" + .file 1 "world" + +// CHECK: .file "hello" +// CHECK-ERRORS:6:9: error: input can't have .file dwarf directives when -g is used to generate dwarf debug info for assembly code diff --git a/test/MC/AsmParser/directive_file.s b/test/MC/AsmParser/directive_file.s index 3160d5c..121890e 100644 --- a/test/MC/AsmParser/directive_file.s +++ b/test/MC/AsmParser/directive_file.s @@ -2,7 +2,8 @@ .file "hello" .file 1 "world" + .file 2 "directory" "file" # CHECK: .file "hello" # CHECK: .file 1 "world" - +# CHECK: .file 2 "directory" "file" diff --git a/test/MC/AsmParser/directive_incbin.s b/test/MC/AsmParser/directive_incbin.s new file mode 100644 index 0000000..55f9c79 --- /dev/null +++ b/test/MC/AsmParser/directive_incbin.s @@ -0,0 +1,6 @@ +# RUN: llvm-mc -triple i386-unknown-unknown %s -I %p | FileCheck %s + +.data +.incbin "incbin_abcd" + +# CHECK: .ascii "abcd\n" diff --git a/test/MC/AsmParser/incbin_abcd b/test/MC/AsmParser/incbin_abcd new file mode 100644 index 0000000..acbe86c --- /dev/null +++ b/test/MC/AsmParser/incbin_abcd @@ -0,0 +1 @@ +abcd diff --git a/test/MC/AsmParser/lit.local.cfg b/test/MC/AsmParser/lit.local.cfg new file mode 100644 index 0000000..6c49f08 --- /dev/null +++ b/test/MC/AsmParser/lit.local.cfg @@ -0,0 +1,6 @@ +config.suffixes = ['.s'] + +targets = set(config.root.targets_to_build.split()) +if not 'X86' in targets: + config.unsupported = True + diff --git a/test/MC/AsmParser/macro-args.s b/test/MC/AsmParser/macro-args.s index 808b6eb..4b87899 100644 --- a/test/MC/AsmParser/macro-args.s +++ b/test/MC/AsmParser/macro-args.s @@ -8,3 +8,13 @@ GET is_sse, %eax // CHECK: movl is_sse@GOTOFF(%ebx), %eax + +.macro bar + .long $n +.endm + +bar 1, 2, 3 +bar + +// CHECK: .long 3 +// CHECK: .long 0 diff --git a/test/MC/AsmParser/pr11865.s b/test/MC/AsmParser/pr11865.s new file mode 100644 index 0000000..1c03e11 --- /dev/null +++ b/test/MC/AsmParser/pr11865.s @@ -0,0 +1,6 @@ +// RUN: llvm-mc -triple i386-unknown-unknown %s + +i: + .long g +g = h +h = i diff --git a/test/MC/AsmParser/variables-invalid.s b/test/MC/AsmParser/variables-invalid.s index 9656889..c466d42 100644 --- a/test/MC/AsmParser/variables-invalid.s +++ b/test/MC/AsmParser/variables-invalid.s @@ -2,7 +2,7 @@ // RUN: FileCheck --input-file %t %s .data -// CHECK: invalid assignment to 't0_v0' +// CHECK: Recursive use of 't0_v0' t0_v0 = t0_v0 + 1 t1_v1 = 1 @@ -13,5 +13,16 @@ t2_s0: t2_s0 = 2 t3_s0 = t2_s0 + 1 + .long t3_s0 // CHECK: invalid reassignment of non-absolute variable 't3_s0' t3_s0 = 1 + + +// CHECK: Recursive use of 't4_s2' + t4_s0 = t4_s1 + t4_s1 = t4_s2 + t4_s2 = t4_s0 + +// CHECK: Recursive use of 't5_s1' + t5_s0 = t5_s1 + 1 + t5_s1 = t5_s0 diff --git a/test/MC/COFF/dg.exp b/test/MC/COFF/dg.exp deleted file mode 100644 index d46d700..0000000 --- a/test/MC/COFF/dg.exp +++ /dev/null @@ -1,5 +0,0 @@ -load_lib llvm.exp - -if { [llvm_supports_target X86] } { - RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,s}]] -} diff --git a/test/MC/COFF/global_ctors.ll b/test/MC/COFF/global_ctors.ll new file mode 100644 index 0000000..4d6b1c7 --- /dev/null +++ b/test/MC/COFF/global_ctors.ll @@ -0,0 +1,28 @@ +; Test that global ctors are emitted into the proper COFF section for the +; target. Mingw uses .ctors, whereas MSVC uses .CRT$XC*. +; RUN: llc < %s -mtriple i686-pc-win32 | FileCheck %s --check-prefix WIN32 +; RUN: llc < %s -mtriple x86_64-pc-win32 | FileCheck %s --check-prefix WIN32 +; RUN: llc < %s -mtriple i686-pc-mingw32 | FileCheck %s --check-prefix MINGW32 +; RUN: llc < %s -mtriple x86_64-pc-mingw32 | FileCheck %s --check-prefix MINGW32 + +@.str = private unnamed_addr constant [13 x i8] c"constructing\00", align 1 +@.str2 = private unnamed_addr constant [5 x i8] c"main\00", align 1 + +@llvm.global_ctors = appending global [1 x { i32, void ()* }] [{ i32, void ()* } { i32 65535, void ()* @a_global_ctor }] + +declare i32 @puts(i8*) + +define void @a_global_ctor() nounwind { + %1 = call i32 @puts(i8* getelementptr inbounds ([13 x i8]* @.str, i32 0, i32 0)) + ret void +} + +define i32 @main() nounwind { + %1 = call i32 @puts(i8* getelementptr inbounds ([5 x i8]* @.str2, i32 0, i32 0)) + ret i32 0 +} + +; WIN32: .section .CRT$XCU,"r" +; WIN32: a_global_ctor +; MINGW32: .section .ctors,"w" +; MINGW32: a_global_ctor diff --git a/test/MC/COFF/lit.local.cfg b/test/MC/COFF/lit.local.cfg new file mode 100644 index 0000000..41a8434 --- /dev/null +++ b/test/MC/COFF/lit.local.cfg @@ -0,0 +1,6 @@ +config.suffixes = ['.s', '.ll'] + +targets = set(config.root.targets_to_build.split()) +if not 'X86' in targets: + config.unsupported = True + diff --git a/test/MC/COFF/secrel32.s b/test/MC/COFF/secrel32.s new file mode 100644 index 0000000..ce148db --- /dev/null +++ b/test/MC/COFF/secrel32.s @@ -0,0 +1,14 @@ +// RUN: llvm-mc -filetype=obj -triple i686-pc-win32 %s | coff-dump.py | FileCheck %s + +// check that we produce the correct relocation for .secrel32 + +Lfoo: + .secrel32 Lfoo + +// CHECK: Relocations = [ +// CHECK-NEXT: 0 = { +// CHECK-NEXT: VirtualAddress = 0x0 +// CHECK-NEXT: SymbolTableIndex = 0 +// CHECK-NEXT: Type = IMAGE_REL_I386_SECREL (11) +// CHECK-NEXT: SymbolName = .text +// CHECK-NEXT: } diff --git a/test/MC/COFF/symbol-mangling.ll b/test/MC/COFF/symbol-mangling.ll new file mode 100644 index 0000000..f1b4b4b --- /dev/null +++ b/test/MC/COFF/symbol-mangling.ll @@ -0,0 +1,17 @@ +; The purpose of this test is to see if the MC layer properly handles symbol +; names needing quoting on MS/Windows. This code is generated by clang when +; using -cxx-abi microsoft. + +; RUN: llc -filetype=asm -mtriple i686-pc-win32 %s -o - | FileCheck %s + +; CHECK: ?sayhi@A@@QBEXXZ + +%struct.A = type {} + +define i32 @main() { +entry: + tail call void @"\01?sayhi@A@@QBEXXZ"(%struct.A* null) + ret i32 0 +} + +declare void @"\01?sayhi@A@@QBEXXZ"(%struct.A*) diff --git a/test/MC/Disassembler/ARM/arm-tests.txt b/test/MC/Disassembler/ARM/arm-tests.txt index 69a094d..ce1446b 100644 --- a/test/MC/Disassembler/ARM/arm-tests.txt +++ b/test/MC/Disassembler/ARM/arm-tests.txt @@ -201,7 +201,7 @@ 0x20 0x51 0x17 0xe6 # CHECK: strdeq r2, r3, [r0], -r8 -0xf8 0x24 0x00 0x00 +0xf8 0x20 0x00 0x00 # CHECK: ldrdeq r2, r3, [r0], -r12 0xdc 0x24 0x00 0x00 @@ -215,7 +215,7 @@ # CHECK: vldmdb r2!, {s7, s8, s9, s10, s11} 0x05 0x3a 0x72 0xed -# CHECK: vldr.32 s23, [r2, #660] +# CHECK: vldr s23, [r2, #660] 0xa5 0xba 0xd2 0xed # CHECK: strtvc r5, [r3], r0, lsr #20 @@ -317,3 +317,7 @@ # CHECK: stc2l p0, c0, [r2], #-96 0x18 0x0 0x62 0xfc + +# CHECK: ldmgt sp!, {r9} +0x00 0x02 0xbd 0xc8 + diff --git a/test/MC/Disassembler/ARM/dg.exp b/test/MC/Disassembler/ARM/dg.exp deleted file mode 100644 index fc2f17a..0000000 --- a/test/MC/Disassembler/ARM/dg.exp +++ /dev/null @@ -1,6 +0,0 @@ -load_lib llvm.exp - -if { [llvm_supports_target ARM] } { - RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{txt}]] -} - diff --git a/test/MC/Disassembler/ARM/fp-encoding.txt b/test/MC/Disassembler/ARM/fp-encoding.txt index f3e0261..9095b84 100644 --- a/test/MC/Disassembler/ARM/fp-encoding.txt +++ b/test/MC/Disassembler/ARM/fp-encoding.txt @@ -152,46 +152,46 @@ # CHECK: vmov r0, r1, d16 0x00 0x1b 0xd0 0xed -# CHECK: vldr.64 d17, [r0] +# CHECK: vldr d17, [r0] 0x08 0x1b 0x92 0xed 0x08 0x1b 0x12 0xed -# CHECK: vldr.64 d1, [r2, #32] -# CHECK: vldr.64 d1, [r2, #-32] +# CHECK: vldr d1, [r2, #32] +# CHECK: vldr d1, [r2, #-32] 0x00 0x2b 0x93 0xed -# CHECK: vldr.64 d2, [r3] +# CHECK: vldr d2, [r3] 0x00 0x3b 0x9f 0xed -# CHECK: vldr.64 d3, [pc] +# CHECK: vldr d3, [pc] 0x00 0x6a 0xd0 0xed -# CHECK: vldr.32 s13, [r0] +# CHECK: vldr s13, [r0] 0x08 0x0a 0xd2 0xed 0x08 0x0a 0x52 0xed -# CHECK: vldr.32 s1, [r2, #32] -# CHECK: vldr.32 s1, [r2, #-32] +# CHECK: vldr s1, [r2, #32] +# CHECK: vldr s1, [r2, #-32] 0x00 0x1a 0x93 0xed -# CHECK: vldr.32 s2, [r3] +# CHECK: vldr s2, [r3] 0x00 0x2a 0xdf 0xed -# CHECK: vldr.32 s5, [pc] +# CHECK: vldr s5, [pc] 0x00 0x4b 0x81 0xed 0x06 0x4b 0x81 0xed 0x06 0x4b 0x01 0xed -# CHECK: vstr.64 d4, [r1] -# CHECK: vstr.64 d4, [r1, #24] -# CHECK: vstr.64 d4, [r1, #-24] +# CHECK: vstr d4, [r1] +# CHECK: vstr d4, [r1, #24] +# CHECK: vstr d4, [r1, #-24] 0x00 0x2a 0x81 0xed 0x06 0x2a 0x81 0xed 0x06 0x2a 0x01 0xed -# CHECK: vstr.32 s4, [r1] -# CHECK: vstr.32 s4, [r1, #24] -# CHECK: vstr.32 s4, [r1, #-24] +# CHECK: vstr s4, [r1] +# CHECK: vstr s4, [r1, #24] +# CHECK: vstr s4, [r1, #-24] 0x0c 0x2b 0x91 0xec 0x06 0x1a 0x91 0xec diff --git a/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt b/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt index 6fdb55e..8146b5c 100644 --- a/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt @@ -1,4 +1,4 @@ # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {potentially undefined instruction encoding} # invalid (imod, M, iflags) combination -0x93 0x1c 0x02 0xf1 +0x93 0x00 0x02 0xf1 diff --git a/test/MC/Disassembler/ARM/invalid-IT-CC15.txt b/test/MC/Disassembler/ARM/invalid-IT-CC15.txt new file mode 100644 index 0000000..17e25ea --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-IT-CC15.txt @@ -0,0 +1,18 @@ +# RUN: llvm-mc --disassemble %s -triple=thumbv7-unknown-unknown |& grep und +# rdar://10841671 + +0xe3 0xbf +0xdf 0xed 0x61 0x3b +0x71 0xee 0xe0 0x1b +0x72 0xee 0xa3 0x2b +0xdf 0xed 0x60 0x0b + +# This is test is dealing with a undefined condition code value of 15 in the +# above sequence of junk bytes and not allowing the disassembler to abort on +# printing the final instruction in this list. +# +# ittte al +# vldr d19, [pc, #388] +# vsub.f64 d17, d17, d16 +# vadd.f64 d18, d18, d19 +# vldr<und> d16, [pc, #384] diff --git a/test/MC/Disassembler/ARM/invalid-LDRT-arm.txt b/test/MC/Disassembler/ARM/invalid-LDRT-arm.txt deleted file mode 100644 index 067dcb3..0000000 --- a/test/MC/Disassembler/ARM/invalid-LDRT-arm.txt +++ /dev/null @@ -1,12 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} - -# Opcode=0 Name=PHI Format=(42) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 0| 0: 1: 1: 0| 0: 0: 1: 1| 0: 1: 1: 1| 0: 1: 0: 1| 0: 0: 0: 1| 0: 0: 0: 1| 0: 0: 0: 0| -# ------------------------------------------------------------------------------------------------- -# -# The bytes have Inst{4} = 1, so it's not an LDRT Encoding A2 instruction. -0x10 0x51 0x37 0xe6 - - diff --git a/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt b/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt new file mode 100644 index 0000000..8ff3a2b --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt @@ -0,0 +1,13 @@ +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=1839 Name=VST1d8Twb_register Format=ARM_FORMAT_NLdSt(30) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 1: 0: 0: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 1: 1: 0| 0: 0: 1: 0| 1: 1: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# A8.6.391 VST1 (multiple single elements) +# This encoding looks like: vst1.8 {d0,d1,d2}, [r0, :128] +# But bits 5-4 for the alignment of 128 encoded as align = 0b10, is available only if <list> +# contains two or four registers. rdar://11220250 +0x00 0xf9 0x2f 0x06 diff --git a/test/MC/Disassembler/ARM/ldrd-armv4.txt b/test/MC/Disassembler/ARM/ldrd-armv4.txt new file mode 100644 index 0000000..bb87ade --- /dev/null +++ b/test/MC/Disassembler/ARM/ldrd-armv4.txt @@ -0,0 +1,15 @@ +# RUN: llvm-mc --disassemble %s -triple=armv4-linux-gnueabi |& FileCheck %s -check-prefix=V4 +# RUN: llvm-mc --disassemble %s -triple=armv5te-linux-gnueabi |& FileCheck %s -check-prefix=V5TE + +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| X: X: X: 1| X: X: X: X| 1: 1: X: 1| X: X: X: X| +# ------------------------------------------------------------------------------------------------- +# +# A8.6.68 LDRD (register) +# if Rt{0} = 1 then UNDEFINED; + +# V4: invalid instruction encoding +# V5TE: ldrd +0xd0 0x10 0x00 0x01 + diff --git a/test/MC/Disassembler/ARM/lit.local.cfg b/test/MC/Disassembler/ARM/lit.local.cfg new file mode 100644 index 0000000..22a76e5 --- /dev/null +++ b/test/MC/Disassembler/ARM/lit.local.cfg @@ -0,0 +1,6 @@ +config.suffixes = ['.txt'] + +targets = set(config.root.targets_to_build.split()) +if not 'ARM' in targets: + config.unsupported = True + diff --git a/test/MC/Disassembler/ARM/neon-tests.txt b/test/MC/Disassembler/ARM/neon-tests.txt index 1e03deb..f44c2a0 100644 --- a/test/MC/Disassembler/ARM/neon-tests.txt +++ b/test/MC/Disassembler/ARM/neon-tests.txt @@ -30,7 +30,7 @@ # CHECK: vorr d0, d15, d15 0x1f 0x01 0x2f 0xf2 -# CHECK: vmov.i64 q6, #0xFF00FF00FF +# CHECK: vmov.i64 q6, #0xff00ff00ff 0x75 0xce 0x81 0xf2 # CHECK: vmvn.i32 d0, #0x0 @@ -69,10 +69,10 @@ # CHECK: vpop {d8} 0x02 0x8b 0xbd 0xec -# CHECK: vorr.i32 q15, #0x4F0000 +# CHECK: vorr.i32 q15, #0x4f0000 0x5f 0xe5 0xc4 0xf2 -# CHECK: vbic.i32 q2, #0xA900 +# CHECK: vbic.i32 q2, #0xa900 0x79 0x43 0x82 0xf3 # CHECK: vst2.32 {d16, d18}, [r2, :64], r2 diff --git a/test/MC/Disassembler/ARM/neon.txt b/test/MC/Disassembler/ARM/neon.txt index 5d2df93..58fe20e 100644 --- a/test/MC/Disassembler/ARM/neon.txt +++ b/test/MC/Disassembler/ARM/neon.txt @@ -307,9 +307,9 @@ 0xf2 0x01 0x50 0xf2 # CHECK: vbic q8, q8, q9 0x3f 0x07 0xc7 0xf3 -# CHECK: vbic.i32 d16, #0xFF000000 +# CHECK: vbic.i32 d16, #0xff000000 0x7f 0x07 0xc7 0xf3 -# CHECK: vbic.i32 q8, #0xFF000000 +# CHECK: vbic.i32 q8, #0xff000000 0xb0 0x01 0x71 0xf2 # CHECK: vorn d16, d17, d16 @@ -587,11 +587,11 @@ 0x10 0x06 0xc2 0xf2 # CHECK: vmov.i32 d16, #0x20000000 0x10 0x0c 0xc2 0xf2 -# CHECK: vmov.i32 d16, #0x20FF +# CHECK: vmov.i32 d16, #0x20ff 0x10 0x0d 0xc2 0xf2 -# CHECK: vmov.i32 d16, #0x20FFFF +# CHECK: vmov.i32 d16, #0x20ffff 0x33 0x0e 0xc1 0xf3 -# CHECK: vmov.i64 d16, #0xFF0000FF0000FFFF +# CHECK: vmov.i64 d16, #0xff0000ff0000ffff 0x58 0x0e 0xc0 0xf2 # CHECK: vmov.i8 q8, #0x8 0x50 0x08 0xc1 0xf2 @@ -607,11 +607,11 @@ 0x50 0x06 0xc2 0xf2 # CHECK: vmov.i32 q8, #0x20000000 0x50 0x0c 0xc2 0xf2 -# CHECK: vmov.i32 q8, #0x20FF +# CHECK: vmov.i32 q8, #0x20ff 0x50 0x0d 0xc2 0xf2 -# CHECK: vmov.i32 q8, #0x20FFFF +# CHECK: vmov.i32 q8, #0x20ffff 0x73 0x0e 0xc1 0xf3 -# CHECK: vmov.i64 q8, #0xFF0000FF0000FFFF +# CHECK: vmov.i64 q8, #0xff0000ff0000ffff 0x30 0x08 0xc1 0xf2 # CHECK: vmvn.i16 d16, #0x10 0x30 0x0a 0xc1 0xf2 @@ -625,9 +625,9 @@ 0x30 0x06 0xc2 0xf2 # CHECK: vmvn.i32 d16, #0x20000000 0x30 0x0c 0xc2 0xf2 -# CHECK: vmvn.i32 d16, #0x20FF +# CHECK: vmvn.i32 d16, #0x20ff 0x30 0x0d 0xc2 0xf2 -# CHECK: vmvn.i32 d16, #0x20FFFF +# CHECK: vmvn.i32 d16, #0x20ffff 0x30 0x0a 0xc8 0xf2 # CHECK: vmovl.s8 q8, d16 0x30 0x0a 0xd0 0xf2 @@ -1856,3 +1856,390 @@ 0xe9 0x1a 0xb2 0x4e # CHECK: vcvttmi.f32.f16 s2, s19 + +0x1d 0x76 0x66 0xf4 +# CHECK: vld1.8 {d23, d24, d25}, [r6, :64]! +0x9d 0x62 0x6f 0xf4 +# CHECK: vld1.32 {d22, d23, d24, d25}, [pc, :64]! +0x9d 0xaa 0x41 0xf4 +# CHECK: vst1.32 {d26, d27}, [r1, :64]! + +0x10 0x0f 0x83 0xf2 +0x50 0x0f 0x83 0xf2 +# CHECK: vmov.f32 d0, #1.600000e+01 +# CHECK: vmov.f32 q0, #1.600000e+01 + +# rdar://10798451 +0xe7 0xf9 0x32 0x1d +# CHECK vld2.8 {d17[], d19[]}, [r7, :16], r2 +0xe7 0xf9 0x3d 0x1d +# CHECK vld2.8 {d17[], d19[]}, [r7, :16]! +0xe7 0xf9 0x3f 0x1d +# CHECK vld2.8 {d17[], d19[]}, [r7, :16] + +# rdar://11034702 +0x0d 0x87 0x04 0xf4 +# CHECK: vst1.8 {d8}, [r4]! +0x4d 0x87 0x04 0xf4 +# CHECK: vst1.16 {d8}, [r4]! +0x8d 0x87 0x04 0xf4 +# CHECK: vst1.32 {d8}, [r4]! +0xcd 0x87 0x04 0xf4 +# CHECK: vst1.64 {d8}, [r4]! +0x06 0x87 0x04 0xf4 +# CHECK: vst1.8 {d8}, [r4], r6 +0x46 0x87 0x04 0xf4 +# CHECK: vst1.16 {d8}, [r4], r6 +0x86 0x87 0x04 0xf4 +# CHECK: vst1.32 {d8}, [r4], r6 +0xc6 0x87 0x04 0xf4 +# CHECK: vst1.64 {d8}, [r4], r6 + +0x0d 0x8a 0x04 0xf4 +# CHECK: vst1.8 {d8, d9}, [r4]! +0x4d 0x8a 0x04 0xf4 +# CHECK: vst1.16 {d8, d9}, [r4]! +0x8d 0x8a 0x04 0xf4 +# CHECK: vst1.32 {d8, d9}, [r4]! +0xcd 0x8a 0x04 0xf4 +# CHECK: vst1.64 {d8, d9}, [r4]! +0x06 0x8a 0x04 0xf4 +# CHECK: vst1.8 {d8, d9}, [r4], r6 +0x46 0x8a 0x04 0xf4 +# CHECK: vst1.16 {d8, d9}, [r4], r6 +0x86 0x8a 0x04 0xf4 +# CHECK: vst1.32 {d8, d9}, [r4], r6 +0xc6 0x8a 0x04 0xf4 +# CHECK: vst1.64 {d8, d9}, [r4], r6 + +0x0d 0x86 0x04 0xf4 +# CHECK: vst1.8 {d8, d9, d10}, [r4]! +0x4d 0x86 0x04 0xf4 +# CHECK: vst1.16 {d8, d9, d10}, [r4]! +0x8d 0x86 0x04 0xf4 +# CHECK: vst1.32 {d8, d9, d10}, [r4]! +0xcd 0x86 0x04 0xf4 +# CHECK: vst1.64 {d8, d9, d10}, [r4]! +0x06 0x86 0x04 0xf4 +# CHECK: vst1.8 {d8, d9, d10}, [r4], r6 +0x46 0x86 0x04 0xf4 +# CHECK: vst1.16 {d8, d9, d10}, [r4], r6 +0x86 0x86 0x04 0xf4 +# CHECK: vst1.32 {d8, d9, d10}, [r4], r6 +0xc6 0x86 0x04 0xf4 +# CHECK: vst1.64 {d8, d9, d10}, [r4], r6 + +0x0d 0x82 0x04 0xf4 +# CHECK: vst1.8 {d8, d9, d10, d11}, [r4]! +0x4d 0x82 0x04 0xf4 +# CHECK: vst1.16 {d8, d9, d10, d11}, [r4]! +0x8d 0x82 0x04 0xf4 +# CHECK: vst1.32 {d8, d9, d10, d11}, [r4]! +0xcd 0x82 0x04 0xf4 +# CHECK: vst1.64 {d8, d9, d10, d11}, [r4]! +0x06 0x82 0x04 0xf4 +# CHECK: vst1.8 {d8, d9, d10, d11}, [r4], r6 +0x46 0x82 0x04 0xf4 +# CHECK: vst1.16 {d8, d9, d10, d11}, [r4], r6 +0x86 0x82 0x04 0xf4 +# CHECK: vst1.32 {d8, d9, d10, d11}, [r4], r6 +0xc6 0x82 0x04 0xf4 +# CHECK: vst1.64 {d8, d9, d10, d11}, [r4], r6 + +0x0d 0x88 0x04 0xf4 +# CHECK: vst2.8 {d8, d9}, [r4]! +0x4d 0x88 0x04 0xf4 +# CHECK: vst2.16 {d8, d9}, [r4]! +0x8d 0x88 0x04 0xf4 +# CHECK: vst2.32 {d8, d9}, [r4]! +0x06 0x88 0x04 0xf4 +# CHECK: vst2.8 {d8, d9}, [r4], r6 +0x46 0x88 0x04 0xf4 +# CHECK: vst2.16 {d8, d9}, [r4], r6 +0x86 0x88 0x04 0xf4 +# CHECK: vst2.32 {d8, d9}, [r4], r6 + +0x0d 0x89 0x04 0xf4 +# CHECK: vst2.8 {d8, d10}, [r4]! +0x4d 0x89 0x04 0xf4 +# CHECK: vst2.16 {d8, d10}, [r4]! +0x8d 0x89 0x04 0xf4 +# CHECK: vst2.32 {d8, d10}, [r4]! +0x06 0x89 0x04 0xf4 +# CHECK: vst2.8 {d8, d10}, [r4], r6 +0x46 0x89 0x04 0xf4 +# CHECK: vst2.16 {d8, d10}, [r4], r6 +0x86 0x89 0x04 0xf4 +# CHECK: vst2.32 {d8, d10}, [r4], r6 + +0x0d 0x84 0x04 0xf4 +# CHECK: vst3.8 {d8, d9, d10}, [r4]! +0x4d 0x84 0x04 0xf4 +# CHECK: vst3.16 {d8, d9, d10}, [r4]! +0x8d 0x84 0x04 0xf4 +# CHECK: vst3.32 {d8, d9, d10}, [r4]! +0x06 0x85 0x04 0xf4 +# CHECK: vst3.8 {d8, d10, d12}, [r4], r6 +0x46 0x85 0x04 0xf4 +# CHECK: vst3.16 {d8, d10, d12}, [r4], r6 +0x86 0x85 0x04 0xf4 +# CHECK: vst3.32 {d8, d10, d12}, [r4], r6 + +0x0d 0x80 0x04 0xf4 +# CHECK: vst4.8 {d8, d9, d10, d11}, [r4]! +0x4d 0x80 0x04 0xf4 +# CHECK: vst4.16 {d8, d9, d10, d11}, [r4]! +0x8d 0x80 0x04 0xf4 +# CHECK: vst4.32 {d8, d9, d10, d11}, [r4]! +0x06 0x81 0x04 0xf4 +# CHECK: vst4.8 {d8, d10, d12, d14}, [r4], r6 +0x46 0x81 0x04 0xf4 +# CHECK: vst4.16 {d8, d10, d12, d14}, [r4], r6 +0x86 0x81 0x04 0xf4 +# CHECK: vst4.32 {d8, d10, d12, d14}, [r4], r6 + +0x4f 0x8a 0x04 0xf4 +# CHECK: vst1.16 {d8, d9}, [r4] +0x8f 0x8a 0x04 0xf4 +# CHECK: vst1.32 {d8, d9}, [r4] +0xcf 0x8a 0x04 0xf4 +# CHECK: vst1.64 {d8, d9}, [r4] +0x0f 0x8a 0x04 0xf4 +# CHECK: vst1.8 {d8, d9}, [r4] + +0x4f 0x88 0x04 0xf4 +# CHECK: vst2.16 {d8, d9}, [r4] +0x8f 0x88 0x04 0xf4 +# CHECK: vst2.32 {d8, d9}, [r4] +0x0f 0x88 0x04 0xf4 +# CHECK: vst2.8 {d8, d9}, [r4] + +0x4d 0x88 0x04 0xf4 +# CHECK: vst2.16 {d8, d9}, [r4]! +0x46 0x88 0x04 0xf4 +# CHECK: vst2.16 {d8, d9}, [r4], r6 +0x8d 0x88 0x04 0xf4 +# CHECK: vst2.32 {d8, d9}, [r4]! +0x86 0x88 0x04 0xf4 +# CHECK: vst2.32 {d8, d9}, [r4], r6 +0x0d 0x88 0x04 0xf4 +# CHECK: vst2.8 {d8, d9}, [r4]! +0x06 0x88 0x04 0xf4 +# CHECK: vst2.8 {d8, d9}, [r4], r6 + +0x4f 0x89 0x04 0xf4 +# CHECK: vst2.16 {d8, d10}, [r4] +0x8f 0x89 0x04 0xf4 +# CHECK: vst2.32 {d8, d10}, [r4] +0x0f 0x89 0x04 0xf4 +# CHECK: vst2.8 {d8, d10}, [r4] + +0x0f 0x84 0x04 0xf4 +# CHECK: vst3.8 {d8, d9, d10}, [r4] +0x4f 0x84 0x04 0xf4 +# CHECK: vst3.16 {d8, d9, d10}, [r4] +0x8f 0x84 0x04 0xf4 +# CHECK: vst3.32 {d8, d9, d10}, [r4] + +0x0f 0x80 0x04 0xf4 +# CHECK: vst4.8 {d8, d9, d10, d11}, [r4] +0x4f 0x80 0x04 0xf4 +# CHECK: vst4.16 {d8, d9, d10, d11}, [r4] +0x8f 0x80 0x04 0xf4 +# CHECK: vst4.32 {d8, d9, d10, d11}, [r4] + +0x0f 0x85 0x04 0xf4 +# CHECK: vst3.8 {d8, d10, d12}, [r4] +0x4f 0x85 0x04 0xf4 +# CHECK: vst3.16 {d8, d10, d12}, [r4] +0x8f 0x85 0x04 0xf4 +# CHECK: vst3.32 {d8, d10, d12}, [r4] + +0x0f 0x81 0x04 0xf4 +# CHECK: vst4.8 {d8, d10, d12, d14}, [r4] +0x4f 0x81 0x04 0xf4 +# CHECK: vst4.16 {d8, d10, d12, d14}, [r4] +0x8f 0x81 0x04 0xf4 +# CHECK: vst4.32 {d8, d10, d12, d14}, [r4] + +# rdar://11204059 +0x0d 0x87 0x24 0xf4 +# CHECK: vld1.8 {d8}, [r4]! +0x4d 0x87 0x24 0xf4 +# CHECK: vld1.16 {d8}, [r4]! +0x8d 0x87 0x24 0xf4 +# CHECK: vld1.32 {d8}, [r4]! +0xcd 0x87 0x24 0xf4 +# CHECK: vld1.64 {d8}, [r4]! +0x06 0x87 0x24 0xf4 +# CHECK: vld1.8 {d8}, [r4], r6 +0x46 0x87 0x24 0xf4 +# CHECK: vld1.16 {d8}, [r4], r6 +0x86 0x87 0x24 0xf4 +# CHECK: vld1.32 {d8}, [r4], r6 +0xc6 0x87 0x24 0xf4 +# CHECK: vld1.64 {d8}, [r4], r6 +0x0d 0x8a 0x24 0xf4 +# CHECK: vld1.8 {d8, d9}, [r4]! +0x4d 0x8a 0x24 0xf4 +# CHECK: vld1.16 {d8, d9}, [r4]! +0x8d 0x8a 0x24 0xf4 +# CHECK: vld1.32 {d8, d9}, [r4]! +0xcd 0x8a 0x24 0xf4 +# CHECK: vld1.64 {d8, d9}, [r4]! +0x06 0x8a 0x24 0xf4 +# CHECK: vld1.8 {d8, d9}, [r4], r6 +0x46 0x8a 0x24 0xf4 +# CHECK: vld1.16 {d8, d9}, [r4], r6 +0x86 0x8a 0x24 0xf4 +# CHECK: vld1.32 {d8, d9}, [r4], r6 +0xc6 0x8a 0x24 0xf4 +# CHECK: vld1.64 {d8, d9}, [r4], r6 +0x0d 0x86 0x24 0xf4 +# CHECK: vld1.8 {d8, d9, d10}, [r4]! +0x4d 0x86 0x24 0xf4 +# CHECK: vld1.16 {d8, d9, d10}, [r4]! +0x8d 0x86 0x24 0xf4 +# CHECK: vld1.32 {d8, d9, d10}, [r4]! +0xcd 0x86 0x24 0xf4 +# CHECK: vld1.64 {d8, d9, d10}, [r4]! +0x06 0x86 0x24 0xf4 +# CHECK: vld1.8 {d8, d9, d10}, [r4], r6 +0x46 0x86 0x24 0xf4 +# CHECK: vld1.16 {d8, d9, d10}, [r4], r6 +0x86 0x86 0x24 0xf4 +# CHECK: vld1.32 {d8, d9, d10}, [r4], r6 +0xc6 0x86 0x24 0xf4 +# CHECK: vld1.64 {d8, d9, d10}, [r4], r6 +0x0d 0x82 0x24 0xf4 +# CHECK: vld1.8 {d8, d9, d10, d11}, [r4]! +0x4d 0x82 0x24 0xf4 +# CHECK: vld1.16 {d8, d9, d10, d11}, [r4]! +0x8d 0x82 0x24 0xf4 +# CHECK: vld1.32 {d8, d9, d10, d11}, [r4]! +0xcd 0x82 0x24 0xf4 +# CHECK: vld1.64 {d8, d9, d10, d11}, [r4]! +0x06 0x82 0x24 0xf4 +# CHECK: vld1.8 {d8, d9, d10, d11}, [r4], r6 +0x46 0x82 0x24 0xf4 +# CHECK: vld1.16 {d8, d9, d10, d11}, [r4], r6 +0x86 0x82 0x24 0xf4 +# CHECK: vld1.32 {d8, d9, d10, d11}, [r4], r6 +0xc6 0x82 0x24 0xf4 +# CHECK: vld1.64 {d8, d9, d10, d11}, [r4], r6 +0x0d 0x88 0x24 0xf4 +# CHECK: vld2.8 {d8, d9}, [r4]! +0x4d 0x88 0x24 0xf4 +# CHECK: vld2.16 {d8, d9}, [r4]! +0x8d 0x88 0x24 0xf4 +# CHECK: vld2.32 {d8, d9}, [r4]! +0x06 0x88 0x24 0xf4 +# CHECK: vld2.8 {d8, d9}, [r4], r6 +0x46 0x88 0x24 0xf4 +# CHECK: vld2.16 {d8, d9}, [r4], r6 +0x86 0x88 0x24 0xf4 +# CHECK: vld2.32 {d8, d9}, [r4], r6 +0x0d 0x89 0x24 0xf4 +# CHECK: vld2.8 {d8, d10}, [r4]! +0x4d 0x89 0x24 0xf4 +# CHECK: vld2.16 {d8, d10}, [r4]! +0x8d 0x89 0x24 0xf4 +# CHECK: vld2.32 {d8, d10}, [r4]! +0x06 0x89 0x24 0xf4 +# CHECK: vld2.8 {d8, d10}, [r4], r6 +0x46 0x89 0x24 0xf4 +# CHECK: vld2.16 {d8, d10}, [r4], r6 +0x86 0x89 0x24 0xf4 +# CHECK: vld2.32 {d8, d10}, [r4], r6 +0x0d 0x84 0x24 0xf4 +# CHECK: vld3.8 {d8, d9, d10}, [r4]! +0x4d 0x84 0x24 0xf4 +# CHECK: vld3.16 {d8, d9, d10}, [r4]! +0x8d 0x84 0x24 0xf4 +# CHECK: vld3.32 {d8, d9, d10}, [r4]! +0x06 0x85 0x24 0xf4 +# CHECK: vld3.8 {d8, d10, d12}, [r4], r6 +0x46 0x85 0x24 0xf4 +# CHECK: vld3.16 {d8, d10, d12}, [r4], r6 +0x86 0x85 0x24 0xf4 +# CHECK: vld3.32 {d8, d10, d12}, [r4], r6 +0x0d 0x80 0x24 0xf4 +# CHECK: vld4.8 {d8, d9, d10, d11}, [r4]! +0x4d 0x80 0x24 0xf4 +# CHECK: vld4.16 {d8, d9, d10, d11}, [r4]! +0x8d 0x80 0x24 0xf4 +# CHECK: vld4.32 {d8, d9, d10, d11}, [r4]! +0x06 0x81 0x24 0xf4 +# CHECK: vld4.8 {d8, d10, d12, d14}, [r4], r6 +0x46 0x81 0x24 0xf4 +# CHECK: vld4.16 {d8, d10, d12, d14}, [r4], r6 +0x86 0x81 0x24 0xf4 +# CHECK: vld4.32 {d8, d10, d12, d14}, [r4], r6 +0x4f 0x8a 0x24 0xf4 +# CHECK: vld1.16 {d8, d9}, [r4] +0x8f 0x8a 0x24 0xf4 +# CHECK: vld1.32 {d8, d9}, [r4] +0xcf 0x8a 0x24 0xf4 +# CHECK: vld1.64 {d8, d9}, [r4] +0x0f 0x8a 0x24 0xf4 +# CHECK: vld1.8 {d8, d9}, [r4] +0x4f 0x88 0x24 0xf4 +# CHECK: vld2.16 {d8, d9}, [r4] +0x8f 0x88 0x24 0xf4 +# CHECK: vld2.32 {d8, d9}, [r4] +0x0f 0x88 0x24 0xf4 +# CHECK: vld2.8 {d8, d9}, [r4] +0x4d 0x88 0x24 0xf4 +# CHECK: vld2.16 {d8, d9}, [r4]! +0x46 0x88 0x24 0xf4 +# CHECK: vld2.16 {d8, d9}, [r4], r6 +0x8d 0x88 0x24 0xf4 +# CHECK: vld2.32 {d8, d9}, [r4]! +0x86 0x88 0x24 0xf4 +# CHECK: vld2.32 {d8, d9}, [r4], r6 +0x0d 0x88 0x24 0xf4 +# CHECK: vld2.8 {d8, d9}, [r4]! +0x06 0x88 0x24 0xf4 +# CHECK: vld2.8 {d8, d9}, [r4], r6 +0x4f 0x89 0x24 0xf4 +# CHECK: vld2.16 {d8, d10}, [r4] +0x8f 0x89 0x24 0xf4 +# CHECK: vld2.32 {d8, d10}, [r4] +0x0f 0x89 0x24 0xf4 +# CHECK: vld2.8 {d8, d10}, [r4] +0x4d 0x83 0x24 0xf4 +# CHECK: vld2.16 {d8, d9, d10, d11}, [r4]! +0x46 0x83 0x24 0xf4 +# CHECK: vld2.16 {d8, d9, d10, d11}, [r4], r6 +0x8d 0x83 0x24 0xf4 +# CHECK: vld2.32 {d8, d9, d10, d11}, [r4]! +0x86 0x83 0x24 0xf4 +# CHECK: vld2.32 {d8, d9, d10, d11}, [r4], r6 +0x0d 0x83 0x24 0xf4 +# CHECK: vld2.8 {d8, d9, d10, d11}, [r4]! +0x06 0x83 0x24 0xf4 +# CHECK: vld2.8 {d8, d9, d10, d11}, [r4], r6 +0x0f 0x84 0x24 0xf4 +# CHECK: vld3.8 {d8, d9, d10}, [r4] +0x4f 0x84 0x24 0xf4 +# CHECK: vld3.16 {d8, d9, d10}, [r4] +0x8f 0x84 0x24 0xf4 +# CHECK: vld3.32 {d8, d9, d10}, [r4] +0x0f 0x80 0x24 0xf4 +# CHECK: vld4.8 {d8, d9, d10, d11}, [r4] +0x4f 0x80 0x24 0xf4 +# CHECK: vld4.16 {d8, d9, d10, d11}, [r4] +0x8f 0x80 0x24 0xf4 +# CHECK: vld4.32 {d8, d9, d10, d11}, [r4] +0x0f 0x85 0x24 0xf4 +# CHECK: vld3.8 {d8, d10, d12}, [r4] +0x4f 0x85 0x24 0xf4 +# CHECK: vld3.16 {d8, d10, d12}, [r4] +0x8f 0x85 0x24 0xf4 +# CHECK: vld3.32 {d8, d10, d12}, [r4] +0x0f 0x81 0x24 0xf4 +# CHECK: vld4.8 {d8, d10, d12, d14}, [r4] +0x4f 0x81 0x24 0xf4 +# CHECK: vld4.16 {d8, d10, d12, d14}, [r4] +0x8f 0x81 0x24 0xf4 +# CHECK: vld4.32 {d8, d10, d12, d14}, [r4] diff --git a/test/MC/Disassembler/ARM/neont2.txt b/test/MC/Disassembler/ARM/neont2.txt index 577703c..efe7e60 100644 --- a/test/MC/Disassembler/ARM/neont2.txt +++ b/test/MC/Disassembler/ARM/neont2.txt @@ -301,9 +301,9 @@ 0x50 0xef 0xf2 0x01 # CHECK: vbic q8, q8, q9 0xc7 0xff 0x3f 0x07 -# CHECK: vbic.i32 d16, #0xFF000000 +# CHECK: vbic.i32 d16, #0xff000000 0xc7 0xff 0x7f 0x07 -# CHECK: vbic.i32 q8, #0xFF000000 +# CHECK: vbic.i32 q8, #0xff000000 0x71 0xef 0xb0 0x01 # CHECK: vorn d16, d17, d16 @@ -486,11 +486,11 @@ 0xc2 0xef 0x10 0x06 # CHECK: vmov.i32 d16, #0x20000000 0xc2 0xef 0x10 0x0c -# CHECK: vmov.i32 d16, #0x20FF +# CHECK: vmov.i32 d16, #0x20ff 0xc2 0xef 0x10 0x0d -# CHECK: vmov.i32 d16, #0x20FFFF +# CHECK: vmov.i32 d16, #0x20ffff 0xc1 0xff 0x33 0x0e -# CHECK: vmov.i64 d16, #0xFF0000FF0000FFFF +# CHECK: vmov.i64 d16, #0xff0000ff0000ffff 0xc0 0xef 0x58 0x0e # CHECK: vmov.i8 q8, #0x8 0xc1 0xef 0x50 0x08 @@ -506,11 +506,11 @@ 0xc2 0xef 0x50 0x06 # CHECK: vmov.i32 q8, #0x20000000 0xc2 0xef 0x50 0x0c -# CHECK: vmov.i32 q8, #0x20FF +# CHECK: vmov.i32 q8, #0x20ff 0xc2 0xef 0x50 0x0d -# CHECK: vmov.i32 q8, #0x20FFFF +# CHECK: vmov.i32 q8, #0x20ffff 0xc1 0xff 0x73 0x0e -# CHECK: vmov.i64 q8, #0xFF0000FF0000FFFF +# CHECK: vmov.i64 q8, #0xff0000ff0000ffff 0xc1 0xef 0x30 0x08 # CHECK: vmvn.i16 d16, #0x10 0xc1 0xef 0x30 0x0a @@ -524,9 +524,9 @@ 0xc2 0xef 0x30 0x06 # CHECK: vmvn.i32 d16, #0x20000000 0xc2 0xef 0x30 0x0c -# CHECK: vmvn.i32 d16, #0x20FF +# CHECK: vmvn.i32 d16, #0x20ff 0xc2 0xef 0x30 0x0d -# CHECK: vmvn.i32 d16, #0x20FFFF +# CHECK: vmvn.i32 d16, #0x20ffff 0xc8 0xef 0x30 0x0a # CHECK: vmovl.s8 q8, d16 0xd0 0xef 0x30 0x0a @@ -1584,3 +1584,379 @@ # CHECK: vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0, :64] 0xc0 0xf9 0x4f 0x1b # CHECK: vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] + +0x63 0xf9 0x37 0xc9 +# CHECK: vld2.8 {d28, d30}, [r3, :256], r7 + +# rdar://10798451 +0xe7 0xf9 0x32 0x1d +# CHECK vld2.8 {d17[], d19[]}, [r7, :16], r2 +0xe7 0xf9 0x3d 0x1d +# CHECK vld2.8 {d17[], d19[]}, [r7, :16]! +0xe7 0xf9 0x3f 0x1d +# CHECK vld2.8 {d17[], d19[]}, [r7, :16] + +# rdar://11034702 +0x04 0xf9 0x0d 0x87 +# CHECK: vst1.8 {d8}, [r4]! +0x04 0xf9 0x4d 0x87 +# CHECK: vst1.16 {d8}, [r4]! +0x04 0xf9 0x8d 0x87 +# CHECK: vst1.32 {d8}, [r4]! +0x04 0xf9 0xcd 0x87 +# CHECK: vst1.64 {d8}, [r4]! +0x04 0xf9 0x06 0x87 +# CHECK: vst1.8 {d8}, [r4], r6 +0x04 0xf9 0x46 0x87 +# CHECK: vst1.16 {d8}, [r4], r6 +0x04 0xf9 0x86 0x87 +# CHECK: vst1.32 {d8}, [r4], r6 +0x04 0xf9 0xc6 0x87 +# CHECK: vst1.64 {d8}, [r4], r6 + +0x04 0xf9 0x0d 0x8a +# CHECK: vst1.8 {d8, d9}, [r4]! +0x04 0xf9 0x4d 0x8a +# CHECK: vst1.16 {d8, d9}, [r4]! +0x04 0xf9 0x8d 0x8a +# CHECK: vst1.32 {d8, d9}, [r4]! +0x04 0xf9 0xcd 0x8a +# CHECK: vst1.64 {d8, d9}, [r4]! +0x04 0xf9 0x06 0x8a +# CHECK: vst1.8 {d8, d9}, [r4], r6 +0x04 0xf9 0x46 0x8a +# CHECK: vst1.16 {d8, d9}, [r4], r6 +0x04 0xf9 0x86 0x8a +# CHECK: vst1.32 {d8, d9}, [r4], r6 +0x04 0xf9 0xc6 0x8a +# CHECK: vst1.64 {d8, d9}, [r4], r6 + +0x04 0xf9 0x0d 0x86 +# CHECK: vst1.8 {d8, d9, d10}, [r4]! +0x04 0xf9 0x4d 0x86 +# CHECK: vst1.16 {d8, d9, d10}, [r4]! +0x04 0xf9 0x8d 0x86 +# CHECK: vst1.32 {d8, d9, d10}, [r4]! +0x04 0xf9 0xcd 0x86 +# CHECK: vst1.64 {d8, d9, d10}, [r4]! +0x04 0xf9 0x06 0x86 +# CHECK: vst1.8 {d8, d9, d10}, [r4], r6 +0x04 0xf9 0x46 0x86 +# CHECK: vst1.16 {d8, d9, d10}, [r4], r6 +0x04 0xf9 0x86 0x86 +# CHECK: vst1.32 {d8, d9, d10}, [r4], r6 +0x04 0xf9 0xc6 0x86 +# CHECK: vst1.64 {d8, d9, d10}, [r4], r6 + +0x04 0xf9 0x0d 0x82 +# CHECK: vst1.8 {d8, d9, d10, d11}, [r4]! +0x04 0xf9 0x4d 0x82 +# CHECK: vst1.16 {d8, d9, d10, d11}, [r4]! +0x04 0xf9 0x8d 0x82 +# CHECK: vst1.32 {d8, d9, d10, d11}, [r4]! +0x04 0xf9 0xcd 0x82 +# CHECK: vst1.64 {d8, d9, d10, d11}, [r4]! +0x04 0xf9 0x06 0x82 +# CHECK: vst1.8 {d8, d9, d10, d11}, [r4], r6 +0x04 0xf9 0x46 0x82 +# CHECK: vst1.16 {d8, d9, d10, d11}, [r4], r6 +0x04 0xf9 0x86 0x82 +# CHECK: vst1.32 {d8, d9, d10, d11}, [r4], r6 +0x04 0xf9 0xc6 0x82 +# CHECK: vst1.64 {d8, d9, d10, d11}, [r4], r6 + +0x04 0xf9 0x0d 0x88 +# CHECK: vst2.8 {d8, d9}, [r4]! +0x04 0xf9 0x4d 0x88 +# CHECK: vst2.16 {d8, d9}, [r4]! +0x04 0xf9 0x8d 0x88 +# CHECK: vst2.32 {d8, d9}, [r4]! +0x04 0xf9 0x06 0x88 +# CHECK: vst2.8 {d8, d9}, [r4], r6 +0x04 0xf9 0x46 0x88 +# CHECK: vst2.16 {d8, d9}, [r4], r6 +0x04 0xf9 0x86 0x88 +# CHECK: vst2.32 {d8, d9}, [r4], r6 + +0x04 0xf9 0x0d 0x89 +# CHECK: vst2.8 {d8, d10}, [r4]! +0x04 0xf9 0x4d 0x89 +# CHECK: vst2.16 {d8, d10}, [r4]! +0x04 0xf9 0x8d 0x89 +# CHECK: vst2.32 {d8, d10}, [r4]! +0x04 0xf9 0x06 0x89 +# CHECK: vst2.8 {d8, d10}, [r4], r6 +0x04 0xf9 0x46 0x89 +# CHECK: vst2.16 {d8, d10}, [r4], r6 +0x04 0xf9 0x86 0x89 +# CHECK: vst2.32 {d8, d10}, [r4], r6 + +0x04 0xf9 0x0d 0x84 +# CHECK: vst3.8 {d8, d9, d10}, [r4]! +0x04 0xf9 0x4d 0x84 +# CHECK: vst3.16 {d8, d9, d10}, [r4]! +0x04 0xf9 0x8d 0x84 +# CHECK: vst3.32 {d8, d9, d10}, [r4]! +0x04 0xf9 0x06 0x85 +# CHECK: vst3.8 {d8, d10, d12}, [r4], r6 +0x04 0xf9 0x46 0x85 +# CHECK: vst3.16 {d8, d10, d12}, [r4], r6 +0x04 0xf9 0x86 0x85 +# CHECK: vst3.32 {d8, d10, d12}, [r4], r6 + +0x04 0xf9 0x0d 0x80 +# CHECK: vst4.8 {d8, d9, d10, d11}, [r4]! +0x04 0xf9 0x4d 0x80 +# CHECK: vst4.16 {d8, d9, d10, d11}, [r4]! +0x04 0xf9 0x8d 0x80 +# CHECK: vst4.32 {d8, d9, d10, d11}, [r4]! +0x04 0xf9 0x06 0x81 +# CHECK: vst4.8 {d8, d10, d12, d14}, [r4], r6 +0x04 0xf9 0x46 0x81 +# CHECK: vst4.16 {d8, d10, d12, d14}, [r4], r6 +0x04 0xf9 0x86 0x81 +# CHECK: vst4.32 {d8, d10, d12, d14}, [r4], r6 + +0x04 0xf9 0x4f 0x8a +# CHECK: vst1.16 {d8, d9}, [r4] +0x04 0xf9 0x8f 0x8a +# CHECK: vst1.32 {d8, d9}, [r4] +0x04 0xf9 0xcf 0x8a +# CHECK: vst1.64 {d8, d9}, [r4] +0x04 0xf9 0x0f 0x8a +# CHECK: vst1.8 {d8, d9}, [r4] +0x04 0xf9 0x4f 0x88 +# CHECK: vst2.16 {d8, d9}, [r4] +0x04 0xf9 0x8f 0x88 +# CHECK: vst2.32 {d8, d9}, [r4] +0x04 0xf9 0x0f 0x88 +# CHECK: vst2.8 {d8, d9}, [r4] +0x04 0xf9 0x4d 0x88 +# CHECK: vst2.16 {d8, d9}, [r4]! +0x04 0xf9 0x46 0x88 +# CHECK: vst2.16 {d8, d9}, [r4], r6 +0x04 0xf9 0x8d 0x88 +# CHECK: vst2.32 {d8, d9}, [r4]! +0x04 0xf9 0x86 0x88 +# CHECK: vst2.32 {d8, d9}, [r4], r6 +0x04 0xf9 0x0d 0x88 +# CHECK: vst2.8 {d8, d9}, [r4]! +0x04 0xf9 0x06 0x88 +# CHECK: vst2.8 {d8, d9}, [r4], r6 + +0x04 0xf9 0x4f 0x89 +# CHECK: vst2.16 {d8, d10}, [r4] +0x04 0xf9 0x8f 0x89 +# CHECK: vst2.32 {d8, d10}, [r4] +0x04 0xf9 0x0f 0x89 +# CHECK: vst2.8 {d8, d10}, [r4] + +0x04 0xf9 0x0f 0x84 +# CHECK: vst3.8 {d8, d9, d10}, [r4] +0x04 0xf9 0x4f 0x84 +# CHECK: vst3.16 {d8, d9, d10}, [r4] +0x04 0xf9 0x8f 0x84 +# CHECK: vst3.32 {d8, d9, d10}, [r4] + +0x04 0xf9 0x0f 0x80 +# CHECK: vst4.8 {d8, d9, d10, d11}, [r4] +0x04 0xf9 0x4f 0x80 +# CHECK: vst4.16 {d8, d9, d10, d11}, [r4] +0x04 0xf9 0x8f 0x80 +# CHECK: vst4.32 {d8, d9, d10, d11}, [r4] + +0x04 0xf9 0x0f 0x85 +# CHECK: vst3.8 {d8, d10, d12}, [r4] +0x04 0xf9 0x4f 0x85 +# CHECK: vst3.16 {d8, d10, d12}, [r4] +0x04 0xf9 0x8f 0x85 +# CHECK: vst3.32 {d8, d10, d12}, [r4] + +0x04 0xf9 0x0f 0x81 +# CHECK: vst4.8 {d8, d10, d12, d14}, [r4] +0x04 0xf9 0x4f 0x81 +# CHECK: vst4.16 {d8, d10, d12, d14}, [r4] +0x04 0xf9 0x8f 0x81 +# CHECK: vst4.32 {d8, d10, d12, d14}, [r4] + +# rdar://11204059 +0x24 0xf9 0x0d 0x87 +# CHECK: vld1.8 {d8}, [r4]! +0x24 0xf9 0x4d 0x87 +# CHECK: vld1.16 {d8}, [r4]! +0x24 0xf9 0x8d 0x87 +# CHECK: vld1.32 {d8}, [r4]! +0x24 0xf9 0xcd 0x87 +# CHECK: vld1.64 {d8}, [r4]! +0x24 0xf9 0x06 0x87 +# CHECK: vld1.8 {d8}, [r4], r6 +0x24 0xf9 0x46 0x87 +# CHECK: vld1.16 {d8}, [r4], r6 +0x24 0xf9 0x86 0x87 +# CHECK: vld1.32 {d8}, [r4], r6 +0x24 0xf9 0xc6 0x87 +# CHECK: vld1.64 {d8}, [r4], r6 +0x24 0xf9 0x0d 0x8a +# CHECK: vld1.8 {d8, d9}, [r4]! +0x24 0xf9 0x4d 0x8a +# CHECK: vld1.16 {d8, d9}, [r4]! +0x24 0xf9 0x8d 0x8a +# CHECK: vld1.32 {d8, d9}, [r4]! +0x24 0xf9 0xcd 0x8a +# CHECK: vld1.64 {d8, d9}, [r4]! +0x24 0xf9 0x06 0x8a +# CHECK: vld1.8 {d8, d9}, [r4], r6 +0x24 0xf9 0x46 0x8a +# CHECK: vld1.16 {d8, d9}, [r4], r6 +0x24 0xf9 0x86 0x8a +# CHECK: vld1.32 {d8, d9}, [r4], r6 +0x24 0xf9 0xc6 0x8a +# CHECK: vld1.64 {d8, d9}, [r4], r6 +0x24 0xf9 0x0d 0x86 +# CHECK: vld1.8 {d8, d9, d10}, [r4]! +0x24 0xf9 0x4d 0x86 +# CHECK: vld1.16 {d8, d9, d10}, [r4]! +0x24 0xf9 0x8d 0x86 +# CHECK: vld1.32 {d8, d9, d10}, [r4]! +0x24 0xf9 0xcd 0x86 +# CHECK: vld1.64 {d8, d9, d10}, [r4]! +0x24 0xf9 0x06 0x86 +# CHECK: vld1.8 {d8, d9, d10}, [r4], r6 +0x24 0xf9 0x46 0x86 +# CHECK: vld1.16 {d8, d9, d10}, [r4], r6 +0x24 0xf9 0x86 0x86 +# CHECK: vld1.32 {d8, d9, d10}, [r4], r6 +0x24 0xf9 0xc6 0x86 +# CHECK: vld1.64 {d8, d9, d10}, [r4], r6 +0x24 0xf9 0x0d 0x82 +# CHECK: vld1.8 {d8, d9, d10, d11}, [r4]! +0x24 0xf9 0x4d 0x82 +# CHECK: vld1.16 {d8, d9, d10, d11}, [r4]! +0x24 0xf9 0x8d 0x82 +# CHECK: vld1.32 {d8, d9, d10, d11}, [r4]! +0x24 0xf9 0xcd 0x82 +# CHECK: vld1.64 {d8, d9, d10, d11}, [r4]! +0x24 0xf9 0x06 0x82 +# CHECK: vld1.8 {d8, d9, d10, d11}, [r4], r6 +0x24 0xf9 0x46 0x82 +# CHECK: vld1.16 {d8, d9, d10, d11}, [r4], r6 +0x24 0xf9 0x86 0x82 +# CHECK: vld1.32 {d8, d9, d10, d11}, [r4], r6 +0x24 0xf9 0xc6 0x82 +# CHECK: vld1.64 {d8, d9, d10, d11}, [r4], r6 +0x24 0xf9 0x0d 0x88 +# CHECK: vld2.8 {d8, d9}, [r4]! +0x24 0xf9 0x4d 0x88 +# CHECK: vld2.16 {d8, d9}, [r4]! +0x24 0xf9 0x8d 0x88 +# CHECK: vld2.32 {d8, d9}, [r4]! +0x24 0xf9 0x06 0x88 +# CHECK: vld2.8 {d8, d9}, [r4], r6 +0x24 0xf9 0x46 0x88 +# CHECK: vld2.16 {d8, d9}, [r4], r6 +0x24 0xf9 0x86 0x88 +# CHECK: vld2.32 {d8, d9}, [r4], r6 +0x24 0xf9 0x0d 0x89 +# CHECK: vld2.8 {d8, d10}, [r4]! +0x24 0xf9 0x4d 0x89 +# CHECK: vld2.16 {d8, d10}, [r4]! +0x24 0xf9 0x8d 0x89 +# CHECK: vld2.32 {d8, d10}, [r4]! +0x24 0xf9 0x06 0x89 +# CHECK: vld2.8 {d8, d10}, [r4], r6 +0x24 0xf9 0x46 0x89 +# CHECK: vld2.16 {d8, d10}, [r4], r6 +0x24 0xf9 0x86 0x89 +# CHECK: vld2.32 {d8, d10}, [r4], r6 +0x24 0xf9 0x0d 0x84 +# CHECK: vld3.8 {d8, d9, d10}, [r4]! +0x24 0xf9 0x4d 0x84 +# CHECK: vld3.16 {d8, d9, d10}, [r4]! +0x24 0xf9 0x8d 0x84 +# CHECK: vld3.32 {d8, d9, d10}, [r4]! +0x24 0xf9 0x06 0x85 +# CHECK: vld3.8 {d8, d10, d12}, [r4], r6 +0x24 0xf9 0x46 0x85 +# CHECK: vld3.16 {d8, d10, d12}, [r4], r6 +0x24 0xf9 0x86 0x85 +# CHECK: vld3.32 {d8, d10, d12}, [r4], r6 +0x24 0xf9 0x0d 0x80 +# CHECK: vld4.8 {d8, d9, d10, d11}, [r4]! +0x24 0xf9 0x4d 0x80 +# CHECK: vld4.16 {d8, d9, d10, d11}, [r4]! +0x24 0xf9 0x8d 0x80 +# CHECK: vld4.32 {d8, d9, d10, d11}, [r4]! +0x24 0xf9 0x06 0x81 +# CHECK: vld4.8 {d8, d10, d12, d14}, [r4], r6 +0x24 0xf9 0x46 0x81 +# CHECK: vld4.16 {d8, d10, d12, d14}, [r4], r6 +0x24 0xf9 0x86 0x81 +# CHECK: vld4.32 {d8, d10, d12, d14}, [r4], r6 +0x24 0xf9 0x4f 0x8a +# CHECK: vld1.16 {d8, d9}, [r4] +0x24 0xf9 0x8f 0x8a +# CHECK: vld1.32 {d8, d9}, [r4] +0x24 0xf9 0xcf 0x8a +# CHECK: vld1.64 {d8, d9}, [r4] +0x24 0xf9 0x0f 0x8a +# CHECK: vld1.8 {d8, d9}, [r4] +0x24 0xf9 0x4f 0x88 +# CHECK: vld2.16 {d8, d9}, [r4] +0x24 0xf9 0x8f 0x88 +# CHECK: vld2.32 {d8, d9}, [r4] +0x24 0xf9 0x0f 0x88 +# CHECK: vld2.8 {d8, d9}, [r4] +0x24 0xf9 0x4d 0x88 +# CHECK: vld2.16 {d8, d9}, [r4]! +0x24 0xf9 0x46 0x88 +# CHECK: vld2.16 {d8, d9}, [r4], r6 +0x24 0xf9 0x8d 0x88 +# CHECK: vld2.32 {d8, d9}, [r4]! +0x24 0xf9 0x86 0x88 +# CHECK: vld2.32 {d8, d9}, [r4], r6 +0x24 0xf9 0x0d 0x88 +# CHECK: vld2.8 {d8, d9}, [r4]! +0x24 0xf9 0x06 0x88 +# CHECK: vld2.8 {d8, d9}, [r4], r6 +0x24 0xf9 0x4f 0x89 +# CHECK: vld2.16 {d8, d10}, [r4] +0x24 0xf9 0x8f 0x89 +# CHECK: vld2.32 {d8, d10}, [r4] +0x24 0xf9 0x0f 0x89 +# CHECK: vld2.8 {d8, d10}, [r4] +0x24 0xf9 0x4d 0x83 +# CHECK: vld2.16 {d8, d9, d10, d11}, [r4]! +0x24 0xf9 0x46 0x83 +# CHECK: vld2.16 {d8, d9, d10, d11}, [r4], r6 +0x24 0xf9 0x8d 0x83 +# CHECK: vld2.32 {d8, d9, d10, d11}, [r4]! +0x24 0xf9 0x86 0x83 +# CHECK: vld2.32 {d8, d9, d10, d11}, [r4], r6 +0x24 0xf9 0x0d 0x83 +# CHECK: vld2.8 {d8, d9, d10, d11}, [r4]! +0x24 0xf9 0x06 0x83 +# CHECK: vld2.8 {d8, d9, d10, d11}, [r4], r6 +0x24 0xf9 0x0f 0x84 +# CHECK: vld3.8 {d8, d9, d10}, [r4] +0x24 0xf9 0x4f 0x84 +# CHECK: vld3.16 {d8, d9, d10}, [r4] +0x24 0xf9 0x8f 0x84 +# CHECK: vld3.32 {d8, d9, d10}, [r4] +0x24 0xf9 0x0f 0x80 +# CHECK: vld4.8 {d8, d9, d10, d11}, [r4] +0x24 0xf9 0x4f 0x80 +# CHECK: vld4.16 {d8, d9, d10, d11}, [r4] +0x24 0xf9 0x8f 0x80 +# CHECK: vld4.32 {d8, d9, d10, d11}, [r4] +0x24 0xf9 0x0f 0x85 +# CHECK: vld3.8 {d8, d10, d12}, [r4] +0x24 0xf9 0x4f 0x85 +# CHECK: vld3.16 {d8, d10, d12}, [r4] +0x24 0xf9 0x8f 0x85 +# CHECK: vld3.32 {d8, d10, d12}, [r4] +0x24 0xf9 0x0f 0x81 +# CHECK: vld4.8 {d8, d10, d12, d14}, [r4] +0x24 0xf9 0x4f 0x81 +# CHECK: vld4.16 {d8, d10, d12, d14}, [r4] +0x24 0xf9 0x8f 0x81 +# CHECK: vld4.32 {d8, d10, d12, d14}, [r4] diff --git a/test/MC/Disassembler/ARM/unpredictable-ADC-arm.txt b/test/MC/Disassembler/ARM/unpredictable-ADC-arm.txt new file mode 100644 index 0000000..275bae2f --- /dev/null +++ b/test/MC/Disassembler/ARM/unpredictable-ADC-arm.txt @@ -0,0 +1,17 @@ +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s + +# CHECK: potentially undefined +# CHECK: 0x1f 0x12 0xb0 0x00 +0x1f 0x12 0xb0 0x00 + +# CHECK: potentially undefined +# CHECK: 0x13 0xf2 0xb0 0x00 +0x13 0xf2 0xb0 0x00 + +# CHECK: potentially undefined +# CHECK: 0x13 0x1f 0xb0 0x00 +0x13 0x1f 0xb0 0x00 + +# CHECK: potentially undefined +# CHECK: 0x13 0x12 0xbf 0x00 +0x13 0x12 0xbf 0x00 diff --git a/test/MC/Disassembler/ARM/unpredictable-ADDREXT3-arm.txt b/test/MC/Disassembler/ARM/unpredictable-ADDREXT3-arm.txt new file mode 100644 index 0000000..635b66e --- /dev/null +++ b/test/MC/Disassembler/ARM/unpredictable-ADDREXT3-arm.txt @@ -0,0 +1,16 @@ +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s + +# CHECK: potentially undefined +# CHECK: 0xd1 0xf1 0x5f 0x01 +0xd1 0xf1 0x5f 0x01 +# CHECK: potentially undefined +# CHECK: 0xf1 0xf1 0x5f 0x01 +0xf1 0xf1 0x5f 0x01 +# CHECK: potentially undefined +# CHECK: 0xf1 0xf1 0x5f 0x01 +0xf1 0xf1 0x5f 0x01 +# CHECK: potentially undefined +# CHECK: 0xd1 0xe1 0x4f 0x01 +0xd1 0xe1 0x4f 0x01 + + diff --git a/test/MC/Disassembler/ARM/unpredictable-LDR-arm.txt b/test/MC/Disassembler/ARM/unpredictable-LDR-arm.txt new file mode 100644 index 0000000..ed5e350 --- /dev/null +++ b/test/MC/Disassembler/ARM/unpredictable-LDR-arm.txt @@ -0,0 +1,22 @@ +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s + +# CHECK: potentially undefined +# CHECK: 0xff 0x00 0xb9 0x00 +0xff 0x00 0xb9 0x00 + +# CHECK: potentially undefined +# CHECK: 0xfb 0xf0 0xb9 0x00 +0xfb 0xf0 0xb9 0x00 + +# CHECK: potentially undefined +# CHECK: 0xfb 0x01 0xb9 0x00 +0xfb 0x01 0xb9 0x00 + +# CHECK: potentially undefined +# CHECK: 0xfb 0x00 0xbf 0x00 +0xfb 0x00 0xbf 0x00 + +# CHECK: potentially undefined +# CHECK: 0xfb 0x90 0xb9 0x00 +0xfb 0x90 0xb9 0x00 + diff --git a/test/MC/Disassembler/ARM/invalid-LDRD-arm.txt b/test/MC/Disassembler/ARM/unpredictable-LDRD-arm.txt index f8f23ed..a8f54f7 100644 --- a/test/MC/Disassembler/ARM/invalid-LDRD-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-LDRD-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # ------------------------------------------------------------------------------------------------- @@ -7,4 +7,7 @@ # # A8.6.68 LDRD (register) # if Rt{0} = 1 then UNDEFINED; + +# CHECK: potentially undefined +# CHECK: 0xd0 0x10 0x00 0x00 0xd0 0x10 0x00 0x00 diff --git a/test/MC/Disassembler/ARM/invalid-LSL-regform.txt b/test/MC/Disassembler/ARM/unpredictable-LSL-regform.txt index 6a1f11f..f7d6bc6 100644 --- a/test/MC/Disassembler/ARM/invalid-LSL-regform.txt +++ b/test/MC/Disassembler/ARM/unpredictable-LSL-regform.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s # Opcode=196 Name=MOVs Format=ARM_FORMAT_DPSOREGFRM(5) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 @@ -8,4 +8,6 @@ # # A8.6.89 LSL (register) # if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; + +# CHECK: warning: potentially undefined instruction encoding 0x12 0xf1 0xa0 0xe1 diff --git a/test/MC/Disassembler/ARM/unpredictable-MUL-arm.txt b/test/MC/Disassembler/ARM/unpredictable-MUL-arm.txt new file mode 100644 index 0000000..3db86cc --- /dev/null +++ b/test/MC/Disassembler/ARM/unpredictable-MUL-arm.txt @@ -0,0 +1,17 @@ +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s + +# CHECK: potentially undefined +# CHECK: 0x93 0x12 0x01 0x00 +0x93 0x12 0x01 0x00 + +# CHECK: potentially undefined +# CHECK: 0x92 0x0f 0x01 0x00 +0x92 0x0f 0x01 0x00 + +# CHECK: potentially undefined +# CHECK: 0x9f 0x02 0x01 0x00 +0x9f 0x02 0x01 0x00 + +# CHECK: potentially undefined +# CHECK: 0x92 0x01 0x0f 0x00 +0x92 0x01 0x0f 0x00 diff --git a/test/MC/Disassembler/ARM/invalid-RSC-arm.txt b/test/MC/Disassembler/ARM/unpredictable-RSC-arm.txt index 096b909..5b13610 100644 --- a/test/MC/Disassembler/ARM/invalid-RSC-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-RSC-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s # Opcode=261 Name=RSCrs Format=ARM_FORMAT_DPSOREGFRM(5) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 @@ -6,4 +6,6 @@ # | 0: 0: 1: 1| 0: 0: 0: 0| 1: 1: 1: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 0: 0: 0| 0: 1: 0: 1| 1: 1: 1: 1| # ------------------------------------------------------------------------------------------------- # if d == 15 || n == 15 || m == 15 || s == 15 then UNPREDICTABLE; + +# CHECK: warning: potentially undefined instruction encoding 0x5f 0xf8 0xe4 0x30 diff --git a/test/MC/Disassembler/ARM/unpredictable-SHADD16-arm.txt b/test/MC/Disassembler/ARM/unpredictable-SHADD16-arm.txt new file mode 100644 index 0000000..8ec49ca --- /dev/null +++ b/test/MC/Disassembler/ARM/unpredictable-SHADD16-arm.txt @@ -0,0 +1,7 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s + +# CHECK: warning: potentially undefined +# CHECK: shadd16 r5, r7, r0 +0x10 0x51 0x37 0xe6 + + diff --git a/test/MC/Disassembler/ARM/invalid-SSAT-arm.txt b/test/MC/Disassembler/ARM/unpredictable-SSAT-arm.txt index b236f8e..874378e 100644 --- a/test/MC/Disassembler/ARM/invalid-SSAT-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-SSAT-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s # Opcode=322 Name=SSAT Format=ARM_FORMAT_SATFRM(13) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 @@ -8,4 +8,6 @@ # # A8.6.183 SSAT # if d == 15 || n == 15 then UNPREDICTABLE; + +# CHECK:warning: potentially undefined instruction encoding 0x1a 0xf4 0xa0 0xe6 diff --git a/test/MC/Disassembler/ARM/invalid-STRBrs-arm.txt b/test/MC/Disassembler/ARM/unpredictable-STRBrs-arm.txt index d3998bd..fef6125 100644 --- a/test/MC/Disassembler/ARM/invalid-STRBrs-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-STRBrs-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s # Opcode=355 Name=STRBrs Format=ARM_FORMAT_STFRM(7) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 @@ -7,4 +7,6 @@ # ------------------------------------------------------------------------------------------------- # # if t == 15 then UNPREDICTABLE + +# CHECK: warning: potentially undefined instruction encoding 0x00 0xf0 0xcf 0xe7 diff --git a/test/MC/Disassembler/ARM/invalid-UQADD8-arm.txt b/test/MC/Disassembler/ARM/unpredictable-UQADD8-arm.txt index fb3e711..4c4c9ab 100644 --- a/test/MC/Disassembler/ARM/invalid-UQADD8-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-UQADD8-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s # Opcode=426 Name=UQADD8 Format=ARM_FORMAT_DPFRM(4) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 @@ -10,3 +10,7 @@ # # if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; 0x9f 0x5f 0x66 0xe6 + +# CHECK: warning: potentially undefined +# CHECK: uqadd8 r5, r6, pc + diff --git a/test/MC/Disassembler/ARM/unpredictables-thumb.txt b/test/MC/Disassembler/ARM/unpredictables-thumb.txt new file mode 100644 index 0000000..e7645f0 --- /dev/null +++ b/test/MC/Disassembler/ARM/unpredictables-thumb.txt @@ -0,0 +1,5 @@ +# RUN: llvm-mc --disassemble %s -triple=thumbv7 |& FileCheck %s + +0x01 0x47 +# CHECK: 3:1: warning: potentially undefined +# CHECK: bx r0 diff --git a/test/MC/Disassembler/ARM/vfp4.txt b/test/MC/Disassembler/ARM/vfp4.txt new file mode 100644 index 0000000..4f2c732 --- /dev/null +++ b/test/MC/Disassembler/ARM/vfp4.txt @@ -0,0 +1,37 @@ +# RUN: llvm-mc < %s -triple thumbv7-unknown-unknown --disassemble -mattr=+neon,+vfp4 | FileCheck %s + +# CHECK: vfma.f64 d16, d18, d17 +0xe2 0xee 0xa1 0x0b + +# CHECK: vfma.f32 s2, s4, s0 +0xa2 0xee 0x00 0x1a + +# CHECK: vfma.f32 d16, d18, d17 +0x42 0xef 0xb1 0x0c + +# CHECK: vfma.f32 q2, q4, q0 +0x08 0xef 0x50 0x4c + +# CHECK: vfnms.f64 d16, d18, d17 +0xd2 0xee 0xa1 0x0b + +# CHECK: vfnms.f32 s2, s4, s0 +0x92 0xee 0x00 0x1a + +# CHECK: vfms.f64 d16, d18, d17 +0xe2 0xee 0xe1 0x0b + +# CHECK: vfms.f32 s2, s4, s0 +0xa2 0xee 0x40 0x1a + +# CHECK: vfms.f32 d16, d18, d17 +0x62 0xef 0xb1 0x0c + +# CHECK: vfms.f32 q2, q4, q0 +0x28 0xef 0x50 0x4c + +# CHECK: vfnma.f64 d16, d18, d17 +0xd2 0xee 0xe1 0x0b + +# CHECK: vfnma.f32 s2, s4, s0 +0x92 0xee 0x40 0x1a diff --git a/test/MC/Disassembler/MBlaze/dg.exp b/test/MC/Disassembler/MBlaze/dg.exp deleted file mode 100644 index 0be99a3..0000000 --- a/test/MC/Disassembler/MBlaze/dg.exp +++ /dev/null @@ -1,6 +0,0 @@ -load_lib llvm.exp - -if { [llvm_supports_target MBlaze] } { - RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{txt}]] -} - diff --git a/test/MC/Disassembler/MBlaze/lit.local.cfg b/test/MC/Disassembler/MBlaze/lit.local.cfg new file mode 100644 index 0000000..3955b4e --- /dev/null +++ b/test/MC/Disassembler/MBlaze/lit.local.cfg @@ -0,0 +1,6 @@ +config.suffixes = ['.txt'] + +targets = set(config.root.targets_to_build.split()) +if not 'MBlaze' in targets: + config.unsupported = True + diff --git a/test/MC/Disassembler/MBlaze/mblaze_mbar.txt b/test/MC/Disassembler/MBlaze/mblaze_mbar.txt new file mode 100644 index 0000000..6beba86 --- /dev/null +++ b/test/MC/Disassembler/MBlaze/mblaze_mbar.txt @@ -0,0 +1,14 @@ +# RUN: llvm-mc --disassemble %s -triple=mblaze-unknown-unknown | FileCheck %s + +################################################################################ +# Memory Barrier instructions +################################################################################ + +# CHECK: mbar 0 +0xB8 0x02 0x00 0x04 + +# CHECK: mbar 1 +0xB8 0x22 0x00 0x04 + +# CHECK: mbar 2 +0xB8 0x42 0x00 0x04 diff --git a/test/MC/Disassembler/MBlaze/mblaze_pattern.txt b/test/MC/Disassembler/MBlaze/mblaze_pattern.txt index 1268378..cb19ee0 100644 --- a/test/MC/Disassembler/MBlaze/mblaze_pattern.txt +++ b/test/MC/Disassembler/MBlaze/mblaze_pattern.txt @@ -12,3 +12,6 @@ # CHECK: pcmpeq r0, r1, r2 0x88 0x01 0x14 0x00 + +# CHECK: clz r0, r1 +0x90 0x01 0x00 0xE0 diff --git a/test/MC/Disassembler/X86/dg.exp b/test/MC/Disassembler/X86/dg.exp deleted file mode 100644 index a4d0e7c..0000000 --- a/test/MC/Disassembler/X86/dg.exp +++ /dev/null @@ -1,6 +0,0 @@ -load_lib llvm.exp - -if { [llvm_supports_target X86] } { - RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{txt}]] -} - diff --git a/test/MC/Disassembler/X86/intel-syntax.txt b/test/MC/Disassembler/X86/intel-syntax.txt index 54b242d..3391e45 100644 --- a/test/MC/Disassembler/X86/intel-syntax.txt +++ b/test/MC/Disassembler/X86/intel-syntax.txt @@ -77,3 +77,31 @@ # CHECK: test RAX, 0 0x48 0xa9 0x00 0x00 0x00 0x00 + +# CHECK: sysret +0x48 0x0f 0x07 + +# CHECK: sysret +0x0f 0x07 + +# CHECK: sysexit +0x48 0x0f 0x35 + +# CHECK: sysexit +0x0f 0x35 + +# CHECK: iret +0x66 0xcf + +# CHECK: iretd +0xcf + +# CHECK: iretq +0x48 0xcf + +# CHECK: ret +0x66 0xc3 + +# CHECK: retf +0x66 0xcb + diff --git a/test/MC/Disassembler/X86/invalid-cmp-imm.txt b/test/MC/Disassembler/X86/invalid-cmp-imm.txt new file mode 100644 index 0000000..bf8699b --- /dev/null +++ b/test/MC/Disassembler/X86/invalid-cmp-imm.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=x86_64-apple-darwin9 |& grep {invalid instruction encoding} + +# This instruction would decode as cmpordps if the immediate byte was less than 8. +0x0f 0xc2 0xc7 0x08 +# This instruction would decode as cmpordpd if the immediate byte was less than 8. +0x66 0x0f 0xc2 0xc7 0x08 +# This instruction would decode as cmpordss if the immediate byte was less than 8. +0xf3 0x0f 0xc2 0xc7 0x08 +# This instruction would decode as cmpordsd if the immediate byte was less than 8. +0xf2 0x0f 0xc2 0xc7 0x08 diff --git a/test/MC/Disassembler/X86/lit.local.cfg b/test/MC/Disassembler/X86/lit.local.cfg new file mode 100644 index 0000000..6211b3e --- /dev/null +++ b/test/MC/Disassembler/X86/lit.local.cfg @@ -0,0 +1,6 @@ +config.suffixes = ['.txt'] + +targets = set(config.root.targets_to_build.split()) +if not 'X86' in targets: + config.unsupported = True + diff --git a/test/MC/Disassembler/X86/simple-tests.txt b/test/MC/Disassembler/X86/simple-tests.txt index 2dc918c..c0e77d06 100644 --- a/test/MC/Disassembler/X86/simple-tests.txt +++ b/test/MC/Disassembler/X86/simple-tests.txt @@ -6,6 +6,11 @@ # CHECK: int $33 0xCD 0x21 +# CHECK: jrcxz -127 +0xe3 0x81 + +# CHECK: jecxz -127 +0x67 0xe3 0x81 # CHECK: addb %al, (%rax) 0 0 @@ -28,6 +33,9 @@ # CHECK: vmcall 0x0f 0x01 0xc1 +# CHECK: vmfunc +0x0f 0x01 0xd4 + # CHECK: vmlaunch 0x0f 0x01 0xc2 @@ -52,6 +60,30 @@ # CHECK: vmptrst 0x0f 0xc7 0x38 +# CHECK: vmrun +0x0f 0x01 0xd8 + +# CHECK: vmmcall +0x0f 0x01 0xd9 + +# CHECK: vmload +0x0f 0x01 0xda + +# CHECK: vmsave +0x0f 0x01 0xdb + +# CHECK: stgi +0x0f 0x01 0xdc + +# CHECK: clgi +0x0f 0x01 0xdd + +# CHECK: skinit +0x0f 0x01 0xde + +# CHECK: invlpga +0x0f 0x01 0xdf + # CHECK: movl $0, -4(%rbp) 0xc7 0x45 0xfc 0x00 0x00 0x00 0x00 @@ -309,6 +341,9 @@ # CHECK: invvpid (%rax), %rax 0x66 0x0f 0x38 0x81 0x00 +# CHECK: invpcid (%rax), %rax +0x66 0x0f 0x38 0x82 0x00 + # CHECK: nop 0x90 @@ -518,3 +553,179 @@ # CHECK: andnq (%rax), %r15, %rax 0xc4 0xe2 0x80 0xf2 0x00 + +# CHECK: blsrl (%rax), %r15d +0xc4 0xe2 0x00 0xf3 0x08 + +# CHECK: blsrq (%rax), %r15 +0xc4 0xe2 0x80 0xf3 0x08 + +# CHECK: blsmskl (%rax), %r15d +0xc4 0xe2 0x00 0xf3 0x10 + +# CHECK: blsmskq (%rax), %r15 +0xc4 0xe2 0x80 0xf3 0x10 + +# CHECK: blsil (%rax), %r15d +0xc4 0xe2 0x00 0xf3 0x18 + +# CHECK: blsiq (%rax), %r15 +0xc4 0xe2 0x80 0xf3 0x18 + +# CHECK: bextrl %r12d, (%rax), %r10d +0xc4 0x62 0x18 0xf7 0x10 + +# CHECK: bextrl %r12d, %r11d, %r10d +0xc4 0x42 0x18 0xf7 0xd3 + +# CHECK: bextrq %r12, (%rax), %r10 +0xc4 0x62 0x98 0xf7 0x10 + +# CHECK: bextrq %r12, %r11, %r10 +0xc4 0x42 0x98 0xf7 0xd3 + +# CHECK: bzhil %r12d, (%rax), %r10d +0xc4 0x62 0x18 0xf5 0x10 + +# CHECK: bzhil %r12d, %r11d, %r10d +0xc4 0x42 0x18 0xf5 0xd3 + +# CHECK: bzhiq %r12, (%rax), %r10 +0xc4 0x62 0x98 0xf5 0x10 + +# CHECK: bzhiq %r12, %r11, %r10 +0xc4 0x42 0x98 0xf5 0xd3 + +# CHECK: pextl %r12d, %r11d, %r10d +0xc4 0x42 0x22 0xf5 0xd4 + +# CHECK: pextl (%rax), %r11d, %r10d +0xc4 0x62 0x22 0xf5 0x10 + +# CHECK: pextq %r12, %r11, %r10 +0xc4 0x42 0xa2 0xf5 0xd4 + +# CHECK: pextq (%rax), %r11, %r10 +0xc4 0x62 0xa2 0xf5 0x10 + +# CHECK: pdepl %r12d, %r11d, %r10d +0xc4 0x42 0x23 0xf5 0xd4 + +# CHECK: pdepl (%rax), %r11d, %r10d +0xc4 0x62 0x23 0xf5 0x10 + +# CHECK: pdepq %r12, %r11, %r10 +0xc4 0x42 0xa3 0xf5 0xd4 + +# CHECK: pdepq (%rax), %r11, %r10 +0xc4 0x62 0xa3 0xf5 0x10 + +# CHECK: mulxl %r12d, %r11d, %r10d +0xc4 0x42 0x23 0xf6 0xd4 + +# CHECK: mulxl (%rax), %r11d, %r10d +0xc4 0x62 0x23 0xf6 0x10 + +# CHECK: mulxq %r12, %r11, %r10 +0xc4 0x42 0xa3 0xf6 0xd4 + +# CHECK: mulxq (%rax), %r11, %r10 +0xc4 0x62 0xa3 0xf6 0x10 + +# CHECK: rorxl $1, %r12d, %r10d +0xc4 0x43 0x7b 0xf0 0xd4 0x01 + +# CHECK: rorxl $31, (%rax), %r10d +0xc4 0x63 0x7b 0xf0 0x10 0x1f + +# CHECK: rorxq $1, %r12, %r10 +0xc4 0x43 0xfb 0xf0 0xd4 0x01 + +# CHECK: rorxq $63, (%rax), %r10 +0xc4 0x63 0xfb 0xf0 0x10 0x3f + +# CHECK: shlxl %r12d, (%rax), %r10d +0xc4 0x62 0x19 0xf7 0x10 + +# CHECK: shlxl %r12d, %r11d, %r10d +0xc4 0x42 0x19 0xf7 0xd3 + +# CHECK: shlxq %r12, (%rax), %r10 +0xc4 0x62 0x99 0xf7 0x10 + +# CHECK: shlxq %r12, %r11, %r10 +0xc4 0x42 0x99 0xf7 0xd3 + +# CHECK: sarxl %r12d, (%rax), %r10d +0xc4 0x62 0x1a 0xf7 0x10 + +# CHECK: sarxl %r12d, %r11d, %r10d +0xc4 0x42 0x1a 0xf7 0xd3 + +# CHECK: sarxq %r12, (%rax), %r10 +0xc4 0x62 0x9a 0xf7 0x10 + +# CHECK: sarxq %r12, %r11, %r10 +0xc4 0x42 0x9a 0xf7 0xd3 + +# CHECK: shrxl %r12d, (%rax), %r10d +0xc4 0x62 0x1b 0xf7 0x10 + +# CHECK: shrxl %r12d, %r11d, %r10d +0xc4 0x42 0x1b 0xf7 0xd3 + +# CHECK: shrxq %r12, (%rax), %r10 +0xc4 0x62 0x9b 0xf7 0x10 + +# CHECK: shrxq %r12, %r11, %r10 +0xc4 0x42 0x9b 0xf7 0xd3 + +# CHECK: vfmadd132ps %xmm11, %xmm12, %xmm10 +0xc4 0x42 0x19 0x98 0xd3 + +# CHECK: vfmadd132pd %xmm11, %xmm12, %xmm10 +0xc4 0x42 0x99 0x98 0xd3 + +# CHECK: vfmadd132ps %ymm11, %ymm12, %ymm10 +0xc4 0x42 0x1d 0x98 0xd3 + +# CHECK: vfmadd132pd %ymm11, %ymm12, %ymm10 +0xc4 0x42 0x9d 0x98 0xd3 + +# CHECK: vfmadd132ps (%rax), %xmm12, %xmm10 +0xc4 0x62 0x19 0x98 0x10 + +# CHECK: vfmadd132pd (%rax), %xmm12, %xmm10 +0xc4 0x62 0x99 0x98 0x10 + +# CHECK: vfmadd132ps (%rax), %ymm12, %ymm10 +0xc4 0x62 0x1d 0x98 0x10 + +# CHECK: vfmadd132pd (%rax), %ymm12, %ymm10 +0xc4 0x62 0x9d 0x98 0x10 + +# CHECK: vfmadd132ss %xmm11, %xmm12, %xmm10 +0xc4 0x42 0x19 0x99 0xd3 + +# CHECK: vfmadd132sd %xmm11, %xmm12, %xmm10 +0xc4 0x42 0x99 0x99 0xd3 + +# CHECK: vfmadd132ss (%rax), %xmm12, %xmm10 +0xc4 0x62 0x19 0x99 0x10 + +# CHECK: vfmadd132sd (%rax), %xmm12, %xmm10 +0xc4 0x62 0x99 0x99 0x10 + +# CHECK: vfmaddss (%rcx), %xmm1, %xmm0, %xmm0 +0xc4 0xe3 0xf9 0x6a 0x01 0x10 + +# CHECK: vfmaddss %xmm1, (%rcx), %xmm0, %xmm0 +0xc4 0xe3 0x79 0x6a 0x01 0x10 + +# CHECK: vpermil2ps $1, 4(%rax), %xmm2, %xmm3, %xmm0 +0xc4 0xe3 0xe1 0x48 0x40 0x04 0x21 + +# rdar://8812056 lldb doesn't print the x86 lock prefix when disassembling +# CHECK: lock +# CHECK-NEXT: xaddq %rcx, %rbx +0xf0 0x48 0x0f 0xc1 0xcb diff --git a/test/MC/Disassembler/X86/x86-32.txt b/test/MC/Disassembler/X86/x86-32.txt index c4437ba..739fa6a 100644 --- a/test/MC/Disassembler/X86/x86-32.txt +++ b/test/MC/Disassembler/X86/x86-32.txt @@ -11,6 +11,12 @@ # CHECK: calll 0xff 0xd0 +# CHECK: jecxz -127 +0xe3 0x81 + +# CHECK: jcxz -127 +0x67 0xe3 0x81 + # CHECK: incl 0x40 @@ -63,6 +69,9 @@ # CHECK: vmcall 0x0f 0x01 0xc1 +# CHECK: vmfunc +0x0f 0x01 0xd4 + # CHECK: vmlaunch 0x0f 0x01 0xc2 @@ -87,6 +96,30 @@ # CHECK: vmptrst 0x0f 0xc7 0x38 +# CHECK: vmrun +0x0f 0x01 0xd8 + +# CHECK: vmmcall +0x0f 0x01 0xd9 + +# CHECK: vmload +0x0f 0x01 0xda + +# CHECK: vmsave +0x0f 0x01 0xdb + +# CHECK: stgi +0x0f 0x01 0xdc + +# CHECK: clgi +0x0f 0x01 0xdd + +# CHECK: skinit +0x0f 0x01 0xde + +# CHECK: invlpga +0x0f 0x01 0xdf + # CHECK: movl $0, -4(%ebp) 0xc7 0x45 0xfc 0x00 0x00 0x00 0x00 @@ -328,6 +361,9 @@ # CHECK: invvpid (%eax), %eax 0x66 0x0f 0x38 0x81 0x00 +# CHECK: invpcid (%eax), %eax +0x66 0x0f 0x38 0x82 0x00 + # CHECK: nop 0x90 @@ -385,6 +421,18 @@ # CHECK: movl %eax, 0 0xa3 0x00 0x00 0x00 0x00 +# CHECK: cmpordpd %xmm7, %xmm0 +0x66 0x0f 0xc2 0xc7 0x07 + +# CHECK: cmpordps %xmm7, %xmm0 +0x0f 0xc2 0xc7 0x07 + +# CHECK: cmpordsd %xmm7, %xmm0 +0xf2 0x0f 0xc2 0xc7 0x07 + +# CHECK: cmpordss %xmm7, %xmm0 +0xf3 0x0f 0xc2 0xc7 0x07 + # CHECK: vaddps %xmm3, %xmm7, %xmm0 0xc4 0xe1 0x00 0x58 0xc3 @@ -495,3 +543,72 @@ # CHECK: andnl (%eax), %edi, %eax 0xc4 0xe2 0x80 0xf2 0x00 + +# CHECK: blsrl (%eax), %edi +0xc4 0xe2 0x40 0xf3 0x08 + +# CHECK: blsmskl (%eax), %edi +0xc4 0xe2 0x40 0xf3 0x10 + +# CHECK: blsil (%eax), %edi +0xc4 0xe2 0x40 0xf3 0x18 + +# CHECK: bextrl %esi, (%eax), %edx +0xc4 0xe2 0x08 0xf7 0x10 + +# CHECK: bextrl %esi, %ebx, %edx +0xc4 0xe2 0x08 0xf7 0xd3 + +# CHECK: bzhil %esi, (%eax), %edx +0xc4 0xe2 0x08 0xf5 0x10 + +# CHECK: bzhil %esi, %ebx, %edx +0xc4 0xe2 0x08 0xf5 0xd3 + +# CHECK: pextl %esp, %ecx, %edx +0xc4 0xe2 0x72 0xf5 0xd4 + +# CHECK: pextl (%eax), %ecx, %edx +0xc4 0xe2 0x72 0xf5 0x10 + +# CHECK: pdepl %esp, %ecx, %edx +0xc4 0xe2 0x73 0xf5 0xd4 + +# CHECK: pdepl (%eax), %ecx, %edx +0xc4 0xe2 0x73 0xf5 0x10 + +# CHECK: mulxl %esp, %ecx, %edx +0xc4 0xe2 0x73 0xf6 0xd4 + +# CHECK: mulxl (%eax), %ecx, %edx +0xc4 0xe2 0x73 0xf6 0x10 + +# CHECK: mulxl %esp, %ecx, %edx +0xc4 0xe2 0xf3 0xf6 0xd4 + +# CHECK: mulxl (%eax), %ecx, %edx +0xc4 0xe2 0xf3 0xf6 0x10 + +# CHECK: rorxl $1, %esp, %edx +0xc4 0xe3 0x7b 0xf0 0xd4 0x01 + +# CHECK: rorxl $31, (%eax), %edx +0xc4 0xe3 0x7b 0xf0 0x10 0x1f + +# CHECK: shlxl %esi, (%eax), %edx +0xc4 0xe2 0x09 0xf7 0x10 + +# CHECK: shlxl %esi, %ebx, %edx +0xc4 0xe2 0x09 0xf7 0xd3 + +# CHECK: sarxl %esi, (%eax), %edx +0xc4 0xe2 0x0a 0xf7 0x10 + +# CHECK: sarxl %esi, %ebx, %edx +0xc4 0xe2 0x0a 0xf7 0xd3 + +# CHECK: shrxl %esi, (%eax), %edx +0xc4 0xe2 0x0b 0xf7 0x10 + +# CHECK: shrxl %esi, %ebx, %edx +0xc4 0xe2 0x0b 0xf7 0xd3 diff --git a/test/MC/Disassembler/X86/x86-64.txt b/test/MC/Disassembler/X86/x86-64.txt new file mode 100644 index 0000000..f4b8f46 --- /dev/null +++ b/test/MC/Disassembler/X86/x86-64.txt @@ -0,0 +1,63 @@ +# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s + +# Coverage + +# CHECK: vcmptrue_usps +0xc5 0x04 0xc2 0xc7 0x1f + +# CHECK: vcmptrue_uspd +0xc5 0x05 0xc2 0xc7 0x1f + +# CHECK: vcmptrue_usss +0xc5 0x06 0xc2 0xc7 0x1f + +# CHECK: vcmptrue_ussd +0xc5 0x07 0xc2 0xc7 0x1f + +# CHECK: vcmpeq_uqps +0xc5 0x04 0xc2 0xc7 0x08 + +# CHECK: vcmpeq_uqpd +0xc5 0x05 0xc2 0xc7 0x08 + +# CHECK: vcmpeq_uqss +0xc5 0x06 0xc2 0xc7 0x08 + +# CHECK: vcmpeq_uqsd +0xc5 0x07 0xc2 0xc7 0x08 + +# CHECK: vcmpeqps +0xc5 0x04 0xc2 0xc7 0x00 + +# CHECK: vcmpeqpd +0xc5 0x05 0xc2 0xc7 0x00 + +# CHECK: vcmpeqss +0xc5 0x06 0xc2 0xc7 0x00 + +# CHECK: vcmpeqsd +0xc5 0x07 0xc2 0xc7 0x00 + +# CHECK: cmpeqps +0x0f 0xc2 0xc7 0x00 + +# CHECK: cmpeqpd +0x66 0x0f 0xc2 0xc7 0x00 + +# CHECK: cmpeqss +0xf3 0x0f 0xc2 0xc7 0x00 + +# CHECK: cmpeqsd +0xf2 0x0f 0xc2 0xc7 0x00 + +# CHECK: cmpordps +0x0f 0xc2 0xc7 0x07 + +# CHECK: cmpordpd +0x66 0x0f 0xc2 0xc7 0x07 + +# CHECK: cmpordss +0xf3 0x0f 0xc2 0xc7 0x07 + +# CHECK: cmpordsd +0xf2 0x0f 0xc2 0xc7 0x07 diff --git a/test/MC/ELF/cfi-escape.s b/test/MC/ELF/cfi-escape.s new file mode 100644 index 0000000..3a5af00 --- /dev/null +++ b/test/MC/ELF/cfi-escape.s @@ -0,0 +1,42 @@ +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s + +f: + .cfi_startproc + nop + .cfi_escape 0x15, 7, 0x7f # DW_CFA_val_offset_sf, %esp, 8/-8 + nop + .cfi_endproc + +// CHECK: # Section 4 +// CHECK-NEXT: (('sh_name', 0x00000011) # '.eh_frame' +// CHECK-NEXT: ('sh_type', 0x00000001) +// CHECK-NEXT: ('sh_flags', 0x0000000000000002) +// CHECK-NEXT: ('sh_addr', 0x0000000000000000) +// CHECK-NEXT: ('sh_offset', 0x0000000000000048) +// CHECK-NEXT: ('sh_size', 0x0000000000000030) +// CHECK-NEXT: ('sh_link', 0x00000000) +// CHECK-NEXT: ('sh_info', 0x00000000) +// CHECK-NEXT: ('sh_addralign', 0x0000000000000008) +// CHECK-NEXT: ('sh_entsize', 0x0000000000000000) +// CHECK-NEXT: ('_section_data', '14000000 00000000 017a5200 01781001 1b0c0708 90010000 14000000 1c000000 00000000 02000000 00411507 7f000000') +// CHECK-NEXT: ), +// CHECK-NEXT: # Section 5 +// CHECK-NEXT: (('sh_name', 0x0000000c) # '.rela.eh_frame' +// CHECK-NEXT: ('sh_type', 0x00000004) +// CHECK-NEXT: ('sh_flags', 0x0000000000000000) +// CHECK-NEXT: ('sh_addr', 0x0000000000000000) +// CHECK-NEXT: ('sh_offset', 0x0000000000000390) +// CHECK-NEXT: ('sh_size', 0x0000000000000018) +// CHECK-NEXT: ('sh_link', 0x00000007) +// CHECK-NEXT: ('sh_info', 0x00000004) +// CHECK-NEXT: ('sh_addralign', 0x0000000000000008) +// CHECK-NEXT: ('sh_entsize', 0x0000000000000018) +// CHECK-NEXT: ('_relocations', [ +// CHECK-NEXT: # Relocation 0 +// CHECK-NEXT: (('r_offset', 0x0000000000000020) +// CHECK-NEXT: ('r_sym', 0x00000002) +// CHECK-NEXT: ('r_type', 0x00000002) +// CHECK-NEXT: ('r_addend', 0x0000000000000000) +// CHECK-NEXT: ), +// CHECK-NEXT: ]) +// CHECK-NEXT: ), diff --git a/test/MC/ELF/cfi-restore.s b/test/MC/ELF/cfi-restore.s new file mode 100644 index 0000000..0fc3129 --- /dev/null +++ b/test/MC/ELF/cfi-restore.s @@ -0,0 +1,42 @@ +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s + +f: + .cfi_startproc + nop + .cfi_restore %rbp + nop + .cfi_endproc + +// CHECK: # Section 4 +// CHECK-NEXT: (('sh_name', 0x00000011) # '.eh_frame' +// CHECK-NEXT: ('sh_type', 0x00000001) +// CHECK-NEXT: ('sh_flags', 0x0000000000000002) +// CHECK-NEXT: ('sh_addr', 0x0000000000000000) +// CHECK-NEXT: ('sh_offset', 0x0000000000000048) +// CHECK-NEXT: ('sh_size', 0x0000000000000030) +// CHECK-NEXT: ('sh_link', 0x00000000) +// CHECK-NEXT: ('sh_info', 0x00000000) +// CHECK-NEXT: ('sh_addralign', 0x0000000000000008) +// CHECK-NEXT: ('sh_entsize', 0x0000000000000000) +// CHECK-NEXT: ('_section_data', '14000000 00000000 017a5200 01781001 1b0c0708 90010000 14000000 1c000000 00000000 02000000 0041c600 00000000') +// CHECK-NEXT: ), +// CHECK-NEXT: # Section 5 +// CHECK-NEXT: (('sh_name', 0x0000000c) # '.rela.eh_frame' +// CHECK-NEXT: ('sh_type', 0x00000004) +// CHECK-NEXT: ('sh_flags', 0x0000000000000000) +// CHECK-NEXT: ('sh_addr', 0x0000000000000000) +// CHECK-NEXT: ('sh_offset', 0x0000000000000390) +// CHECK-NEXT: ('sh_size', 0x0000000000000018) +// CHECK-NEXT: ('sh_link', 0x00000007) +// CHECK-NEXT: ('sh_info', 0x00000004) +// CHECK-NEXT: ('sh_addralign', 0x0000000000000008) +// CHECK-NEXT: ('sh_entsize', 0x0000000000000018) +// CHECK-NEXT: ('_relocations', [ +// CHECK-NEXT: # Relocation 0 +// CHECK-NEXT: (('r_offset', 0x0000000000000020) +// CHECK-NEXT: ('r_sym', 0x00000002) +// CHECK-NEXT: ('r_type', 0x00000002) +// CHECK-NEXT: ('r_addend', 0x0000000000000000) +// CHECK-NEXT: ), +// CHECK-NEXT: ]) +// CHECK-NEXT: ), diff --git a/test/MC/ELF/cfi-signal-frame.s b/test/MC/ELF/cfi-signal-frame.s new file mode 100644 index 0000000..cf6d160 --- /dev/null +++ b/test/MC/ELF/cfi-signal-frame.s @@ -0,0 +1,23 @@ +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s + +f: + .cfi_startproc + .cfi_signal_frame + .cfi_endproc + +g: + .cfi_startproc + .cfi_endproc + +// CHECK: (('sh_name', 0x00000011) # '.eh_frame' +// CHECK-NEXT: ('sh_type', 0x00000001) +// CHECK-NEXT: ('sh_flags', 0x0000000000000002) +// CHECK-NEXT: ('sh_addr', 0x0000000000000000) +// CHECK-NEXT: ('sh_offset', 0x0000000000000040) +// CHECK-NEXT: ('sh_size', 0x0000000000000058) +// CHECK-NEXT: ('sh_link', 0x00000000) +// CHECK-NEXT: ('sh_info', 0x00000000) +// CHECK-NEXT: ('sh_addralign', 0x0000000000000008) +// CHECK-NEXT: ('sh_entsize', 0x0000000000000000) +// CHECK-NEXT: ('_section_data', '14000000 00000000 017a5253 00017810 011b0c07 08900100 10000000 1c000000 00000000 00000000 00000000 14000000 00000000 017a5200 01781001 1b0c0708 90010000 10000000 1c000000 00000000 00000000 00000000') +// CHECK-NEXT: ), diff --git a/test/MC/ELF/dg.exp b/test/MC/ELF/dg.exp deleted file mode 100644 index d46d700..0000000 --- a/test/MC/ELF/dg.exp +++ /dev/null @@ -1,5 +0,0 @@ -load_lib llvm.exp - -if { [llvm_supports_target X86] } { - RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,s}]] -} diff --git a/test/MC/ELF/gen-dwarf.s b/test/MC/ELF/gen-dwarf.s new file mode 100644 index 0000000..b090e08 --- /dev/null +++ b/test/MC/ELF/gen-dwarf.s @@ -0,0 +1,70 @@ +// RUN: llvm-mc -g -triple i686-pc-linux-gnu %s -filetype=obj -o - | elf-dump | FileCheck %s + + +// Test that on ELF the debug info has a relocation to debug_abbrev and one to +// to debug_line. + + + .text + .globl foo + .type foo, @function + .align 4 +foo: + ret + .size foo, .-foo + +// Section 4 is .debug_line +// CHECK: # Section 4 +// CHECK-NEXT: # '.debug_line' + + + +// The two relocations, one to symbol 6 and one to 4 +// CHECK: # '.rel.debug_info' +// CHECK-NEXT: ('sh_type', +// CHECK-NEXT: ('sh_flags' +// CHECK-NEXT: ('sh_addr', +// CHECK-NEXT: ('sh_offset', +// CHECK-NEXT: ('sh_size', +// CHECK-NEXT: ('sh_link', +// CHECK-NEXT: ('sh_info', +// CHECK-NEXT: ('sh_addralign', +// CHECK-NEXT: ('sh_entsize', +// CHECK-NEXT: ('_relocations', [ +// CHECK-NEXT: # Relocation 0 +// CHECK-NEXT: (('r_offset', 0x00000006) +// CHECK-NEXT: ('r_sym', 0x000006) +// CHECK-NEXT: ('r_type', 0x01) +// CHECK-NEXT: ), +// CHECK-NEXT: # Relocation 1 +// CHECK-NEXT: (('r_offset', 0x0000000c) +// CHECK-NEXT: ('r_sym', 0x000004) +// CHECK-NEXT: ('r_type', 0x01) +// CHECK-NEXT: ), + + +// Section 8 is .debug_abbrev +// CHECK: # Section 8 +// CHECK-NEXT: (('sh_name', 0x00000001) # '.debug_abbrev' + +// Symbol 4 is section 4 (.debug_line) +// CHECK: # Symbol 4 +// CHECK-NEXT: (('st_name', 0x00000000) # '' +// CHECK-NEXT: ('st_value', 0x00000000) +// CHECK-NEXT: ('st_size', 0x00000000) +// CHECK-NEXT: ('st_bind', 0x0) +// CHECK-NEXT: ('st_type', 0x3) +// CHECK-NEXT: ('st_other', 0x00) +// CHECK-NEXT: ('st_shndx', 0x0004) +// CHECK-NEXT: ), + +// Symbol 6 is section 8 (.debug_abbrev) +// CHECK: # Symbol 6 +// CHECK-NEXT: (('st_name', 0x00000000) # '' +// CHECK-NEXT: ('st_value', 0x00000000) +// CHECK-NEXT: ('st_size', 0x00000000) +// CHECK-NEXT: ('st_bind', 0x0) +// CHECK-NEXT: ('st_type', 0x3) +// CHECK-NEXT: ('st_other', 0x00) +// CHECK-NEXT: ('st_shndx', 0x0008) +// CHECK-NEXT: ), diff --git a/test/MC/ELF/global-offset.s b/test/MC/ELF/global-offset.s index 8cc5dbb..81ae5d7 100644 --- a/test/MC/ELF/global-offset.s +++ b/test/MC/ELF/global-offset.s @@ -6,6 +6,10 @@ addl $_GLOBAL_OFFSET_TABLE_, %ebx leal _GLOBAL_OFFSET_TABLE_(%ebx), %ebx +// But not in this case +foo: + addl _GLOBAL_OFFSET_TABLE_-foo,%ebx + // CHECK: ('sh_name', 0x00000005) # '.text' // CHECK-NEXT: ('sh_type', // CHECK-NEXT: ('sh_flags', @@ -16,4 +20,4 @@ // CHECK-NEXT: ('sh_info', // CHECK-NEXT: ('sh_addralign', // CHECK-NEXT: ('sh_entsize', -// CHECK-NEXT: ('_section_data', '81c30200 00008d9b 02000000') +// CHECK-NEXT: ('_section_data', '81c30200 00008d9b 02000000 031d0200 0000') diff --git a/test/MC/ELF/lit.local.cfg b/test/MC/ELF/lit.local.cfg new file mode 100644 index 0000000..56bf008 --- /dev/null +++ b/test/MC/ELF/lit.local.cfg @@ -0,0 +1,6 @@ +config.suffixes = ['.ll', '.s'] + +targets = set(config.root.targets_to_build.split()) +if not 'X86' in targets: + config.unsupported = True + diff --git a/test/MC/ELF/many-section.s b/test/MC/ELF/many-section.s index e7e723a..b729e66 100644 --- a/test/MC/ELF/many-section.s +++ b/test/MC/ELF/many-section.s @@ -1,5 +1,5 @@ // RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o %t -// RUN: llvm-nm %t | FileCheck %s +// RUN: llvm-nm -a %t | FileCheck %s // CHECK: s000a // CHECK-NOT: U diff --git a/test/MC/ELF/relocation-386.s b/test/MC/ELF/relocation-386.s index 4421763..85da2eb 100644 --- a/test/MC/ELF/relocation-386.s +++ b/test/MC/ELF/relocation-386.s @@ -160,6 +160,18 @@ // CHECK-NEXT: ('r_sym', 0x00000d) // CHECK-NEXT: ('r_type', 0x21) // CHECK-NEXT: ), +// Relocation 25 (_GLOBAL_OFFSET_TABLE_-bar2) is of type R_386_GOTPC. +// CHECK-NEXT: Relocation 25 +// CHECK-NEXT: (('r_offset', 0x00000094) +// CHECK-NEXT: ('r_sym', 0x00000b) +// CHECK-NEXT: ('r_type', 0x0a) +// CHECK-NEXT: ), +// Relocation 26 (und_symbol-bar2) is of type R_386_PC32 +// CHECK-NEXT: Relocation 26 +// CHECK-NEXT: (('r_offset', 0x0000009a) +// CHECK-NEXT: ('r_sym', 0x00000e) +// CHECK-NEXT: ('r_type', 0x02) +// CHECK-NEXT: ), // Section 4 is bss // CHECK: # Section 4 @@ -225,6 +237,8 @@ bar2: movl zed@DTPOFF(%eax), %eax pushl $bar addl foo@GOTTPOFF(%edx), %eax + subl _GLOBAL_OFFSET_TABLE_-bar2, %ebx + leal und_symbol-bar2(%edx),%ecx .section zedsec,"awT",@progbits zed: diff --git a/test/MC/ELF/tls-i386.s b/test/MC/ELF/tls-i386.s index 197418d..922d4c6 100644 --- a/test/MC/ELF/tls-i386.s +++ b/test/MC/ELF/tls-i386.s @@ -9,6 +9,13 @@ movl foo5@TPOFF(%eax), %eax movl foo6@DTPOFF(%eax), %eax movl foo7@INDNTPOFF, %eax + .long foo8@NTPOFF + .long foo9@GOTNTPOFF + .long fooA@TLSGD + .long fooB@TLSLDM + .long fooC@TPOFF + .long fooD@DTPOFF + .long fooE@INDNTPOFF // CHECK: (('st_name', 0x00000001) # 'foo1' // CHECK-NEXT: ('st_value', 0x00000000) @@ -72,3 +79,67 @@ // CHECK-NEXT: ('st_other', 0x00) // CHECK-NEXT: ('st_shndx', 0x0000) // CHECK-NEXT: ), +// CHECK-NEXT: # Symbol 12 +// CHECK-NEXT: (('st_name', 0x00000024) # 'foo8' +// CHECK-NEXT: ('st_value', 0x00000000) +// CHECK-NEXT: ('st_size', 0x00000000) +// CHECK-NEXT: ('st_bind', 0x1) +// CHECK-NEXT: ('st_type', 0x6) +// CHECK-NEXT: ('st_other', 0x00) +// CHECK-NEXT: ('st_shndx', 0x0000) +// CHECK-NEXT: ), +// CHECK-NEXT: # Symbol 13 +// CHECK-NEXT: (('st_name', 0x00000029) # 'foo9' +// CHECK-NEXT: ('st_value', 0x00000000) +// CHECK-NEXT: ('st_size', 0x00000000) +// CHECK-NEXT: ('st_bind', 0x1) +// CHECK-NEXT: ('st_type', 0x6) +// CHECK-NEXT: ('st_other', 0x00) +// CHECK-NEXT: ('st_shndx', 0x0000) +// CHECK-NEXT: ), +// CHECK-NEXT: # Symbol 14 +// CHECK-NEXT: (('st_name', 0x0000002e) # 'fooA' +// CHECK-NEXT: ('st_value', 0x00000000) +// CHECK-NEXT: ('st_size', 0x00000000) +// CHECK-NEXT: ('st_bind', 0x1) +// CHECK-NEXT: ('st_type', 0x6) +// CHECK-NEXT: ('st_other', 0x00) +// CHECK-NEXT: ('st_shndx', 0x0000) +// CHECK-NEXT: ), +// CHECK-NEXT: # Symbol 15 +// CHECK-NEXT: (('st_name', 0x00000033) # 'fooB' +// CHECK-NEXT: ('st_value', 0x00000000) +// CHECK-NEXT: ('st_size', 0x00000000) +// CHECK-NEXT: ('st_bind', 0x1) +// CHECK-NEXT: ('st_type', 0x6) +// CHECK-NEXT: ('st_other', 0x00) +// CHECK-NEXT: ('st_shndx', 0x0000) +// CHECK-NEXT: ), +// CHECK-NEXT: # Symbol 16 +// CHECK-NEXT: (('st_name', 0x00000038) # 'fooC' +// CHECK-NEXT: ('st_value', 0x00000000) +// CHECK-NEXT: ('st_size', 0x00000000) +// CHECK-NEXT: ('st_bind', 0x1) +// CHECK-NEXT: ('st_type', 0x6) +// CHECK-NEXT: ('st_other', 0x00) +// CHECK-NEXT: ('st_shndx', 0x0000) +// CHECK-NEXT: ), +// CHECK-NEXT: # Symbol 17 +// CHECK-NEXT: (('st_name', 0x0000003d) # 'fooD' +// CHECK-NEXT: ('st_value', 0x00000000) +// CHECK-NEXT: ('st_size', 0x00000000) +// CHECK-NEXT: ('st_bind', 0x1) +// CHECK-NEXT: ('st_type', 0x6) +// CHECK-NEXT: ('st_other', 0x00) +// CHECK-NEXT: ('st_shndx', 0x0000) +// CHECK-NEXT: ), +// CHECK-NEXT: # Symbol 18 +// CHECK-NEXT: (('st_name', 0x00000042) # 'fooE' +// CHECK-NEXT: ('st_value', 0x00000000) +// CHECK-NEXT: ('st_size', 0x00000000) +// CHECK-NEXT: ('st_bind', 0x1) +// CHECK-NEXT: ('st_type', 0x6) +// CHECK-NEXT: ('st_other', 0x00) +// CHECK-NEXT: ('st_shndx', 0x0000) +// CHECK-NEXT: ), + diff --git a/test/MC/ELF/tls.s b/test/MC/ELF/tls.s index d6d7de6..fe2bb4e 100644 --- a/test/MC/ELF/tls.s +++ b/test/MC/ELF/tls.s @@ -5,12 +5,14 @@ leaq foo1@TLSGD(%rip), %rdi leaq foo2@GOTTPOFF(%rip), %rdi leaq foo3@TLSLD(%rip), %rdi - + .long foo4@GOTTPOFF + .long foo5@TLSLD + .long foo6@TLSGD .section .zed,"awT",@progbits foobar: .long 43 -// CHECK: (('st_name', 0x00000010) # 'foobar' +// CHECK: (('st_name', 0x0000001f) # 'foobar' // CHECK-NEXT: ('st_bind', 0x0) // CHECK-NEXT: ('st_type', 0x6) // CHECK-NEXT: ('st_other', 0x00) @@ -46,3 +48,30 @@ foobar: // CHECK-NEXT: ('st_value', 0x0000000000000000) // CHECK-NEXT: ('st_size', 0x0000000000000000) // CHECK-NEXT: ), +// CHECK-NEXT: # Symbol 10 +// CHECK-NEXT: (('st_name', 0x00000010) # 'foo4' +// CHECK-NEXT: ('st_bind', 0x1) +// CHECK-NEXT: ('st_type', 0x6) +// CHECK-NEXT: ('st_other', 0x00) +// CHECK-NEXT: ('st_shndx', 0x0000) +// CHECK-NEXT: ('st_value', 0x0000000000000000) +// CHECK-NEXT: ('st_size', 0x0000000000000000) +// CHECK-NEXT: ), +// CHECK-NEXT: # Symbol 11 +// CHECK-NEXT: (('st_name', 0x00000015) # 'foo5' +// CHECK-NEXT: ('st_bind', 0x1) +// CHECK-NEXT: ('st_type', 0x6) +// CHECK-NEXT: ('st_other', 0x00) +// CHECK-NEXT: ('st_shndx', 0x0000) +// CHECK-NEXT: ('st_value', 0x0000000000000000) +// CHECK-NEXT: ('st_size', 0x0000000000000000) +// CHECK-NEXT: ), +// CHECK-NEXT: # Symbol 12 +// CHECK-NEXT: (('st_name', 0x0000001a) # 'foo6' +// CHECK-NEXT: ('st_bind', 0x1) +// CHECK-NEXT: ('st_type', 0x6) +// CHECK-NEXT: ('st_other', 0x00) +// CHECK-NEXT: ('st_shndx', 0x0000) +// CHECK-NEXT: ('st_value', 0x0000000000000000) +// CHECK-NEXT: ('st_size', 0x0000000000000000) +// CHECK-NEXT: ), diff --git a/test/MC/ELF/type.s b/test/MC/ELF/type.s index 2b25a6b..ec53e4f 100644 --- a/test/MC/ELF/type.s +++ b/test/MC/ELF/type.s @@ -12,6 +12,10 @@ bar: // Test that gnu_unique_object is accepted. .type zed,@gnu_unique_object +ifunc: + .global ifunc + .type ifunc,@gnu_indirect_function + // CHECK: # Symbol 4 // CHECK-NEXT: (('st_name', 0x00000005) # 'bar' // CHECK-NEXT: ('st_bind', 0x1) @@ -30,3 +34,13 @@ bar: // CHECK-NEXT: ('st_value', 0x0000000000000000) // CHECK-NEXT: ('st_size', 0x0000000000000000) // CHECK-NEXT: ), +// CHECK-NEXT: # Symbol 6 +// CHECK-NEXT: (('st_name', 0x00000009) # 'ifunc' +// CHECK-NEXT: ('st_bind', 0x1) +// CHECK-NEXT: ('st_type', 0xa) +// CHECK-NEXT: ('st_other', 0x00) +// CHECK-NEXT: ('st_shndx', 0x0001) +// CHECK-NEXT: ('st_value', 0x0000000000000000) +// CHECK-NEXT: ('st_size', 0x0000000000000000) +// CHECK-NEXT: ), + diff --git a/test/MC/MBlaze/dg.exp b/test/MC/MBlaze/dg.exp deleted file mode 100644 index 0c4e78e..0000000 --- a/test/MC/MBlaze/dg.exp +++ /dev/null @@ -1,5 +0,0 @@ -load_lib llvm.exp - -if { [llvm_supports_target MBlaze] } { - RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp,s}]] -} diff --git a/test/MC/MBlaze/lit.local.cfg b/test/MC/MBlaze/lit.local.cfg new file mode 100644 index 0000000..b0e1d85 --- /dev/null +++ b/test/MC/MBlaze/lit.local.cfg @@ -0,0 +1,6 @@ +config.suffixes = ['.ll', '.c', '.cpp', '.s'] + +targets = set(config.root.targets_to_build.split()) +if not 'MBlaze' in targets: + config.unsupported = True + diff --git a/test/MC/ARM/darwin-ARM-reloc.s b/test/MC/MachO/ARM/darwin-ARM-reloc.s index 86b45e0..b98c80c 100644 --- a/test/MC/ARM/darwin-ARM-reloc.s +++ b/test/MC/MachO/ARM/darwin-ARM-reloc.s @@ -12,19 +12,21 @@ _f1: .data _d0: -Ld0_0: +Ld0_0: .long Lsc0_0 - Ld0_0 - + .section __TEXT,__cstring,cstring_literals Lsc0_0: .long 0 + .subsections_via_symbols + @ CHECK: ('cputype', 12) @ CHECK: ('cpusubtype', 9) @ CHECK: ('filetype', 1) @ CHECK: ('num_load_commands', 3) @ CHECK: ('load_commands_size', 364) -@ CHECK: ('flag', 0) +@ CHECK: ('flag', 8192) @ CHECK: ('load_commands', [ @ CHECK: # Load Command 0 @ CHECK: (('command', 1) diff --git a/test/MC/ARM/darwin-Thumb-reloc.s b/test/MC/MachO/ARM/darwin-Thumb-reloc.s index 567573d..567573d 100644 --- a/test/MC/ARM/darwin-Thumb-reloc.s +++ b/test/MC/MachO/ARM/darwin-Thumb-reloc.s diff --git a/test/MC/MachO/ARM/empty-function-nop.ll b/test/MC/MachO/ARM/empty-function-nop.ll new file mode 100644 index 0000000..ef86ebc --- /dev/null +++ b/test/MC/MachO/ARM/empty-function-nop.ll @@ -0,0 +1,15 @@ +; RUN: llc < %s -filetype=obj -mtriple=thumbv6-apple-darwin -o - | macho-dump --dump-section-data | FileCheck -check-prefix=CHECK-T1 %s +; RUN: llc < %s -filetype=obj -mtriple=thumbv7-apple-darwin -o - | macho-dump --dump-section-data | FileCheck -check-prefix=CHECK-T2 %s +; RUN: llc < %s -filetype=obj -mtriple=armv6-apple-darwin -o - | macho-dump --dump-section-data | FileCheck -check-prefix=CHECK-ARM %s +; RUN: llc < %s -filetype=obj -mtriple=armv7-apple-darwin -o - | macho-dump --dump-section-data | FileCheck -check-prefix=CHECK-ARMV7 %s + +; Empty functions need a NOP in them for MachO to prevent DWARF FDEs from +; getting all mucked up. See lib/CodeGen/AsmPrinter/AsmPrinter.cpp for +; details. +define internal fastcc void @empty_function() { + unreachable +} +; CHECK-T1: ('_section_data', 'c046') +; CHECK-T2: ('_section_data', '00bf') +; CHECK-ARM: ('_section_data', '0000a0e1') +; CHECK-ARMV7: ('_section_data', '00f020e3') diff --git a/test/MC/MachO/ARM/lit.local.cfg b/test/MC/MachO/ARM/lit.local.cfg new file mode 100644 index 0000000..8976463 --- /dev/null +++ b/test/MC/MachO/ARM/lit.local.cfg @@ -0,0 +1,6 @@ +config.suffixes = ['.s'] + +targets = set(config.root.targets_to_build.split()) +if not 'ARM' in targets: + config.unsupported = True + diff --git a/test/MC/MachO/ARM/no-subsections-reloc.s b/test/MC/MachO/ARM/no-subsections-reloc.s new file mode 100644 index 0000000..7701c59 --- /dev/null +++ b/test/MC/MachO/ARM/no-subsections-reloc.s @@ -0,0 +1,18 @@ +@ RUN: llvm-mc -n -triple thumbv7-apple-darwin10 %s -filetype=obj -o %t.obj +@ RUN: macho-dump --dump-section-data < %t.obj > %t.dump +@ RUN: FileCheck < %t.dump %s + +@ When not using subsections-via-symbols, references to non-local symbols +@ in the same section can be resolved at assembly time w/o relocations. + + .syntax unified + .text + .thumb + .thumb_func _foo +_foo: + ldr r3, bar +bar: + .long 0 + +@ CHECK: 'num_reloc', 0 +@ CHECK: '_section_data', 'dff80030 00000000' diff --git a/test/MC/ARM/nop-armv4-padding.s b/test/MC/MachO/ARM/nop-armv4-padding.s index 8f646db..8f646db 100644 --- a/test/MC/ARM/nop-armv4-padding.s +++ b/test/MC/MachO/ARM/nop-armv4-padding.s diff --git a/test/MC/ARM/nop-armv6t2-padding.s b/test/MC/MachO/ARM/nop-armv6t2-padding.s index 0e25718..c38ad2d 100644 --- a/test/MC/ARM/nop-armv6t2-padding.s +++ b/test/MC/MachO/ARM/nop-armv6t2-padding.s @@ -7,4 +7,4 @@ x: .align 4 add r0, r1, r2 -@ CHECK: ('_section_data', '020081e0 007820e3 007820e3 007820e3 020081e0') +@ CHECK: ('_section_data', '020081e0 00f020e3 00f020e3 00f020e3 020081e0') diff --git a/test/MC/ARM/nop-thumb-padding.s b/test/MC/MachO/ARM/nop-thumb-padding.s index 1e173f1..1e173f1 100644 --- a/test/MC/ARM/nop-thumb-padding.s +++ b/test/MC/MachO/ARM/nop-thumb-padding.s diff --git a/test/MC/ARM/nop-thumb2-padding.s b/test/MC/MachO/ARM/nop-thumb2-padding.s index a8aa3a1..a8aa3a1 100644 --- a/test/MC/ARM/nop-thumb2-padding.s +++ b/test/MC/MachO/ARM/nop-thumb2-padding.s diff --git a/test/MC/MachO/ARM/relax-thumb-ldr-literal.s b/test/MC/MachO/ARM/relax-thumb-ldr-literal.s new file mode 100644 index 0000000..8d26f6d --- /dev/null +++ b/test/MC/MachO/ARM/relax-thumb-ldr-literal.s @@ -0,0 +1,13 @@ +@ RUN: llvm-mc -n -triple thumbv7-apple-darwin10 %s -filetype=obj -o %t.obj +@ RUN: macho-dump --dump-section-data < %t.obj > %t.dump +@ RUN: FileCheck < %t.dump %s + + .syntax unified + .text + .thumb + .thumb_func _foo +_foo: + ldr r2, (_foo - 4) + +@ CHECK: ('num_reloc', 0) +@ CHECK: ('_section_data', '5ff80820') diff --git a/test/MC/MachO/ARM/relax-thumb2-branches.s b/test/MC/MachO/ARM/relax-thumb2-branches.s new file mode 100644 index 0000000..7916d42 --- /dev/null +++ b/test/MC/MachO/ARM/relax-thumb2-branches.s @@ -0,0 +1,14 @@ +@ RUN: llvm-mc -triple=thumbv7-apple-darwin -show-encoding %s -filetype=obj -o - | macho-dump --dump-section-data | FileCheck %s + + ble Lfoo @ wide encoding + + .space 258 +Lfoo: + nop + + ble Lbaz @ narrow encoding + .space 256 +Lbaz: + +@ CHECK: '_section_data', '40f38180 +@ CHECK: 000000bf 7fdd diff --git a/test/MC/MachO/ARM/static-movt-relocs.s b/test/MC/MachO/ARM/static-movt-relocs.s new file mode 100644 index 0000000..dce5683 --- /dev/null +++ b/test/MC/MachO/ARM/static-movt-relocs.s @@ -0,0 +1,23 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumbv7-apple-darwin10 -filetype=obj -o - < %s | macho-dump | FileCheck %s + .thumb + .thumb_func foo +foo: + movw r0, :lower16:(bar + 16) + movt r0, :upper16:(bar + 16) + bx r0 + + +@ CHECK: ('_relocations', [ +@ CHECK: # Relocation 0 +@ CHECK: (('word-0', 0x4), +@ CHECK: ('word-1', 0x8e000001)), +@ CHECK: # Relocation 1 +@ CHECK: (('word-0', 0x10), +@ CHECK: ('word-1', 0x16ffffff)), +@ CHECK: # Relocation 2 +@ CHECK: (('word-0', 0x0), +@ CHECK: ('word-1', 0x8c000001)), +@ CHECK: # Relocation 3 +@ CHECK: (('word-0', 0x0), +@ CHECK: ('word-1', 0x14ffffff)), +@ CHECK: ]) diff --git a/test/MC/MachO/ARM/thumb2-function-relative-load.s b/test/MC/MachO/ARM/thumb2-function-relative-load.s new file mode 100644 index 0000000..622007d --- /dev/null +++ b/test/MC/MachO/ARM/thumb2-function-relative-load.s @@ -0,0 +1,13 @@ +@ RUN: llvm-mc -n -triple thumbv7-apple-darwin10 %s -filetype=obj -o %t.obj +@ RUN: macho-dump --dump-section-data < %t.obj > %t.dump +@ RUN: FileCheck < %t.dump %s + .syntax unified + .text + .thumb + .thumb_func _foo +_foo: + ldr lr, (_foo - 4) + + .subsections_via_symbols + +@ CHECK: ('_section_data', '5ff808e0') diff --git a/test/MC/ARM/thumb2-movt-fixup.s b/test/MC/MachO/ARM/thumb2-movt-fixup.s index ddd95b5..ddd95b5 100644 --- a/test/MC/ARM/thumb2-movt-fixup.s +++ b/test/MC/MachO/ARM/thumb2-movt-fixup.s diff --git a/test/MC/MachO/darwin-x86_64-diff-reloc-assign.s b/test/MC/MachO/darwin-x86_64-diff-reloc-assign.s new file mode 100644 index 0000000..49cfa41 --- /dev/null +++ b/test/MC/MachO/darwin-x86_64-diff-reloc-assign.s @@ -0,0 +1,27 @@ +// RUN: llvm-mc -triple x86_64-apple-darwin9 %s -filetype=obj -o - | macho-dump --dump-section-data | FileCheck %s + +// Test case for rdar://10743265 + +// This tests that this expression does not cause a crash and produces two +// relocation entries: +// Relocation information (__TEXT,__text) 2 entries +// address pcrel length extern type scattered symbolnum/value +// 00000000 False long True SUB False _base +// 00000000 False long True UNSIGND False _start_ap_2 + +_base = . + +.long (0x2000) + _start_ap_2 - _base +.word 0 + +_start_ap_2: + cli + +// CHECK: ('_relocations', [ +// CHECK: # Relocation 0 +// CHECK: (('word-0', 0x0), +// CHECK: ('word-1', 0x5c000000)), +// CHECK: # Relocation 1 +// CHECK: (('word-0', 0x0), +// CHECK: ('word-1', 0xc000001)), +// CHECK: ]) diff --git a/test/MC/MachO/dg.exp b/test/MC/MachO/dg.exp deleted file mode 100644 index ca6aefe..0000000 --- a/test/MC/MachO/dg.exp +++ /dev/null @@ -1,6 +0,0 @@ -load_lib llvm.exp - -if { [llvm_supports_target X86] } { - RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{s}]] -} - diff --git a/test/MC/MachO/file.s b/test/MC/MachO/file.s new file mode 100644 index 0000000..0168747 --- /dev/null +++ b/test/MC/MachO/file.s @@ -0,0 +1,22 @@ +// RUN: llvm-mc -triple i386-apple-darwin9 %s -filetype=obj -o - | macho-dump --dump-section-data | FileCheck %s + + .file 1 "dir/foo" + nop + +// CHECK: ('_section_data', '90') +// CHECK-NEXT: # Section 1 +// CHECK-NEXT: (('section_name', '__debug_line\x00\x00\x00\x00') +// CHECK-NEXT: ('segment_name', '__DWARF\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK-NEXT: ('address', 1) +// CHECK-NEXT: ('size', 45) +// CHECK-NEXT: ('offset', 221) +// CHECK-NEXT: ('alignment', 0) +// CHECK-NEXT: ('reloc_offset', 0) +// CHECK-NEXT: ('num_reloc', 0) +// CHECK-NEXT: ('flags', 0x2000000) +// CHECK-NEXT: ('reserved1', 0) +// CHECK-NEXT: ('reserved2', 0) +// CHECK-NEXT: ), +// CHECK-NEXT: ('_relocations', [ +// CHECK-NEXT: ]) +// CHECK-NEXT: ('_section_data', '29000000 02001e00 00000101 fb0e0d00 01010101 00000001 00000164 69720000 666f6f00 01000000 02000001 01') diff --git a/test/MC/MachO/gen-dwarf.s b/test/MC/MachO/gen-dwarf.s new file mode 100644 index 0000000..4fbc32d --- /dev/null +++ b/test/MC/MachO/gen-dwarf.s @@ -0,0 +1,122 @@ +// RUN: llvm-mc -g -triple i386-apple-darwin10 %s -filetype=obj -o %t +// RUN: llvm-dwarfdump %t | FileCheck %s + +.globl _bar +_bar: + movl $0, %eax +L1: leave + ret +_foo: +_baz: + nop +.data +_x: .long 1 + +// CHECK: file format Mach-O 32-bit i386 + +// CHECK: .debug_abbrev contents: +// CHECK: Abbrev table for offset: 0x00000000 +// CHECK: [1] DW_TAG_compile_unit DW_CHILDREN_yes +// CHECK: DW_AT_stmt_list DW_FORM_data4 +// CHECK: DW_AT_low_pc DW_FORM_addr +// CHECK: DW_AT_high_pc DW_FORM_addr +// CHECK: DW_AT_name DW_FORM_string +// CHECK: DW_AT_comp_dir DW_FORM_string +// CHECK: DW_AT_producer DW_FORM_string +// CHECK: DW_AT_language DW_FORM_data2 + +// CHECK: [2] DW_TAG_label DW_CHILDREN_yes +// CHECK: DW_AT_name DW_FORM_string +// CHECK: DW_AT_decl_file DW_FORM_data4 +// CHECK: DW_AT_decl_line DW_FORM_data4 +// CHECK: DW_AT_low_pc DW_FORM_addr +// CHECK: DW_AT_prototyped DW_FORM_flag + +// CHECK: [3] DW_TAG_unspecified_parameters DW_CHILDREN_no + + +// CHECK: .debug_info contents: + +// We don't check the leading addresses these are at. +// CHECK: DW_TAG_compile_unit [1] * +// CHECK: DW_AT_stmt_list [DW_FORM_data4] (0x00000000) +// CHECK: DW_AT_low_pc [DW_FORM_addr] (0x0000000000000000) +// CHECK: DW_AT_high_pc [DW_FORM_addr] (0x0000000000000008) +// We don't check the file name as it is a temp directory +// CHECK: DW_AT_name [DW_FORM_string] +// We don't check the DW_AT_comp_dir which is the current working directory +// CHECK: DW_AT_producer [DW_FORM_string] ("llvm-mc (based on {{.*}})") +// CHECK: DW_AT_language [DW_FORM_data2] (0x8001) + +// CHECK: DW_TAG_label [2] * +// CHECK: DW_AT_name [DW_FORM_string] ("bar") +// CHECK: DW_AT_decl_file [DW_FORM_data4] (0x00000001) +// CHECK: DW_AT_decl_line [DW_FORM_data4] (0x00000005) +// CHECK: DW_AT_low_pc [DW_FORM_addr] (0x0000000000000000) +// CHECK: DW_AT_prototyped [DW_FORM_flag] (0x00) + +// CHECK: DW_TAG_unspecified_parameters [3] + +// CHECK: NULL + +// CHECK: DW_TAG_label [2] * +// CHECK: DW_AT_name [DW_FORM_string] ("foo") +// CHECK: DW_AT_decl_file [DW_FORM_data4] (0x00000001) +// CHECK: DW_AT_decl_line [DW_FORM_data4] (0x00000009) +// CHECK: DW_AT_low_pc [DW_FORM_addr] (0x0000000000000007) +// CHECK: DW_AT_prototyped [DW_FORM_flag] (0x00) + +// CHECK: DW_TAG_unspecified_parameters [3] + +// CHECK: NULL + +// CHECK: DW_TAG_label [2] * +// CHECK: DW_AT_name [DW_FORM_string] ("baz") +// CHECK: DW_AT_decl_file [DW_FORM_data4] (0x00000001) +// CHECK: DW_AT_decl_line [DW_FORM_data4] (0x0000000a) +// CHECK: DW_AT_low_pc [DW_FORM_addr] (0x0000000000000007) +// CHECK: DW_AT_prototyped [DW_FORM_flag] (0x00) + +// CHECK: DW_TAG_unspecified_parameters [3] + +// CHECK: NULL + +// CHECK: NULL + +// CHECK: .debug_aranges contents: +// CHECK: Address Range Header: length = 0x0000001c, version = 0x0002, cu_offset = 0x00000000, addr_size = 0x04, seg_size = 0x00 + +// CHECK: .debug_lines contents: +// CHECK: Line table prologue: +// We don't check the total_length as it includes lengths of temp paths +// CHECK: version: 2 +// We don't check the prologue_length as it too includes lengths of temp paths +// CHECK: min_inst_length: 1 +// CHECK: default_is_stmt: 1 +// CHECK: line_base: -5 +// CHECK: line_range: 14 +// CHECK: opcode_base: 13 +// CHECK: standard_opcode_lengths[DW_LNS_copy] = 0 +// CHECK: standard_opcode_lengths[DW_LNS_advance_pc] = 1 +// CHECK: standard_opcode_lengths[DW_LNS_advance_line] = 1 +// CHECK: standard_opcode_lengths[DW_LNS_set_file] = 1 +// CHECK: standard_opcode_lengths[DW_LNS_set_column] = 1 +// CHECK: standard_opcode_lengths[DW_LNS_negate_stmt] = 0 +// CHECK: standard_opcode_lengths[DW_LNS_set_basic_block] = 0 +// CHECK: standard_opcode_lengths[DW_LNS_const_add_pc] = 0 +// CHECK: standard_opcode_lengths[DW_LNS_fixed_advance_pc] = 1 +// CHECK: standard_opcode_lengths[DW_LNS_set_prologue_end] = 0 +// CHECK: standard_opcode_lengths[DW_LNS_set_epilogue_begin] = 0 +// CHECK: standard_opcode_lengths[DW_LNS_set_isa] = 1 +// We don't check include_directories as it has a temp path +// CHECK: Dir Mod Time File Len File Name +// CHECK: ---- ---------- ---------- --------------------------- +// CHECK: file_names[ 1] 1 0x00000000 0x00000000 gen-dwarf.s + +// CHECK: Address Line Column File ISA Flags +// CHECK: ------------------ ------ ------ ------ --- ------------- +// CHECK: 0x0000000000000000 6 0 1 0 is_stmt +// CHECK: 0x0000000000000005 7 0 1 0 is_stmt +// CHECK: 0x0000000000000006 8 0 1 0 is_stmt +// CHECK: 0x0000000000000007 11 0 1 0 is_stmt +// CHECK: 0x0000000000000008 11 0 1 0 is_stmt end_sequence diff --git a/test/MC/MachO/lit.local.cfg b/test/MC/MachO/lit.local.cfg new file mode 100644 index 0000000..6c49f08 --- /dev/null +++ b/test/MC/MachO/lit.local.cfg @@ -0,0 +1,6 @@ +config.suffixes = ['.s'] + +targets = set(config.root.targets_to_build.split()) +if not 'X86' in targets: + config.unsupported = True + diff --git a/test/MC/MachO/reloc-pcrel-offset.s b/test/MC/MachO/reloc-pcrel-offset.s index e0f12bf..e113e96 100644 --- a/test/MC/MachO/reloc-pcrel-offset.s +++ b/test/MC/MachO/reloc-pcrel-offset.s @@ -11,4 +11,7 @@ .text _a: +_b: call _a + + .subsections_via_symbols diff --git a/test/MC/MachO/reloc-pcrel.s b/test/MC/MachO/reloc-pcrel.s index fff7cc0..1133415 100644 --- a/test/MC/MachO/reloc-pcrel.s +++ b/test/MC/MachO/reloc-pcrel.s @@ -8,13 +8,13 @@ // CHECK: ('word-1', 0x6)), // CHECK: # Relocation 2 // CHECK: (('word-0', 0x40), -// CHECK: ('word-1', 0xd000002)), +// CHECK: ('word-1', 0xd000003)), // CHECK: # Relocation 3 // CHECK: (('word-0', 0x3b), -// CHECK: ('word-1', 0xd000002)), +// CHECK: ('word-1', 0xd000003)), // CHECK: # Relocation 4 // CHECK: (('word-0', 0x36), -// CHECK: ('word-1', 0xd000002)), +// CHECK: ('word-1', 0xd000003)), // CHECK: # Relocation 5 // CHECK: (('word-0', 0xe0000031), // CHECK: ('word-1', 0x4)), @@ -36,15 +36,16 @@ // CHECK-NEXT: ]) xorl %eax,%eax - + .globl _a _a: xorl %eax,%eax _b: +_d: xorl %eax,%eax L0: xorl %eax,%eax -L1: +L1: call L0 call L0 - 1 @@ -60,3 +61,5 @@ L1: call _c + 1 // call _a - L0 call _b - L0 + + .subsections_via_symbols diff --git a/test/MC/Mips/elf-bigendian.ll b/test/MC/Mips/elf-bigendian.ll new file mode 100644 index 0000000..875ba3b --- /dev/null +++ b/test/MC/Mips/elf-bigendian.ll @@ -0,0 +1,45 @@ +; RUN: llc -filetype=obj -mtriple mips-unknown-linux %s -o - | elf-dump --dump-section-data | FileCheck %s + +; Check that this is big endian. +; CHECK: ('e_indent[EI_DATA]', 0x02) + +; Make sure that a section table (text) entry is correct. +; CHECK: (('sh_name', 0x{{[0]*}}5) # '.text' +; CHECKNEXT: ('sh_type', 0x{{[0]*}}1) +; CHECKNEXT: ('sh_flags', 0x{{[0]*}}6) +; CHECKNEXT: ('sh_addr', 0x{{{[0-9,a-f]+}}) +; CHECKNEXT: ('sh_offset', 0x{{{[0-9,a-f]+}}) +; CHECKNEXT: ('sh_size', 0x{{{[0-9,a-f]+}}) +; CHECKNEXT: ('sh_link', 0x{{[0]+}}) +; CHECKNEXT: ('sh_info', 0x{{[0]+}}) +; CHECKNEXT: ('sh_addralign', 0x{{[0]*}}4) +; CHECKNEXT: ('sh_entsize', 0x{{[0]+}}) + +; See that at least first 3 instructions are correct: GP prologue +; CHECKNEXT: ('_section_data', '3c1c0000 279c0000 0399e021 {{[0-9,a-f]*}}') + +; ModuleID = '../br1.c' +target datalayout = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32" +target triple = "mips-unknown-linux" + +@x = global i32 1, align 4 +@str = private unnamed_addr constant [4 x i8] c"goo\00" +@str2 = private unnamed_addr constant [4 x i8] c"foo\00" + +define i32 @main() nounwind { +entry: + %0 = load i32* @x, align 4 + %tobool = icmp eq i32 %0, 0 + br i1 %tobool, label %if.end, label %foo + +if.end: ; preds = %entry + %puts = tail call i32 @puts(i8* getelementptr inbounds ([4 x i8]* @str, i32 0, i32 0)) + br label %foo + +foo: ; preds = %entry, %if.end + %puts2 = tail call i32 @puts(i8* getelementptr inbounds ([4 x i8]* @str2, i32 0, i32 0)) + ret i32 0 +} + +declare i32 @puts(i8* nocapture) nounwind + diff --git a/test/MC/Mips/elf-relsym.ll b/test/MC/Mips/elf-relsym.ll new file mode 100644 index 0000000..0f74437 --- /dev/null +++ b/test/MC/Mips/elf-relsym.ll @@ -0,0 +1,29 @@ +; RUN: llc -filetype=obj -mtriple mipsel-unknown-linux %s -o - | elf-dump --dump-section-data | FileCheck %s + +; Check that the appropriate symbols were created. + +; CHECK: (('st_name', 0x{{[0-9|a-f]+}}) # '$.str' +; CHECK: (('st_name', 0x{{[0-9|a-f]+}}) # '$.str1' +; CHECK: (('st_name', 0x{{[0-9|a-f]+}}) # '$CPI0_0' +; CHECK: (('st_name', 0x{{[0-9|a-f]+}}) # '$CPI0_1' + +@.str = private unnamed_addr constant [6 x i8] c"abcde\00", align 1 +@gc1 = external global i8* +@.str1 = private unnamed_addr constant [5 x i8] c"fghi\00", align 1 +@gc2 = external global i8* +@gd1 = external global double +@gd2 = external global double + +define void @foo1() nounwind { +entry: + store i8* getelementptr inbounds ([6 x i8]* @.str, i32 0, i32 0), i8** @gc1, align 4 + store i8* getelementptr inbounds ([5 x i8]* @.str1, i32 0, i32 0), i8** @gc2, align 4 + %0 = load double* @gd1, align 8 + %add = fadd double %0, 2.500000e+00 + store double %add, double* @gd1, align 8 + %1 = load double* @gd2, align 8 + %add1 = fadd double %1, 4.500000e+00 + store double %add1, double* @gd2, align 8 + ret void +} + diff --git a/test/MC/Mips/elf-tls.ll b/test/MC/Mips/elf-tls.ll new file mode 100644 index 0000000..b4183b8 --- /dev/null +++ b/test/MC/Mips/elf-tls.ll @@ -0,0 +1,36 @@ +; RUN: llc -filetype=obj -mtriple mipsel-unknown-linux %s -o - | elf-dump --dump-section-data | FileCheck %s + +; Check that the appropriate relocations were created. + +; CHECK: ('r_type', 0x2b) +; CHECK: ('r_type', 0x2c) +; CHECK: ('r_type', 0x2d) + +@t1 = thread_local global i32 0, align 4 + +define i32 @f1() nounwind { +entry: + %tmp = load i32* @t1, align 4 + ret i32 %tmp + +} + + +@t2 = external thread_local global i32 + +define i32 @f2() nounwind { +entry: + %tmp = load i32* @t2, align 4 + ret i32 %tmp + +} + +@f3.i = internal thread_local unnamed_addr global i32 1, align 4 + +define i32 @f3() nounwind { +entry: + %0 = load i32* @f3.i, align 4 + %inc = add nsw i32 %0, 1 + store i32 %inc, i32* @f3.i, align 4 + ret i32 %inc +} diff --git a/test/MC/Mips/elf_basic.s b/test/MC/Mips/elf_basic.s new file mode 100644 index 0000000..7a79fa0 --- /dev/null +++ b/test/MC/Mips/elf_basic.s @@ -0,0 +1,32 @@ +// 32 bit big endian +// RUN: llvm-mc -filetype=obj -triple mips-unknown-linux %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=CHECK-BE32 %s +// 32 bit little endian +// RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=CHECK-LE32 %s +// 64 bit big endian +// RUN: llvm-mc -filetype=obj -arch=mips64 -triple mips64-unknown-linux %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=CHECK-BE64 %s +// 64 bit little endian +// RUN: llvm-mc -filetype=obj -arch=mips64el -triple mips64el-unknown-linux %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=CHECK-LE64 %s + +// Check that we produce 32 bit with each endian. + +// This is 32 bit. +// CHECK-BE32: ('e_indent[EI_CLASS]', 0x01) +// This is big endian. +// CHECK-BE32: ('e_indent[EI_DATA]', 0x02) + +// This is 32 bit. +// CHECK-LE32: ('e_indent[EI_CLASS]', 0x01) +// This is little endian. +// CHECK-LE32: ('e_indent[EI_DATA]', 0x01) + +// Check that we produce 64 bit with each endian. + +// This is 64 bit. +// CHECK-BE64: ('e_indent[EI_CLASS]', 0x02) +// This is big endian. +// CHECK-BE64: ('e_indent[EI_DATA]', 0x02) + +// This is 64 bit. +// CHECK-LE64: ('e_indent[EI_CLASS]', 0x02) +// This is little endian. +// CHECK-LE64: ('e_indent[EI_DATA]', 0x01) diff --git a/test/MC/Mips/lit.local.cfg b/test/MC/Mips/lit.local.cfg new file mode 100644 index 0000000..d2e3b28 --- /dev/null +++ b/test/MC/Mips/lit.local.cfg @@ -0,0 +1,6 @@ +config.suffixes = ['.ll', '.c', '.cpp', '.s'] + +targets = set(config.root.targets_to_build.split()) +if not 'Mips' in targets: + config.unsupported = True + diff --git a/test/MC/Mips/pr11877.s b/test/MC/Mips/pr11877.s new file mode 100644 index 0000000..d354ce4 --- /dev/null +++ b/test/MC/Mips/pr11877.s @@ -0,0 +1,6 @@ +// RUN: llvm-mc -triple mips-unknown-unknown %s + +i: + .long g +g = h +h = i diff --git a/test/MC/X86/2011-09-06-NoNewline.s b/test/MC/X86/2011-09-06-NoNewline.s new file mode 100644 index 0000000..bc681a3 --- /dev/null +++ b/test/MC/X86/2011-09-06-NoNewline.s @@ -0,0 +1,3 @@ +// RUN: llvm-mc -triple i386-unknown-unknown %s +// PR10869 +movl %gs:8, %eax
\ No newline at end of file diff --git a/test/MC/X86/address-size.s b/test/MC/X86/address-size.s new file mode 100644 index 0000000..b105b40 --- /dev/null +++ b/test/MC/X86/address-size.s @@ -0,0 +1,13 @@ +// RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s + + .code64 + movb $0x0, (%esi) +// CHECK: encoding: [0x67,0xc6,0x06,0x00] + movb $0x0, (%rsi) +// CHECK: encoding: [0xc6,0x06,0x00] + + .code32 + movb $0x0, (%si) +// CHECK: encoding: [0x67,0xc6,0x06,0x00] + movb $0x0, (%esi) +// CHECK: encoding: [0xc6,0x06,0x00] diff --git a/test/MC/X86/dg.exp b/test/MC/X86/dg.exp deleted file mode 100644 index ec87b69..0000000 --- a/test/MC/X86/dg.exp +++ /dev/null @@ -1,5 +0,0 @@ -load_lib llvm.exp - -if { [llvm_supports_target X86] } { - RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp,s}]] -} diff --git a/test/MC/X86/intel-syntax-2.s b/test/MC/X86/intel-syntax-2.s new file mode 100644 index 0000000..ca4afc3 --- /dev/null +++ b/test/MC/X86/intel-syntax-2.s @@ -0,0 +1,7 @@ +// RUN: llvm-mc -triple x86_64-unknown-unknown %s | FileCheck %s + + .intel_syntax +_test: +// CHECK: movl $257, -4(%rsp) + mov DWORD PTR [RSP - 4], 257 + diff --git a/test/MC/X86/intel-syntax-encoding.s b/test/MC/X86/intel-syntax-encoding.s new file mode 100644 index 0000000..03b0551 --- /dev/null +++ b/test/MC/X86/intel-syntax-encoding.s @@ -0,0 +1,57 @@ +// RUN: llvm-mc -x86-asm-syntax=intel -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s + +// CHECK: encoding: [0x66,0x83,0xf0,0x0c] + xor ax, 12 +// CHECK: encoding: [0x83,0xf0,0x0c] + xor eax, 12 +// CHECK: encoding: [0x48,0x83,0xf0,0x0c] + xor rax, 12 + +// CHECK: encoding: [0x66,0x83,0xc8,0x0c] + or ax, 12 +// CHECK: encoding: [0x83,0xc8,0x0c] + or eax, 12 +// CHECK: encoding: [0x48,0x83,0xc8,0x0c] + or rax, 12 + +// CHECK: encoding: [0x66,0x83,0xf8,0x0c] + cmp ax, 12 +// CHECK: encoding: [0x83,0xf8,0x0c] + cmp eax, 12 +// CHECK: encoding: [0x48,0x83,0xf8,0x0c] + cmp rax, 12 + +// CHECK: encoding: [0x48,0x89,0x44,0x24,0xf0] + mov QWORD PTR [RSP - 16], RAX + +// CHECK: encoding: [0x66,0x83,0xc0,0xf4] + add ax, -12 +// CHECK: encoding: [0x83,0xc0,0xf4] + add eax, -12 +// CHECK: encoding: [0x48,0x83,0xc0,0xf4] + add rax, -12 + +LBB0_3: +// CHECK: encoding: [0xeb,A] + jmp LBB0_3 +// CHECK: encoding: [0xf2,0x0f,0x10,0x2c,0x25,0xf8,0xff,0xff,0xff] + movsd XMM5, QWORD PTR [-8] + +// CHECK: encoding: [0xd1,0xe7] + shl EDI, 1 + +// CHECK: encoding: [0x0f,0xc2,0xd1,0x01] + cmpltps XMM2, XMM1 + +// CHECK: encoding: [0xc3] + ret + +// CHECK: encoding: [0xcb] + retf + +// CHECK: encoding: [0xc2,0x08,0x00] + ret 8 + +// CHECK: encoding: [0xca,0x08,0x00] + retf 8 + diff --git a/test/MC/X86/intel-syntax.s b/test/MC/X86/intel-syntax.s new file mode 100644 index 0000000..7cd5677 --- /dev/null +++ b/test/MC/X86/intel-syntax.s @@ -0,0 +1,66 @@ +// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel %s | FileCheck %s + +_test: + xor EAX, EAX + ret + +_main: +// CHECK: movl $257, -4(%rsp) + mov DWORD PTR [RSP - 4], 257 +// CHECK: movl $258, 4(%rsp) + mov DWORD PTR [RSP + 4], 258 +// CHECK: movq $123, -16(%rsp) + mov QWORD PTR [RSP - 16], 123 +// CHECK: movb $97, -17(%rsp) + mov BYTE PTR [RSP - 17], 97 +// CHECK: movl -4(%rsp), %eax + mov EAX, DWORD PTR [RSP - 4] +// CHECK: movq (%rsp), %rax + mov RAX, QWORD PTR [RSP] +// CHECK: movl $-4, -4(%rsp) + mov DWORD PTR [RSP - 4], -4 +// CHECK: movq 0, %rcx + mov RCX, QWORD PTR [0] +// CHECK: movl -24(%rsp,%rax,4), %eax + mov EAX, DWORD PTR [RSP + 4*RAX - 24] +// CHECK: movb %dil, (%rdx,%rcx) + mov BYTE PTR [RDX + RCX], DIL +// CHECK: movzwl 2(%rcx), %edi + movzx EDI, WORD PTR [RCX + 2] +// CHECK: callq _test + call _test +// CHECK: andw $12, %ax + and ax, 12 +// CHECK: andw $-12, %ax + and ax, -12 +// CHECK: andw $257, %ax + and ax, 257 +// CHECK: andw $-257, %ax + and ax, -257 +// CHECK: andl $12, %eax + and eax, 12 +// CHECK: andl $-12, %eax + and eax, -12 +// CHECK: andl $257, %eax + and eax, 257 +// CHECK: andl $-257, %eax + and eax, -257 +// CHECK: andq $12, %rax + and rax, 12 +// CHECK: andq $-12, %rax + and rax, -12 +// CHECK: andq $257, %rax + and rax, 257 +// CHECK: andq $-257, %rax + and rax, -257 +// CHECK: fld %st(0) + fld ST(0) +// CHECK: movl %fs:(%rdi), %eax + mov EAX, DWORD PTR FS:[RDI] +// CHECK: leal (,%rdi,4), %r8d + lea R8D, DWORD PTR [4*RDI] +// CHECK: movl _fnan(,%ecx,4), %ecx + mov ECX, DWORD PTR [4*ECX + _fnan] +// CHECK: movq %fs:320, %rax + mov RAX, QWORD PTR FS:[320] + ret diff --git a/test/MC/X86/lit.local.cfg b/test/MC/X86/lit.local.cfg new file mode 100644 index 0000000..eee568e --- /dev/null +++ b/test/MC/X86/lit.local.cfg @@ -0,0 +1,12 @@ +config.suffixes = ['.ll', '.c', '.cpp', '.s'] + +def getRoot(config): + if not config.parent: + return config + return getRoot(config.parent) + +root = getRoot(config) + +targets = set(root.targets_to_build.split()) +if not 'X86' in targets: + config.unsupported = True diff --git a/test/MC/X86/x86-32-coverage.s b/test/MC/X86/x86-32-coverage.s index 0954ce2..6c27b85 100644 --- a/test/MC/X86/x86-32-coverage.s +++ b/test/MC/X86/x86-32-coverage.s @@ -500,6 +500,9 @@ // CHECK: sysexit sysexit +// CHECK: sysexitl + sysexitl + // CHECK: ud2 ud2 @@ -4417,6 +4420,10 @@ // CHECK: encoding: [0x0f,0x35] sysexit +// CHECK: sysexitl +// CHECK: encoding: [0x0f,0x35] + sysexitl + // CHECK: fxsave 3735928559(%ebx,%ecx,8) // CHECK: encoding: [0x0f,0xae,0x84,0xcb,0xef,0xbe,0xad,0xde] fxsave 0xdeadbeef(%ebx,%ecx,8) @@ -18401,6 +18408,9 @@ // CHECK: vmcall vmcall +// CHECK: vmfunc + vmfunc + // CHECK: vmclear 3735928559(%ebx,%ecx,8) vmclear 0xdeadbeef(%ebx,%ecx,8) @@ -18458,6 +18468,30 @@ // CHECK: vmxon 305419896 vmxon 0x12345678 +// CHECK: vmrun %eax + vmrun %eax + +// CHECK: vmmcall + vmmcall + +// CHECK: vmload %eax + vmload %eax + +// CHECK: vmsave %eax + vmsave %eax + +// CHECK: stgi + stgi + +// CHECK: clgi + clgi + +// CHECK: skinit %eax + skinit %eax + +// CHECK: invlpga %ecx, %eax + invlpga %ecx, %eax + // CHECK: phaddw 3735928559(%ebx,%ecx,8), %mm3 phaddw 0xdeadbeef(%ebx,%ecx,8),%mm3 diff --git a/test/MC/X86/x86-32.s b/test/MC/X86/x86-32.s index 19f1445..57a0037 100644 --- a/test/MC/X86/x86-32.s +++ b/test/MC/X86/x86-32.s @@ -28,6 +28,9 @@ vmcall // CHECK: vmcall // CHECK: encoding: [0x0f,0x01,0xc1] + vmfunc +// CHECK: vmfunc +// CHECK: encoding: [0x0f,0x01,0xd4] vmlaunch // CHECK: vmlaunch // CHECK: encoding: [0x0f,0x01,0xc2] @@ -41,7 +44,32 @@ // CHECK: swapgs // CHECK: encoding: [0x0f,0x01,0xf8] -rdtscp + vmrun %eax +// CHECK: vmrun %eax +// CHECK: encoding: [0x0f,0x01,0xd8] + vmmcall +// CHECK: vmmcall +// CHECK: encoding: [0x0f,0x01,0xd9] + vmload %eax +// CHECK: vmload %eax +// CHECK: encoding: [0x0f,0x01,0xda] + vmsave %eax +// CHECK: vmsave %eax +// CHECK: encoding: [0x0f,0x01,0xdb] + stgi +// CHECK: stgi +// CHECK: encoding: [0x0f,0x01,0xdc] + clgi +// CHECK: clgi +// CHECK: encoding: [0x0f,0x01,0xdd] + skinit %eax +// CHECK: skinit %eax +// CHECK: encoding: [0x0f,0x01,0xde] + invlpga %ecx, %eax +// CHECK: invlpga %ecx, %eax +// CHECK: encoding: [0x0f,0x01,0xdf] + + rdtscp // CHECK: rdtscp // CHECK: encoding: [0x0f,0x01,0xf9] @@ -69,9 +97,9 @@ rdtscp sal $1, %eax // moffset forms of moves, rdar://7947184 -movb 0, %al // CHECK: movb 0, %al # encoding: [0xa0,A,A,A,A] -movw 0, %ax // CHECK: movw 0, %ax # encoding: [0x66,0xa1,A,A,A,A] -movl 0, %eax // CHECK: movl 0, %eax # encoding: [0xa1,A,A,A,A] +movb 0, %al // CHECK: movb 0, %al # encoding: [0xa0,0x00,0x00,0x00,0x00] +movw 0, %ax // CHECK: movw 0, %ax # encoding: [0x66,0xa1,0x00,0x00,0x00,0x00] +movl 0, %eax // CHECK: movl 0, %eax # encoding: [0xa1,0x00,0x00,0x00,0x00] // rdar://7973775 into @@ -962,3 +990,11 @@ xchgl %ecx, %eax // CHECK: xchgl %ecx, %eax // CHECK: encoding: [0x91] xchgl %eax, %ecx + +// CHECK: retw +// CHECK: encoding: [0x66,0xc3] +retw + +// CHECK: lretw +// CHECK: encoding: [0x66,0xcb] +lretw diff --git a/test/MC/X86/x86-64.s b/test/MC/X86/x86-64.s index a9cdaa4..6a2d5bb 100644 --- a/test/MC/X86/x86-64.s +++ b/test/MC/X86/x86-64.s @@ -50,6 +50,9 @@ // CHECK: ret ret +// CHECK: retw + retw + // FIXME: Check that this matches SUB32ri8 // CHECK: subl $1, %eax subl $1, %eax @@ -339,15 +342,28 @@ rclb $1, %bl // CHECK: rclb %bl # encoding: [0xd0,0xd3] rclb $2, %bl // CHECK: rclb $2, %bl # encoding: [0xc0,0xd3,0x02] // rdar://8418316 -// CHECK: shldw $1, %bx, %bx -// CHECK: shldw $1, %bx, %bx -// CHECK: shrdw $1, %bx, %bx -// CHECK: shrdw $1, %bx, %bx - -shld %bx,%bx -shld $1, %bx,%bx -shrd %bx,%bx -shrd $1, %bx,%bx +// PR12173 +// CHECK: shldw %cl, %bx, %dx +// CHECK: shldw %cl, %bx, %dx +// CHECK: shldw $1, %bx, %dx +// CHECK: shldw %cl, %bx, (%rax) +// CHECK: shldw %cl, %bx, (%rax) +// CHECK: shrdw %cl, %bx, %dx +// CHECK: shrdw %cl, %bx, %dx +// CHECK: shrdw $1, %bx, %dx +// CHECK: shrdw %cl, %bx, (%rax) +// CHECK: shrdw %cl, %bx, (%rax) + +shld %bx, %dx +shld %cl, %bx, %dx +shld $1, %bx, %dx +shld %bx, (%rax) +shld %cl, %bx, (%rax) +shrd %bx, %dx +shrd %cl, %bx, %dx +shrd $1, %bx, %dx +shrd %bx, (%rax) +shrd %cl, %bx, (%rax) // CHECK: sldtl %ecx // CHECK: encoding: [0x0f,0x00,0xc1] @@ -459,6 +475,7 @@ cwtl // CHECK: cwtl cbw // CHECK: cbtw cwd // CHECK: cwtd cdq // CHECK: cltd +cqo // CHECK: cqto // rdar://8456378 and PR7557 - fstsw fstsw %ax @@ -827,6 +844,7 @@ iretq lretq // CHECK: lretq # encoding: [0x48,0xcb] lretl // CHECK: lretl # encoding: [0xcb] lret // CHECK: lretl # encoding: [0xcb] +lretw // CHECK: lretw # encoding: [0x66,0xcb] // rdar://8403907 sysret @@ -1039,6 +1057,9 @@ xsetbv // CHECK: xsetbv # encoding: [0x0f,0x01,0xd1] movsl movsl %ds:(%rsi), %es:(%rdi) movsl (%rsi), %es:(%rdi) +// rdar://10883092 +// CHECK: movsd + movsl (%rsi), (%rdi) // CHECK: movsq # encoding: [0x48,0xa5] // CHECK: movsq @@ -1191,3 +1212,15 @@ xchgl %ecx, %eax // CHECK: xchgl %ecx, %eax // CHECK: encoding: [0x91] xchgl %eax, %ecx + +// CHECK: sysexit +// CHECK: encoding: [0x0f,0x35] +sysexit + +// CHECK: sysexitl +// CHECK: encoding: [0x0f,0x35] +sysexitl + +// CHECK: sysexitq +// CHECK: encoding: [0x48,0x0f,0x35] +sysexitq diff --git a/test/MC/X86/x86_64-avx-encoding.s b/test/MC/X86/x86_64-avx-encoding.s index d3b226f..bd5559a 100644 --- a/test/MC/X86/x86_64-avx-encoding.s +++ b/test/MC/X86/x86_64-avx-encoding.s @@ -600,6 +600,774 @@ vdivpd -4(%rcx,%rbx,8), %xmm10, %xmm11 // CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x03] vcmpunordsd -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: vcmpps $8, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x08] + vcmpeq_uqps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $9, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x09] + vcmpngeps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $10, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x0a] + vcmpngtps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $11, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x0b] + vcmpfalseps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $12, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x0c] + vcmpneq_oqps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $13, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x0d] + vcmpgeps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $14, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x0e] + vcmpgtps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $15, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x0f] + vcmptrueps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $16, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x10] + vcmpeq_osps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $17, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x11] + vcmplt_oqps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $18, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x12] + vcmple_oqps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $19, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x13] + vcmpunord_sps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $20, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x14] + vcmpneq_usps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $21, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x15] + vcmpnlt_uqps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $22, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x16] + vcmpnle_uqps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $23, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x17] + vcmpord_sps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $24, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x18] + vcmpeq_usps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $25, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x19] + vcmpnge_uqps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $26, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x1a] + vcmpngt_uqps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $27, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x1b] + vcmpfalse_osps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $28, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x1c] + vcmpneq_osps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $29, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x1d] + vcmpge_oqps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $30, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x1e] + vcmpgt_oqps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $31, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x1f] + vcmptrue_usps %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpps $8, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x08] + vcmpeq_uqps -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpps $9, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x09] + vcmpngeps -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpps $10, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x0a] + vcmpngtps -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpps $11, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x0b] + vcmpfalseps -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpps $12, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x0c] + vcmpneq_oqps -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpps $13, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x0d] + vcmpgeps -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpps $14, -4(%rbx,%rcx,8), %xmm6, %xmm2 +// CHECK: encoding: [0xc5,0xc8,0xc2,0x54,0xcb,0xfc,0x0e] + vcmpgtps -4(%rbx,%rcx,8), %xmm6, %xmm2 + +// CHECK: vcmpps $15, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x0f] + vcmptrueps -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpps $16, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x10] + vcmpeq_osps -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpps $17, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x11] + vcmplt_oqps -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpps $18, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x12] + vcmple_oqps -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpps $19, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x13] + vcmpunord_sps -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpps $20, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x14] + vcmpneq_usps -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpps $21, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x15] + vcmpnlt_uqps -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpps $22, -4(%rbx,%rcx,8), %xmm6, %xmm2 +// CHECK: encoding: [0xc5,0xc8,0xc2,0x54,0xcb,0xfc,0x16] + vcmpnle_uqps -4(%rbx,%rcx,8), %xmm6, %xmm2 + +// CHECK: vcmpps $23, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x17] + vcmpord_sps -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpps $24, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x18] + vcmpeq_usps -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpps $25, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x19] + vcmpnge_uqps -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpps $26, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x1a] + vcmpngt_uqps -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpps $27, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x1b] + vcmpfalse_osps -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpps $28, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x1c] + vcmpneq_osps -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpps $29, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x1d] + vcmpge_oqps -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpps $30, -4(%rbx,%rcx,8), %xmm6, %xmm2 +// CHECK: encoding: [0xc5,0xc8,0xc2,0x54,0xcb,0xfc,0x1e] + vcmpgt_oqps -4(%rbx,%rcx,8), %xmm6, %xmm2 + +// CHECK: vcmpps $31, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x1f] + vcmptrue_usps -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmppd $8, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x08] + vcmpeq_uqpd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $9, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x09] + vcmpngepd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $10, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x0a] + vcmpngtpd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $11, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x0b] + vcmpfalsepd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $12, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x0c] + vcmpneq_oqpd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $13, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x0d] + vcmpgepd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $14, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x0e] + vcmpgtpd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $15, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x0f] + vcmptruepd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $16, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x10] + vcmpeq_ospd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $17, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x11] + vcmplt_oqpd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $18, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x12] + vcmple_oqpd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $19, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x13] + vcmpunord_spd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $20, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x14] + vcmpneq_uspd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $21, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x15] + vcmpnlt_uqpd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $22, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x16] + vcmpnle_uqpd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $23, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x17] + vcmpord_spd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $24, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x18] + vcmpeq_uspd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $25, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x19] + vcmpnge_uqpd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $26, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x1a] + vcmpngt_uqpd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $27, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x1b] + vcmpfalse_ospd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $28, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x1c] + vcmpneq_ospd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $29, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x1d] + vcmpge_oqpd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $30, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x1e] + vcmpgt_oqpd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $31, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x1f] + vcmptrue_uspd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmppd $8, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x08] + vcmpeq_uqpd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmppd $9, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x09] + vcmpngepd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmppd $10, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x0a] + vcmpngtpd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmppd $11, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x0b] + vcmpfalsepd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmppd $12, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x0c] + vcmpneq_oqpd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmppd $13, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x0d] + vcmpgepd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmppd $14, -4(%rbx,%rcx,8), %xmm6, %xmm2 +// CHECK: encoding: [0xc5,0xc9,0xc2,0x54,0xcb,0xfc,0x0e] + vcmpgtpd -4(%rbx,%rcx,8), %xmm6, %xmm2 + +// CHECK: vcmppd $15, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x0f] + vcmptruepd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmppd $16, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x10] + vcmpeq_ospd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmppd $17, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x11] + vcmplt_oqpd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmppd $18, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x12] + vcmple_oqpd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmppd $19, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x13] + vcmpunord_spd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmppd $20, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x14] + vcmpneq_uspd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmppd $21, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x15] + vcmpnlt_uqpd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmppd $22, -4(%rbx,%rcx,8), %xmm6, %xmm2 +// CHECK: encoding: [0xc5,0xc9,0xc2,0x54,0xcb,0xfc,0x16] + vcmpnle_uqpd -4(%rbx,%rcx,8), %xmm6, %xmm2 + +// CHECK: vcmppd $23, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x17] + vcmpord_spd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmppd $24, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x18] + vcmpeq_uspd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmppd $25, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x19] + vcmpnge_uqpd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmppd $26, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x1a] + vcmpngt_uqpd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmppd $27, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x1b] + vcmpfalse_ospd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmppd $28, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x1c] + vcmpneq_ospd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmppd $29, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x1d] + vcmpge_oqpd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmppd $30, -4(%rbx,%rcx,8), %xmm6, %xmm2 +// CHECK: encoding: [0xc5,0xc9,0xc2,0x54,0xcb,0xfc,0x1e] + vcmpgt_oqpd -4(%rbx,%rcx,8), %xmm6, %xmm2 + +// CHECK: vcmppd $31, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x1f] + vcmptrue_uspd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpss $8, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x08] + vcmpeq_uqss %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $9, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x09] + vcmpngess %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $10, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x0a] + vcmpngtss %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $11, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x0b] + vcmpfalsess %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $12, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x0c] + vcmpneq_oqss %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $13, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x0d] + vcmpgess %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $14, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x0e] + vcmpgtss %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $15, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x0f] + vcmptruess %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $16, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x10] + vcmpeq_osss %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $17, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x11] + vcmplt_oqss %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $18, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x12] + vcmple_oqss %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $19, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x13] + vcmpunord_sss %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $20, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x14] + vcmpneq_usss %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $21, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x15] + vcmpnlt_uqss %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $22, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x16] + vcmpnle_uqss %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $23, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x17] + vcmpord_sss %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $24, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x18] + vcmpeq_usss %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $25, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x19] + vcmpnge_uqss %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $26, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x1a] + vcmpngt_uqss %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $27, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x1b] + vcmpfalse_osss %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $28, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x1c] + vcmpneq_osss %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $29, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x1d] + vcmpge_oqss %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $30, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x1e] + vcmpgt_oqss %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $31, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x1f] + vcmptrue_usss %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpss $8, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x08] + vcmpeq_uqss -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpss $9, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x09] + vcmpngess -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpss $10, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x0a] + vcmpngtss -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpss $11, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x0b] + vcmpfalsess -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpss $12, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x0c] + vcmpneq_oqss -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpss $13, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x0d] + vcmpgess -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpss $14, -4(%rbx,%rcx,8), %xmm6, %xmm2 +// CHECK: encoding: [0xc5,0xca,0xc2,0x54,0xcb,0xfc,0x0e] + vcmpgtss -4(%rbx,%rcx,8), %xmm6, %xmm2 + +// CHECK: vcmpss $15, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x0f] + vcmptruess -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpss $16, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x10] + vcmpeq_osss -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpss $17, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x11] + vcmplt_oqss -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpss $18, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x12] + vcmple_oqss -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpss $19, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x13] + vcmpunord_sss -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpss $20, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x14] + vcmpneq_usss -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpss $21, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x15] + vcmpnlt_uqss -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpss $22, -4(%rbx,%rcx,8), %xmm6, %xmm2 +// CHECK: encoding: [0xc5,0xca,0xc2,0x54,0xcb,0xfc,0x16] + vcmpnle_uqss -4(%rbx,%rcx,8), %xmm6, %xmm2 + +// CHECK: vcmpss $23, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x17] + vcmpord_sss -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpss $24, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x18] + vcmpeq_usss -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpss $25, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x19] + vcmpnge_uqss -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpss $26, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x1a] + vcmpngt_uqss -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpss $27, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x1b] + vcmpfalse_osss -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpss $28, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x1c] + vcmpneq_osss -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpss $29, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x1d] + vcmpge_oqss -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpss $30, -4(%rbx,%rcx,8), %xmm6, %xmm2 +// CHECK: encoding: [0xc5,0xca,0xc2,0x54,0xcb,0xfc,0x1e] + vcmpgt_oqss -4(%rbx,%rcx,8), %xmm6, %xmm2 + +// CHECK: vcmpss $31, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x1f] + vcmptrue_usss -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpsd $8, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x08] + vcmpeq_uqsd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $9, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x09] + vcmpngesd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $10, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x0a] + vcmpngtsd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $11, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x0b] + vcmpfalsesd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $12, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x0c] + vcmpneq_oqsd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $13, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x0d] + vcmpgesd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $14, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x0e] + vcmpgtsd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $15, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x0f] + vcmptruesd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $16, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x10] + vcmpeq_ossd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $17, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x11] + vcmplt_oqsd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $18, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x12] + vcmple_oqsd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $19, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x13] + vcmpunord_ssd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $20, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x14] + vcmpneq_ussd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $21, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x15] + vcmpnlt_uqsd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $22, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x16] + vcmpnle_uqsd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $23, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x17] + vcmpord_ssd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $24, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x18] + vcmpeq_ussd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $25, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x19] + vcmpnge_uqsd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $26, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x1a] + vcmpngt_uqsd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $27, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x1b] + vcmpfalse_ossd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $28, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x1c] + vcmpneq_ossd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $29, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x1d] + vcmpge_oqsd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $30, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x1e] + vcmpgt_oqsd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $31, %xmm11, %xmm12, %xmm13 +// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x1f] + vcmptrue_ussd %xmm11, %xmm12, %xmm13 + +// CHECK: vcmpsd $8, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x08] + vcmpeq_uqsd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpsd $9, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x09] + vcmpngesd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpsd $10, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x0a] + vcmpngtsd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpsd $11, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x0b] + vcmpfalsesd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpsd $12, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x0c] + vcmpneq_oqsd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpsd $13, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x0d] + vcmpgesd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpsd $14, -4(%rbx,%rcx,8), %xmm6, %xmm2 +// CHECK: encoding: [0xc5,0xcb,0xc2,0x54,0xcb,0xfc,0x0e] + vcmpgtsd -4(%rbx,%rcx,8), %xmm6, %xmm2 + +// CHECK: vcmpsd $15, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x0f] + vcmptruesd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpsd $16, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x10] + vcmpeq_ossd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpsd $17, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x11] + vcmplt_oqsd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpsd $18, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x12] + vcmple_oqsd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpsd $19, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x13] + vcmpunord_ssd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpsd $20, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x14] + vcmpneq_ussd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpsd $21, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x15] + vcmpnlt_uqsd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpsd $22, -4(%rbx,%rcx,8), %xmm6, %xmm2 +// CHECK: encoding: [0xc5,0xcb,0xc2,0x54,0xcb,0xfc,0x16] + vcmpnle_uqsd -4(%rbx,%rcx,8), %xmm6, %xmm2 + +// CHECK: vcmpsd $23, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x17] + vcmpord_ssd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpsd $24, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x18] + vcmpeq_ussd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpsd $25, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x19] + vcmpnge_uqsd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpsd $26, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x1a] + vcmpngt_uqsd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpsd $27, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x1b] + vcmpfalse_ossd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpsd $28, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x1c] + vcmpneq_ossd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpsd $29, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x1d] + vcmpge_oqsd -4(%rbx,%rcx,8), %xmm12, %xmm13 + +// CHECK: vcmpsd $30, -4(%rbx,%rcx,8), %xmm6, %xmm2 +// CHECK: encoding: [0xc5,0xcb,0xc2,0x54,0xcb,0xfc,0x1e] + vcmpgt_oqsd -4(%rbx,%rcx,8), %xmm6, %xmm2 + +// CHECK: vcmpsd $31, -4(%rbx,%rcx,8), %xmm12, %xmm13 +// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x1f] + vcmptrue_ussd -4(%rbx,%rcx,8), %xmm12, %xmm13 + // CHECK: vucomiss %xmm11, %xmm12 // CHECK: encoding: [0xc4,0x41,0x78,0x2e,0xe3] vucomiss %xmm11, %xmm12 @@ -3346,3 +4114,10 @@ vdivpd -4(%rcx,%rbx,8), %xmm10, %xmm11 _foo: nop vpshufb _foo(%rip), %xmm0, %xmm0 + +// CHECK: vblendvps %ymm1, _foo2(%rip), %ymm0, %ymm0 +// CHECK: encoding: [0xc4,0xe3,0x7d,0x4a,0x05,A,A,A,A,0x10] +// CHECK: fixup A - offset: 5, value: _foo2-5 +_foo2: + nop + vblendvps %ymm1, _foo2(%rip), %ymm0, %ymm0 diff --git a/test/MC/X86/x86_64-bmi-encoding.s b/test/MC/X86/x86_64-bmi-encoding.s new file mode 100644 index 0000000..3e69d4a --- /dev/null +++ b/test/MC/X86/x86_64-bmi-encoding.s @@ -0,0 +1,202 @@ +// RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s + +// CHECK: blsmskl %r11d, %r10d +// CHECK: encoding: [0xc4,0xc2,0x28,0xf3,0xd3] + blsmskl %r11d, %r10d + +// CHECK: blsmskq %r11, %r10 +// CHECK: encoding: [0xc4,0xc2,0xa8,0xf3,0xd3] + blsmskq %r11, %r10 + +// CHECK: blsmskl (%rax), %r10d +// CHECK: encoding: [0xc4,0xe2,0x28,0xf3,0x10] + blsmskl (%rax), %r10d + +// CHECK: blsmskq (%rax), %r10 +// CHECK: encoding: [0xc4,0xe2,0xa8,0xf3,0x10] + blsmskq (%rax), %r10 + +// CHECK: blsil %r11d, %r10d +// CHECK: encoding: [0xc4,0xc2,0x28,0xf3,0xdb] + blsil %r11d, %r10d + +// CHECK: blsiq %r11, %r10 +// CHECK: encoding: [0xc4,0xc2,0xa8,0xf3,0xdb] + blsiq %r11, %r10 + +// CHECK: blsil (%rax), %r10d +// CHECK: encoding: [0xc4,0xe2,0x28,0xf3,0x18] + blsil (%rax), %r10d + +// CHECK: blsiq (%rax), %r10 +// CHECK: encoding: [0xc4,0xe2,0xa8,0xf3,0x18] + blsiq (%rax), %r10 + +// CHECK: blsrl %r11d, %r10d +// CHECK: encoding: [0xc4,0xc2,0x28,0xf3,0xcb] + blsrl %r11d, %r10d + +// CHECK: blsrq %r11, %r10 +// CHECK: encoding: [0xc4,0xc2,0xa8,0xf3,0xcb] + blsrq %r11, %r10 + +// CHECK: blsrl (%rax), %r10d +// CHECK: encoding: [0xc4,0xe2,0x28,0xf3,0x08] + blsrl (%rax), %r10d + +// CHECK: blsrq (%rax), %r10 +// CHECK: encoding: [0xc4,0xe2,0xa8,0xf3,0x08] + blsrq (%rax), %r10 + +// CHECK: andnl (%rax), %r11d, %r10d +// CHECK: encoding: [0xc4,0x62,0x20,0xf2,0x10] + andnl (%rax), %r11d, %r10d + +// CHECK: andnq (%rax), %r11, %r10 +// CHECK: encoding: [0xc4,0x62,0xa0,0xf2,0x10] + andnq (%rax), %r11, %r10 + +// CHECK: bextrl %r12d, (%rax), %r10d +// CHECK: encoding: [0xc4,0x62,0x18,0xf7,0x10] + bextrl %r12d, (%rax), %r10d + +// CHECK: bextrl %r12d, %r11d, %r10d +// CHECK: encoding: [0xc4,0x42,0x18,0xf7,0xd3] + bextrl %r12d, %r11d, %r10d + +// CHECK: bextrq %r12, (%rax), %r10 +// CHECK: encoding: [0xc4,0x62,0x98,0xf7,0x10] + bextrq %r12, (%rax), %r10 + +// CHECK: bextrq %r12, %r11, %r10 +// CHECK: encoding: [0xc4,0x42,0x98,0xf7,0xd3] + bextrq %r12, %r11, %r10 + +// CHECK: bzhil %r12d, (%rax), %r10d +// CHECK: encoding: [0xc4,0x62,0x18,0xf5,0x10] + bzhil %r12d, (%rax), %r10d + +// CHECK: bzhil %r12d, %r11d, %r10d +// CHECK: encoding: [0xc4,0x42,0x18,0xf5,0xd3] + bzhil %r12d, %r11d, %r10d + +// CHECK: bzhiq %r12, (%rax), %r10 +// CHECK: encoding: [0xc4,0x62,0x98,0xf5,0x10] + bzhiq %r12, (%rax), %r10 + +// CHECK: bzhiq %r12, %r11, %r10 +// CHECK: encoding: [0xc4,0x42,0x98,0xf5,0xd3] + bzhiq %r12, %r11, %r10 + +// CHECK: pextl %r12d, %r11d, %r10d +// CHECK: encoding: [0xc4,0x42,0x22,0xf5,0xd4] + pextl %r12d, %r11d, %r10d + +// CHECK: pextl (%rax), %r11d, %r10d +// CHECK: encoding: [0xc4,0x62,0x22,0xf5,0x10] + pextl (%rax), %r11d, %r10d + +// CHECK: pextq %r12, %r11, %r10 +// CHECK: encoding: [0xc4,0x42,0xa2,0xf5,0xd4] + pextq %r12, %r11, %r10 + +// CHECK: pextq (%rax), %r11, %r10 +// CHECK: encoding: [0xc4,0x62,0xa2,0xf5,0x10] + pextq (%rax), %r11, %r10 + +// CHECK: pdepl %r12d, %r11d, %r10d +// CHECK: encoding: [0xc4,0x42,0x23,0xf5,0xd4] + pdepl %r12d, %r11d, %r10d + +// CHECK: pdepl (%rax), %r11d, %r10d +// CHECK: encoding: [0xc4,0x62,0x23,0xf5,0x10] + pdepl (%rax), %r11d, %r10d + +// CHECK: pdepq %r12, %r11, %r10 +// CHECK: encoding: [0xc4,0x42,0xa3,0xf5,0xd4] + pdepq %r12, %r11, %r10 + +// CHECK: pdepq (%rax), %r11, %r10 +// CHECK: encoding: [0xc4,0x62,0xa3,0xf5,0x10] + pdepq (%rax), %r11, %r10 + +// CHECK: mulxl %r12d, %r11d, %r10d +// CHECK: encoding: [0xc4,0x42,0x23,0xf6,0xd4] + mulxl %r12d, %r11d, %r10d + +// CHECK: mulxl (%rax), %r11d, %r10d +// CHECK: encoding: [0xc4,0x62,0x23,0xf6,0x10] + mulxl (%rax), %r11d, %r10d + +// CHECK: mulxq %r12, %r11, %r10 +// CHECK: encoding: [0xc4,0x42,0xa3,0xf6,0xd4] + mulxq %r12, %r11, %r10 + +// CHECK: mulxq (%rax), %r11, %r10 +// CHECK: encoding: [0xc4,0x62,0xa3,0xf6,0x10] + mulxq (%rax), %r11, %r10 + +// CHECK: rorxl $10, %r12d, %r10d +// CHECK: encoding: [0xc4,0x43,0x7b,0xf0,0xd4,0x0a] + rorxl $10, %r12d, %r10d + +// CHECK: rorxl $31, (%rax), %r10d +// CHECK: encoding: [0xc4,0x63,0x7b,0xf0,0x10,0x1f] + rorxl $31, (%rax), %r10d + +// CHECK: rorxq $1, %r12, %r10 +// CHECK: encoding: [0xc4,0x43,0xfb,0xf0,0xd4,0x01] + rorxq $1, %r12, %r10 + +// CHECK: rorxq $63, (%rax), %r10 +// CHECK: encoding: [0xc4,0x63,0xfb,0xf0,0x10,0x3f] + rorxq $63, (%rax), %r10 + +// CHECK: shlxl %r12d, (%rax), %r10d +// CHECK: encoding: [0xc4,0x62,0x19,0xf7,0x10] + shlxl %r12d, (%rax), %r10d + +// CHECK: shlxl %r12d, %r11d, %r10d +// CHECK: encoding: [0xc4,0x42,0x19,0xf7,0xd3] + shlxl %r12d, %r11d, %r10d + +// CHECK: shlxq %r12, (%rax), %r10 +// CHECK: encoding: [0xc4,0x62,0x99,0xf7,0x10] + shlxq %r12, (%rax), %r10 + +// CHECK: shlxq %r12, %r11, %r10 +// CHECK: encoding: [0xc4,0x42,0x99,0xf7,0xd3] + shlxq %r12, %r11, %r10 + +// CHECK: sarxl %r12d, (%rax), %r10d +// CHECK: encoding: [0xc4,0x62,0x1a,0xf7,0x10] + sarxl %r12d, (%rax), %r10d + +// CHECK: sarxl %r12d, %r11d, %r10d +// CHECK: encoding: [0xc4,0x42,0x1a,0xf7,0xd3] + sarxl %r12d, %r11d, %r10d + +// CHECK: sarxq %r12, (%rax), %r10 +// CHECK: encoding: [0xc4,0x62,0x9a,0xf7,0x10] + sarxq %r12, (%rax), %r10 + +// CHECK: sarxq %r12, %r11, %r10 +// CHECK: encoding: [0xc4,0x42,0x9a,0xf7,0xd3] + sarxq %r12, %r11, %r10 + +// CHECK: shrxl %r12d, (%rax), %r10d +// CHECK: encoding: [0xc4,0x62,0x1b,0xf7,0x10] + shrxl %r12d, (%rax), %r10d + +// CHECK: shrxl %r12d, %r11d, %r10d +// CHECK: encoding: [0xc4,0x42,0x1b,0xf7,0xd3] + shrxl %r12d, %r11d, %r10d + +// CHECK: shrxq %r12, (%rax), %r10 +// CHECK: encoding: [0xc4,0x62,0x9b,0xf7,0x10] + shrxq %r12, (%rax), %r10 + +// CHECK: shrxq %r12, %r11, %r10 +// CHECK: encoding: [0xc4,0x42,0x9b,0xf7,0xd3] + shrxq %r12, %r11, %r10 + diff --git a/test/MC/X86/x86_64-fma4-encoding.s b/test/MC/X86/x86_64-fma4-encoding.s new file mode 100644 index 0000000..805fc23 --- /dev/null +++ b/test/MC/X86/x86_64-fma4-encoding.s @@ -0,0 +1,391 @@ +// RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s + +// vfmadd +// CHECK: vfmaddss (%rcx), %xmm1, %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0xf9,0x6a,0x01,0x10] + vfmaddss (%rcx), %xmm1, %xmm0, %xmm0 + +// CHECK: vfmaddss %xmm1, (%rcx), %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0x79,0x6a,0x01,0x10] + vfmaddss %xmm1, (%rcx),%xmm0, %xmm0 + +// CHECK: vfmaddss %xmm2, %xmm1, %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0xf9,0x6a,0xc2,0x10] + vfmaddss %xmm2, %xmm1, %xmm0, %xmm0 + +// CHECK: vfmaddsd (%rcx), %xmm1, %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0xf9,0x6b,0x01,0x10] + vfmaddsd (%rcx), %xmm1, %xmm0, %xmm0 + +// CHECK: vfmaddsd %xmm1, (%rcx), %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0x79,0x6b,0x01,0x10] + vfmaddsd %xmm1, (%rcx),%xmm0, %xmm0 + +// CHECK: vfmaddsd %xmm2, %xmm1, %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0xf9,0x6b,0xc2,0x10] + vfmaddsd %xmm2, %xmm1, %xmm0, %xmm0 + +// CHECK: vfmaddps (%rcx), %xmm1, %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0xf9,0x68,0x01,0x10] + vfmaddps (%rcx), %xmm1, %xmm0, %xmm0 + +// CHECK: vfmaddps %xmm1, (%rcx), %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0x79,0x68,0x01,0x10] + vfmaddps %xmm1, (%rcx),%xmm0, %xmm0 + +// CHECK: vfmaddps %xmm2, %xmm1, %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0xf9,0x68,0xc2,0x10] + vfmaddps %xmm2, %xmm1, %xmm0, %xmm0 + +// CHECK: vfmaddpd (%rcx), %xmm1, %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0xf9,0x69,0x01,0x10] + vfmaddpd (%rcx), %xmm1, %xmm0, %xmm0 + +// CHECK: vfmaddpd %xmm1, (%rcx), %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0x79,0x69,0x01,0x10] + vfmaddpd %xmm1, (%rcx),%xmm0, %xmm0 + +// CHECK: vfmaddpd %xmm2, %xmm1, %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0xf9,0x69,0xc2,0x10] + vfmaddpd %xmm2, %xmm1, %xmm0, %xmm0 + +// CHECK: vfmaddps (%rcx), %ymm1, %ymm0, %ymm0 +// CHECK: encoding: [0xc4,0xe3,0xfd,0x68,0x01,0x10] + vfmaddps (%rcx), %ymm1, %ymm0, %ymm0 + +// CHECK: vfmaddps %ymm1, (%rcx), %ymm0, %ymm0 +// CHECK: encoding: [0xc4,0xe3,0x7d,0x68,0x01,0x10] + vfmaddps %ymm1, (%rcx),%ymm0, %ymm0 + +// CHECK: vfmaddps %ymm2, %ymm1, %ymm0, %ymm0 +// CHECK: encoding: [0xc4,0xe3,0xfd,0x68,0xc2,0x10] + vfmaddps %ymm2, %ymm1, %ymm0, %ymm0 + +// CHECK: vfmaddpd (%rcx), %ymm1, %ymm0, %ymm0 +// CHECK: encoding: [0xc4,0xe3,0xfd,0x69,0x01,0x10] + vfmaddpd (%rcx), %ymm1, %ymm0, %ymm0 + +// CHECK: vfmaddpd %ymm1, (%rcx), %ymm0, %ymm0 +// CHECK: encoding: [0xc4,0xe3,0x7d,0x69,0x01,0x10] + vfmaddpd %ymm1, (%rcx),%ymm0, %ymm0 + +// CHECK: vfmaddpd %ymm2, %ymm1, %ymm0, %ymm0 +// CHECK: encoding: [0xc4,0xe3,0xfd,0x69,0xc2,0x10] + vfmaddpd %ymm2, %ymm1, %ymm0, %ymm0 + +// vfmsub +// CHECK: vfmsubss (%rcx), %xmm1, %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0xf9,0x6e,0x01,0x10] + vfmsubss (%rcx), %xmm1, %xmm0, %xmm0 + +// CHECK: vfmsubss %xmm1, (%rcx), %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0x79,0x6e,0x01,0x10] + vfmsubss %xmm1, (%rcx),%xmm0, %xmm0 + +// CHECK: vfmsubss %xmm2, %xmm1, %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0xf9,0x6e,0xc2,0x10] + vfmsubss %xmm2, %xmm1, %xmm0, %xmm0 + +// CHECK: vfmsubsd (%rcx), %xmm1, %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0xf9,0x6f,0x01,0x10] + vfmsubsd (%rcx), %xmm1, %xmm0, %xmm0 + +// CHECK: vfmsubsd %xmm1, (%rcx), %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0x79,0x6f,0x01,0x10] + vfmsubsd %xmm1, (%rcx),%xmm0, %xmm0 + +// CHECK: vfmsubsd %xmm2, %xmm1, %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0xf9,0x6f,0xc2,0x10] + vfmsubsd %xmm2, %xmm1, %xmm0, %xmm0 + +// CHECK: vfmsubps (%rcx), %xmm1, %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0xf9,0x6c,0x01,0x10] + vfmsubps (%rcx), %xmm1, %xmm0, %xmm0 + +// CHECK: vfmsubps %xmm1, (%rcx), %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0x79,0x6c,0x01,0x10] + vfmsubps %xmm1, (%rcx),%xmm0, %xmm0 + +// CHECK: vfmsubps %xmm2, %xmm1, %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0xf9,0x6c,0xc2,0x10] + vfmsubps %xmm2, %xmm1, %xmm0, %xmm0 + +// CHECK: vfmsubpd (%rcx), %xmm1, %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0xf9,0x6d,0x01,0x10] + vfmsubpd (%rcx), %xmm1, %xmm0, %xmm0 + +// CHECK: vfmsubpd %xmm1, (%rcx), %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0x79,0x6d,0x01,0x10] + vfmsubpd %xmm1, (%rcx),%xmm0, %xmm0 + +// CHECK: vfmsubpd %xmm2, %xmm1, %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0xf9,0x6d,0xc2,0x10] + vfmsubpd %xmm2, %xmm1, %xmm0, %xmm0 + +// CHECK: vfmsubps (%rcx), %ymm1, %ymm0, %ymm0 +// CHECK: encoding: [0xc4,0xe3,0xfd,0x6c,0x01,0x10] + vfmsubps (%rcx), %ymm1, %ymm0, %ymm0 + +// CHECK: vfmsubps %ymm1, (%rcx), %ymm0, %ymm0 +// CHECK: encoding: [0xc4,0xe3,0x7d,0x6c,0x01,0x10] + vfmsubps %ymm1, (%rcx),%ymm0, %ymm0 + +// CHECK: vfmsubps %ymm2, %ymm1, %ymm0, %ymm0 +// CHECK: encoding: [0xc4,0xe3,0xfd,0x6c,0xc2,0x10] + vfmsubps %ymm2, %ymm1, %ymm0, %ymm0 + +// CHECK: vfmsubpd (%rcx), %ymm1, %ymm0, %ymm0 +// CHECK: encoding: [0xc4,0xe3,0xfd,0x6d,0x01,0x10] + vfmsubpd (%rcx), %ymm1, %ymm0, %ymm0 + +// CHECK: vfmsubpd %ymm1, (%rcx), %ymm0, %ymm0 +// CHECK: encoding: [0xc4,0xe3,0x7d,0x6d,0x01,0x10] + vfmsubpd %ymm1, (%rcx),%ymm0, %ymm0 + +// CHECK: vfmsubpd %ymm2, %ymm1, %ymm0, %ymm0 +// CHECK: encoding: [0xc4,0xe3,0xfd,0x6d,0xc2,0x10] + vfmsubpd %ymm2, %ymm1, %ymm0, %ymm0 + +// vfnmadd +// CHECK: vfnmaddss (%rcx), %xmm1, %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0xf9,0x7a,0x01,0x10] + vfnmaddss (%rcx), %xmm1, %xmm0, %xmm0 + +// CHECK: vfnmaddss %xmm1, (%rcx), %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0x79,0x7a,0x01,0x10] + vfnmaddss %xmm1, (%rcx),%xmm0, %xmm0 + +// CHECK: vfnmaddss %xmm2, %xmm1, %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0xf9,0x7a,0xc2,0x10] + vfnmaddss %xmm2, %xmm1, %xmm0, %xmm0 + +// CHECK: vfnmaddsd (%rcx), %xmm1, %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0xf9,0x7b,0x01,0x10] + vfnmaddsd (%rcx), %xmm1, %xmm0, %xmm0 + +// CHECK: vfnmaddsd %xmm1, (%rcx), %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0x79,0x7b,0x01,0x10] + vfnmaddsd %xmm1, (%rcx),%xmm0, %xmm0 + +// CHECK: vfnmaddsd %xmm2, %xmm1, %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0xf9,0x7b,0xc2,0x10] + vfnmaddsd %xmm2, %xmm1, %xmm0, %xmm0 + +// CHECK: vfnmaddps (%rcx), %xmm1, %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0xf9,0x78,0x01,0x10] + vfnmaddps (%rcx), %xmm1, %xmm0, %xmm0 + +// CHECK: vfnmaddps %xmm1, (%rcx), %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0x79,0x78,0x01,0x10] + vfnmaddps %xmm1, (%rcx),%xmm0, %xmm0 + +// CHECK: vfnmaddps %xmm2, %xmm1, %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0xf9,0x78,0xc2,0x10] + vfnmaddps %xmm2, %xmm1, %xmm0, %xmm0 + +// CHECK: vfnmaddpd (%rcx), %xmm1, %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0xf9,0x79,0x01,0x10] + vfnmaddpd (%rcx), %xmm1, %xmm0, %xmm0 + +// CHECK: vfnmaddpd %xmm1, (%rcx), %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0x79,0x79,0x01,0x10] + vfnmaddpd %xmm1, (%rcx),%xmm0, %xmm0 + +// CHECK: vfnmaddpd %xmm2, %xmm1, %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0xf9,0x79,0xc2,0x10] + vfnmaddpd %xmm2, %xmm1, %xmm0, %xmm0 + +// CHECK: vfnmaddps (%rcx), %ymm1, %ymm0, %ymm0 +// CHECK: encoding: [0xc4,0xe3,0xfd,0x78,0x01,0x10] + vfnmaddps (%rcx), %ymm1, %ymm0, %ymm0 + +// CHECK: vfnmaddps %ymm1, (%rcx), %ymm0, %ymm0 +// CHECK: encoding: [0xc4,0xe3,0x7d,0x78,0x01,0x10] + vfnmaddps %ymm1, (%rcx),%ymm0, %ymm0 + +// CHECK: vfnmaddps %ymm2, %ymm1, %ymm0, %ymm0 +// CHECK: encoding: [0xc4,0xe3,0xfd,0x78,0xc2,0x10] + vfnmaddps %ymm2, %ymm1, %ymm0, %ymm0 + +// CHECK: vfnmaddpd (%rcx), %ymm1, %ymm0, %ymm0 +// CHECK: encoding: [0xc4,0xe3,0xfd,0x79,0x01,0x10] + vfnmaddpd (%rcx), %ymm1, %ymm0, %ymm0 + +// CHECK: vfnmaddpd %ymm1, (%rcx), %ymm0, %ymm0 +// CHECK: encoding: [0xc4,0xe3,0x7d,0x79,0x01,0x10] + vfnmaddpd %ymm1, (%rcx),%ymm0, %ymm0 + +// CHECK: vfnmaddpd %ymm2, %ymm1, %ymm0, %ymm0 +// CHECK: encoding: [0xc4,0xe3,0xfd,0x79,0xc2,0x10] + vfnmaddpd %ymm2, %ymm1, %ymm0, %ymm0 + +// vfnmsub +// CHECK: vfnmsubss (%rcx), %xmm1, %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0xf9,0x7e,0x01,0x10] + vfnmsubss (%rcx), %xmm1, %xmm0, %xmm0 + +// CHECK: vfnmsubss %xmm1, (%rcx), %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0x79,0x7e,0x01,0x10] + vfnmsubss %xmm1, (%rcx),%xmm0, %xmm0 + +// CHECK: vfnmsubss %xmm2, %xmm1, %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0xf9,0x7e,0xc2,0x10] + vfnmsubss %xmm2, %xmm1, %xmm0, %xmm0 + +// CHECK: vfnmsubsd (%rcx), %xmm1, %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0xf9,0x7f,0x01,0x10] + vfnmsubsd (%rcx), %xmm1, %xmm0, %xmm0 + +// CHECK: vfnmsubsd %xmm1, (%rcx), %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0x79,0x7f,0x01,0x10] + vfnmsubsd %xmm1, (%rcx),%xmm0, %xmm0 + +// CHECK: vfnmsubsd %xmm2, %xmm1, %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0xf9,0x7f,0xc2,0x10] + vfnmsubsd %xmm2, %xmm1, %xmm0, %xmm0 + +// CHECK: vfnmsubps (%rcx), %xmm1, %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0xf9,0x7c,0x01,0x10] + vfnmsubps (%rcx), %xmm1, %xmm0, %xmm0 + +// CHECK: vfnmsubps %xmm1, (%rcx), %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0x79,0x7c,0x01,0x10] + vfnmsubps %xmm1, (%rcx),%xmm0, %xmm0 + +// CHECK: vfnmsubps %xmm2, %xmm1, %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0xf9,0x7c,0xc2,0x10] + vfnmsubps %xmm2, %xmm1, %xmm0, %xmm0 + +// CHECK: vfnmsubpd (%rcx), %xmm1, %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0xf9,0x7d,0x01,0x10] + vfnmsubpd (%rcx), %xmm1, %xmm0, %xmm0 + +// CHECK: vfnmsubpd %xmm1, (%rcx), %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0x79,0x7d,0x01,0x10] + vfnmsubpd %xmm1, (%rcx),%xmm0, %xmm0 + +// CHECK: vfnmsubpd %xmm2, %xmm1, %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0xf9,0x7d,0xc2,0x10] + vfnmsubpd %xmm2, %xmm1, %xmm0, %xmm0 + +// CHECK: vfnmsubps (%rcx), %ymm1, %ymm0, %ymm0 +// CHECK: encoding: [0xc4,0xe3,0xfd,0x7c,0x01,0x10] + vfnmsubps (%rcx), %ymm1, %ymm0, %ymm0 + +// CHECK: vfnmsubps %ymm1, (%rcx), %ymm0, %ymm0 +// CHECK: encoding: [0xc4,0xe3,0x7d,0x7c,0x01,0x10] + vfnmsubps %ymm1, (%rcx),%ymm0, %ymm0 + +// CHECK: vfnmsubps %ymm2, %ymm1, %ymm0, %ymm0 +// CHECK: encoding: [0xc4,0xe3,0xfd,0x7c,0xc2,0x10] + vfnmsubps %ymm2, %ymm1, %ymm0, %ymm0 + +// CHECK: vfnmsubpd (%rcx), %ymm1, %ymm0, %ymm0 +// CHECK: encoding: [0xc4,0xe3,0xfd,0x7d,0x01,0x10] + vfnmsubpd (%rcx), %ymm1, %ymm0, %ymm0 + +// CHECK: vfnmsubpd %ymm1, (%rcx), %ymm0, %ymm0 +// CHECK: encoding: [0xc4,0xe3,0x7d,0x7d,0x01,0x10] + vfnmsubpd %ymm1, (%rcx),%ymm0, %ymm0 + +// CHECK: vfnmsubpd %ymm2, %ymm1, %ymm0, %ymm0 +// CHECK: encoding: [0xc4,0xe3,0xfd,0x7d,0xc2,0x10] + vfnmsubpd %ymm2, %ymm1, %ymm0, %ymm0 + +// vfmaddsub +// CHECK: vfmaddsubps (%rcx), %xmm1, %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0xf9,0x5c,0x01,0x10] + vfmaddsubps (%rcx), %xmm1, %xmm0, %xmm0 + +// CHECK: vfmaddsubps %xmm1, (%rcx), %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0x79,0x5c,0x01,0x10] + vfmaddsubps %xmm1, (%rcx),%xmm0, %xmm0 + +// CHECK: vfmaddsubps %xmm2, %xmm1, %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0xf9,0x5c,0xc2,0x10] + vfmaddsubps %xmm2, %xmm1, %xmm0, %xmm0 + +// CHECK: vfmaddsubpd (%rcx), %xmm1, %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0xf9,0x5d,0x01,0x10] + vfmaddsubpd (%rcx), %xmm1, %xmm0, %xmm0 + +// CHECK: vfmaddsubpd %xmm1, (%rcx), %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0x79,0x5d,0x01,0x10] + vfmaddsubpd %xmm1, (%rcx),%xmm0, %xmm0 + +// CHECK: vfmaddsubpd %xmm2, %xmm1, %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0xf9,0x5d,0xc2,0x10] + vfmaddsubpd %xmm2, %xmm1, %xmm0, %xmm0 + +// CHECK: vfmaddsubps (%rcx), %ymm1, %ymm0, %ymm0 +// CHECK: encoding: [0xc4,0xe3,0xfd,0x5c,0x01,0x10] + vfmaddsubps (%rcx), %ymm1, %ymm0, %ymm0 + +// CHECK: vfmaddsubps %ymm1, (%rcx), %ymm0, %ymm0 +// CHECK: encoding: [0xc4,0xe3,0x7d,0x5c,0x01,0x10] + vfmaddsubps %ymm1, (%rcx),%ymm0, %ymm0 + +// CHECK: vfmaddsubps %ymm2, %ymm1, %ymm0, %ymm0 +// CHECK: encoding: [0xc4,0xe3,0xfd,0x5c,0xc2,0x10] + vfmaddsubps %ymm2, %ymm1, %ymm0, %ymm0 + +// CHECK: vfmaddsubpd (%rcx), %ymm1, %ymm0, %ymm0 +// CHECK: encoding: [0xc4,0xe3,0xfd,0x5d,0x01,0x10] + vfmaddsubpd (%rcx), %ymm1, %ymm0, %ymm0 + +// CHECK: vfmaddsubpd %ymm1, (%rcx), %ymm0, %ymm0 +// CHECK: encoding: [0xc4,0xe3,0x7d,0x5d,0x01,0x10] + vfmaddsubpd %ymm1, (%rcx),%ymm0, %ymm0 + +// CHECK: vfmaddsubpd %ymm2, %ymm1, %ymm0, %ymm0 +// CHECK: encoding: [0xc4,0xe3,0xfd,0x5d,0xc2,0x10] + vfmaddsubpd %ymm2, %ymm1, %ymm0, %ymm0 + +// vfmsubadd +// CHECK: vfmsubaddps (%rcx), %xmm1, %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0xf9,0x5e,0x01,0x10] + vfmsubaddps (%rcx), %xmm1, %xmm0, %xmm0 + +// CHECK: vfmsubaddps %xmm1, (%rcx), %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0x79,0x5e,0x01,0x10] + vfmsubaddps %xmm1, (%rcx),%xmm0, %xmm0 + +// CHECK: vfmsubaddps %xmm2, %xmm1, %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0xf9,0x5e,0xc2,0x10] + vfmsubaddps %xmm2, %xmm1, %xmm0, %xmm0 + +// CHECK: vfmsubaddpd (%rcx), %xmm1, %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0xf9,0x5f,0x01,0x10] + vfmsubaddpd (%rcx), %xmm1, %xmm0, %xmm0 + +// CHECK: vfmsubaddpd %xmm1, (%rcx), %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0x79,0x5f,0x01,0x10] + vfmsubaddpd %xmm1, (%rcx),%xmm0, %xmm0 + +// CHECK: vfmsubaddpd %xmm2, %xmm1, %xmm0, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0xf9,0x5f,0xc2,0x10] + vfmsubaddpd %xmm2, %xmm1, %xmm0, %xmm0 + +// CHECK: vfmsubaddps (%rcx), %ymm1, %ymm0, %ymm0 +// CHECK: encoding: [0xc4,0xe3,0xfd,0x5e,0x01,0x10] + vfmsubaddps (%rcx), %ymm1, %ymm0, %ymm0 + +// CHECK: vfmsubaddps %ymm1, (%rcx), %ymm0, %ymm0 +// CHECK: encoding: [0xc4,0xe3,0x7d,0x5e,0x01,0x10] + vfmsubaddps %ymm1, (%rcx),%ymm0, %ymm0 + +// CHECK: vfmsubaddps %ymm2, %ymm1, %ymm0, %ymm0 +// CHECK: encoding: [0xc4,0xe3,0xfd,0x5e,0xc2,0x10] + vfmsubaddps %ymm2, %ymm1, %ymm0, %ymm0 + +// CHECK: vfmsubaddpd (%rcx), %ymm1, %ymm0, %ymm0 +// CHECK: encoding: [0xc4,0xe3,0xfd,0x5f,0x01,0x10] + vfmsubaddpd (%rcx), %ymm1, %ymm0, %ymm0 + +// CHECK: vfmsubaddpd %ymm1, (%rcx), %ymm0, %ymm0 +// CHECK: encoding: [0xc4,0xe3,0x7d,0x5f,0x01,0x10] + vfmsubaddpd %ymm1, (%rcx),%ymm0, %ymm0 + +// CHECK: vfmsubaddpd %ymm2, %ymm1, %ymm0, %ymm0 +// CHECK: encoding: [0xc4,0xe3,0xfd,0x5f,0xc2,0x10] + vfmsubaddpd %ymm2, %ymm1, %ymm0, %ymm0 diff --git a/test/MC/X86/x86_64-xop-encoding.s b/test/MC/X86/x86_64-xop-encoding.s new file mode 100644 index 0000000..1137b71 --- /dev/null +++ b/test/MC/X86/x86_64-xop-encoding.s @@ -0,0 +1,584 @@ +// RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s + +////////////////////////// +// 2 operand instructions +///////////////////////// + +// vphsubwd +// CHECK: vphsubwd (%rcx,%rax), %xmm1 +// CHECK: encoding: [0x8f,0xe9,0x78,0xe2,0x0c,0x01] + vphsubwd (%rcx,%rax), %xmm1 +// CHECK: vphsubwd %xmm0, %xmm1 +// CHECK: encoding: [0x8f,0xe9,0x78,0xe2,0xc8] + vphsubwd %xmm0, %xmm1 + +// vphsubdq +// CHECK: vphsubdq (%rcx,%rax), %xmm1 +// CHECK: encoding: [0x8f,0xe9,0x78,0xe3,0x0c,0x01] + vphsubdq (%rcx,%rax), %xmm1 +// CHECK: vphsubdq %xmm0, %xmm1 +// CHECK: encoding: [0x8f,0xe9,0x78,0xe3,0xc8] + vphsubdq %xmm0, %xmm1 + +// vphsubbw +// CHECK: vphsubbw (%rax), %xmm1 +// CHECK: encoding: [0x8f,0xe9,0x78,0xe1,0x08] + vphsubbw (%rax), %xmm1 +// CHECK: vphsubbw %xmm2, %xmm1 +// CHECK: encoding: [0x8f,0xe9,0x78,0xe1,0xca] + vphsubbw %xmm2, %xmm1 + +// vphaddwq +// CHECK: vphaddwq (%rcx), %xmm4 +// CHECK: encoding: [0x8f,0xe9,0x78,0xc7,0x21] + vphaddwq (%rcx), %xmm4 +// CHECK: vphaddwq %xmm6, %xmm2 +// CHECK: encoding: [0x8f,0xe9,0x78,0xc7,0xd6] + vphaddwq %xmm6, %xmm2 + +// vphaddwd +// CHECK: vphaddwd (%rdx,%rax), %xmm7 +// CHECK: encoding: [0x8f,0xe9,0x78,0xc6,0x3c,0x02] + vphaddwd (%rdx,%rax), %xmm7 +// CHECK: vphaddwd %xmm3, %xmm4 +// CHECK: encoding: [0x8f,0xe9,0x78,0xc6,0xe3] + vphaddwd %xmm3, %xmm4 + +// vphadduwq +// CHECK: vphadduwq (%rcx,%rax), %xmm6 +// CHECK: encoding: [0x8f,0xe9,0x78,0xd7,0x34,0x01] + vphadduwq (%rcx,%rax), %xmm6 +// CHECK: vphadduwq %xmm7, %xmm0 +// CHECK: encoding: [0x8f,0xe9,0x78,0xd7,0xc7] + vphadduwq %xmm7, %xmm0 + +// vphadduwd +// CHECK: vphadduwd (%rax), %xmm5 +// CHECK: encoding: [0x8f,0xe9,0x78,0xd6,0x28] + vphadduwd (%rax), %xmm5 +// CHECK: vphadduwd %xmm2, %xmm1 +// CHECK: encoding: [0x8f,0xe9,0x78,0xd6,0xca] + vphadduwd %xmm2, %xmm1 + +// vphaddudq +// CHECK: vphaddudq 8(%rcx,%rax), %xmm4 +// CHECK: encoding: [0x8f,0xe9,0x78,0xdb,0x64,0x01,0x08] + vphaddudq 8(%rcx,%rax), %xmm4 +// CHECK: vphaddudq %xmm6, %xmm2 +// CHECK: encoding: [0x8f,0xe9,0x78,0xdb,0xd6] + vphaddudq %xmm6, %xmm2 + +// vphaddubw +// CHECK: vphaddubw (%rcx), %xmm3 +// CHECK: encoding: [0x8f,0xe9,0x78,0xd1,0x19] + vphaddubw (%rcx), %xmm3 +// CHECK: vphaddubw %xmm5, %xmm0 +// CHECK: encoding: [0x8f,0xe9,0x78,0xd1,0xc5] + vphaddubw %xmm5, %xmm0 + +// vphaddubq +// CHECK: vphaddubq (%rcx), %xmm4 +// CHECK: encoding: [0x8f,0xe9,0x78,0xd3,0x21] + vphaddubq (%rcx), %xmm4 +// CHECK: vphaddubq %xmm2, %xmm2 +// CHECK: encoding: [0x8f,0xe9,0x78,0xd3,0xd2] + vphaddubq %xmm2, %xmm2 + +// vphaddubd +// CHECK: vphaddubd (%rax), %xmm5 +// CHECK: encoding: [0x8f,0xe9,0x78,0xd2,0x28] + vphaddubd (%rax), %xmm5 +// CHECK: vphaddubd %xmm5, %xmm7 +// CHECK: encoding: [0x8f,0xe9,0x78,0xd2,0xfd] + vphaddubd %xmm5, %xmm7 + +// vphadddq +// CHECK: vphadddq (%rdx), %xmm4 +// CHECK: encoding: [0x8f,0xe9,0x78,0xcb,0x22] + vphadddq (%rdx), %xmm4 +// CHECK: vphadddq %xmm4, %xmm5 +// CHECK: encoding: [0x8f,0xe9,0x78,0xcb,0xec] + vphadddq %xmm4, %xmm5 + +// vphaddbw +// CHECK: vphaddbw (%rcx,%rax), %xmm1 +// CHECK: encoding: [0x8f,0xe9,0x78,0xc1,0x0c,0x01] + vphaddbw (%rcx,%rax), %xmm1 +// CHECK: vphaddbw %xmm5, %xmm6 +// CHECK: encoding: [0x8f,0xe9,0x78,0xc1,0xf5] + vphaddbw %xmm5, %xmm6 + +// vphaddbq +// CHECK: vphaddbq (%rcx,%rax), %xmm1 +// CHECK: encoding: [0x8f,0xe9,0x78,0xc3,0x0c,0x01] + vphaddbq (%rcx,%rax), %xmm1 +// CHECK: vphaddbq %xmm2, %xmm0 +// CHECK: encoding: [0x8f,0xe9,0x78,0xc3,0xc2] + vphaddbq %xmm2, %xmm0 + +// vphaddbd +// CHECK: vphaddbd (%rcx,%rax), %xmm1 +// CHECK: encoding: [0x8f,0xe9,0x78,0xc2,0x0c,0x01] + vphaddbd (%rcx,%rax), %xmm1 +// CHECK: vphaddbd %xmm1, %xmm3 +// CHECK: encoding: [0x8f,0xe9,0x78,0xc2,0xd9] + vphaddbd %xmm1, %xmm3 + +// vfrczss +// CHECK: vfrczss (%rcx,%rax), %xmm1 +// CHECK: encoding: [0x8f,0xe9,0x78,0x82,0x0c,0x01] + vfrczss (%rcx,%rax), %xmm1 +// CHECK: vfrczss %xmm5, %xmm7 +// CHECK: encoding: [0x8f,0xe9,0x78,0x82,0xfd] + vfrczss %xmm5, %xmm7 + +// vfrczsd +// CHECK: vfrczsd (%rcx,%rax), %xmm1 +// CHECK: encoding: [0x8f,0xe9,0x78,0x83,0x0c,0x01] + vfrczsd (%rcx,%rax), %xmm1 +// CHECK: vfrczsd %xmm7, %xmm0 +// CHECK: encoding: [0x8f,0xe9,0x78,0x83,0xc7] + vfrczsd %xmm7, %xmm0 + +// vfrczps +// CHECK: vfrczps 4(%rax), %xmm3 +// CHECK: encoding: [0x8f,0xe9,0x78,0x80,0x58,0x04] + vfrczps 4(%rax), %xmm3 +// CHECK: vfrczps %xmm6, %xmm5 +// CHECK: encoding: [0x8f,0xe9,0x78,0x80,0xee] + vfrczps %xmm6, %xmm5 +// CHECK: vfrczps (%rcx), %xmm1 +// CHECK: encoding: [0x8f,0xe9,0x78,0x80,0x09] + vfrczps (%rcx), %xmm1 +// CHECK: vfrczps %ymm2, %ymm4 +// CHECK: encoding: [0x8f,0xe9,0x7c,0x80,0xe2] + vfrczps %ymm2, %ymm4 + +// vfrczpd +// CHECK: vfrczpd (%rcx,%rax), %xmm1 +// CHECK: encoding: [0x8f,0xe9,0x78,0x81,0x0c,0x01] + vfrczpd (%rcx,%rax), %xmm1 +// CHECK: vfrczpd %xmm7, %xmm0 +// CHECK: encoding: [0x8f,0xe9,0x78,0x81,0xc7] + vfrczpd %xmm7, %xmm0 +// CHECK: vfrczpd (%rcx,%rax), %ymm2 +// CHECK: encoding: [0x8f,0xe9,0x7c,0x81,0x14,0x01] + vfrczpd (%rcx,%rax), %ymm2 +// CHECK: vfrczpd %ymm5, %ymm3 +// CHECK: encoding: [0x8f,0xe9,0x7c,0x81,0xdd] + vfrczpd %ymm5, %ymm3 + + + +////////////////////////// +// 3 operand instructions +///////////////////////// + +// vpshlw +// CHECK: vpshlw %xmm0, %xmm1, %xmm2 +// CHECK: encoding: [0x8f,0xe9,0x78,0x95,0xd1] + vpshlw %xmm0, %xmm1, %xmm2 +// CHECK: vpshlw (%rax), %xmm1, %xmm2 +// CHECK: encoding: [0x8f,0xe9,0xf0,0x95,0x10] + vpshlw (%rax), %xmm1, %xmm2 +// CHECK: vpshlw %xmm0, (%rax,%rcx), %xmm2 +// CHECK: encoding: [0x8f,0xe9,0x78,0x95,0x14,0x08] + vpshlw %xmm0, (%rax,%rcx), %xmm2 + +// vpshlq +// CHECK: vpshlq %xmm2, %xmm4, %xmm6 +// CHECK: encoding: [0x8f,0xe9,0x68,0x97,0xf4] + vpshlq %xmm2, %xmm4, %xmm6 +// CHECK: vpshlq (%rcx), %xmm2, %xmm1 +// CHECK: encoding: [0x8f,0xe9,0xe8,0x97,0x09] + vpshlq (%rcx), %xmm2, %xmm1 +// CHECK: vpshlq %xmm5, (%rdx,%rcx), %xmm6 +// CHECK: encoding: [0x8f,0xe9,0x50,0x97,0x34,0x0a] + vpshlq %xmm5, (%rdx,%rcx), %xmm6 + +// vpshld +// CHECK: vpshld %xmm7, %xmm5, %xmm3 +// CHECK: encoding: [0x8f,0xe9,0x40,0x96,0xdd] + vpshld %xmm7, %xmm5, %xmm3 +// CHECK: vpshld 4(%rax), %xmm3, %xmm3 +// CHECK: encoding: [0x8f,0xe9,0xe0,0x96,0x58,0x04] + vpshld 4(%rax), %xmm3, %xmm3 +// CHECK: vpshld %xmm1, (%rax,%rcx), %xmm5 +// CHECK: encoding: [0x8f,0xe9,0x70,0x96,0x2c,0x08] + vpshld %xmm1, (%rax,%rcx), %xmm5 + +// vpshlb +// CHECK: vpshlb %xmm1, %xmm2, %xmm3 +// CHECK: encoding: [0x8f,0xe9,0x70,0x94,0xda] + vpshlb %xmm1, %xmm2, %xmm3 +// CHECK: vpshlb (%rcx), %xmm0, %xmm7 +// CHECK: encoding: [0x8f,0xe9,0xf8,0x94,0x39] + vpshlb (%rcx), %xmm0, %xmm7 +// CHECK: vpshlb %xmm2, (%rax,%rdx), %xmm3 +// CHECK: encoding: [0x8f,0xe9,0x68,0x94,0x1c,0x10] + vpshlb %xmm2, (%rax,%rdx), %xmm3 + +// vpshaw +// CHECK: vpshaw %xmm7, %xmm5, %xmm3 +// CHECK: encoding: [0x8f,0xe9,0x40,0x99,0xdd] + vpshaw %xmm7, %xmm5, %xmm3 +// CHECK: vpshaw (%rax), %xmm2, %xmm1 +// CHECK: encoding: [0x8f,0xe9,0xe8,0x99,0x08] + vpshaw (%rax), %xmm2, %xmm1 +// CHECK: vpshaw %xmm0, 8(%rax,%rcx), %xmm3 +// CHECK: encoding: [0x8f,0xe9,0x78,0x99,0x5c,0x08,0x08] + vpshaw %xmm0, 8(%rax,%rcx), %xmm3 + +// vpshaq +// CHECK: vpshaq %xmm4, %xmm4, %xmm4 +// CHECK: encoding: [0x8f,0xe9,0x58,0x9b,0xe4] + vpshaq %xmm4, %xmm4, %xmm4 +// CHECK: vpshaq (%rcx), %xmm2, %xmm0 +// CHECK: encoding: [0x8f,0xe9,0xe8,0x9b,0x01] + vpshaq (%rcx), %xmm2, %xmm0 +// CHECK: vpshaq %xmm6, (%rax,%rcx), %xmm5 +// CHECK: encoding: [0x8f,0xe9,0x48,0x9b,0x2c,0x08] + vpshaq %xmm6, (%rax,%rcx), %xmm5 + +// vpshad +// CHECK: vpshad %xmm5, %xmm4, %xmm0 +// CHECK: encoding: [0x8f,0xe9,0x50,0x9a,0xc4] + vpshad %xmm5, %xmm4, %xmm0 +// CHECK: vpshad (%rax), %xmm2, %xmm5 +// CHECK: encoding: [0x8f,0xe9,0xe8,0x9a,0x28] + vpshad (%rax), %xmm2, %xmm5 +// CHECK: vpshad %xmm2, (%rax), %xmm5 +// CHECK: encoding: [0x8f,0xe9,0x68,0x9a,0x28] + vpshad %xmm2, (%rax), %xmm5 + +// vpshab +// CHECK: vpshab %xmm1, %xmm1, %xmm0 +// CHECK: encoding: [0x8f,0xe9,0x70,0x98,0xc1] + vpshab %xmm1, %xmm1, %xmm0 +// CHECK: vpshab (%rcx), %xmm4, %xmm0 +// CHECK: encoding: [0x8f,0xe9,0xd8,0x98,0x01] + vpshab (%rcx), %xmm4, %xmm0 +// CHECK: vpshab %xmm5, (%rcx), %xmm3 +// CHECK: encoding: [0x8f,0xe9,0x50,0x98,0x19] + vpshab %xmm5, (%rcx), %xmm3 + +// vprotw +// CHECK: vprotw (%rax), %xmm3, %xmm6 +// CHECK: encoding: [0x8f,0xe9,0xe0,0x91,0x30] + vprotw (%rax), %xmm3, %xmm6 +// CHECK: vprotw %xmm5, (%rax,%rcx), %xmm1 +// CHECK: encoding: [0x8f,0xe9,0x50,0x91,0x0c,0x08] + vprotw %xmm5, (%rax,%rcx), %xmm1 +// CHECK: vprotw %xmm0, %xmm1, %xmm2 +// CHECK: encoding: [0x8f,0xe9,0x78,0x91,0xd1] + vprotw %xmm0, %xmm1, %xmm2 +// CHECK: vprotw $42, (%rcx), %xmm1 +// CHECK: encoding: [0x8f,0xe8,0x78,0xc1,0x09,0x2a] + vprotw $42, (%rcx), %xmm1 +// CHECK: vprotw $41, (%rax), %xmm4 +// CHECK: encoding: [0x8f,0xe8,0x78,0xc1,0x20,0x29] + vprotw $41, (%rax), %xmm4 +// CHECK: vprotw $40, %xmm1, %xmm3 +// CHECK: encoding: [0x8f,0xe8,0x78,0xc1,0xd9,0x28] + vprotw $40, %xmm1, %xmm3 + +// vprotq +// CHECK: vprotq (%rax), %xmm1, %xmm2 +// CHECK: encoding: [0x8f,0xe9,0xf0,0x93,0x10] + vprotq (%rax), %xmm1, %xmm2 +// CHECK: vprotq (%rax,%rcx), %xmm1, %xmm2 +// CHECK: encoding: [0x8f,0xe9,0xf0,0x93,0x14,0x08] + vprotq (%rax,%rcx), %xmm1, %xmm2 +// CHECK: vprotq %xmm0, %xmm1, %xmm2 +// CHECK: encoding: [0x8f,0xe9,0x78,0x93,0xd1] + vprotq %xmm0, %xmm1, %xmm2 +// CHECK: vprotq $42, (%rax), %xmm2 +// CHECK: encoding: [0x8f,0xe8,0x78,0xc3,0x10,0x2a] + vprotq $42, (%rax), %xmm2 +// CHECK: vprotq $42, (%rax,%rcx), %xmm2 +// CHECK: encoding: [0x8f,0xe8,0x78,0xc3,0x14,0x08,0x2a] + vprotq $42, (%rax,%rcx), %xmm2 +// CHECK: vprotq $42, %xmm1, %xmm2 +// CHECK: encoding: [0x8f,0xe8,0x78,0xc3,0xd1,0x2a] + vprotq $42, %xmm1, %xmm2 + +// vprotd +// CHECK: vprotd (%rax), %xmm0, %xmm3 +// CHECK: encoding: [0x8f,0xe9,0xf8,0x92,0x18] + vprotd (%rax), %xmm0, %xmm3 +// CHECK: vprotd %xmm2, (%rax,%rcx), %xmm4 +// CHECK: encoding: [0x8f,0xe9,0x68,0x92,0x24,0x08] + vprotd %xmm2, (%rax,%rcx), %xmm4 +// CHECK: vprotd %xmm5, %xmm3, %xmm2 +// CHECK: encoding: [0x8f,0xe9,0x50,0x92,0xd3] + vprotd %xmm5, %xmm3, %xmm2 +// CHECK: vprotd $43, (%rcx), %xmm6 +// CHECK: encoding: [0x8f,0xe8,0x78,0xc2,0x31,0x2b] + vprotd $43, (%rcx), %xmm6 +// CHECK: vprotd $44, (%rax,%rcx), %xmm7 +// CHECK: encoding: [0x8f,0xe8,0x78,0xc2,0x3c,0x08,0x2c] + vprotd $44, (%rax,%rcx), %xmm7 +// CHECK: vprotd $45, %xmm4, %xmm4 +// CHECK: encoding: [0x8f,0xe8,0x78,0xc2,0xe4,0x2d] + vprotd $45, %xmm4, %xmm4 + +// vprotb +// CHECK: vprotb (%rcx), %xmm2, %xmm5 +// CHECK: encoding: [0x8f,0xe9,0xe8,0x90,0x29] + vprotb (%rcx), %xmm2, %xmm5 +// CHECK: vprotb %xmm5, (%rax,%rcx), %xmm4 +// CHECK: encoding: [0x8f,0xe9,0x50,0x90,0x24,0x08] + vprotb %xmm5, (%rax,%rcx), %xmm4 +// CHECK: vprotb %xmm4, %xmm3, %xmm2 +// CHECK: encoding: [0x8f,0xe9,0x58,0x90,0xd3] + vprotb %xmm4, %xmm3, %xmm2 +// CHECK: vprotb $46, (%rax), %xmm3 +// CHECK: encoding: [0x8f,0xe8,0x78,0xc0,0x18,0x2e] + vprotb $46, (%rax), %xmm3 +// CHECK: vprotb $47, (%rax,%rcx), %xmm7 +// CHECK: encoding: [0x8f,0xe8,0x78,0xc0,0x3c,0x08,0x2f] + vprotb $47, (%rax,%rcx), %xmm7 +// CHECK: vprotb $48, %xmm5, %xmm5 +// CHECK: encoding: [0x8f,0xe8,0x78,0xc0,0xed,0x30] + vprotb $48, %xmm5, %xmm5 + +////////////////////////// +// 4 operand instructions +///////////////////////// + +// vpmadcswd +// CHECK: vpmadcswd %xmm1, %xmm2, %xmm3, %xmm4 +// CHECK: encoding: [0x8f,0xe8,0x60,0xb6,0xe2,0x10] + vpmadcswd %xmm1, %xmm2, %xmm3, %xmm4 +// CHECK: vpmadcswd %xmm1, (%rax), %xmm3, %xmm4 +// CHECK: encoding: [0x8f,0xe8,0x60,0xb6,0x20,0x10] + vpmadcswd %xmm1, (%rax), %xmm3, %xmm4 + +// vpmadcsswd +// CHECK: vpmadcsswd %xmm1, %xmm4, %xmm6, %xmm4 +// CHECK: encoding: [0x8f,0xe8,0x48,0xa6,0xe4,0x10] + vpmadcsswd %xmm1, %xmm4, %xmm6, %xmm4 +// CHECK: vpmadcsswd %xmm1, (%rax,%rcx), %xmm3, %xmm4 +// CHECK: encoding: [0x8f,0xe8,0x60,0xa6,0x24,0x08,0x10] + vpmadcsswd %xmm1, (%rax,%rcx), %xmm3, %xmm4 + +// vpmacsww +// CHECK: vpmacsww %xmm0, %xmm2, %xmm5, %xmm4 +// CHECK: encoding: [0x8f,0xe8,0x50,0x95,0xe2,0x00] + vpmacsww %xmm0, %xmm2, %xmm5, %xmm4 +// CHECK: vpmacsww %xmm1, (%rax), %xmm6, %xmm4 +// CHECK: encoding: [0x8f,0xe8,0x48,0x95,0x20,0x10] + vpmacsww %xmm1, (%rax), %xmm6, %xmm4 + +// vpmacswd +// CHECK: vpmacswd %xmm4, %xmm5, %xmm6, %xmm7 +// CHECK: encoding: [0x8f,0xe8,0x48,0x96,0xfd,0x40] + vpmacswd %xmm4, %xmm5, %xmm6, %xmm7 +// CHECK: vpmacswd %xmm0, (%rax), %xmm1, %xmm2 +// CHECK: encoding: [0x8f,0xe8,0x70,0x96,0x10,0x00] + vpmacswd %xmm0, (%rax), %xmm1, %xmm2 + +// vpmacssww +// CHECK: vpmacssww %xmm4, %xmm3, %xmm2, %xmm1 +// CHECK: encoding: [0x8f,0xe8,0x68,0x85,0xcb,0x40] + vpmacssww %xmm4, %xmm3, %xmm2, %xmm1 +// CHECK: vpmacssww %xmm6, (%rcx), %xmm7, %xmm7 +// CHECK: encoding: [0x8f,0xe8,0x40,0x85,0x39,0x60] + vpmacssww %xmm6, (%rcx), %xmm7, %xmm7 + +// vpmacsswd +// CHECK: vpmacsswd %xmm4, %xmm2, %xmm4, %xmm2 +// CHECK: encoding: [0x8f,0xe8,0x58,0x86,0xd2,0x40] + vpmacsswd %xmm4, %xmm2, %xmm4, %xmm2 +// CHECK: vpmacsswd %xmm0, 8(%rax,%rcx), %xmm1, %xmm0 +// CHECK: encoding: [0x8f,0xe8,0x70,0x86,0x44,0x08,0x08,0x00] + vpmacsswd %xmm0, 8(%rax,%rcx), %xmm1, %xmm0 + +// vpmacssdql +// CHECK: vpmacssdql %xmm1, %xmm1, %xmm2, %xmm4 +// CHECK: encoding: [0x8f,0xe8,0x68,0x87,0xe1,0x10] + vpmacssdql %xmm1, %xmm1, %xmm2, %xmm4 +// CHECK: vpmacssdql %xmm7, (%rcx), %xmm6, %xmm5 +// CHECK: encoding: [0x8f,0xe8,0x48,0x87,0x29,0x70] + vpmacssdql %xmm7, (%rcx), %xmm6, %xmm5 + +// vpmacssdqh +// CHECK: vpmacssdqh %xmm3, %xmm2, %xmm0, %xmm1 +// CHECK: encoding: [0x8f,0xe8,0x78,0x8f,0xca,0x30] + vpmacssdqh %xmm3, %xmm2, %xmm0, %xmm1 +// CHECK: vpmacssdqh %xmm7, (%rax,%rcx), %xmm2, %xmm3 +// CHECK: encoding: [0x8f,0xe8,0x68,0x8f,0x1c,0x08,0x70] + vpmacssdqh %xmm7, (%rax,%rcx), %xmm2, %xmm3 + +// vpmacssdd +// CHECK: vpmacssdd %xmm2, %xmm2, %xmm3, %xmm5 +// CHECK: encoding: [0x8f,0xe8,0x60,0x8e,0xea,0x20] + vpmacssdd %xmm2, %xmm2, %xmm3, %xmm5 +// CHECK: vpmacssdd %xmm4, (%rax), %xmm1, %xmm2 +// CHECK: encoding: [0x8f,0xe8,0x70,0x8e,0x10,0x40] + vpmacssdd %xmm4, (%rax), %xmm1, %xmm2 + +// vpmacsdql +// CHECK: vpmacsdql %xmm3, %xmm0, %xmm6, %xmm7 +// CHECK: encoding: [0x8f,0xe8,0x48,0x97,0xf8,0x30] + vpmacsdql %xmm3, %xmm0, %xmm6, %xmm7 +// CHECK: vpmacsdql %xmm5, 8(%rcx), %xmm3, %xmm5 +// CHECK: encoding: [0x8f,0xe8,0x60,0x97,0x69,0x08,0x50] + vpmacsdql %xmm5, 8(%rcx), %xmm3, %xmm5 + +// vpmacsdqh +// CHECK: vpmacsdqh %xmm7, %xmm5, %xmm3, %xmm2 +// CHECK: encoding: [0x8f,0xe8,0x60,0x9f,0xd5,0x70] + vpmacsdqh %xmm7, %xmm5, %xmm3, %xmm2 +// CHECK: vpmacsdqh %xmm5, 4(%rax), %xmm2, %xmm0 +// CHECK: encoding: [0x8f,0xe8,0x68,0x9f,0x40,0x04,0x50] + vpmacsdqh %xmm5, 4(%rax), %xmm2, %xmm0 + +// vpmacsdd +// CHECK: vpmacsdd %xmm4, %xmm6, %xmm4, %xmm2 +// CHECK: encoding: [0x8f,0xe8,0x58,0x9e,0xd6,0x40] + vpmacsdd %xmm4, %xmm6, %xmm4, %xmm2 +// CHECK: vpmacsdd %xmm4, (%rax,%rcx), %xmm4, %xmm3 +// CHECK: encoding: [0x8f,0xe8,0x58,0x9e,0x1c,0x08,0x40] + vpmacsdd %xmm4, (%rax,%rcx), %xmm4, %xmm3 + +// vpcomw +// CHECK: vpcomw $42, %xmm2, %xmm3, %xmm4 +// CHECK: encoding: [0x8f,0xe8,0x60,0xcd,0xe2,0x2a] + vpcomw $42, %xmm2, %xmm3, %xmm4 +// CHECK: vpcomw $42, (%rax), %xmm3, %xmm4 +// CHECK: encoding: [0x8f,0xe8,0x60,0xcd,0x20,0x2a] + vpcomw $42, (%rax), %xmm3, %xmm4 + +// vpcomuw +// CHECK: vpcomuw $43, %xmm1, %xmm3, %xmm5 +// CHECK: encoding: [0x8f,0xe8,0x60,0xed,0xe9,0x2b] + vpcomuw $43, %xmm1, %xmm3, %xmm5 +// CHECK: vpcomuw $44, (%rax,%rcx), %xmm0, %xmm6 +// CHECK: encoding: [0x8f,0xe8,0x78,0xed,0x34,0x08,0x2c] + vpcomuw $44, (%rax,%rcx), %xmm0, %xmm6 + +// vpcomuq +// CHECK: vpcomuq $45, %xmm3, %xmm3, %xmm7 +// CHECK: encoding: [0x8f,0xe8,0x60,0xef,0xfb,0x2d] + vpcomuq $45, %xmm3, %xmm3, %xmm7 +// CHECK: vpcomuq $46, (%rax), %xmm3, %xmm1 +// CHECK: encoding: [0x8f,0xe8,0x60,0xef,0x08,0x2e] + vpcomuq $46, (%rax), %xmm3, %xmm1 + +// vpcomud +// CHECK: vpcomud $47, %xmm0, %xmm1, %xmm2 +// CHECK: encoding: [0x8f,0xe8,0x70,0xee,0xd0,0x2f] + vpcomud $47, %xmm0, %xmm1, %xmm2 +// CHECK: vpcomud $48, 4(%rax), %xmm6, %xmm3 +// CHECK: encoding: [0x8f,0xe8,0x48,0xee,0x58,0x04,0x30] + vpcomud $48, 4(%rax), %xmm6, %xmm3 + +// vpcomub +// CHECK: vpcomub $49, %xmm3, %xmm4, %xmm5 +// CHECK: encoding: [0x8f,0xe8,0x58,0xec,0xeb,0x31] + vpcomub $49, %xmm3, %xmm4, %xmm5 +// CHECK: vpcomub $50, (%rcx), %xmm6, %xmm2 +// CHECK: encoding: [0x8f,0xe8,0x48,0xec,0x11,0x32] + vpcomub $50, (%rcx), %xmm6, %xmm2 + +// vpcomq +// CHECK: vpcomq $51, %xmm3, %xmm0, %xmm5 +// CHECK: encoding: [0x8f,0xe8,0x78,0xcf,0xeb,0x33] + vpcomq $51, %xmm3, %xmm0, %xmm5 +// CHECK: vpcomq $52, (%rax), %xmm1, %xmm7 +// CHECK: encoding: [0x8f,0xe8,0x70,0xcf,0x38,0x34] + vpcomq $52, (%rax), %xmm1, %xmm7 + +// vpcomd +// CHECK: vpcomd $53, %xmm3, %xmm3, %xmm0 +// CHECK: encoding: [0x8f,0xe8,0x60,0xce,0xc3,0x35] + vpcomd $53, %xmm3, %xmm3, %xmm0 +// CHECK: vpcomd $54, (%rcx), %xmm2, %xmm2 +// CHECK: encoding: [0x8f,0xe8,0x68,0xce,0x11,0x36] + vpcomd $54, (%rcx), %xmm2, %xmm2 + +// vpcomb +// CHECK: vpcomb $55, %xmm6, %xmm4, %xmm2 +// CHECK: encoding: [0x8f,0xe8,0x58,0xcc,0xd6,0x37] + vpcomb $55, %xmm6, %xmm4, %xmm2 +// CHECK: vpcomb $56, 8(%rax), %xmm3, %xmm2 +// CHECK: encoding: [0x8f,0xe8,0x60,0xcc,0x50,0x08,0x38] + vpcomb $56, 8(%rax), %xmm3, %xmm2 + + +// vpperm +// CHECK: vpperm %xmm1, %xmm2, %xmm3, %xmm4 +// CHECK: encoding: [0x8f,0xe8,0x60,0xa3,0xe2,0x10] + vpperm %xmm1, %xmm2, %xmm3, %xmm4 +// CHECK: vpperm (%rax), %xmm2, %xmm3, %xmm4 +// CHECK: encoding: [0x8f,0xe8,0xe0,0xa3,0x20,0x20] + vpperm (%rax), %xmm2, %xmm3, %xmm4 +// CHECK: vpperm %xmm1, (%rax), %xmm3, %xmm4 +// CHECK: encoding: [0x8f,0xe8,0x60,0xa3,0x20,0x10] + vpperm %xmm1, (%rax), %xmm3, %xmm4 + +// vpcmov +// CHECK: vpcmov %xmm1, %xmm2, %xmm3, %xmm4 +// CHECK: encoding: [0x8f,0xe8,0x60,0xa2,0xe2,0x10] + vpcmov %xmm1, %xmm2, %xmm3, %xmm4 +// CHECK: vpcmov (%rax), %xmm2, %xmm3, %xmm4 +// CHECK: encoding: [0x8f,0xe8,0xe0,0xa2,0x20,0x20] + vpcmov (%rax), %xmm2, %xmm3, %xmm4 +// CHECK: vpcmov %xmm1, (%rax), %xmm3, %xmm4 +// CHECK: encoding: [0x8f,0xe8,0x60,0xa2,0x20,0x10] + vpcmov %xmm1, (%rax), %xmm3, %xmm4 +// CHECK: vpcmov %ymm1, %ymm2, %ymm3, %ymm4 +// CHECK: encoding: [0x8f,0xe8,0x64,0xa2,0xe2,0x10] + vpcmov %ymm1, %ymm2, %ymm3, %ymm4 +// CHECK: vpcmov (%rax), %ymm2, %ymm3, %ymm4 +// CHECK: encoding: [0x8f,0xe8,0xe4,0xa2,0x20,0x20] + vpcmov (%rax), %ymm2, %ymm3, %ymm4 +// CHECK: vpcmov %ymm1, (%rax), %ymm3, %ymm4 +// CHECK: encoding: [0x8f,0xe8,0x64,0xa2,0x20,0x10] + vpcmov %ymm1, (%rax), %ymm3, %ymm4 + + +////////////////////////// +// 5 operand instructions +///////////////////////// +// vpermil2pd +// CHECK: vpermil2pd $1, %xmm5, %xmm2, %xmm1, %xmm7 +// CHECK: encoding: [0xc4,0xe3,0x71,0x49,0xfa,0x51] + vpermil2pd $1, %xmm5, %xmm2, %xmm1, %xmm7 +// CHECK: vpermil2pd $2, (%rax), %xmm3, %xmm3, %xmm4 +// CHECK: encoding: [0xc4,0xe3,0xe1,0x49,0x20,0x32] + vpermil2pd $2, (%rax), %xmm3, %xmm3, %xmm4 +// CHECK: vpermil2pd $3, 8(%rax), %ymm0, %ymm4, %ymm6 +// CHECK: encoding: [0xc4,0xe3,0xdd,0x49,0x70,0x08,0x03] + vpermil2pd $3, 8(%rax), %ymm0, %ymm4, %ymm6 +// CHECK: vpermil2pd $0, %xmm3, (%rax,%rcx), %xmm1, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0x71,0x49,0x04,0x08,0x30] + vpermil2pd $0, %xmm3, (%rax,%rcx), %xmm1, %xmm0 +// CHECK: vpermil2pd $1, %ymm1, %ymm2, %ymm3, %ymm4 +// CHECK: encoding: [0xc4,0xe3,0x65,0x49,0xe2,0x11] + vpermil2pd $1, %ymm1, %ymm2, %ymm3, %ymm4 +// CHECK: vpermil2pd $2, %ymm1, (%rax), %ymm3, %ymm4 +// CHECK: encoding: [0xc4,0xe3,0x65,0x49,0x20,0x12] + vpermil2pd $2, %ymm1, (%rax), %ymm3, %ymm4 + +// vpermil2ps +// CHECK: vpermil2ps $0, %xmm4, %xmm3, %xmm2, %xmm1 +// CHECK: encoding: [0xc4,0xe3,0x69,0x48,0xcb,0x40] + vpermil2ps $0, %xmm4, %xmm3, %xmm2, %xmm1 +// CHECK: vpermil2ps $1, 4(%rax), %xmm2, %xmm3, %xmm0 +// CHECK: encoding: [0xc4,0xe3,0xe1,0x48,0x40,0x04,0x21] + vpermil2ps $1, 4(%rax), %xmm2, %xmm3, %xmm0 +// CHECK: vpermil2ps $2, (%rax), %ymm1, %ymm5, %ymm6 +// CHECK: encoding: [0xc4,0xe3,0xd5,0x48,0x30,0x12] + vpermil2ps $2, (%rax), %ymm1, %ymm5, %ymm6 +// CHECK: vpermil2ps $3, %xmm1, (%rax), %xmm3, %xmm4 +// CHECK: encoding: [0xc4,0xe3,0x61,0x48,0x20,0x13] + vpermil2ps $3, %xmm1, (%rax), %xmm3, %xmm4 +// CHECK: vpermil2ps $0, %ymm4, %ymm4, %ymm2, %ymm2 +// CHECK: encoding: [0xc4,0xe3,0x6d,0x48,0xd4,0x40] + vpermil2ps $0, %ymm4, %ymm4, %ymm2, %ymm2 +// CHECK: vpermil2pd $1, %ymm1, 4(%rax), %ymm1, %ymm0 +// CHECK: encoding: [0xc4,0xe3,0x75,0x49,0x40,0x04,0x11] + vpermil2pd $1, %ymm1, 4(%rax), %ymm1, %ymm0 + diff --git a/test/MC/X86/x86_errors.s b/test/MC/X86/x86_errors.s index e0a2c676..f161e06 100644 --- a/test/MC/X86/x86_errors.s +++ b/test/MC/X86/x86_errors.s @@ -15,3 +15,16 @@ addl $0, 0(%rax) # 8 "test.s" movi $8,%eax + +movl 0(%rax), 0(%edx) // error: invalid operand for instruction + +// 32: error: instruction requires a CPU feature not currently enabled +sysexitq + +// rdar://10710167 +// 64: error: expected scale expression +lea (%rsp, %rbp, $4), %rax + +// rdar://10423777 +// 64: error: index register is 32-bit, but base register is 64-bit +movq (%rsi,%ecx),%xmm0 |
