diff options
Diffstat (limited to 'test/MC/Disassembler')
33 files changed, 6668 insertions, 504 deletions
diff --git a/test/MC/Disassembler/AArch64/a64-ignored-fields.txt b/test/MC/Disassembler/AArch64/a64-ignored-fields.txt new file mode 100644 index 0000000..966530d --- /dev/null +++ b/test/MC/Disassembler/AArch64/a64-ignored-fields.txt @@ -0,0 +1,8 @@ +# RUN: llvm-mc -triple=aarch64 -disassemble -show-encoding < %s | FileCheck %s + +# The "Rm" bits are ignored, but the canonical representation has them filled +# with 0s. This is what we should produce even if the input bit-pattern had +# something else there. + +# CHECK: fcmp s31, #0.0 // encoding: [0xe8,0x23,0x20,0x1e] +0xe8 0x23 0x33 0x1e diff --git a/test/MC/Disassembler/AArch64/basic-a64-instructions.txt b/test/MC/Disassembler/AArch64/basic-a64-instructions.txt new file mode 100644 index 0000000..4fa2d50 --- /dev/null +++ b/test/MC/Disassembler/AArch64/basic-a64-instructions.txt @@ -0,0 +1,4200 @@ +# RUN: llvm-mc -triple=aarch64 -disassemble < %s | FileCheck %s + +#------------------------------------------------------------------------------ +# Add/sub (immediate) +#------------------------------------------------------------------------------ +# CHECK: add w4, w5, #0 +# CHECK: add w2, w3, #4095 +# CHECK: add w30, w29, #1, lsl #12 +# CHECK: add w13, w5, #4095, lsl #12 +# CHECK: add x5, x7, #1638 +0xa4 0x0 0x0 0x11 +0x62 0xfc 0x3f 0x11 +0xbe 0x7 0x40 0x11 +0xad 0xfc 0x7f 0x11 +0xe5 0x98 0x19 0x91 + +# CHECK: add w20, wsp, #801 +# CHECK: add wsp, wsp, #1104 +# CHECK: add wsp, w30, #4084 +0xf4 0x87 0xc 0x11 +0xff 0x43 0x11 0x11 +0xdf 0xd3 0x3f 0x11 + +# CHECK: add x0, x24, #291 +# CHECK: add x3, x24, #4095, lsl #12 +# CHECK: add x8, sp, #1074 +# CHECK: add sp, x29, #3816 +0x0 0x8f 0x4 0x91 +0x3 0xff 0x7f 0x91 +0xe8 0xcb 0x10 0x91 +0xbf 0xa3 0x3b 0x91 + +# CHECK: sub w0, wsp, #4077 +# CHECK: sub w4, w20, #546, lsl #12 +# CHECK: sub sp, sp, #288 +# CHECK: sub wsp, w19, #16 +0xe0 0xb7 0x3f 0x51 +0x84 0x8a 0x48 0x51 +0xff 0x83 0x4 0xd1 +0x7f 0x42 0x0 0x51 + + +# CHECK: adds w13, w23, #291, lsl #12 +# CHECK: cmn w2, #4095 +# CHECK: adds w20, wsp, #0 +# CHECK: cmn x3, #1, lsl #12 +0xed 0x8e 0x44 0x31 +0x5f 0xfc 0x3f 0x31 +0xf4 0x3 0x0 0x31 +0x7f 0x4 0x40 0xb1 + +# CHECK: cmp sp, #20, lsl #12 +# CHECK: cmp x30, #4095 +# CHECK: subs x4, sp, #3822 +0xff 0x53 0x40 0xf1 +0xdf 0xff 0x3f 0xf1 +0xe4 0xbb 0x3b 0xf1 + +# These should really be CMN +# CHECK: cmn w3, #291, lsl #12 +# CHECK: cmn wsp, #1365 +# CHECK: cmn sp, #1092, lsl #12 +0x7f 0x8c 0x44 0x31 +0xff 0x57 0x15 0x31 +0xff 0x13 0x51 0xb1 + +# CHECK: mov sp, x30 +# CHECK: mov wsp, w20 +# CHECK: mov x11, sp +# CHECK: mov w24, wsp +0xdf 0x3 0x0 0x91 +0x9f 0x2 0x0 0x11 +0xeb 0x3 0x0 0x91 +0xf8 0x3 0x0 0x11 + +#------------------------------------------------------------------------------ +# Add-subtract (shifted register) +#------------------------------------------------------------------------------ + +# CHECK: add w3, w5, w7 +# CHECK: add wzr, w3, w5 +# CHECK: add w20, wzr, w4 +# CHECK: add w4, w6, wzr +# CHECK: add w11, w13, w15 +# CHECK: add w9, w3, wzr, lsl #10 +# CHECK: add w17, w29, w20, lsl #31 +# CHECK: add w21, w22, w23, lsr #0 +# CHECK: add w24, w25, w26, lsr #18 +# CHECK: add w27, w28, w29, lsr #31 +# CHECK: add w2, w3, w4, asr #0 +# CHECK: add w5, w6, w7, asr #21 +# CHECK: add w8, w9, w10, asr #31 +0xa3 0x0 0x7 0xb +0x7f 0x0 0x5 0xb +0xf4 0x3 0x4 0xb +0xc4 0x0 0x1f 0xb +0xab 0x1 0xf 0xb +0x69 0x28 0x1f 0xb +0xb1 0x7f 0x14 0xb +0xd5 0x2 0x57 0xb +0x38 0x4b 0x5a 0xb +0x9b 0x7f 0x5d 0xb +0x62 0x0 0x84 0xb +0xc5 0x54 0x87 0xb +0x28 0x7d 0x8a 0xb + +# CHECK: add x3, x5, x7 +# CHECK: add xzr, x3, x5 +# CHECK: add x20, xzr, x4 +# CHECK: add x4, x6, xzr +# CHECK: add x11, x13, x15 +# CHECK: add x9, x3, xzr, lsl #10 +# CHECK: add x17, x29, x20, lsl #63 +# CHECK: add x21, x22, x23, lsr #0 +# CHECK: add x24, x25, x26, lsr #18 +# CHECK: add x27, x28, x29, lsr #63 +# CHECK: add x2, x3, x4, asr #0 +# CHECK: add x5, x6, x7, asr #21 +# CHECK: add x8, x9, x10, asr #63 +0xa3 0x0 0x7 0x8b +0x7f 0x0 0x5 0x8b +0xf4 0x3 0x4 0x8b +0xc4 0x0 0x1f 0x8b +0xab 0x1 0xf 0x8b +0x69 0x28 0x1f 0x8b +0xb1 0xff 0x14 0x8b +0xd5 0x2 0x57 0x8b +0x38 0x4b 0x5a 0x8b +0x9b 0xff 0x5d 0x8b +0x62 0x0 0x84 0x8b +0xc5 0x54 0x87 0x8b +0x28 0xfd 0x8a 0x8b + +# CHECK: adds w3, w5, w7 +# CHECK: cmn w3, w5 +# CHECK: adds w20, wzr, w4 +# CHECK: adds w4, w6, wzr +# CHECK: adds w11, w13, w15 +# CHECK: adds w9, w3, wzr, lsl #10 +# CHECK: adds w17, w29, w20, lsl #31 +# CHECK: adds w21, w22, w23, lsr #0 +# CHECK: adds w24, w25, w26, lsr #18 +# CHECK: adds w27, w28, w29, lsr #31 +# CHECK: adds w2, w3, w4, asr #0 +# CHECK: adds w5, w6, w7, asr #21 +# CHECK: adds w8, w9, w10, asr #31 +0xa3 0x0 0x7 0x2b +0x7f 0x0 0x5 0x2b +0xf4 0x3 0x4 0x2b +0xc4 0x0 0x1f 0x2b +0xab 0x1 0xf 0x2b +0x69 0x28 0x1f 0x2b +0xb1 0x7f 0x14 0x2b +0xd5 0x2 0x57 0x2b +0x38 0x4b 0x5a 0x2b +0x9b 0x7f 0x5d 0x2b +0x62 0x0 0x84 0x2b +0xc5 0x54 0x87 0x2b +0x28 0x7d 0x8a 0x2b + +# CHECK: adds x3, x5, x7 +# CHECK: cmn x3, x5 +# CHECK: adds x20, xzr, x4 +# CHECK: adds x4, x6, xzr +# CHECK: adds x11, x13, x15 +# CHECK: adds x9, x3, xzr, lsl #10 +# CHECK: adds x17, x29, x20, lsl #63 +# CHECK: adds x21, x22, x23, lsr #0 +# CHECK: adds x24, x25, x26, lsr #18 +# CHECK: adds x27, x28, x29, lsr #63 +# CHECK: adds x2, x3, x4, asr #0 +# CHECK: adds x5, x6, x7, asr #21 +# CHECK: adds x8, x9, x10, asr #63 +0xa3 0x0 0x7 0xab +0x7f 0x0 0x5 0xab +0xf4 0x3 0x4 0xab +0xc4 0x0 0x1f 0xab +0xab 0x1 0xf 0xab +0x69 0x28 0x1f 0xab +0xb1 0xff 0x14 0xab +0xd5 0x2 0x57 0xab +0x38 0x4b 0x5a 0xab +0x9b 0xff 0x5d 0xab +0x62 0x0 0x84 0xab +0xc5 0x54 0x87 0xab +0x28 0xfd 0x8a 0xab + +# CHECK: sub w3, w5, w7 +# CHECK: sub wzr, w3, w5 +# CHECK: sub w20, wzr, w4 +# CHECK: sub w4, w6, wzr +# CHECK: sub w11, w13, w15 +# CHECK: sub w9, w3, wzr, lsl #10 +# CHECK: sub w17, w29, w20, lsl #31 +# CHECK: sub w21, w22, w23, lsr #0 +# CHECK: sub w24, w25, w26, lsr #18 +# CHECK: sub w27, w28, w29, lsr #31 +# CHECK: sub w2, w3, w4, asr #0 +# CHECK: sub w5, w6, w7, asr #21 +# CHECK: sub w8, w9, w10, asr #31 +0xa3 0x0 0x7 0x4b +0x7f 0x0 0x5 0x4b +0xf4 0x3 0x4 0x4b +0xc4 0x0 0x1f 0x4b +0xab 0x1 0xf 0x4b +0x69 0x28 0x1f 0x4b +0xb1 0x7f 0x14 0x4b +0xd5 0x2 0x57 0x4b +0x38 0x4b 0x5a 0x4b +0x9b 0x7f 0x5d 0x4b +0x62 0x0 0x84 0x4b +0xc5 0x54 0x87 0x4b +0x28 0x7d 0x8a 0x4b + +# CHECK: sub x3, x5, x7 +# CHECK: sub xzr, x3, x5 +# CHECK: sub x20, xzr, x4 +# CHECK: sub x4, x6, xzr +# CHECK: sub x11, x13, x15 +# CHECK: sub x9, x3, xzr, lsl #10 +# CHECK: sub x17, x29, x20, lsl #63 +# CHECK: sub x21, x22, x23, lsr #0 +# CHECK: sub x24, x25, x26, lsr #18 +# CHECK: sub x27, x28, x29, lsr #63 +# CHECK: sub x2, x3, x4, asr #0 +# CHECK: sub x5, x6, x7, asr #21 +# CHECK: sub x8, x9, x10, asr #63 +0xa3 0x0 0x7 0xcb +0x7f 0x0 0x5 0xcb +0xf4 0x3 0x4 0xcb +0xc4 0x0 0x1f 0xcb +0xab 0x1 0xf 0xcb +0x69 0x28 0x1f 0xcb +0xb1 0xff 0x14 0xcb +0xd5 0x2 0x57 0xcb +0x38 0x4b 0x5a 0xcb +0x9b 0xff 0x5d 0xcb +0x62 0x0 0x84 0xcb +0xc5 0x54 0x87 0xcb +0x28 0xfd 0x8a 0xcb + +# CHECK: subs w3, w5, w7 +# CHECK: cmp w3, w5 +# CHECK: subs w20, wzr, w4 +# CHECK: subs w4, w6, wzr +# CHECK: subs w11, w13, w15 +# CHECK: subs w9, w3, wzr, lsl #10 +# CHECK: subs w17, w29, w20, lsl #31 +# CHECK: subs w21, w22, w23, lsr #0 +# CHECK: subs w24, w25, w26, lsr #18 +# CHECK: subs w27, w28, w29, lsr #31 +# CHECK: subs w2, w3, w4, asr #0 +# CHECK: subs w5, w6, w7, asr #21 +# CHECK: subs w8, w9, w10, asr #31 +0xa3 0x0 0x7 0x6b +0x7f 0x0 0x5 0x6b +0xf4 0x3 0x4 0x6b +0xc4 0x0 0x1f 0x6b +0xab 0x1 0xf 0x6b +0x69 0x28 0x1f 0x6b +0xb1 0x7f 0x14 0x6b +0xd5 0x2 0x57 0x6b +0x38 0x4b 0x5a 0x6b +0x9b 0x7f 0x5d 0x6b +0x62 0x0 0x84 0x6b +0xc5 0x54 0x87 0x6b +0x28 0x7d 0x8a 0x6b + +# CHECK: subs x3, x5, x7 +# CHECK: cmp x3, x5 +# CHECK: subs x20, xzr, x4 +# CHECK: subs x4, x6, xzr +# CHECK: subs x11, x13, x15 +# CHECK: subs x9, x3, xzr, lsl #10 +# CHECK: subs x17, x29, x20, lsl #63 +# CHECK: subs x21, x22, x23, lsr #0 +# CHECK: subs x24, x25, x26, lsr #18 +# CHECK: subs x27, x28, x29, lsr #63 +# CHECK: subs x2, x3, x4, asr #0 +# CHECK: subs x5, x6, x7, asr #21 +# CHECK: subs x8, x9, x10, asr #63 +0xa3 0x0 0x7 0xeb +0x7f 0x0 0x5 0xeb +0xf4 0x3 0x4 0xeb +0xc4 0x0 0x1f 0xeb +0xab 0x1 0xf 0xeb +0x69 0x28 0x1f 0xeb +0xb1 0xff 0x14 0xeb +0xd5 0x2 0x57 0xeb +0x38 0x4b 0x5a 0xeb +0x9b 0xff 0x5d 0xeb +0x62 0x0 0x84 0xeb +0xc5 0x54 0x87 0xeb +0x28 0xfd 0x8a 0xeb + +# CHECK: cmn w0, w3 +# CHECK: cmn wzr, w4 +# CHECK: cmn w5, wzr +# CHECK: cmn w6, w7 +# CHECK: cmn w8, w9, lsl #15 +# CHECK: cmn w10, w11, lsl #31 +# CHECK: cmn w12, w13, lsr #0 +# CHECK: cmn w14, w15, lsr #21 +# CHECK: cmn w16, w17, lsr #31 +# CHECK: cmn w18, w19, asr #0 +# CHECK: cmn w20, w21, asr #22 +# CHECK: cmn w22, w23, asr #31 +0x1f 0x0 0x3 0x2b +0xff 0x3 0x4 0x2b +0xbf 0x0 0x1f 0x2b +0xdf 0x0 0x7 0x2b +0x1f 0x3d 0x9 0x2b +0x5f 0x7d 0xb 0x2b +0x9f 0x1 0x4d 0x2b +0xdf 0x55 0x4f 0x2b +0x1f 0x7e 0x51 0x2b +0x5f 0x2 0x93 0x2b +0x9f 0x5a 0x95 0x2b +0xdf 0x7e 0x97 0x2b + +# CHECK: cmn x0, x3 +# CHECK: cmn xzr, x4 +# CHECK: cmn x5, xzr +# CHECK: cmn x6, x7 +# CHECK: cmn x8, x9, lsl #15 +# CHECK: cmn x10, x11, lsl #63 +# CHECK: cmn x12, x13, lsr #0 +# CHECK: cmn x14, x15, lsr #41 +# CHECK: cmn x16, x17, lsr #63 +# CHECK: cmn x18, x19, asr #0 +# CHECK: cmn x20, x21, asr #55 +# CHECK: cmn x22, x23, asr #63 +0x1f 0x0 0x3 0xab +0xff 0x3 0x4 0xab +0xbf 0x0 0x1f 0xab +0xdf 0x0 0x7 0xab +0x1f 0x3d 0x9 0xab +0x5f 0xfd 0xb 0xab +0x9f 0x1 0x4d 0xab +0xdf 0xa5 0x4f 0xab +0x1f 0xfe 0x51 0xab +0x5f 0x2 0x93 0xab +0x9f 0xde 0x95 0xab +0xdf 0xfe 0x97 0xab + +# CHECK: cmp w0, w3 +# CHECK: cmp wzr, w4 +# CHECK: cmp w5, wzr +# CHECK: cmp w6, w7 +# CHECK: cmp w8, w9, lsl #15 +# CHECK: cmp w10, w11, lsl #31 +# CHECK: cmp w12, w13, lsr #0 +# CHECK: cmp w14, w15, lsr #21 +# CHECK: cmp w16, w17, lsr #31 +# CHECK: cmp w18, w19, asr #0 +# CHECK: cmp w20, w21, asr #22 +# CHECK: cmp w22, w23, asr #31 +0x1f 0x0 0x3 0x6b +0xff 0x3 0x4 0x6b +0xbf 0x0 0x1f 0x6b +0xdf 0x0 0x7 0x6b +0x1f 0x3d 0x9 0x6b +0x5f 0x7d 0xb 0x6b +0x9f 0x1 0x4d 0x6b +0xdf 0x55 0x4f 0x6b +0x1f 0x7e 0x51 0x6b +0x5f 0x2 0x93 0x6b +0x9f 0x5a 0x95 0x6b +0xdf 0x7e 0x97 0x6b + +# CHECK: cmp x0, x3 +# CHECK: cmp xzr, x4 +# CHECK: cmp x5, xzr +# CHECK: cmp x6, x7 +# CHECK: cmp x8, x9, lsl #15 +# CHECK: cmp x10, x11, lsl #63 +# CHECK: cmp x12, x13, lsr #0 +# CHECK: cmp x14, x15, lsr #41 +# CHECK: cmp x16, x17, lsr #63 +# CHECK: cmp x18, x19, asr #0 +# CHECK: cmp x20, x21, asr #55 +# CHECK: cmp x22, x23, asr #63 +0x1f 0x0 0x3 0xeb +0xff 0x3 0x4 0xeb +0xbf 0x0 0x1f 0xeb +0xdf 0x0 0x7 0xeb +0x1f 0x3d 0x9 0xeb +0x5f 0xfd 0xb 0xeb +0x9f 0x1 0x4d 0xeb +0xdf 0xa5 0x4f 0xeb +0x1f 0xfe 0x51 0xeb +0x5f 0x2 0x93 0xeb +0x9f 0xde 0x95 0xeb +0xdf 0xfe 0x97 0xeb + +# CHECK: sub w29, wzr, w30 +# CHECK: sub w30, wzr, wzr +# CHECK: sub wzr, wzr, w0 +# CHECK: sub w28, wzr, w27 +# CHECK: sub w26, wzr, w25, lsl #29 +# CHECK: sub w24, wzr, w23, lsl #31 +# CHECK: sub w22, wzr, w21, lsr #0 +# CHECK: sub w20, wzr, w19, lsr #1 +# CHECK: sub w18, wzr, w17, lsr #31 +# CHECK: sub w16, wzr, w15, asr #0 +# CHECK: sub w14, wzr, w13, asr #12 +# CHECK: sub w12, wzr, w11, asr #31 +0xfd 0x3 0x1e 0x4b +0xfe 0x3 0x1f 0x4b +0xff 0x3 0x0 0x4b +0xfc 0x3 0x1b 0x4b +0xfa 0x77 0x19 0x4b +0xf8 0x7f 0x17 0x4b +0xf6 0x3 0x55 0x4b +0xf4 0x7 0x53 0x4b +0xf2 0x7f 0x51 0x4b +0xf0 0x3 0x8f 0x4b +0xee 0x33 0x8d 0x4b +0xec 0x7f 0x8b 0x4b + +# CHECK: sub x29, xzr, x30 +# CHECK: sub x30, xzr, xzr +# CHECK: sub xzr, xzr, x0 +# CHECK: sub x28, xzr, x27 +# CHECK: sub x26, xzr, x25, lsl #29 +# CHECK: sub x24, xzr, x23, lsl #31 +# CHECK: sub x22, xzr, x21, lsr #0 +# CHECK: sub x20, xzr, x19, lsr #1 +# CHECK: sub x18, xzr, x17, lsr #31 +# CHECK: sub x16, xzr, x15, asr #0 +# CHECK: sub x14, xzr, x13, asr #12 +# CHECK: sub x12, xzr, x11, asr #31 +0xfd 0x3 0x1e 0xcb +0xfe 0x3 0x1f 0xcb +0xff 0x3 0x0 0xcb +0xfc 0x3 0x1b 0xcb +0xfa 0x77 0x19 0xcb +0xf8 0x7f 0x17 0xcb +0xf6 0x3 0x55 0xcb +0xf4 0x7 0x53 0xcb +0xf2 0x7f 0x51 0xcb +0xf0 0x3 0x8f 0xcb +0xee 0x33 0x8d 0xcb +0xec 0x7f 0x8b 0xcb + +# CHECK: subs w29, wzr, w30 +# CHECK: subs w30, wzr, wzr +# CHECK: cmp wzr, w0 +# CHECK: subs w28, wzr, w27 +# CHECK: subs w26, wzr, w25, lsl #29 +# CHECK: subs w24, wzr, w23, lsl #31 +# CHECK: subs w22, wzr, w21, lsr #0 +# CHECK: subs w20, wzr, w19, lsr #1 +# CHECK: subs w18, wzr, w17, lsr #31 +# CHECK: subs w16, wzr, w15, asr #0 +# CHECK: subs w14, wzr, w13, asr #12 +# CHECK: subs w12, wzr, w11, asr #31 +0xfd 0x3 0x1e 0x6b +0xfe 0x3 0x1f 0x6b +0xff 0x3 0x0 0x6b +0xfc 0x3 0x1b 0x6b +0xfa 0x77 0x19 0x6b +0xf8 0x7f 0x17 0x6b +0xf6 0x3 0x55 0x6b +0xf4 0x7 0x53 0x6b +0xf2 0x7f 0x51 0x6b +0xf0 0x3 0x8f 0x6b +0xee 0x33 0x8d 0x6b +0xec 0x7f 0x8b 0x6b + +# CHECK: subs x29, xzr, x30 +# CHECK: subs x30, xzr, xzr +# CHECK: cmp xzr, x0 +# CHECK: subs x28, xzr, x27 +# CHECK: subs x26, xzr, x25, lsl #29 +# CHECK: subs x24, xzr, x23, lsl #31 +# CHECK: subs x22, xzr, x21, lsr #0 +# CHECK: subs x20, xzr, x19, lsr #1 +# CHECK: subs x18, xzr, x17, lsr #31 +# CHECK: subs x16, xzr, x15, asr #0 +# CHECK: subs x14, xzr, x13, asr #12 +# CHECK: subs x12, xzr, x11, asr #31 +0xfd 0x3 0x1e 0xeb +0xfe 0x3 0x1f 0xeb +0xff 0x3 0x0 0xeb +0xfc 0x3 0x1b 0xeb +0xfa 0x77 0x19 0xeb +0xf8 0x7f 0x17 0xeb +0xf6 0x3 0x55 0xeb +0xf4 0x7 0x53 0xeb +0xf2 0x7f 0x51 0xeb +0xf0 0x3 0x8f 0xeb +0xee 0x33 0x8d 0xeb +0xec 0x7f 0x8b 0xeb + +#------------------------------------------------------------------------------ +# Add-subtract (shifted register) +#------------------------------------------------------------------------------ + +# CHECK: adc w29, w27, w25 +# CHECK: adc wzr, w3, w4 +# CHECK: adc w9, wzr, w10 +# CHECK: adc w20, w0, wzr +0x7d 0x3 0x19 0x1a +0x7f 0x0 0x4 0x1a +0xe9 0x3 0xa 0x1a +0x14 0x0 0x1f 0x1a + +# CHECK: adc x29, x27, x25 +# CHECK: adc xzr, x3, x4 +# CHECK: adc x9, xzr, x10 +# CHECK: adc x20, x0, xzr +0x7d 0x3 0x19 0x9a +0x7f 0x0 0x4 0x9a +0xe9 0x3 0xa 0x9a +0x14 0x0 0x1f 0x9a + +# CHECK: adcs w29, w27, w25 +# CHECK: adcs wzr, w3, w4 +# CHECK: adcs w9, wzr, w10 +# CHECK: adcs w20, w0, wzr +0x7d 0x3 0x19 0x3a +0x7f 0x0 0x4 0x3a +0xe9 0x3 0xa 0x3a +0x14 0x0 0x1f 0x3a + +# CHECK: adcs x29, x27, x25 +# CHECK: adcs xzr, x3, x4 +# CHECK: adcs x9, xzr, x10 +# CHECK: adcs x20, x0, xzr +0x7d 0x3 0x19 0xba +0x7f 0x0 0x4 0xba +0xe9 0x3 0xa 0xba +0x14 0x0 0x1f 0xba + +# CHECK: sbc w29, w27, w25 +# CHECK: sbc wzr, w3, w4 +# CHECK: ngc w9, w10 +# CHECK: sbc w20, w0, wzr +0x7d 0x3 0x19 0x5a +0x7f 0x0 0x4 0x5a +0xe9 0x3 0xa 0x5a +0x14 0x0 0x1f 0x5a + +# CHECK: sbc x29, x27, x25 +# CHECK: sbc xzr, x3, x4 +# CHECK: ngc x9, x10 +# CHECK: sbc x20, x0, xzr +0x7d 0x3 0x19 0xda +0x7f 0x0 0x4 0xda +0xe9 0x3 0xa 0xda +0x14 0x0 0x1f 0xda + +# CHECK: sbcs w29, w27, w25 +# CHECK: sbcs wzr, w3, w4 +# CHECK: ngcs w9, w10 +# CHECK: sbcs w20, w0, wzr +0x7d 0x3 0x19 0x7a +0x7f 0x0 0x4 0x7a +0xe9 0x3 0xa 0x7a +0x14 0x0 0x1f 0x7a + +# CHECK: sbcs x29, x27, x25 +# CHECK: sbcs xzr, x3, x4 +# CHECK: ngcs x9, x10 +# CHECK: sbcs x20, x0, xzr +0x7d 0x3 0x19 0xfa +0x7f 0x0 0x4 0xfa +0xe9 0x3 0xa 0xfa +0x14 0x0 0x1f 0xfa + +# CHECK: ngc w3, w12 +# CHECK: ngc wzr, w9 +# CHECK: ngc w23, wzr +0xe3 0x3 0xc 0x5a +0xff 0x3 0x9 0x5a +0xf7 0x3 0x1f 0x5a + +# CHECK: ngc x29, x30 +# CHECK: ngc xzr, x0 +# CHECK: ngc x0, xzr +0xfd 0x3 0x1e 0xda +0xff 0x3 0x0 0xda +0xe0 0x3 0x1f 0xda + +# CHECK: ngcs w3, w12 +# CHECK: ngcs wzr, w9 +# CHECK: ngcs w23, wzr +0xe3 0x3 0xc 0x7a +0xff 0x3 0x9 0x7a +0xf7 0x3 0x1f 0x7a + +# CHECK: ngcs x29, x30 +# CHECK: ngcs xzr, x0 +# CHECK: ngcs x0, xzr +0xfd 0x3 0x1e 0xfa +0xff 0x3 0x0 0xfa +0xe0 0x3 0x1f 0xfa + +#------------------------------------------------------------------------------ +# Compare and branch (immediate) +#------------------------------------------------------------------------------ + +# CHECK: sbfx x1, x2, #3, #2 +# CHECK: asr x3, x4, #63 +# CHECK: asr wzr, wzr, #31 +# CHECK: sbfx w12, w9, #0, #1 +0x41 0x10 0x43 0x93 +0x83 0xfc 0x7f 0x93 +0xff 0x7f 0x1f 0x13 +0x2c 0x1 0x0 0x13 + +# CHECK: ubfiz x4, x5, #52, #11 +# CHECK: ubfx xzr, x4, #0, #1 +# CHECK: ubfiz x4, xzr, #1, #6 +# CHECK: lsr x5, x6, #12 +0xa4 0x28 0x4c 0xd3 +0x9f 0x0 0x40 0xd3 +0xe4 0x17 0x7f 0xd3 +0xc5 0xfc 0x4c 0xd3 + +# CHECK: bfi x4, x5, #52, #11 +# CHECK: bfxil xzr, x4, #0, #1 +# CHECK: bfi x4, xzr, #1, #6 +# CHECK: bfxil x5, x6, #12, #52 +0xa4 0x28 0x4c 0xb3 +0x9f 0x0 0x40 0xb3 +0xe4 0x17 0x7f 0xb3 +0xc5 0xfc 0x4c 0xb3 + +# CHECK: sxtb w1, w2 +# CHECK: sxtb xzr, w3 +# CHECK: sxth w9, w10 +# CHECK: sxth x0, w1 +# CHECK: sxtw x3, w30 +0x41 0x1c 0x0 0x13 +0x7f 0x1c 0x40 0x93 +0x49 0x3d 0x0 0x13 +0x20 0x3c 0x40 0x93 +0xc3 0x7f 0x40 0x93 + +# CHECK: uxtb w1, w2 +# CHECK: uxth w9, w10 +# CHECK: ubfx x3, x30, #0, #32 +0x41 0x1c 0x0 0x53 +0x49 0x3d 0x0 0x53 +0xc3 0x7f 0x40 0xd3 + +# CHECK: asr w3, w2, #0 +# CHECK: asr w9, w10, #31 +# CHECK: asr x20, x21, #63 +# CHECK: asr w1, wzr, #3 +0x43 0x7c 0x0 0x13 +0x49 0x7d 0x1f 0x13 +0xb4 0xfe 0x7f 0x93 +0xe1 0x7f 0x3 0x13 + +# CHECK: lsr w3, w2, #0 +# CHECK: lsr w9, w10, #31 +# CHECK: lsr x20, x21, #63 +# CHECK: lsr wzr, wzr, #3 +0x43 0x7c 0x0 0x53 +0x49 0x7d 0x1f 0x53 +0xb4 0xfe 0x7f 0xd3 +0xff 0x7f 0x3 0x53 + +# CHECK: lsr w3, w2, #0 +# CHECK: lsl w9, w10, #31 +# CHECK: lsl x20, x21, #63 +# CHECK: lsl w1, wzr, #3 +0x43 0x7c 0x0 0x53 +0x49 0x1 0x1 0x53 +0xb4 0x2 0x41 0xd3 +0xe1 0x73 0x1d 0x53 + +# CHECK: sbfx w9, w10, #0, #1 +# CHECK: sbfiz x2, x3, #63, #1 +# CHECK: asr x19, x20, #0 +# CHECK: sbfiz x9, x10, #5, #59 +# CHECK: asr w9, w10, #0 +# CHECK: sbfiz w11, w12, #31, #1 +# CHECK: sbfiz w13, w14, #29, #3 +# CHECK: sbfiz xzr, xzr, #10, #11 +0x49 0x1 0x0 0x13 +0x62 0x0 0x41 0x93 +0x93 0xfe 0x40 0x93 +0x49 0xe9 0x7b 0x93 +0x49 0x7d 0x0 0x13 +0x8b 0x1 0x1 0x13 +0xcd 0x9 0x3 0x13 +0xff 0x2b 0x76 0x93 + +# CHECK: sbfx w9, w10, #0, #1 +# CHECK: asr x2, x3, #63 +# CHECK: asr x19, x20, #0 +# CHECK: asr x9, x10, #5 +# CHECK: asr w9, w10, #0 +# CHECK: asr w11, w12, #31 +# CHECK: asr w13, w14, #29 +# CHECK: sbfx xzr, xzr, #10, #11 +0x49 0x1 0x0 0x13 +0x62 0xfc 0x7f 0x93 +0x93 0xfe 0x40 0x93 +0x49 0xfd 0x45 0x93 +0x49 0x7d 0x0 0x13 +0x8b 0x7d 0x1f 0x13 +0xcd 0x7d 0x1d 0x13 +0xff 0x53 0x4a 0x93 + +# CHECK: bfxil w9, w10, #0, #1 +# CHECK: bfi x2, x3, #63, #1 +# CHECK: bfxil x19, x20, #0, #64 +# CHECK: bfi x9, x10, #5, #59 +# CHECK: bfxil w9, w10, #0, #32 +# CHECK: bfi w11, w12, #31, #1 +# CHECK: bfi w13, w14, #29, #3 +# CHECK: bfi xzr, xzr, #10, #11 +0x49 0x1 0x0 0x33 +0x62 0x0 0x41 0xb3 +0x93 0xfe 0x40 0xb3 +0x49 0xe9 0x7b 0xb3 +0x49 0x7d 0x0 0x33 +0x8b 0x1 0x1 0x33 +0xcd 0x9 0x3 0x33 +0xff 0x2b 0x76 0xb3 + +# CHECK: bfxil w9, w10, #0, #1 +# CHECK: bfxil x2, x3, #63, #1 +# CHECK: bfxil x19, x20, #0, #64 +# CHECK: bfxil x9, x10, #5, #59 +# CHECK: bfxil w9, w10, #0, #32 +# CHECK: bfxil w11, w12, #31, #1 +# CHECK: bfxil w13, w14, #29, #3 +# CHECK: bfxil xzr, xzr, #10, #11 +0x49 0x1 0x0 0x33 +0x62 0xfc 0x7f 0xb3 +0x93 0xfe 0x40 0xb3 +0x49 0xfd 0x45 0xb3 +0x49 0x7d 0x0 0x33 +0x8b 0x7d 0x1f 0x33 +0xcd 0x7d 0x1d 0x33 +0xff 0x53 0x4a 0xb3 + +# CHECK: ubfx w9, w10, #0, #1 +# CHECK: lsl x2, x3, #63 +# CHECK: lsr x19, x20, #0 +# CHECK: lsl x9, x10, #5 +# CHECK: lsr w9, w10, #0 +# CHECK: lsl w11, w12, #31 +# CHECK: lsl w13, w14, #29 +# CHECK: ubfiz xzr, xzr, #10, #11 +0x49 0x1 0x0 0x53 +0x62 0x0 0x41 0xd3 +0x93 0xfe 0x40 0xd3 +0x49 0xe9 0x7b 0xd3 +0x49 0x7d 0x0 0x53 +0x8b 0x1 0x1 0x53 +0xcd 0x9 0x3 0x53 +0xff 0x2b 0x76 0xd3 + +# CHECK: ubfx w9, w10, #0, #1 +# CHECK: lsr x2, x3, #63 +# CHECK: lsr x19, x20, #0 +# CHECK: lsr x9, x10, #5 +# CHECK: lsr w9, w10, #0 +# CHECK: lsr w11, w12, #31 +# CHECK: lsr w13, w14, #29 +# CHECK: ubfx xzr, xzr, #10, #11 +0x49 0x1 0x0 0x53 +0x62 0xfc 0x7f 0xd3 +0x93 0xfe 0x40 0xd3 +0x49 0xfd 0x45 0xd3 +0x49 0x7d 0x0 0x53 +0x8b 0x7d 0x1f 0x53 +0xcd 0x7d 0x1d 0x53 +0xff 0x53 0x4a 0xd3 + + +#------------------------------------------------------------------------------ +# Compare and branch (immediate) +#------------------------------------------------------------------------------ + +# CHECK: cbz w5, #4 +# CHECK: cbz x5, #0 +# CHECK: cbnz x2, #-4 +# CHECK: cbnz x26, #1048572 +0x25 0x0 0x0 0x34 +0x05 0x0 0x0 0xb4 +0xe2 0xff 0xff 0xb5 +0xfa 0xff 0x7f 0xb5 + +# CHECK: cbz wzr, #0 +# CHECK: cbnz xzr, #0 +0x1f 0x0 0x0 0x34 +0x1f 0x0 0x0 0xb5 + +#------------------------------------------------------------------------------ +# Conditional branch (immediate) +#------------------------------------------------------------------------------ + +# CHECK: b.ne #4 +# CHECK: b.ge #1048572 +# CHECK: b.ge #-4 +0x21 0x00 0x00 0x54 +0xea 0xff 0x7f 0x54 +0xea 0xff 0xff 0x54 + +#------------------------------------------------------------------------------ +# Conditional compare (immediate) +#------------------------------------------------------------------------------ + +# CHECK: ccmp w1, #31, #0, eq +# CHECK: ccmp w3, #0, #15, hs +# CHECK: ccmp wzr, #15, #13, hs +0x20 0x08 0x5f 0x7a +0x6f 0x28 0x40 0x7a +0xed 0x2b 0x4f 0x7a + +# CHECK: ccmp x9, #31, #0, le +# CHECK: ccmp x3, #0, #15, gt +# CHECK: ccmp xzr, #5, #7, ne +0x20 0xd9 0x5f 0xfa +0x6f 0xc8 0x40 0xfa +0xe7 0x1b 0x45 0xfa + +# CHECK: ccmn w1, #31, #0, eq +# CHECK: ccmn w3, #0, #15, hs +# CHECK: ccmn wzr, #15, #13, hs +0x20 0x08 0x5f 0x3a +0x6f 0x28 0x40 0x3a +0xed 0x2b 0x4f 0x3a + +# CHECK: ccmn x9, #31, #0, le +# CHECK: ccmn x3, #0, #15, gt +# CHECK: ccmn xzr, #5, #7, ne +0x20 0xd9 0x5f 0xba +0x6f 0xc8 0x40 0xba +0xe7 0x1b 0x45 0xba + +#------------------------------------------------------------------------------ +# Conditional compare (register) +#------------------------------------------------------------------------------ + +# CHECK: ccmp w1, wzr, #0, eq +# CHECK: ccmp w3, w0, #15, hs +# CHECK: ccmp wzr, w15, #13, hs +0x20 0x00 0x5f 0x7a +0x6f 0x20 0x40 0x7a +0xed 0x23 0x4f 0x7a + +# CHECK: ccmp x9, xzr, #0, le +# CHECK: ccmp x3, x0, #15, gt +# CHECK: ccmp xzr, x5, #7, ne +0x20 0xd1 0x5f 0xfa +0x6f 0xc0 0x40 0xfa +0xe7 0x13 0x45 0xfa + +# CHECK: ccmn w1, wzr, #0, eq +# CHECK: ccmn w3, w0, #15, hs +# CHECK: ccmn wzr, w15, #13, hs +0x20 0x00 0x5f 0x3a +0x6f 0x20 0x40 0x3a +0xed 0x23 0x4f 0x3a + +# CHECK: ccmn x9, xzr, #0, le +# CHECK: ccmn x3, x0, #15, gt +# CHECK: ccmn xzr, x5, #7, ne +0x20 0xd1 0x5f 0xba +0x6f 0xc0 0x40 0xba +0xe7 0x13 0x45 0xba + +#------------------------------------------------------------------------------ +# Conditional branch (immediate) +#------------------------------------------------------------------------------ +# CHECK: csel w1, w0, w19, ne +# CHECK: csel wzr, w5, w9, eq +# CHECK: csel w9, wzr, w30, gt +# CHECK: csel w1, w28, wzr, mi +# CHECK: csel x19, x23, x29, lt +# CHECK: csel xzr, x3, x4, ge +# CHECK: csel x5, xzr, x6, hs +# CHECK: csel x7, x8, xzr, lo +0x1 0x10 0x93 0x1a +0xbf 0x0 0x89 0x1a +0xe9 0xc3 0x9e 0x1a +0x81 0x43 0x9f 0x1a +0xf3 0xb2 0x9d 0x9a +0x7f 0xa0 0x84 0x9a +0xe5 0x23 0x86 0x9a +0x7 0x31 0x9f 0x9a + +# CHECK: csinc w1, w0, w19, ne +# CHECK: csinc wzr, w5, w9, eq +# CHECK: csinc w9, wzr, w30, gt +# CHECK: csinc w1, w28, wzr, mi +# CHECK: csinc x19, x23, x29, lt +# CHECK: csinc xzr, x3, x4, ge +# CHECK: csinc x5, xzr, x6, hs +# CHECK: csinc x7, x8, xzr, lo +0x1 0x14 0x93 0x1a +0xbf 0x4 0x89 0x1a +0xe9 0xc7 0x9e 0x1a +0x81 0x47 0x9f 0x1a +0xf3 0xb6 0x9d 0x9a +0x7f 0xa4 0x84 0x9a +0xe5 0x27 0x86 0x9a +0x7 0x35 0x9f 0x9a + +# CHECK: csinv w1, w0, w19, ne +# CHECK: csinv wzr, w5, w9, eq +# CHECK: csinv w9, wzr, w30, gt +# CHECK: csinv w1, w28, wzr, mi +# CHECK: csinv x19, x23, x29, lt +# CHECK: csinv xzr, x3, x4, ge +# CHECK: csinv x5, xzr, x6, hs +# CHECK: csinv x7, x8, xzr, lo +0x1 0x10 0x93 0x5a +0xbf 0x0 0x89 0x5a +0xe9 0xc3 0x9e 0x5a +0x81 0x43 0x9f 0x5a +0xf3 0xb2 0x9d 0xda +0x7f 0xa0 0x84 0xda +0xe5 0x23 0x86 0xda +0x7 0x31 0x9f 0xda + +# CHECK: csneg w1, w0, w19, ne +# CHECK: csneg wzr, w5, w9, eq +# CHECK: csneg w9, wzr, w30, gt +# CHECK: csneg w1, w28, wzr, mi +# CHECK: csneg x19, x23, x29, lt +# CHECK: csneg xzr, x3, x4, ge +# CHECK: csneg x5, xzr, x6, hs +# CHECK: csneg x7, x8, xzr, lo +0x1 0x14 0x93 0x5a +0xbf 0x4 0x89 0x5a +0xe9 0xc7 0x9e 0x5a +0x81 0x47 0x9f 0x5a +0xf3 0xb6 0x9d 0xda +0x7f 0xa4 0x84 0xda +0xe5 0x27 0x86 0xda +0x7 0x35 0x9f 0xda + +# CHECK: csinc w3, wzr, wzr, ne +# CHECK: csinc x9, xzr, xzr, mi +# CHECK: csinv w20, wzr, wzr, eq +# CHECK: csinv x30, xzr, xzr, lt +0xe3 0x17 0x9f 0x1a +0xe9 0x47 0x9f 0x9a +0xf4 0x3 0x9f 0x5a +0xfe 0xb3 0x9f 0xda + +# CHECK: csinc w3, w5, w5, le +# CHECK: csinc wzr, w4, w4, gt +# CHECK: csinc w9, wzr, wzr, ge +# CHECK: csinc x3, x5, x5, le +# CHECK: csinc xzr, x4, x4, gt +# CHECK: csinc x9, xzr, xzr, ge +0xa3 0xd4 0x85 0x1a +0x9f 0xc4 0x84 0x1a +0xe9 0xa7 0x9f 0x1a +0xa3 0xd4 0x85 0x9a +0x9f 0xc4 0x84 0x9a +0xe9 0xa7 0x9f 0x9a + +# CHECK: csinv w3, w5, w5, le +# CHECK: csinv wzr, w4, w4, gt +# CHECK: csinv w9, wzr, wzr, ge +# CHECK: csinv x3, x5, x5, le +# CHECK: csinv xzr, x4, x4, gt +# CHECK: csinv x9, xzr, xzr, ge +0xa3 0xd0 0x85 0x5a +0x9f 0xc0 0x84 0x5a +0xe9 0xa3 0x9f 0x5a +0xa3 0xd0 0x85 0xda +0x9f 0xc0 0x84 0xda +0xe9 0xa3 0x9f 0xda + +# CHECK: csneg w3, w5, w5, le +# CHECK: csneg wzr, w4, w4, gt +# CHECK: csneg w9, wzr, wzr, ge +# CHECK: csneg x3, x5, x5, le +# CHECK: csneg xzr, x4, x4, gt +# CHECK: csneg x9, xzr, xzr, ge +0xa3 0xd4 0x85 0x5a +0x9f 0xc4 0x84 0x5a +0xe9 0xa7 0x9f 0x5a +0xa3 0xd4 0x85 0xda +0x9f 0xc4 0x84 0xda +0xe9 0xa7 0x9f 0xda + +#------------------------------------------------------------------------------ +# Data-processing (1 source) +#------------------------------------------------------------------------------ + +# CHECK: rbit w0, w7 +# CHECK: rbit x18, x3 +# CHECK: rev16 w17, w1 +# CHECK: rev16 x5, x2 +# CHECK: rev w18, w0 +# CHECK: rev32 x20, x1 +0xe0 0x00 0xc0 0x5a +0x72 0x00 0xc0 0xda +0x31 0x04 0xc0 0x5a +0x45 0x04 0xc0 0xda +0x12 0x08 0xc0 0x5a +0x34 0x08 0xc0 0xda + +# CHECK: rev x22, x2 +# CHECK: clz w24, w3 +# CHECK: clz x26, x4 +# CHECK: cls w3, w5 +# CHECK: cls x20, x5 +0x56 0x0c 0xc0 0xda +0x78 0x10 0xc0 0x5a +0x9a 0x10 0xc0 0xda +0xa3 0x14 0xc0 0x5a +0xb4 0x14 0xc0 0xda + +#------------------------------------------------------------------------------ +# Data-processing (2 source) +#------------------------------------------------------------------------------ + +# CHECK: crc32b w5, w7, w20 +# CHECK: crc32h w28, wzr, w30 +# CHECK: crc32w w0, w1, w2 +# CHECK: crc32x w7, w9, x20 +# CHECK: crc32cb w9, w5, w4 +# CHECK: crc32ch w13, w17, w25 +# CHECK: crc32cw wzr, w3, w5 +# CHECK: crc32cx w18, w16, xzr +0xe5 0x40 0xd4 0x1a +0xfc 0x47 0xde 0x1a +0x20 0x48 0xc2 0x1a +0x27 0x4d 0xd4 0x9a +0xa9 0x50 0xc4 0x1a +0x2d 0x56 0xd9 0x1a +0x7f 0x58 0xc5 0x1a +0x12 0x5e 0xdf 0x9a + +# CHECK: udiv w0, w7, w10 +# CHECK: udiv x9, x22, x4 +# CHECK: sdiv w12, w21, w0 +# CHECK: sdiv x13, x2, x1 +# CHECK: lsl w11, w12, w13 +# CHECK: lsl x14, x15, x16 +# CHECK: lsr w17, w18, w19 +# CHECK: lsr x20, x21, x22 +# CHECK: asr w23, w24, w25 +# CHECK: asr x26, x27, x28 +# CHECK: ror w0, w1, w2 +# CHECK: ror x3, x4, x5 +0xe0 0x08 0xca 0x1a +0xc9 0x0a 0xc4 0x9a +0xac 0x0e 0xc0 0x1a +0x4d 0x0c 0xc1 0x9a +0x8b 0x21 0xcd 0x1a +0xee 0x21 0xd0 0x9a +0x51 0x26 0xd3 0x1a +0xb4 0x26 0xd6 0x9a +0x17 0x2b 0xd9 0x1a +0x7a 0x2b 0xdc 0x9a +0x20 0x2c 0xc2 0x1a +0x83 0x2c 0xc5 0x9a + +# CHECK: lsl w6, w7, w8 +# CHECK: lsl x9, x10, x11 +# CHECK: lsr w12, w13, w14 +# CHECK: lsr x15, x16, x17 +# CHECK: asr w18, w19, w20 +# CHECK: asr x21, x22, x23 +# CHECK: ror w24, w25, w26 +# CHECK: ror x27, x28, x29 +0xe6 0x20 0xc8 0x1a +0x49 0x21 0xcb 0x9a +0xac 0x25 0xce 0x1a +0x0f 0x26 0xd1 0x9a +0x72 0x2a 0xd4 0x1a +0xd5 0x2a 0xd7 0x9a +0x38 0x2f 0xda 0x1a +0x9b 0x2f 0xdd 0x9a + +#------------------------------------------------------------------------------ +# Data-processing (3 sources) +#------------------------------------------------------------------------------ + +# First check some non-canonical encodings where Ra is not 0b11111 (only umulh +# and smulh have them). + +# CHECK: smulh x30, x29, x28 +# CHECK: smulh xzr, x27, x26 +# CHECK: umulh x30, x29, x28 +# CHECK: umulh x23, x30, xzr +0xbe 0x73 0x5c 0x9b +0x7f 0x2f 0x5a 0x9b +0xbe 0x3f 0xdc 0x9b +0xd7 0x77 0xdf 0x9b + +# Now onto the boilerplate stuff + +# CHECK: madd w1, w3, w7, w4 +# CHECK: madd wzr, w0, w9, w11 +# CHECK: madd w13, wzr, w4, w4 +# CHECK: madd w19, w30, wzr, w29 +# CHECK: mul w4, w5, w6 +0x61 0x10 0x7 0x1b +0x1f 0x2c 0x9 0x1b +0xed 0x13 0x4 0x1b +0xd3 0x77 0x1f 0x1b +0xa4 0x7c 0x6 0x1b + +# CHECK: madd x1, x3, x7, x4 +# CHECK: madd xzr, x0, x9, x11 +# CHECK: madd x13, xzr, x4, x4 +# CHECK: madd x19, x30, xzr, x29 +# CHECK: mul x4, x5, x6 +0x61 0x10 0x7 0x9b +0x1f 0x2c 0x9 0x9b +0xed 0x13 0x4 0x9b +0xd3 0x77 0x1f 0x9b +0xa4 0x7c 0x6 0x9b + +# CHECK: msub w1, w3, w7, w4 +# CHECK: msub wzr, w0, w9, w11 +# CHECK: msub w13, wzr, w4, w4 +# CHECK: msub w19, w30, wzr, w29 +# CHECK: mneg w4, w5, w6 +0x61 0x90 0x7 0x1b +0x1f 0xac 0x9 0x1b +0xed 0x93 0x4 0x1b +0xd3 0xf7 0x1f 0x1b +0xa4 0xfc 0x6 0x1b + +# CHECK: msub x1, x3, x7, x4 +# CHECK: msub xzr, x0, x9, x11 +# CHECK: msub x13, xzr, x4, x4 +# CHECK: msub x19, x30, xzr, x29 +# CHECK: mneg x4, x5, x6 +0x61 0x90 0x7 0x9b +0x1f 0xac 0x9 0x9b +0xed 0x93 0x4 0x9b +0xd3 0xf7 0x1f 0x9b +0xa4 0xfc 0x6 0x9b + +# CHECK: smaddl x3, w5, w2, x9 +# CHECK: smaddl xzr, w10, w11, x12 +# CHECK: smaddl x13, wzr, w14, x15 +# CHECK: smaddl x16, w17, wzr, x18 +# CHECK: smull x19, w20, w21 +0xa3 0x24 0x22 0x9b +0x5f 0x31 0x2b 0x9b +0xed 0x3f 0x2e 0x9b +0x30 0x4a 0x3f 0x9b +0x93 0x7e 0x35 0x9b + +# CHECK: smsubl x3, w5, w2, x9 +# CHECK: smsubl xzr, w10, w11, x12 +# CHECK: smsubl x13, wzr, w14, x15 +# CHECK: smsubl x16, w17, wzr, x18 +# CHECK: smnegl x19, w20, w21 +0xa3 0xa4 0x22 0x9b +0x5f 0xb1 0x2b 0x9b +0xed 0xbf 0x2e 0x9b +0x30 0xca 0x3f 0x9b +0x93 0xfe 0x35 0x9b + +# CHECK: umaddl x3, w5, w2, x9 +# CHECK: umaddl xzr, w10, w11, x12 +# CHECK: umaddl x13, wzr, w14, x15 +# CHECK: umaddl x16, w17, wzr, x18 +# CHECK: umull x19, w20, w21 +0xa3 0x24 0xa2 0x9b +0x5f 0x31 0xab 0x9b +0xed 0x3f 0xae 0x9b +0x30 0x4a 0xbf 0x9b +0x93 0x7e 0xb5 0x9b + +# CHECK: umsubl x3, w5, w2, x9 +# CHECK: umsubl xzr, w10, w11, x12 +# CHECK: umsubl x13, wzr, w14, x15 +# CHECK: umsubl x16, w17, wzr, x18 +# CHECK: umnegl x19, w20, w21 +0xa3 0xa4 0xa2 0x9b +0x5f 0xb1 0xab 0x9b +0xed 0xbf 0xae 0x9b +0x30 0xca 0xbf 0x9b +0x93 0xfe 0xb5 0x9b + +# CHECK: smulh x30, x29, x28 +# CHECK: smulh xzr, x27, x26 +# CHECK: smulh x25, xzr, x24 +# CHECK: smulh x23, x22, xzr +0xbe 0x7f 0x5c 0x9b +0x7f 0x7f 0x5a 0x9b +0xf9 0x7f 0x58 0x9b +0xd7 0x7e 0x5f 0x9b + +# CHECK: umulh x30, x29, x28 +# CHECK: umulh xzr, x27, x26 +# CHECK: umulh x25, xzr, x24 +# CHECK: umulh x23, x22, xzr +0xbe 0x7f 0xdc 0x9b +0x7f 0x7f 0xda 0x9b +0xf9 0x7f 0xd8 0x9b +0xd7 0x7e 0xdf 0x9b + +# CHECK: mul w3, w4, w5 +# CHECK: mul wzr, w6, w7 +# CHECK: mul w8, wzr, w9 +# CHECK: mul w10, w11, wzr +# CHECK: mul x12, x13, x14 +# CHECK: mul xzr, x15, x16 +# CHECK: mul x17, xzr, x18 +# CHECK: mul x19, x20, xzr +0x83 0x7c 0x5 0x1b +0xdf 0x7c 0x7 0x1b +0xe8 0x7f 0x9 0x1b +0x6a 0x7d 0x1f 0x1b +0xac 0x7d 0xe 0x9b +0xff 0x7d 0x10 0x9b +0xf1 0x7f 0x12 0x9b +0x93 0x7e 0x1f 0x9b + +# CHECK: mneg w21, w22, w23 +# CHECK: mneg wzr, w24, w25 +# CHECK: mneg w26, wzr, w27 +# CHECK: mneg w28, w29, wzr +0xd5 0xfe 0x17 0x1b +0x1f 0xff 0x19 0x1b +0xfa 0xff 0x1b 0x1b +0xbc 0xff 0x1f 0x1b + +# CHECK: smull x11, w13, w17 +# CHECK: umull x11, w13, w17 +# CHECK: smnegl x11, w13, w17 +# CHECK: umnegl x11, w13, w17 +0xab 0x7d 0x31 0x9b +0xab 0x7d 0xb1 0x9b +0xab 0xfd 0x31 0x9b +0xab 0xfd 0xb1 0x9b + +#------------------------------------------------------------------------------ +# Exception generation +#------------------------------------------------------------------------------ + +# CHECK: svc #0 +# CHECK: svc #65535 +0x1 0x0 0x0 0xd4 +0xe1 0xff 0x1f 0xd4 + +# CHECK: hvc #1 +# CHECK: smc #12000 +# CHECK: brk #12 +# CHECK: hlt #123 +0x22 0x0 0x0 0xd4 +0x3 0xdc 0x5 0xd4 +0x80 0x1 0x20 0xd4 +0x60 0xf 0x40 0xd4 + +# CHECK: dcps1 #42 +# CHECK: dcps2 #9 +# CHECK: dcps3 #1000 +0x41 0x5 0xa0 0xd4 +0x22 0x1 0xa0 0xd4 +0x3 0x7d 0xa0 0xd4 + +# CHECK: dcps1 +# CHECK: dcps2 +# CHECK: dcps3 +0x1 0x0 0xa0 0xd4 +0x2 0x0 0xa0 0xd4 +0x3 0x0 0xa0 0xd4 + +#------------------------------------------------------------------------------ +# Extract (immediate) +#------------------------------------------------------------------------------ + +# CHECK: extr w3, w5, w7, #0 +# CHECK: extr w11, w13, w17, #31 +0xa3 0x0 0x87 0x13 +0xab 0x7d 0x91 0x13 + +# CHECK: extr x3, x5, x7, #15 +# CHECK: extr x11, x13, x17, #63 +0xa3 0x3c 0xc7 0x93 +0xab 0xfd 0xd1 0x93 + +# CHECK: extr x19, x23, x23, #24 +# CHECK: extr x29, xzr, xzr, #63 +# CHECK: extr w9, w13, w13, #31 +0xf3 0x62 0xd7 0x93 +0xfd 0xff 0xdf 0x93 +0xa9 0x7d 0x8d 0x13 + +#------------------------------------------------------------------------------ +# Floating-point compare +#------------------------------------------------------------------------------ + +# CHECK: fcmp s3, s5 +# CHECK: fcmp s31, #0.0 +# CHECK: fcmp s31, #0.0 +0x60 0x20 0x25 0x1e +0xe8 0x23 0x20 0x1e +0xe8 0x23 0x3f 0x1e + +# CHECK: fcmpe s29, s30 +# CHECK: fcmpe s15, #0.0 +# CHECK: fcmpe s15, #0.0 +0xb0 0x23 0x3e 0x1e +0xf8 0x21 0x20 0x1e +0xf8 0x21 0x2f 0x1e + +# CHECK: fcmp d4, d12 +# CHECK: fcmp d23, #0.0 +# CHECK: fcmp d23, #0.0 +0x80 0x20 0x6c 0x1e +0xe8 0x22 0x60 0x1e +0xe8 0x22 0x77 0x1e + +# CHECK: fcmpe d26, d22 +# CHECK: fcmpe d29, #0.0 +# CHECK: fcmpe d29, #0.0 +0x50 0x23 0x76 0x1e +0xb8 0x23 0x60 0x1e +0xb8 0x23 0x6d 0x1e + +#------------------------------------------------------------------------------ +# Floating-point conditional compare +#------------------------------------------------------------------------------ + +# CHECK: fccmp s1, s31, #0, eq +# CHECK: fccmp s3, s0, #15, hs +# CHECK: fccmp s31, s15, #13, hs +0x20 0x04 0x3f 0x1e +0x6f 0x24 0x20 0x1e +0xed 0x27 0x2f 0x1e + +# CHECK: fccmp d9, d31, #0, le +# CHECK: fccmp d3, d0, #15, gt +# CHECK: fccmp d31, d5, #7, ne +0x20 0xd5 0x7f 0x1e +0x6f 0xc4 0x60 0x1e +0xe7 0x17 0x65 0x1e + +# CHECK: fccmpe s1, s31, #0, eq +# CHECK: fccmpe s3, s0, #15, hs +# CHECK: fccmpe s31, s15, #13, hs +0x30 0x04 0x3f 0x1e +0x7f 0x24 0x20 0x1e +0xfd 0x27 0x2f 0x1e + +# CHECK: fccmpe d9, d31, #0, le +# CHECK: fccmpe d3, d0, #15, gt +# CHECK: fccmpe d31, d5, #7, ne +0x30 0xd5 0x7f 0x1e +0x7f 0xc4 0x60 0x1e +0xf7 0x17 0x65 0x1e + +#------------------------------------------------------------------------------- +# Floating-point conditional compare +#------------------------------------------------------------------------------- + +# CHECK: fcsel s3, s20, s9, pl +# CHECK: fcsel d9, d10, d11, mi +0x83 0x5e 0x29 0x1e +0x49 0x4d 0x6b 0x1e + +#------------------------------------------------------------------------------ +# Floating-point data-processing (1 source) +#------------------------------------------------------------------------------ + +# CHECK: fmov s0, s1 +# CHECK: fabs s2, s3 +# CHECK: fneg s4, s5 +# CHECK: fsqrt s6, s7 +# CHECK: fcvt d8, s9 +# CHECK: fcvt h10, s11 +# CHECK: frintn s12, s13 +# CHECK: frintp s14, s15 +# CHECK: frintm s16, s17 +# CHECK: frintz s18, s19 +# CHECK: frinta s20, s21 +# CHECK: frintx s22, s23 +# CHECK: frinti s24, s25 +0x20 0x40 0x20 0x1e +0x62 0xc0 0x20 0x1e +0xa4 0x40 0x21 0x1e +0xe6 0xc0 0x21 0x1e +0x28 0xc1 0x22 0x1e +0x6a 0xc1 0x23 0x1e +0xac 0x41 0x24 0x1e +0xee 0xc1 0x24 0x1e +0x30 0x42 0x25 0x1e +0x72 0xc2 0x25 0x1e +0xb4 0x42 0x26 0x1e +0xf6 0x42 0x27 0x1e +0x38 0xc3 0x27 0x1e + +# CHECK: fmov d0, d1 +# CHECK: fabs d2, d3 +# CHECK: fneg d4, d5 +# CHECK: fsqrt d6, d7 +# CHECK: fcvt s8, d9 +# CHECK: fcvt h10, d11 +# CHECK: frintn d12, d13 +# CHECK: frintp d14, d15 +# CHECK: frintm d16, d17 +# CHECK: frintz d18, d19 +# CHECK: frinta d20, d21 +# CHECK: frintx d22, d23 +# CHECK: frinti d24, d25 +0x20 0x40 0x60 0x1e +0x62 0xc0 0x60 0x1e +0xa4 0x40 0x61 0x1e +0xe6 0xc0 0x61 0x1e +0x28 0x41 0x62 0x1e +0x6a 0xc1 0x63 0x1e +0xac 0x41 0x64 0x1e +0xee 0xc1 0x64 0x1e +0x30 0x42 0x65 0x1e +0x72 0xc2 0x65 0x1e +0xb4 0x42 0x66 0x1e +0xf6 0x42 0x67 0x1e +0x38 0xc3 0x67 0x1e + +# CHECK: fcvt s26, h27 +# CHECK: fcvt d28, h29 +0x7a 0x43 0xe2 0x1e +0xbc 0xc3 0xe2 0x1e + +#------------------------------------------------------------------------------ +# Floating-point data-processing (2 sources) +#------------------------------------------------------------------------------ + +# CHECK: fmul s20, s19, s17 +# CHECK: fdiv s1, s2, s3 +# CHECK: fadd s4, s5, s6 +# CHECK: fsub s7, s8, s9 +# CHECK: fmax s10, s11, s12 +# CHECK: fmin s13, s14, s15 +# CHECK: fmaxnm s16, s17, s18 +# CHECK: fminnm s19, s20, s21 +# CHECK: fnmul s22, s23, s2 +0x74 0xa 0x31 0x1e +0x41 0x18 0x23 0x1e +0xa4 0x28 0x26 0x1e +0x7 0x39 0x29 0x1e +0x6a 0x49 0x2c 0x1e +0xcd 0x59 0x2f 0x1e +0x30 0x6a 0x32 0x1e +0x93 0x7a 0x35 0x1e +0xf6 0x8a 0x38 0x1e + + +# CHECK: fmul d20, d19, d17 +# CHECK: fdiv d1, d2, d3 +# CHECK: fadd d4, d5, d6 +# CHECK: fsub d7, d8, d9 +# CHECK: fmax d10, d11, d12 +# CHECK: fmin d13, d14, d15 +# CHECK: fmaxnm d16, d17, d18 +# CHECK: fminnm d19, d20, d21 +# CHECK: fnmul d22, d23, d24 +0x74 0xa 0x71 0x1e +0x41 0x18 0x63 0x1e +0xa4 0x28 0x66 0x1e +0x7 0x39 0x69 0x1e +0x6a 0x49 0x6c 0x1e +0xcd 0x59 0x6f 0x1e +0x30 0x6a 0x72 0x1e +0x93 0x7a 0x75 0x1e +0xf6 0x8a 0x78 0x1e + +#------------------------------------------------------------------------------ +# Floating-point data-processing (1 source) +#------------------------------------------------------------------------------ + +# CHECK: fmadd s3, s5, s6, s31 +# CHECK: fmadd d3, d13, d0, d23 +# CHECK: fmsub s3, s5, s6, s31 +# CHECK: fmsub d3, d13, d0, d23 +# CHECK: fnmadd s3, s5, s6, s31 +# CHECK: fnmadd d3, d13, d0, d23 +# CHECK: fnmsub s3, s5, s6, s31 +# CHECK: fnmsub d3, d13, d0, d23 +0xa3 0x7c 0x06 0x1f +0xa3 0x5d 0x40 0x1f +0xa3 0xfc 0x06 0x1f +0xa3 0xdd 0x40 0x1f +0xa3 0x7c 0x26 0x1f +0xa3 0x5d 0x60 0x1f +0xa3 0xfc 0x26 0x1f +0xa3 0xdd 0x60 0x1f + +#------------------------------------------------------------------------------ +# Floating-point <-> fixed-point conversion +#------------------------------------------------------------------------------ + +# CHECK: fcvtzs w3, s5, #1 +# CHECK: fcvtzs wzr, s20, #13 +# CHECK: fcvtzs w19, s0, #32 +0xa3 0xfc 0x18 0x1e +0x9f 0xce 0x18 0x1e +0x13 0x80 0x18 0x1e + +# CHECK: fcvtzs x3, s5, #1 +# CHECK: fcvtzs x12, s30, #45 +# CHECK: fcvtzs x19, s0, #64 +0xa3 0xfc 0x18 0x9e +0xcc 0x4f 0x18 0x9e +0x13 0x00 0x18 0x9e + +# CHECK: fcvtzs w3, d5, #1 +# CHECK: fcvtzs wzr, d20, #13 +# CHECK: fcvtzs w19, d0, #32 +0xa3 0xfc 0x58 0x1e +0x9f 0xce 0x58 0x1e +0x13 0x80 0x58 0x1e + +# CHECK: fcvtzs x3, d5, #1 +# CHECK: fcvtzs x12, d30, #45 +# CHECK: fcvtzs x19, d0, #64 +0xa3 0xfc 0x58 0x9e +0xcc 0x4f 0x58 0x9e +0x13 0x00 0x58 0x9e + +# CHECK: fcvtzu w3, s5, #1 +# CHECK: fcvtzu wzr, s20, #13 +# CHECK: fcvtzu w19, s0, #32 +0xa3 0xfc 0x19 0x1e +0x9f 0xce 0x19 0x1e +0x13 0x80 0x19 0x1e + +# CHECK: fcvtzu x3, s5, #1 +# CHECK: fcvtzu x12, s30, #45 +# CHECK: fcvtzu x19, s0, #64 +0xa3 0xfc 0x19 0x9e +0xcc 0x4f 0x19 0x9e +0x13 0x00 0x19 0x9e + +# CHECK: fcvtzu w3, d5, #1 +# CHECK: fcvtzu wzr, d20, #13 +# CHECK: fcvtzu w19, d0, #32 +0xa3 0xfc 0x59 0x1e +0x9f 0xce 0x59 0x1e +0x13 0x80 0x59 0x1e + +# CHECK: fcvtzu x3, d5, #1 +# CHECK: fcvtzu x12, d30, #45 +# CHECK: fcvtzu x19, d0, #64 +0xa3 0xfc 0x59 0x9e +0xcc 0x4f 0x59 0x9e +0x13 0x00 0x59 0x9e + +# CHECK: scvtf s23, w19, #1 +# CHECK: scvtf s31, wzr, #20 +# CHECK: scvtf s14, w0, #32 +0x77 0xfe 0x02 0x1e +0xff 0xb3 0x02 0x1e +0x0e 0x80 0x02 0x1e + +# CHECK: scvtf s23, x19, #1 +# CHECK: scvtf s31, xzr, #20 +# CHECK: scvtf s14, x0, #64 +0x77 0xfe 0x02 0x9e +0xff 0xb3 0x02 0x9e +0x0e 0x00 0x02 0x9e + +# CHECK: scvtf d23, w19, #1 +# CHECK: scvtf d31, wzr, #20 +# CHECK: scvtf d14, w0, #32 +0x77 0xfe 0x42 0x1e +0xff 0xb3 0x42 0x1e +0x0e 0x80 0x42 0x1e + +# CHECK: scvtf d23, x19, #1 +# CHECK: scvtf d31, xzr, #20 +# CHECK: scvtf d14, x0, #64 +0x77 0xfe 0x42 0x9e +0xff 0xb3 0x42 0x9e +0x0e 0x00 0x42 0x9e + +# CHECK: ucvtf s23, w19, #1 +# CHECK: ucvtf s31, wzr, #20 +# CHECK: ucvtf s14, w0, #32 +0x77 0xfe 0x03 0x1e +0xff 0xb3 0x03 0x1e +0x0e 0x80 0x03 0x1e + +# CHECK: ucvtf s23, x19, #1 +# CHECK: ucvtf s31, xzr, #20 +# CHECK: ucvtf s14, x0, #64 +0x77 0xfe 0x03 0x9e +0xff 0xb3 0x03 0x9e +0x0e 0x00 0x03 0x9e + +# CHECK: ucvtf d23, w19, #1 +# CHECK: ucvtf d31, wzr, #20 +# CHECK: ucvtf d14, w0, #32 +0x77 0xfe 0x43 0x1e +0xff 0xb3 0x43 0x1e +0x0e 0x80 0x43 0x1e + +# CHECK: ucvtf d23, x19, #1 +# CHECK: ucvtf d31, xzr, #20 +# CHECK: ucvtf d14, x0, #64 +0x77 0xfe 0x43 0x9e +0xff 0xb3 0x43 0x9e +0x0e 0x00 0x43 0x9e + +#------------------------------------------------------------------------------ +# Floating-point <-> integer conversion +#------------------------------------------------------------------------------ +# CHECK: fcvtns w3, s31 +# CHECK: fcvtns xzr, s12 +# CHECK: fcvtnu wzr, s12 +# CHECK: fcvtnu x0, s0 +0xe3 0x3 0x20 0x1e +0x9f 0x1 0x20 0x9e +0x9f 0x1 0x21 0x1e +0x0 0x0 0x21 0x9e + +# CHECK: fcvtps wzr, s9 +# CHECK: fcvtps x12, s20 +# CHECK: fcvtpu w30, s23 +# CHECK: fcvtpu x29, s3 +0x3f 0x1 0x28 0x1e +0x8c 0x2 0x28 0x9e +0xfe 0x2 0x29 0x1e +0x7d 0x0 0x29 0x9e + +# CHECK: fcvtms w2, s3 +# CHECK: fcvtms x4, s5 +# CHECK: fcvtmu w6, s7 +# CHECK: fcvtmu x8, s9 +0x62 0x0 0x30 0x1e +0xa4 0x0 0x30 0x9e +0xe6 0x0 0x31 0x1e +0x28 0x1 0x31 0x9e + +# CHECK: fcvtzs w10, s11 +# CHECK: fcvtzs x12, s13 +# CHECK: fcvtzu w14, s15 +# CHECK: fcvtzu x15, s16 +0x6a 0x1 0x38 0x1e +0xac 0x1 0x38 0x9e +0xee 0x1 0x39 0x1e +0xf 0x2 0x39 0x9e + +# CHECK: scvtf s17, w18 +# CHECK: scvtf s19, x20 +# CHECK: ucvtf s21, w22 +# CHECK: scvtf s23, x24 +0x51 0x2 0x22 0x1e +0x93 0x2 0x22 0x9e +0xd5 0x2 0x23 0x1e +0x17 0x3 0x22 0x9e + +# CHECK: fcvtas w25, s26 +# CHECK: fcvtas x27, s28 +# CHECK: fcvtau w29, s30 +# CHECK: fcvtau xzr, s0 +0x59 0x3 0x24 0x1e +0x9b 0x3 0x24 0x9e +0xdd 0x3 0x25 0x1e +0x1f 0x0 0x25 0x9e + +# CHECK: fcvtns w3, d31 +# CHECK: fcvtns xzr, d12 +# CHECK: fcvtnu wzr, d12 +# CHECK: fcvtnu x0, d0 +0xe3 0x3 0x60 0x1e +0x9f 0x1 0x60 0x9e +0x9f 0x1 0x61 0x1e +0x0 0x0 0x61 0x9e + +# CHECK: fcvtps wzr, d9 +# CHECK: fcvtps x12, d20 +# CHECK: fcvtpu w30, d23 +# CHECK: fcvtpu x29, d3 +0x3f 0x1 0x68 0x1e +0x8c 0x2 0x68 0x9e +0xfe 0x2 0x69 0x1e +0x7d 0x0 0x69 0x9e + +# CHECK: fcvtms w2, d3 +# CHECK: fcvtms x4, d5 +# CHECK: fcvtmu w6, d7 +# CHECK: fcvtmu x8, d9 +0x62 0x0 0x70 0x1e +0xa4 0x0 0x70 0x9e +0xe6 0x0 0x71 0x1e +0x28 0x1 0x71 0x9e + +# CHECK: fcvtzs w10, d11 +# CHECK: fcvtzs x12, d13 +# CHECK: fcvtzu w14, d15 +# CHECK: fcvtzu x15, d16 +0x6a 0x1 0x78 0x1e +0xac 0x1 0x78 0x9e +0xee 0x1 0x79 0x1e +0xf 0x2 0x79 0x9e + +# CHECK: scvtf d17, w18 +# CHECK: scvtf d19, x20 +# CHECK: ucvtf d21, w22 +# CHECK: ucvtf d23, x24 +0x51 0x2 0x62 0x1e +0x93 0x2 0x62 0x9e +0xd5 0x2 0x63 0x1e +0x17 0x3 0x63 0x9e + +# CHECK: fcvtas w25, d26 +# CHECK: fcvtas x27, d28 +# CHECK: fcvtau w29, d30 +# CHECK: fcvtau xzr, d0 +0x59 0x3 0x64 0x1e +0x9b 0x3 0x64 0x9e +0xdd 0x3 0x65 0x1e +0x1f 0x0 0x65 0x9e + +# CHECK: fmov w3, s9 +# CHECK: fmov s9, w3 +0x23 0x1 0x26 0x1e +0x69 0x0 0x27 0x1e + +# CHECK: fmov x20, d31 +# CHECK: fmov d1, x15 +0xf4 0x3 0x66 0x9e +0xe1 0x1 0x67 0x9e + +# CHECK: fmov x3, v12.d[1] +# CHECK: fmov v1.d[1], x19 +0x83 0x1 0xae 0x9e +0x61 0x2 0xaf 0x9e + +#------------------------------------------------------------------------------ +# Floating-point immediate +#------------------------------------------------------------------------------ + +# CHECK: fmov s2, #0.12500000 +# CHECK: fmov s3, #1.00000000 +# CHECK: fmov d30, #16.00000000 +0x2 0x10 0x28 0x1e +0x3 0x10 0x2e 0x1e +0x1e 0x10 0x66 0x1e + +# CHECK: fmov s4, #1.06250000 +# CHECK: fmov d10, #1.93750000 +0x4 0x30 0x2e 0x1e +0xa 0xf0 0x6f 0x1e + +# CHECK: fmov s12, #-1.00000000 +0xc 0x10 0x3e 0x1e + +# CHECK: fmov d16, #8.50000000 +0x10 0x30 0x64 0x1e + +#------------------------------------------------------------------------------ +# Load-register (literal) +#------------------------------------------------------------------------------ + +# CHECK: ldr w3, #0 +# CHECK: ldr x29, #4 +# CHECK: ldrsw xzr, #-4 +0x03 0x00 0x00 0x18 +0x3d 0x00 0x00 0x58 +0xff 0xff 0xff 0x98 + +# CHECK: ldr s0, #8 +# CHECK: ldr d0, #1048572 +# CHECK: ldr q0, #-1048576 +0x40 0x00 0x00 0x1c +0xe0 0xff 0x7f 0x5c +0x00 0x00 0x80 0x9c + +# CHECK: prfm pldl1strm, #0 +# CHECK: prfm #22, #0 +0x01 0x00 0x00 0xd8 +0x16 0x00 0x00 0xd8 + +#------------------------------------------------------------------------------ +# Load/store exclusive +#------------------------------------------------------------------------------ + +#CHECK: stxrb w18, w8, [sp] +#CHECK: stxrh w24, w15, [x16] +#CHECK: stxr w5, w6, [x17] +#CHECK: stxr w1, x10, [x21] +#CHECK: stxr w1, x10, [x21] +0xe8 0x7f 0x12 0x08 +0x0f 0x7e 0x18 0x48 +0x26 0x7e 0x05 0x88 +0xaa 0x7e 0x01 0xc8 +0xaa 0x7a 0x01 0xc8 + +#CHECK: ldxrb w30, [x0] +#CHECK: ldxrh w17, [x4] +#CHECK: ldxr w22, [sp] +#CHECK: ldxr x11, [x29] +#CHECK: ldxr x11, [x29] +#CHECK: ldxr x11, [x29] +0x1e 0x7c 0x5f 0x08 +0x91 0x7c 0x5f 0x48 +0xf6 0x7f 0x5f 0x88 +0xab 0x7f 0x5f 0xc8 +0xab 0x6f 0x5f 0xc8 +0xab 0x7f 0x5e 0xc8 + +#CHECK: stxp w12, w11, w10, [sp] +#CHECK: stxp wzr, x27, x9, [x12] +0xeb 0x2b 0x2c 0x88 +0x9b 0x25 0x3f 0xc8 + +#CHECK: ldxp w0, wzr, [sp] +#CHECK: ldxp x17, x0, [x18] +#CHECK: ldxp x17, x0, [x18] +0xe0 0x7f 0x7f 0x88 +0x51 0x02 0x7f 0xc8 +0x51 0x02 0x7e 0xc8 + +#CHECK: stlxrb w12, w22, [x0] +#CHECK: stlxrh w10, w1, [x1] +#CHECK: stlxr w9, w2, [x2] +#CHECK: stlxr w9, x3, [sp] + +0x16 0xfc 0x0c 0x08 +0x21 0xfc 0x0a 0x48 +0x42 0xfc 0x09 0x88 +0xe3 0xff 0x09 0xc8 + +#CHECK: ldaxrb w8, [x4] +#CHECK: ldaxrh w7, [x5] +#CHECK: ldaxr w6, [sp] +#CHECK: ldaxr x5, [x6] +#CHECK: ldaxr x5, [x6] +#CHECK: ldaxr x5, [x6] +0x88 0xfc 0x5f 0x08 +0xa7 0xfc 0x5f 0x48 +0xe6 0xff 0x5f 0x88 +0xc5 0xfc 0x5f 0xc8 +0xc5 0xec 0x5f 0xc8 +0xc5 0xfc 0x5e 0xc8 + +#CHECK: stlxp w4, w5, w6, [sp] +#CHECK: stlxp wzr, x6, x7, [x1] +0xe5 0x9b 0x24 0x88 +0x26 0x9c 0x3f 0xc8 + +#CHECK: ldaxp w5, w18, [sp] +#CHECK: ldaxp x6, x19, [x22] +#CHECK: ldaxp x6, x19, [x22] +0xe5 0xcb 0x7f 0x88 +0xc6 0xce 0x7f 0xc8 +0xc6 0xce 0x7e 0xc8 + +#CHECK: stlrb w24, [sp] +#CHECK: stlrh w25, [x30] +#CHECK: stlr w26, [x29] +#CHECK: stlr x27, [x28] +#CHECK: stlr x27, [x28] +#CHECK: stlr x27, [x28] +0xf8 0xff 0x9f 0x08 +0xd9 0xff 0x9f 0x48 +0xba 0xff 0x9f 0x88 +0x9b 0xff 0x9f 0xc8 +0x9b 0xef 0x9f 0xc8 +0x9b 0xff 0x9e 0xc8 + +#CHECK: ldarb w23, [sp] +#CHECK: ldarh w22, [x30] +#CHECK: ldar wzr, [x29] +#CHECK: ldar x21, [x28] +#CHECK: ldar x21, [x28] +#CHECK: ldar x21, [x28] +0xf7 0xff 0xdf 0x08 +0xd6 0xff 0xdf 0x48 +0xbf 0xff 0xdf 0x88 +0x95 0xff 0xdf 0xc8 +0x95 0xef 0xdf 0xc8 +0x95 0xff 0xde 0xc8 + +#------------------------------------------------------------------------------ +# Load/store (unscaled immediate) +#------------------------------------------------------------------------------ + +# CHECK: sturb w9, [sp] +# CHECK: sturh wzr, [x12, #255] +# CHECK: stur w16, [x0, #-256] +# CHECK: stur x28, [x14, #1] +0xe9 0x3 0x0 0x38 +0x9f 0xf1 0xf 0x78 +0x10 0x0 0x10 0xb8 +0xdc 0x11 0x0 0xf8 + +# CHECK: ldurb w1, [x20, #255] +# CHECK: ldurh w20, [x1, #255] +# CHECK: ldur w12, [sp, #255] +# CHECK: ldur xzr, [x12, #255] +0x81 0xf2 0x4f 0x38 +0x34 0xf0 0x4f 0x78 +0xec 0xf3 0x4f 0xb8 +0x9f 0xf1 0x4f 0xf8 + +# CHECK: ldursb x9, [x7, #-256] +# CHECK: ldursh x17, [x19, #-256] +# CHECK: ldursw x20, [x15, #-256] +# CHECK: prfum pldl2keep, [sp, #-256] +# CHECK: ldursb w19, [x1, #-256] +# CHECK: ldursh w15, [x21, #-256] +0xe9 0x0 0x90 0x38 +0x71 0x2 0x90 0x78 +0xf4 0x1 0x90 0xb8 +0xe2 0x3 0x90 0xf8 +0x33 0x0 0xd0 0x38 +0xaf 0x2 0xd0 0x78 + +# CHECK: stur b0, [sp, #1] +# CHECK: stur h12, [x12, #-1] +# CHECK: stur s15, [x0, #255] +# CHECK: stur d31, [x5, #25] +# CHECK: stur q9, [x5] +0xe0 0x13 0x0 0x3c +0x8c 0xf1 0x1f 0x7c +0xf 0xf0 0xf 0xbc +0xbf 0x90 0x1 0xfc +0xa9 0x0 0x80 0x3c + +# CHECK: ldur b3, [sp] +# CHECK: ldur h5, [x4, #-256] +# CHECK: ldur s7, [x12, #-1] +# CHECK: ldur d11, [x19, #4] +# CHECK: ldur q13, [x1, #2] +0xe3 0x3 0x40 0x3c +0x85 0x0 0x50 0x7c +0x87 0xf1 0x5f 0xbc +0x6b 0x42 0x40 0xfc +0x2d 0x20 0xc0 0x3c + +#------------------------------------------------------------------------------ +# Load/store (immediate post-indexed) +#------------------------------------------------------------------------------ + +# E.g. "str xzr, [sp], #4" is *not* unpredictable +# CHECK-NOT: warning: potentially undefined instruction encoding +0xff 0x47 0x40 0xb8 + +# CHECK: strb w9, [x2], #255 +# CHECK: strb w10, [x3], #1 +# CHECK: strb w10, [x3], #-256 +# CHECK: strh w9, [x2], #255 +# CHECK: strh w9, [x2], #1 +# CHECK: strh w10, [x3], #-256 +0x49 0xf4 0xf 0x38 +0x6a 0x14 0x0 0x38 +0x6a 0x4 0x10 0x38 +0x49 0xf4 0xf 0x78 +0x49 0x14 0x0 0x78 +0x6a 0x4 0x10 0x78 + +# CHECK: str w19, [sp], #255 +# CHECK: str w20, [x30], #1 +# CHECK: str w21, [x12], #-256 +# CHECK: str xzr, [x9], #255 +# CHECK: str x2, [x3], #1 +# CHECK: str x19, [x12], #-256 +0xf3 0xf7 0xf 0xb8 +0xd4 0x17 0x0 0xb8 +0x95 0x5 0x10 0xb8 +0x3f 0xf5 0xf 0xf8 +0x62 0x14 0x0 0xf8 +0x93 0x5 0x10 0xf8 + +# CHECK: ldrb w9, [x2], #255 +# CHECK: ldrb w10, [x3], #1 +# CHECK: ldrb w10, [x3], #-256 +# CHECK: ldrh w9, [x2], #255 +# CHECK: ldrh w9, [x2], #1 +# CHECK: ldrh w10, [x3], #-256 +0x49 0xf4 0x4f 0x38 +0x6a 0x14 0x40 0x38 +0x6a 0x4 0x50 0x38 +0x49 0xf4 0x4f 0x78 +0x49 0x14 0x40 0x78 +0x6a 0x4 0x50 0x78 + +# CHECK: ldr w19, [sp], #255 +# CHECK: ldr w20, [x30], #1 +# CHECK: ldr w21, [x12], #-256 +# CHECK: ldr xzr, [x9], #255 +# CHECK: ldr x2, [x3], #1 +# CHECK: ldr x19, [x12], #-256 +0xf3 0xf7 0x4f 0xb8 +0xd4 0x17 0x40 0xb8 +0x95 0x5 0x50 0xb8 +0x3f 0xf5 0x4f 0xf8 +0x62 0x14 0x40 0xf8 +0x93 0x5 0x50 0xf8 + +# CHECK: ldrsb xzr, [x9], #255 +# CHECK: ldrsb x2, [x3], #1 +# CHECK: ldrsb x19, [x12], #-256 +# CHECK: ldrsh xzr, [x9], #255 +# CHECK: ldrsh x2, [x3], #1 +# CHECK: ldrsh x19, [x12], #-256 +# CHECK: ldrsw xzr, [x9], #255 +# CHECK: ldrsw x2, [x3], #1 +# CHECK: ldrsw x19, [x12], #-256 +0x3f 0xf5 0x8f 0x38 +0x62 0x14 0x80 0x38 +0x93 0x5 0x90 0x38 +0x3f 0xf5 0x8f 0x78 +0x62 0x14 0x80 0x78 +0x93 0x5 0x90 0x78 +0x3f 0xf5 0x8f 0xb8 +0x62 0x14 0x80 0xb8 +0x93 0x5 0x90 0xb8 + +# CHECK: ldrsb wzr, [x9], #255 +# CHECK: ldrsb w2, [x3], #1 +# CHECK: ldrsb w19, [x12], #-256 +# CHECK: ldrsh wzr, [x9], #255 +# CHECK: ldrsh w2, [x3], #1 +# CHECK: ldrsh w19, [x12], #-256 +0x3f 0xf5 0xcf 0x38 +0x62 0x14 0xc0 0x38 +0x93 0x5 0xd0 0x38 +0x3f 0xf5 0xcf 0x78 +0x62 0x14 0xc0 0x78 +0x93 0x5 0xd0 0x78 + +# CHECK: str b0, [x0], #255 +# CHECK: str b3, [x3], #1 +# CHECK: str b5, [sp], #-256 +# CHECK: str h10, [x10], #255 +# CHECK: str h13, [x23], #1 +# CHECK: str h15, [sp], #-256 +# CHECK: str s20, [x20], #255 +# CHECK: str s23, [x23], #1 +# CHECK: str s25, [x0], #-256 +# CHECK: str d20, [x20], #255 +# CHECK: str d23, [x23], #1 +# CHECK: str d25, [x0], #-256 +0x0 0xf4 0xf 0x3c +0x63 0x14 0x0 0x3c +0xe5 0x7 0x10 0x3c +0x4a 0xf5 0xf 0x7c +0xed 0x16 0x0 0x7c +0xef 0x7 0x10 0x7c +0x94 0xf6 0xf 0xbc +0xf7 0x16 0x0 0xbc +0x19 0x4 0x10 0xbc +0x94 0xf6 0xf 0xfc +0xf7 0x16 0x0 0xfc +0x19 0x4 0x10 0xfc + +# CHECK: ldr b0, [x0], #255 +# CHECK: ldr b3, [x3], #1 +# CHECK: ldr b5, [sp], #-256 +# CHECK: ldr h10, [x10], #255 +# CHECK: ldr h13, [x23], #1 +# CHECK: ldr h15, [sp], #-256 +# CHECK: ldr s20, [x20], #255 +# CHECK: ldr s23, [x23], #1 +# CHECK: ldr s25, [x0], #-256 +# CHECK: ldr d20, [x20], #255 +# CHECK: ldr d23, [x23], #1 +# CHECK: ldr d25, [x0], #-256 +0x0 0xf4 0x4f 0x3c +0x63 0x14 0x40 0x3c +0xe5 0x7 0x50 0x3c +0x4a 0xf5 0x4f 0x7c +0xed 0x16 0x40 0x7c +0xef 0x7 0x50 0x7c +0x94 0xf6 0x4f 0xbc +0xf7 0x16 0x40 0xbc +0x19 0x4 0x50 0xbc +0x94 0xf6 0x4f 0xfc +0xf7 0x16 0x40 0xfc +0x19 0x4 0x50 0xfc +0x34 0xf4 0xcf 0x3c + +# CHECK: ldr q20, [x1], #255 +# CHECK: ldr q23, [x9], #1 +# CHECK: ldr q25, [x20], #-256 +# CHECK: str q10, [x1], #255 +# CHECK: str q22, [sp], #1 +# CHECK: str q21, [x20], #-256 +0x37 0x15 0xc0 0x3c +0x99 0x6 0xd0 0x3c +0x2a 0xf4 0x8f 0x3c +0xf6 0x17 0x80 0x3c +0x95 0x6 0x90 0x3c + +#------------------------------------------------------------------------------- +# Load-store register (immediate pre-indexed) +#------------------------------------------------------------------------------- + +# E.g. "str xzr, [sp, #4]!" is *not* unpredictable +# CHECK-NOT: warning: potentially undefined instruction encoding +0xff 0xf 0x40 0xf8 + +# CHECK: ldr x3, [x4, #0]! +0x83 0xc 0x40 0xf8 + +# CHECK: strb w9, [x2, #255]! +# CHECK: strb w10, [x3, #1]! +# CHECK: strb w10, [x3, #-256]! +# CHECK: strh w9, [x2, #255]! +# CHECK: strh w9, [x2, #1]! +# CHECK: strh w10, [x3, #-256]! +0x49 0xfc 0xf 0x38 +0x6a 0x1c 0x0 0x38 +0x6a 0xc 0x10 0x38 +0x49 0xfc 0xf 0x78 +0x49 0x1c 0x0 0x78 +0x6a 0xc 0x10 0x78 + +# CHECK: str w19, [sp, #255]! +# CHECK: str w20, [x30, #1]! +# CHECK: str w21, [x12, #-256]! +# CHECK: str xzr, [x9, #255]! +# CHECK: str x2, [x3, #1]! +# CHECK: str x19, [x12, #-256]! +0xf3 0xff 0xf 0xb8 +0xd4 0x1f 0x0 0xb8 +0x95 0xd 0x10 0xb8 +0x3f 0xfd 0xf 0xf8 +0x62 0x1c 0x0 0xf8 +0x93 0xd 0x10 0xf8 + +# CHECK: ldrb w9, [x2, #255]! +# CHECK: ldrb w10, [x3, #1]! +# CHECK: ldrb w10, [x3, #-256]! +# CHECK: ldrh w9, [x2, #255]! +# CHECK: ldrh w9, [x2, #1]! +# CHECK: ldrh w10, [x3, #-256]! +0x49 0xfc 0x4f 0x38 +0x6a 0x1c 0x40 0x38 +0x6a 0xc 0x50 0x38 +0x49 0xfc 0x4f 0x78 +0x49 0x1c 0x40 0x78 +0x6a 0xc 0x50 0x78 + +# CHECK: ldr w19, [sp, #255]! +# CHECK: ldr w20, [x30, #1]! +# CHECK: ldr w21, [x12, #-256]! +# CHECK: ldr xzr, [x9, #255]! +# CHECK: ldr x2, [x3, #1]! +# CHECK: ldr x19, [x12, #-256]! +0xf3 0xff 0x4f 0xb8 +0xd4 0x1f 0x40 0xb8 +0x95 0xd 0x50 0xb8 +0x3f 0xfd 0x4f 0xf8 +0x62 0x1c 0x40 0xf8 +0x93 0xd 0x50 0xf8 + +# CHECK: ldrsb xzr, [x9, #255]! +# CHECK: ldrsb x2, [x3, #1]! +# CHECK: ldrsb x19, [x12, #-256]! +# CHECK: ldrsh xzr, [x9, #255]! +# CHECK: ldrsh x2, [x3, #1]! +# CHECK: ldrsh x19, [x12, #-256]! +# CHECK: ldrsw xzr, [x9, #255]! +# CHECK: ldrsw x2, [x3, #1]! +# CHECK: ldrsw x19, [x12, #-256]! +0x3f 0xfd 0x8f 0x38 +0x62 0x1c 0x80 0x38 +0x93 0xd 0x90 0x38 +0x3f 0xfd 0x8f 0x78 +0x62 0x1c 0x80 0x78 +0x93 0xd 0x90 0x78 +0x3f 0xfd 0x8f 0xb8 +0x62 0x1c 0x80 0xb8 +0x93 0xd 0x90 0xb8 + +# CHECK: ldrsb wzr, [x9, #255]! +# CHECK: ldrsb w2, [x3, #1]! +# CHECK: ldrsb w19, [x12, #-256]! +# CHECK: ldrsh wzr, [x9, #255]! +# CHECK: ldrsh w2, [x3, #1]! +# CHECK: ldrsh w19, [x12, #-256]! +0x3f 0xfd 0xcf 0x38 +0x62 0x1c 0xc0 0x38 +0x93 0xd 0xd0 0x38 +0x3f 0xfd 0xcf 0x78 +0x62 0x1c 0xc0 0x78 +0x93 0xd 0xd0 0x78 + +# CHECK: str b0, [x0, #255]! +# CHECK: str b3, [x3, #1]! +# CHECK: str b5, [sp, #-256]! +# CHECK: str h10, [x10, #255]! +# CHECK: str h13, [x23, #1]! +# CHECK: str h15, [sp, #-256]! +# CHECK: str s20, [x20, #255]! +# CHECK: str s23, [x23, #1]! +# CHECK: str s25, [x0, #-256]! +# CHECK: str d20, [x20, #255]! +# CHECK: str d23, [x23, #1]! +# CHECK: str d25, [x0, #-256]! +0x0 0xfc 0xf 0x3c +0x63 0x1c 0x0 0x3c +0xe5 0xf 0x10 0x3c +0x4a 0xfd 0xf 0x7c +0xed 0x1e 0x0 0x7c +0xef 0xf 0x10 0x7c +0x94 0xfe 0xf 0xbc +0xf7 0x1e 0x0 0xbc +0x19 0xc 0x10 0xbc +0x94 0xfe 0xf 0xfc +0xf7 0x1e 0x0 0xfc +0x19 0xc 0x10 0xfc + +# CHECK: ldr b0, [x0, #255]! +# CHECK: ldr b3, [x3, #1]! +# CHECK: ldr b5, [sp, #-256]! +# CHECK: ldr h10, [x10, #255]! +# CHECK: ldr h13, [x23, #1]! +# CHECK: ldr h15, [sp, #-256]! +# CHECK: ldr s20, [x20, #255]! +# CHECK: ldr s23, [x23, #1]! +# CHECK: ldr s25, [x0, #-256]! +# CHECK: ldr d20, [x20, #255]! +# CHECK: ldr d23, [x23, #1]! +# CHECK: ldr d25, [x0, #-256]! +0x0 0xfc 0x4f 0x3c +0x63 0x1c 0x40 0x3c +0xe5 0xf 0x50 0x3c +0x4a 0xfd 0x4f 0x7c +0xed 0x1e 0x40 0x7c +0xef 0xf 0x50 0x7c +0x94 0xfe 0x4f 0xbc +0xf7 0x1e 0x40 0xbc +0x19 0xc 0x50 0xbc +0x94 0xfe 0x4f 0xfc +0xf7 0x1e 0x40 0xfc +0x19 0xc 0x50 0xfc + +# CHECK: ldr q20, [x1, #255]! +# CHECK: ldr q23, [x9, #1]! +# CHECK: ldr q25, [x20, #-256]! +# CHECK: str q10, [x1, #255]! +# CHECK: str q22, [sp, #1]! +# CHECK: str q21, [x20, #-256]! +0x34 0xfc 0xcf 0x3c +0x37 0x1d 0xc0 0x3c +0x99 0xe 0xd0 0x3c +0x2a 0xfc 0x8f 0x3c +0xf6 0x1f 0x80 0x3c +0x95 0xe 0x90 0x3c + +#------------------------------------------------------------------------------ +# Load/store (unprivileged) +#------------------------------------------------------------------------------ + +# CHECK: sttrb w9, [sp] +# CHECK: sttrh wzr, [x12, #255] +# CHECK: sttr w16, [x0, #-256] +# CHECK: sttr x28, [x14, #1] +0xe9 0x0b 0x0 0x38 +0x9f 0xf9 0xf 0x78 +0x10 0x08 0x10 0xb8 +0xdc 0x19 0x0 0xf8 + +# CHECK: ldtrb w1, [x20, #255] +# CHECK: ldtrh w20, [x1, #255] +# CHECK: ldtr w12, [sp, #255] +# CHECK: ldtr xzr, [x12, #255] +0x81 0xfa 0x4f 0x38 +0x34 0xf8 0x4f 0x78 +0xec 0xfb 0x4f 0xb8 +0x9f 0xf9 0x4f 0xf8 + +# CHECK: ldtrsb x9, [x7, #-256] +# CHECK: ldtrsh x17, [x19, #-256] +# CHECK: ldtrsw x20, [x15, #-256] +# CHECK: ldtrsb w19, [x1, #-256] +# CHECK: ldtrsh w15, [x21, #-256] +0xe9 0x08 0x90 0x38 +0x71 0x0a 0x90 0x78 +0xf4 0x09 0x90 0xb8 +0x33 0x08 0xd0 0x38 +0xaf 0x0a 0xd0 0x78 + +#------------------------------------------------------------------------------ +# Load/store (unsigned immediate) +#------------------------------------------------------------------------------ + +# CHECK: ldr x0, [x0] +# CHECK: ldr x4, [x29] +# CHECK: ldr x30, [x12, #32760] +# CHECK: ldr x20, [sp, #8] +0x0 0x0 0x40 0xf9 +0xa4 0x3 0x40 0xf9 +0x9e 0xfd 0x7f 0xf9 +0xf4 0x7 0x40 0xf9 + +# CHECK: ldr xzr, [sp] +0xff 0x3 0x40 0xf9 + +# CHECK: ldr w2, [sp] +# CHECK: ldr w17, [sp, #16380] +# CHECK: ldr w13, [x2, #4] +0xe2 0x3 0x40 0xb9 +0xf1 0xff 0x7f 0xb9 +0x4d 0x4 0x40 0xb9 + +# CHECK: ldrsw x2, [x5, #4] +# CHECK: ldrsw x23, [sp, #16380] +0xa2 0x4 0x80 0xb9 +0xf7 0xff 0xbf 0xb9 + +# CHECK: ldrh w2, [x4] +# CHECK: ldrsh w23, [x6, #8190] +# CHECK: ldrsh wzr, [sp, #2] +# CHECK: ldrsh x29, [x2, #2] +0x82 0x0 0x40 0x79 +0xd7 0xfc 0xff 0x79 +0xff 0x7 0xc0 0x79 +0x5d 0x4 0x80 0x79 + +# CHECK: ldrb w26, [x3, #121] +# CHECK: ldrb w12, [x2] +# CHECK: ldrsb w27, [sp, #4095] +# CHECK: ldrsb xzr, [x15] +0x7a 0xe4 0x41 0x39 +0x4c 0x0 0x40 0x39 +0xfb 0xff 0xff 0x39 +0xff 0x1 0x80 0x39 + +# CHECK: str x30, [sp] +# CHECK: str w20, [x4, #16380] +# CHECK: strh w20, [x10, #14] +# CHECK: strh w17, [sp, #8190] +# CHECK: strb w23, [x3, #4095] +# CHECK: strb wzr, [x2] +0xfe 0x3 0x0 0xf9 +0x94 0xfc 0x3f 0xb9 +0x54 0x1d 0x0 0x79 +0xf1 0xff 0x3f 0x79 +0x77 0xfc 0x3f 0x39 +0x5f 0x0 0x0 0x39 + +# CHECK: ldr b31, [sp, #4095] +# CHECK: ldr h20, [x2, #8190] +# CHECK: ldr s10, [x19, #16380] +# CHECK: ldr d3, [x10, #32760] +# CHECK: str q12, [sp, #65520] +0xff 0xff 0x7f 0x3d +0x54 0xfc 0x7f 0x7d +0x6a 0xfe 0x7f 0xbd +0x43 0xfd 0x7f 0xfd +0xec 0xff 0xbf 0x3d + +# CHECK: prfm pldl1keep, [sp, #8] +# CHECK: prfm pldl1strm, [x3, #0] +# CHECK: prfm pldl2keep, [x5, #16] +# CHECK: prfm pldl2strm, [x2, #0] +# CHECK: prfm pldl3keep, [x5, #0] +# CHECK: prfm pldl3strm, [x6, #0] +# CHECK: prfm plil1keep, [sp, #8] +# CHECK: prfm plil1strm, [x3, #0] +# CHECK: prfm plil2keep, [x5, #16] +# CHECK: prfm plil2strm, [x2, #0] +# CHECK: prfm plil3keep, [x5, #0] +# CHECK: prfm plil3strm, [x6, #0] +# CHECK: prfm pstl1keep, [sp, #8] +# CHECK: prfm pstl1strm, [x3, #0] +# CHECK: prfm pstl2keep, [x5, #16] +# CHECK: prfm pstl2strm, [x2, #0] +# CHECK: prfm pstl3keep, [x5, #0] +# CHECK: prfm pstl3strm, [x6, #0] +0xe0 0x07 0x80 0xf9 +0x61 0x00 0x80 0xf9 +0xa2 0x08 0x80 0xf9 +0x43 0x00 0x80 0xf9 +0xa4 0x00 0x80 0xf9 +0xc5 0x00 0x80 0xf9 +0xe8 0x07 0x80 0xf9 +0x69 0x00 0x80 0xf9 +0xaa 0x08 0x80 0xf9 +0x4b 0x00 0x80 0xf9 +0xac 0x00 0x80 0xf9 +0xcd 0x00 0x80 0xf9 +0xf0 0x07 0x80 0xf9 +0x71 0x00 0x80 0xf9 +0xb2 0x08 0x80 0xf9 +0x53 0x00 0x80 0xf9 +0xb4 0x00 0x80 0xf9 +0xd5 0x00 0x80 0xf9 + + +#------------------------------------------------------------------------------ +# Load/store (register offset) +#------------------------------------------------------------------------------ + +# CHECK: ldrb w3, [sp, x5] +# CHECK: ldrb w9, [x27, x6] +# CHECK: ldrsb w10, [x30, x7] +# CHECK: ldrb w11, [x29, x3, sxtx] +# CHECK: strb w12, [x28, xzr, sxtx] +# CHECK: ldrb w14, [x26, w6, uxtw] +# CHECK: ldrsb w15, [x25, w7, uxtw] +# CHECK: ldrb w17, [x23, w9, sxtw] +# CHECK: ldrsb x18, [x22, w10, sxtw] +0xe3 0x6b 0x65 0x38 +0x69 0x6b 0x66 0x38 +0xca 0x6b 0xe7 0x38 +0xab 0xeb 0x63 0x38 +0x8c 0xeb 0x3f 0x38 +0x4e 0x4b 0x66 0x38 +0x2f 0x4b 0xe7 0x38 +0xf1 0xca 0x69 0x38 +0xd2 0xca 0xaa 0x38 + +# CHECK: ldrsh w3, [sp, x5] +# CHECK: ldrsh w9, [x27, x6] +# CHECK: ldrh w10, [x30, x7, lsl #1] +# CHECK: strh w11, [x29, x3, sxtx] +# CHECK: ldrh w12, [x28, xzr, sxtx] +# CHECK: ldrsh x13, [x27, x5, sxtx #1] +# CHECK: ldrh w14, [x26, w6, uxtw] +# CHECK: ldrh w15, [x25, w7, uxtw] +# CHECK: ldrsh w16, [x24, w8, uxtw #1] +# CHECK: ldrh w17, [x23, w9, sxtw] +# CHECK: ldrh w18, [x22, w10, sxtw] +# CHECK: strh w19, [x21, wzr, sxtw #1] +0xe3 0x6b 0xe5 0x78 +0x69 0x6b 0xe6 0x78 +0xca 0x7b 0x67 0x78 +0xab 0xeb 0x23 0x78 +0x8c 0xeb 0x7f 0x78 +0x6d 0xfb 0xa5 0x78 +0x4e 0x4b 0x66 0x78 +0x2f 0x4b 0x67 0x78 +0x10 0x5b 0xe8 0x78 +0xf1 0xca 0x69 0x78 +0xd2 0xca 0x6a 0x78 +0xb3 0xda 0x3f 0x78 + +# CHECK: ldr w3, [sp, x5] +# CHECK: ldr s9, [x27, x6] +# CHECK: ldr w10, [x30, x7, lsl #2] +# CHECK: ldr w11, [x29, x3, sxtx] +# CHECK: str s12, [x28, xzr, sxtx] +# CHECK: str w13, [x27, x5, sxtx #2] +# CHECK: str w14, [x26, w6, uxtw] +# CHECK: ldr w15, [x25, w7, uxtw] +# CHECK: ldr w16, [x24, w8, uxtw #2] +# CHECK: ldrsw x17, [x23, w9, sxtw] +# CHECK: ldr w18, [x22, w10, sxtw] +# CHECK: ldrsw x19, [x21, wzr, sxtw #2] +0xe3 0x6b 0x65 0xb8 +0x69 0x6b 0x66 0xbc +0xca 0x7b 0x67 0xb8 +0xab 0xeb 0x63 0xb8 +0x8c 0xeb 0x3f 0xbc +0x6d 0xfb 0x25 0xb8 +0x4e 0x4b 0x26 0xb8 +0x2f 0x4b 0x67 0xb8 +0x10 0x5b 0x68 0xb8 +0xf1 0xca 0xa9 0xb8 +0xd2 0xca 0x6a 0xb8 +0xb3 0xda 0xbf 0xb8 + +# CHECK: ldr x3, [sp, x5] +# CHECK: str x9, [x27, x6] +# CHECK: ldr d10, [x30, x7, lsl #3] +# CHECK: str x11, [x29, x3, sxtx] +# CHECK: ldr x12, [x28, xzr, sxtx] +# CHECK: ldr x13, [x27, x5, sxtx #3] +# CHECK: prfm pldl1keep, [x26, w6, uxtw] +# CHECK: ldr x15, [x25, w7, uxtw] +# CHECK: ldr x16, [x24, w8, uxtw #3] +# CHECK: ldr x17, [x23, w9, sxtw] +# CHECK: ldr x18, [x22, w10, sxtw] +# CHECK: str d19, [x21, wzr, sxtw #3] +0xe3 0x6b 0x65 0xf8 +0x69 0x6b 0x26 0xf8 +0xca 0x7b 0x67 0xfc +0xab 0xeb 0x23 0xf8 +0x8c 0xeb 0x7f 0xf8 +0x6d 0xfb 0x65 0xf8 +0x40 0x4b 0xa6 0xf8 +0x2f 0x4b 0x67 0xf8 +0x10 0x5b 0x68 0xf8 +0xf1 0xca 0x69 0xf8 +0xd2 0xca 0x6a 0xf8 +0xb3 0xda 0x3f 0xfc + +# CHECK: ldr q3, [sp, x5] +# CHECK: ldr q9, [x27, x6] +# CHECK: ldr q10, [x30, x7, lsl #4] +# CHECK: str q11, [x29, x3, sxtx] +# CHECK: str q12, [x28, xzr, sxtx] +# CHECK: str q13, [x27, x5, sxtx #4] +# CHECK: ldr q14, [x26, w6, uxtw] +# CHECK: ldr q15, [x25, w7, uxtw] +# CHECK: ldr q16, [x24, w8, uxtw #4] +# CHECK: ldr q17, [x23, w9, sxtw] +# CHECK: str q18, [x22, w10, sxtw] +# CHECK: ldr q19, [x21, wzr, sxtw #4] +0xe3 0x6b 0xe5 0x3c +0x69 0x6b 0xe6 0x3c +0xca 0x7b 0xe7 0x3c +0xab 0xeb 0xa3 0x3c +0x8c 0xeb 0xbf 0x3c +0x6d 0xfb 0xa5 0x3c +0x4e 0x4b 0xe6 0x3c +0x2f 0x4b 0xe7 0x3c +0x10 0x5b 0xe8 0x3c +0xf1 0xca 0xe9 0x3c +0xd2 0xca 0xaa 0x3c +0xb3 0xda 0xff 0x3c + +#------------------------------------------------------------------------------ +# Load/store register pair (offset) +#------------------------------------------------------------------------------ + +# CHECK: ldp w3, w5, [sp] +# CHECK: stp wzr, w9, [sp, #252] +# CHECK: ldp w2, wzr, [sp, #-256] +# CHECK: ldp w9, w10, [sp, #4] +0xe3 0x17 0x40 0x29 +0xff 0xa7 0x1f 0x29 +0xe2 0x7f 0x60 0x29 +0xe9 0xab 0x40 0x29 + +# CHECK: ldpsw x9, x10, [sp, #4] +# CHECK: ldpsw x9, x10, [x2, #-256] +# CHECK: ldpsw x20, x30, [sp, #252] +0xe9 0xab 0x40 0x69 +0x49 0x28 0x60 0x69 +0xf4 0xfb 0x5f 0x69 + +# CHECK: ldp x21, x29, [x2, #504] +# CHECK: ldp x22, x23, [x3, #-512] +# CHECK: ldp x24, x25, [x4, #8] +0x55 0xf4 0x5f 0xa9 +0x76 0x5c 0x60 0xa9 +0x98 0xe4 0x40 0xa9 + +# CHECK: ldp s29, s28, [sp, #252] +# CHECK: stp s27, s26, [sp, #-256] +# CHECK: ldp s1, s2, [x3, #44] +0xfd 0xf3 0x5f 0x2d +0xfb 0x6b 0x20 0x2d +0x61 0x88 0x45 0x2d + +# CHECK: stp d3, d5, [x9, #504] +# CHECK: stp d7, d11, [x10, #-512] +# CHECK: ldp d2, d3, [x30, #-8] +0x23 0x95 0x1f 0x6d +0x47 0x2d 0x20 0x6d +0xc2 0x8f 0x7f 0x6d + +# CHECK: stp q3, q5, [sp] +# CHECK: stp q17, q19, [sp, #1008] +# CHECK: ldp q23, q29, [x1, #-1024] +0xe3 0x17 0x0 0xad +0xf1 0xcf 0x1f 0xad +0x37 0x74 0x60 0xad + +#------------------------------------------------------------------------------ +# Load/store register pair (post-indexed) +#------------------------------------------------------------------------------ + +# CHECK: ldp w3, w5, [sp], #0 +# CHECK: stp wzr, w9, [sp], #252 +# CHECK: ldp w2, wzr, [sp], #-256 +# CHECK: ldp w9, w10, [sp], #4 +0xe3 0x17 0xc0 0x28 +0xff 0xa7 0x9f 0x28 +0xe2 0x7f 0xe0 0x28 +0xe9 0xab 0xc0 0x28 + +# CHECK: ldpsw x9, x10, [sp], #4 +# CHECK: ldpsw x9, x10, [x2], #-256 +# CHECK: ldpsw x20, x30, [sp], #252 +0xe9 0xab 0xc0 0x68 +0x49 0x28 0xe0 0x68 +0xf4 0xfb 0xdf 0x68 + +# CHECK: ldp x21, x29, [x2], #504 +# CHECK: ldp x22, x23, [x3], #-512 +# CHECK: ldp x24, x25, [x4], #8 +0x55 0xf4 0xdf 0xa8 +0x76 0x5c 0xe0 0xa8 +0x98 0xe4 0xc0 0xa8 + +# CHECK: ldp s29, s28, [sp], #252 +# CHECK: stp s27, s26, [sp], #-256 +# CHECK: ldp s1, s2, [x3], #44 +0xfd 0xf3 0xdf 0x2c +0xfb 0x6b 0xa0 0x2c +0x61 0x88 0xc5 0x2c + +# CHECK: stp d3, d5, [x9], #504 +# CHECK: stp d7, d11, [x10], #-512 +# CHECK: ldp d2, d3, [x30], #-8 +0x23 0x95 0x9f 0x6c +0x47 0x2d 0xa0 0x6c +0xc2 0x8f 0xff 0x6c + +# CHECK: stp q3, q5, [sp], #0 +# CHECK: stp q17, q19, [sp], #1008 +# CHECK: ldp q23, q29, [x1], #-1024 +0xe3 0x17 0x80 0xac +0xf1 0xcf 0x9f 0xac +0x37 0x74 0xe0 0xac + +#------------------------------------------------------------------------------ +# Load/store register pair (pre-indexed) +#------------------------------------------------------------------------------ + +# CHECK: ldp w3, w5, [sp, #0]! +# CHECK: stp wzr, w9, [sp, #252]! +# CHECK: ldp w2, wzr, [sp, #-256]! +# CHECK: ldp w9, w10, [sp, #4]! +0xe3 0x17 0xc0 0x29 +0xff 0xa7 0x9f 0x29 +0xe2 0x7f 0xe0 0x29 +0xe9 0xab 0xc0 0x29 + +# CHECK: ldpsw x9, x10, [sp, #4]! +# CHECK: ldpsw x9, x10, [x2, #-256]! +# CHECK: ldpsw x20, x30, [sp, #252]! +0xe9 0xab 0xc0 0x69 +0x49 0x28 0xe0 0x69 +0xf4 0xfb 0xdf 0x69 + +# CHECK: ldp x21, x29, [x2, #504]! +# CHECK: ldp x22, x23, [x3, #-512]! +# CHECK: ldp x24, x25, [x4, #8]! +0x55 0xf4 0xdf 0xa9 +0x76 0x5c 0xe0 0xa9 +0x98 0xe4 0xc0 0xa9 + +# CHECK: ldp s29, s28, [sp, #252]! +# CHECK: stp s27, s26, [sp, #-256]! +# CHECK: ldp s1, s2, [x3, #44]! +0xfd 0xf3 0xdf 0x2d +0xfb 0x6b 0xa0 0x2d +0x61 0x88 0xc5 0x2d + +# CHECK: stp d3, d5, [x9, #504]! +# CHECK: stp d7, d11, [x10, #-512]! +# CHECK: ldp d2, d3, [x30, #-8]! +0x23 0x95 0x9f 0x6d +0x47 0x2d 0xa0 0x6d +0xc2 0x8f 0xff 0x6d + +# CHECK: stp q3, q5, [sp, #0]! +# CHECK: stp q17, q19, [sp, #1008]! +# CHECK: ldp q23, q29, [x1, #-1024]! +0xe3 0x17 0x80 0xad +0xf1 0xcf 0x9f 0xad +0x37 0x74 0xe0 0xad + +#------------------------------------------------------------------------------ +# Load/store register pair (offset) +#------------------------------------------------------------------------------ + +# CHECK: ldnp w3, w5, [sp] +# CHECK: stnp wzr, w9, [sp, #252] +# CHECK: ldnp w2, wzr, [sp, #-256] +# CHECK: ldnp w9, w10, [sp, #4] +0xe3 0x17 0x40 0x28 +0xff 0xa7 0x1f 0x28 +0xe2 0x7f 0x60 0x28 +0xe9 0xab 0x40 0x28 + +# CHECK: ldnp x21, x29, [x2, #504] +# CHECK: ldnp x22, x23, [x3, #-512] +# CHECK: ldnp x24, x25, [x4, #8] +0x55 0xf4 0x5f 0xa8 +0x76 0x5c 0x60 0xa8 +0x98 0xe4 0x40 0xa8 + +# CHECK: ldnp s29, s28, [sp, #252] +# CHECK: stnp s27, s26, [sp, #-256] +# CHECK: ldnp s1, s2, [x3, #44] +0xfd 0xf3 0x5f 0x2c +0xfb 0x6b 0x20 0x2c +0x61 0x88 0x45 0x2c + +# CHECK: stnp d3, d5, [x9, #504] +# CHECK: stnp d7, d11, [x10, #-512] +# CHECK: ldnp d2, d3, [x30, #-8] +0x23 0x95 0x1f 0x6c +0x47 0x2d 0x20 0x6c +0xc2 0x8f 0x7f 0x6c + +# CHECK: stnp q3, q5, [sp] +# CHECK: stnp q17, q19, [sp, #1008] +# CHECK: ldnp q23, q29, [x1, #-1024] +0xe3 0x17 0x0 0xac +0xf1 0xcf 0x1f 0xac +0x37 0x74 0x60 0xac + +#------------------------------------------------------------------------------ +# Logical (immediate) +#------------------------------------------------------------------------------ +# CHECK: orr w3, w9, #0xffff0000 +# CHECK: orr wsp, w10, #0xe00000ff +# CHECK: orr w9, w10, #0x3ff +0x23 0x3d 0x10 0x32 +0x5f 0x29 0x3 0x32 +0x49 0x25 0x0 0x32 + +# CHECK: and w14, w15, #0x80008000 +# CHECK: and w12, w13, #0xffc3ffc3 +# CHECK: and w11, wzr, #0x30003 +0xee 0x81 0x1 0x12 +0xac 0xad 0xa 0x12 +0xeb 0x87 0x0 0x12 + +# CHECK: eor w3, w6, #0xe0e0e0e0 +# CHECK: eor wsp, wzr, #0x3030303 +# CHECK: eor w16, w17, #0x81818181 +0xc3 0xc8 0x3 0x52 +0xff 0xc7 0x0 0x52 +0x30 0xc6 0x1 0x52 + +# CHECK: ands wzr, w18, #0xcccccccc +# CHECK: ands w19, w20, #0x33333333 +# CHECK: ands w21, w22, #0x99999999 +0x5f 0xe6 0x2 0x72 +0x93 0xe6 0x0 0x72 +0xd5 0xe6 0x1 0x72 + +# CHECK: ands wzr, w3, #0xaaaaaaaa +# CHECK: ands wzr, wzr, #0x55555555 +0x7f 0xf0 0x1 0x72 +0xff 0xf3 0x0 0x72 + +# CHECK: eor x3, x5, #0xffffffffc000000 +# CHECK: and x9, x10, #0x7fffffffffff +# CHECK: orr x11, x12, #0x8000000000000fff +0xa3 0x84 0x66 0xd2 +0x49 0xb9 0x40 0x92 +0x8b 0x31 0x41 0xb2 + +# CHECK: orr x3, x9, #0xffff0000ffff0000 +# CHECK: orr sp, x10, #0xe00000ffe00000ff +# CHECK: orr x9, x10, #0x3ff000003ff +0x23 0x3d 0x10 0xb2 +0x5f 0x29 0x3 0xb2 +0x49 0x25 0x0 0xb2 + +# CHECK: and x14, x15, #0x8000800080008000 +# CHECK: and x12, x13, #0xffc3ffc3ffc3ffc3 +# CHECK: and x11, xzr, #0x3000300030003 +0xee 0x81 0x1 0x92 +0xac 0xad 0xa 0x92 +0xeb 0x87 0x0 0x92 + +# CHECK: eor x3, x6, #0xe0e0e0e0e0e0e0e0 +# CHECK: eor sp, xzr, #0x303030303030303 +# CHECK: eor x16, x17, #0x8181818181818181 +0xc3 0xc8 0x3 0xd2 +0xff 0xc7 0x0 0xd2 +0x30 0xc6 0x1 0xd2 + +# CHECK: ands xzr, x18, #0xcccccccccccccccc +# CHECK: ands x19, x20, #0x3333333333333333 +# CHECK: ands x21, x22, #0x9999999999999999 +0x5f 0xe6 0x2 0xf2 +0x93 0xe6 0x0 0xf2 +0xd5 0xe6 0x1 0xf2 + +# CHECK: ands xzr, x3, #0xaaaaaaaaaaaaaaaa +# CHECK: ands xzr, xzr, #0x5555555555555555 +0x7f 0xf0 0x1 0xf2 +0xff 0xf3 0x0 0xf2 + +# CHECK: orr w3, wzr, #0xf000f +# CHECK: orr x10, xzr, #0xaaaaaaaaaaaaaaaa +0xe3 0x8f 0x0 0x32 +0xea 0xf3 0x1 0xb2 + +# CHECK: orr w3, wzr, #0xffff +# CHECK: orr x9, xzr, #0xffff00000000 +0xe3 0x3f 0x0 0x32 +0xe9 0x3f 0x60 0xb2 + +#------------------------------------------------------------------------------ +# Logical (shifted register) +#------------------------------------------------------------------------------ + +# CHECK: and w12, w23, w21 +# CHECK: and w16, w15, w1, lsl #1 +# CHECK: and w9, w4, w10, lsl #31 +# CHECK: and w3, w30, w11 +# CHECK: and x3, x5, x7, lsl #63 +0xec 0x2 0x15 0xa +0xf0 0x5 0x1 0xa +0x89 0x7c 0xa 0xa +0xc3 0x3 0xb 0xa +0xa3 0xfc 0x7 0x8a + +# CHECK: and x5, x14, x19, asr #4 +# CHECK: and w3, w17, w19, ror #31 +# CHECK: and w0, w2, wzr, lsr #17 +# CHECK: and w3, w30, w11, asr +0xc5 0x11 0x93 0x8a +0x23 0x7e 0xd3 0xa +0x40 0x44 0x5f 0xa +0xc3 0x3 0x8b 0xa + +# CHECK: and xzr, x4, x26 +# CHECK: and w3, wzr, w20, ror +# CHECK: and x7, x20, xzr, asr #63 +0x9f 0x0 0x1a 0x8a +0xe3 0x3 0xd4 0xa +0x87 0xfe 0x9f 0x8a + +# CHECK: bic x13, x20, x14, lsl #47 +# CHECK: bic w2, w7, w9 +# CHECK: orr w2, w7, w0, asr #31 +# CHECK: orr x8, x9, x10, lsl #12 +# CHECK: orn x3, x5, x7, asr +# CHECK: orn w2, w5, w29 +0x8d 0xbe 0x2e 0x8a +0xe2 0x0 0x29 0xa +0xe2 0x7c 0x80 0x2a +0x28 0x31 0xa 0xaa +0xa3 0x0 0xa7 0xaa +0xa2 0x0 0x3d 0x2a + +# CHECK: ands w7, wzr, w9, lsl #1 +# CHECK: ands x3, x5, x20, ror #63 +# CHECK: bics w3, w5, w7 +# CHECK: bics x3, xzr, x3, lsl #1 +# CHECK: tst w3, w7, lsl #31 +# CHECK: tst x2, x20, asr +0xe7 0x7 0x9 0x6a +0xa3 0xfc 0xd4 0xea +0xa3 0x0 0x27 0x6a +0xe3 0x7 0x23 0xea +0x7f 0x7c 0x7 0x6a +0x5f 0x0 0x94 0xea + +# CHECK: mov x3, x6 +# CHECK: mov x3, xzr +# CHECK: mov wzr, w2 +# CHECK: mov w3, w5 +0xe3 0x3 0x6 0xaa +0xe3 0x3 0x1f 0xaa +0xff 0x3 0x2 0x2a +0xe3 0x3 0x5 0x2a + +#------------------------------------------------------------------------------ +# Move wide (immediate) +#------------------------------------------------------------------------------ + +# N.b. (FIXME) canonical aliases aren't produced here because of +# limitation in InstAlias. Lots of the "mov[nz]" instructions should +# be "mov". + +# CHECK: movz w1, #65535 +# CHECK: movz w2, #0, lsl #16 +# CHECK: movn w2, #1234 +0xe1 0xff 0x9f 0x52 +0x2 0x0 0xa0 0x52 +0x42 0x9a 0x80 0x12 + +# CHECK: movz x2, #1234, lsl #32 +# CHECK: movk xzr, #4321, lsl #48 +0x42 0x9a 0xc0 0xd2 +0x3f 0x1c 0xe2 0xf2 + +# CHECK: movz x2, #0 +# CHECK: movk w3, #0 +# CHECK: movz x4, #0, lsl #16 +# CHECK: movk w5, #0, lsl #16 +# CHECK: movz x6, #0, lsl #32 +# CHECK: movk x7, #0, lsl #32 +# CHECK: movz x8, #0, lsl #48 +# CHECK: movk x9, #0, lsl #48 +0x2 0x0 0x80 0xd2 +0x3 0x0 0x80 0x72 +0x4 0x0 0xa0 0xd2 +0x5 0x0 0xa0 0x72 +0x6 0x0 0xc0 0xd2 +0x7 0x0 0xc0 0xf2 +0x8 0x0 0xe0 0xd2 +0x9 0x0 0xe0 0xf2 + +#------------------------------------------------------------------------------ +# PC-relative addressing +#------------------------------------------------------------------------------ + +# It's slightly dodgy using immediates here, but harmless enough when +# it's all that's available. + +# CHECK: adr x2, #1600 +# CHECK: adrp x21, #6553600 +# CHECK: adr x0, #262144 +0x02 0x32 0x00 0x10 +0x15 0x32 0x00 0x90 +0x00 0x00 0x20 0x10 + +#------------------------------------------------------------------------------ +# System +#------------------------------------------------------------------------------ + +# CHECK: nop +# CHECK: hint #127 +# CHECK: nop +# CHECK: yield +# CHECK: wfe +# CHECK: wfi +# CHECK: sev +# CHECK: sevl +0x1f 0x20 0x3 0xd5 +0xff 0x2f 0x3 0xd5 +0x1f 0x20 0x3 0xd5 +0x3f 0x20 0x3 0xd5 +0x5f 0x20 0x3 0xd5 +0x7f 0x20 0x3 0xd5 +0x9f 0x20 0x3 0xd5 +0xbf 0x20 0x3 0xd5 + +# CHECK: clrex +# CHECK: clrex #0 +# CHECK: clrex #7 +# CHECK: clrex +0x5f 0x3f 0x3 0xd5 +0x5f 0x30 0x3 0xd5 +0x5f 0x37 0x3 0xd5 +0x5f 0x3f 0x3 0xd5 + +# CHECK: dsb #0 +# CHECK: dsb #12 +# CHECK: dsb sy +# CHECK: dsb oshld +# CHECK: dsb oshst +# CHECK: dsb osh +# CHECK: dsb nshld +# CHECK: dsb nshst +# CHECK: dsb nsh +# CHECK: dsb ishld +# CHECK: dsb ishst +# CHECK: dsb ish +# CHECK: dsb ld +# CHECK: dsb st +# CHECK: dsb sy +0x9f 0x30 0x3 0xd5 +0x9f 0x3c 0x3 0xd5 +0x9f 0x3f 0x3 0xd5 +0x9f 0x31 0x3 0xd5 +0x9f 0x32 0x3 0xd5 +0x9f 0x33 0x3 0xd5 +0x9f 0x35 0x3 0xd5 +0x9f 0x36 0x3 0xd5 +0x9f 0x37 0x3 0xd5 +0x9f 0x39 0x3 0xd5 +0x9f 0x3a 0x3 0xd5 +0x9f 0x3b 0x3 0xd5 +0x9f 0x3d 0x3 0xd5 +0x9f 0x3e 0x3 0xd5 +0x9f 0x3f 0x3 0xd5 + +# CHECK: dmb #0 +# CHECK: dmb #12 +# CHECK: dmb sy +# CHECK: dmb oshld +# CHECK: dmb oshst +# CHECK: dmb osh +# CHECK: dmb nshld +# CHECK: dmb nshst +# CHECK: dmb nsh +# CHECK: dmb ishld +# CHECK: dmb ishst +# CHECK: dmb ish +# CHECK: dmb ld +# CHECK: dmb st +# CHECK: dmb sy +0xbf 0x30 0x3 0xd5 +0xbf 0x3c 0x3 0xd5 +0xbf 0x3f 0x3 0xd5 +0xbf 0x31 0x3 0xd5 +0xbf 0x32 0x3 0xd5 +0xbf 0x33 0x3 0xd5 +0xbf 0x35 0x3 0xd5 +0xbf 0x36 0x3 0xd5 +0xbf 0x37 0x3 0xd5 +0xbf 0x39 0x3 0xd5 +0xbf 0x3a 0x3 0xd5 +0xbf 0x3b 0x3 0xd5 +0xbf 0x3d 0x3 0xd5 +0xbf 0x3e 0x3 0xd5 +0xbf 0x3f 0x3 0xd5 + +# CHECK: isb +# CHECK: isb #12 +0xdf 0x3f 0x3 0xd5 +0xdf 0x3c 0x3 0xd5 + +# CHECK: msr spsel, #0 +# CHECK: msr daifset, #15 +# CHECK: msr daifclr, #12 +0xbf 0x40 0x0 0xd5 +0xdf 0x4f 0x3 0xd5 +0xff 0x4c 0x3 0xd5 + +# CHECK: sys #7, c5, c9, #7, x5 +# CHECK: sys #0, c15, c15, #2 +# CHECK: sysl x9, #7, c5, c9, #7 +# CHECK: sysl x1, #0, c15, c15, #2 +0xe5 0x59 0xf 0xd5 +0x5f 0xff 0x8 0xd5 +0xe9 0x59 0x2f 0xd5 +0x41 0xff 0x28 0xd5 + +# CHECK: sys #0, c7, c1, #0, xzr +# CHECK: sys #0, c7, c5, #0, xzr +# CHECK: sys #3, c7, c5, #1, x9 +0x1f 0x71 0x8 0xd5 +0x1f 0x75 0x8 0xd5 +0x29 0x75 0xb 0xd5 + +# CHECK: sys #3, c7, c4, #1, x12 +# CHECK: sys #0, c7, c6, #1, xzr +# CHECK: sys #0, c7, c6, #2, x2 +# CHECK: sys #3, c7, c10, #1, x9 +# CHECK: sys #0, c7, c10, #2, x10 +# CHECK: sys #3, c7, c11, #1, x0 +# CHECK: sys #3, c7, c14, #1, x3 +# CHECK: sys #0, c7, c14, #2, x30 +0x2c 0x74 0xb 0xd5 +0x3f 0x76 0x8 0xd5 +0x42 0x76 0x8 0xd5 +0x29 0x7a 0xb 0xd5 +0x4a 0x7a 0x8 0xd5 +0x20 0x7b 0xb 0xd5 +0x23 0x7e 0xb 0xd5 +0x5e 0x7e 0x8 0xd5 + + +# CHECK: msr teecr32_el1, x12 +# CHECK: msr osdtrrx_el1, x12 +# CHECK: msr mdccint_el1, x12 +# CHECK: msr mdscr_el1, x12 +# CHECK: msr osdtrtx_el1, x12 +# CHECK: msr dbgdtr_el0, x12 +# CHECK: msr dbgdtrtx_el0, x12 +# CHECK: msr oseccr_el1, x12 +# CHECK: msr dbgvcr32_el2, x12 +# CHECK: msr dbgbvr0_el1, x12 +# CHECK: msr dbgbvr1_el1, x12 +# CHECK: msr dbgbvr2_el1, x12 +# CHECK: msr dbgbvr3_el1, x12 +# CHECK: msr dbgbvr4_el1, x12 +# CHECK: msr dbgbvr5_el1, x12 +# CHECK: msr dbgbvr6_el1, x12 +# CHECK: msr dbgbvr7_el1, x12 +# CHECK: msr dbgbvr8_el1, x12 +# CHECK: msr dbgbvr9_el1, x12 +# CHECK: msr dbgbvr10_el1, x12 +# CHECK: msr dbgbvr11_el1, x12 +# CHECK: msr dbgbvr12_el1, x12 +# CHECK: msr dbgbvr13_el1, x12 +# CHECK: msr dbgbvr14_el1, x12 +# CHECK: msr dbgbvr15_el1, x12 +# CHECK: msr dbgbcr0_el1, x12 +# CHECK: msr dbgbcr1_el1, x12 +# CHECK: msr dbgbcr2_el1, x12 +# CHECK: msr dbgbcr3_el1, x12 +# CHECK: msr dbgbcr4_el1, x12 +# CHECK: msr dbgbcr5_el1, x12 +# CHECK: msr dbgbcr6_el1, x12 +# CHECK: msr dbgbcr7_el1, x12 +# CHECK: msr dbgbcr8_el1, x12 +# CHECK: msr dbgbcr9_el1, x12 +# CHECK: msr dbgbcr10_el1, x12 +# CHECK: msr dbgbcr11_el1, x12 +# CHECK: msr dbgbcr12_el1, x12 +# CHECK: msr dbgbcr13_el1, x12 +# CHECK: msr dbgbcr14_el1, x12 +# CHECK: msr dbgbcr15_el1, x12 +# CHECK: msr dbgwvr0_el1, x12 +# CHECK: msr dbgwvr1_el1, x12 +# CHECK: msr dbgwvr2_el1, x12 +# CHECK: msr dbgwvr3_el1, x12 +# CHECK: msr dbgwvr4_el1, x12 +# CHECK: msr dbgwvr5_el1, x12 +# CHECK: msr dbgwvr6_el1, x12 +# CHECK: msr dbgwvr7_el1, x12 +# CHECK: msr dbgwvr8_el1, x12 +# CHECK: msr dbgwvr9_el1, x12 +# CHECK: msr dbgwvr10_el1, x12 +# CHECK: msr dbgwvr11_el1, x12 +# CHECK: msr dbgwvr12_el1, x12 +# CHECK: msr dbgwvr13_el1, x12 +# CHECK: msr dbgwvr14_el1, x12 +# CHECK: msr dbgwvr15_el1, x12 +# CHECK: msr dbgwcr0_el1, x12 +# CHECK: msr dbgwcr1_el1, x12 +# CHECK: msr dbgwcr2_el1, x12 +# CHECK: msr dbgwcr3_el1, x12 +# CHECK: msr dbgwcr4_el1, x12 +# CHECK: msr dbgwcr5_el1, x12 +# CHECK: msr dbgwcr6_el1, x12 +# CHECK: msr dbgwcr7_el1, x12 +# CHECK: msr dbgwcr8_el1, x12 +# CHECK: msr dbgwcr9_el1, x12 +# CHECK: msr dbgwcr10_el1, x12 +# CHECK: msr dbgwcr11_el1, x12 +# CHECK: msr dbgwcr12_el1, x12 +# CHECK: msr dbgwcr13_el1, x12 +# CHECK: msr dbgwcr14_el1, x12 +# CHECK: msr dbgwcr15_el1, x12 +# CHECK: msr teehbr32_el1, x12 +# CHECK: msr oslar_el1, x12 +# CHECK: msr osdlr_el1, x12 +# CHECK: msr dbgprcr_el1, x12 +# CHECK: msr dbgclaimset_el1, x12 +# CHECK: msr dbgclaimclr_el1, x12 +# CHECK: msr csselr_el1, x12 +# CHECK: msr vpidr_el2, x12 +# CHECK: msr vmpidr_el2, x12 +# CHECK: msr sctlr_el1, x12 +# CHECK: msr sctlr_el2, x12 +# CHECK: msr sctlr_el3, x12 +# CHECK: msr actlr_el1, x12 +# CHECK: msr actlr_el2, x12 +# CHECK: msr actlr_el3, x12 +# CHECK: msr cpacr_el1, x12 +# CHECK: msr hcr_el2, x12 +# CHECK: msr scr_el3, x12 +# CHECK: msr mdcr_el2, x12 +# CHECK: msr sder32_el3, x12 +# CHECK: msr cptr_el2, x12 +# CHECK: msr cptr_el3, x12 +# CHECK: msr hstr_el2, x12 +# CHECK: msr hacr_el2, x12 +# CHECK: msr mdcr_el3, x12 +# CHECK: msr ttbr0_el1, x12 +# CHECK: msr ttbr0_el2, x12 +# CHECK: msr ttbr0_el3, x12 +# CHECK: msr ttbr1_el1, x12 +# CHECK: msr tcr_el1, x12 +# CHECK: msr tcr_el2, x12 +# CHECK: msr tcr_el3, x12 +# CHECK: msr vttbr_el2, x12 +# CHECK: msr vtcr_el2, x12 +# CHECK: msr dacr32_el2, x12 +# CHECK: msr spsr_el1, x12 +# CHECK: msr spsr_el2, x12 +# CHECK: msr spsr_el3, x12 +# CHECK: msr elr_el1, x12 +# CHECK: msr elr_el2, x12 +# CHECK: msr elr_el3, x12 +# CHECK: msr sp_el0, x12 +# CHECK: msr sp_el1, x12 +# CHECK: msr sp_el2, x12 +# CHECK: msr spsel, x12 +# CHECK: msr nzcv, x12 +# CHECK: msr daif, x12 +# CHECK: msr currentel, x12 +# CHECK: msr spsr_irq, x12 +# CHECK: msr spsr_abt, x12 +# CHECK: msr spsr_und, x12 +# CHECK: msr spsr_fiq, x12 +# CHECK: msr fpcr, x12 +# CHECK: msr fpsr, x12 +# CHECK: msr dspsr_el0, x12 +# CHECK: msr dlr_el0, x12 +# CHECK: msr ifsr32_el2, x12 +# CHECK: msr afsr0_el1, x12 +# CHECK: msr afsr0_el2, x12 +# CHECK: msr afsr0_el3, x12 +# CHECK: msr afsr1_el1, x12 +# CHECK: msr afsr1_el2, x12 +# CHECK: msr afsr1_el3, x12 +# CHECK: msr esr_el1, x12 +# CHECK: msr esr_el2, x12 +# CHECK: msr esr_el3, x12 +# CHECK: msr fpexc32_el2, x12 +# CHECK: msr far_el1, x12 +# CHECK: msr far_el2, x12 +# CHECK: msr far_el3, x12 +# CHECK: msr hpfar_el2, x12 +# CHECK: msr par_el1, x12 +# CHECK: msr pmcr_el0, x12 +# CHECK: msr pmcntenset_el0, x12 +# CHECK: msr pmcntenclr_el0, x12 +# CHECK: msr pmovsclr_el0, x12 +# CHECK: msr pmselr_el0, x12 +# CHECK: msr pmccntr_el0, x12 +# CHECK: msr pmxevtyper_el0, x12 +# CHECK: msr pmxevcntr_el0, x12 +# CHECK: msr pmuserenr_el0, x12 +# CHECK: msr pmintenset_el1, x12 +# CHECK: msr pmintenclr_el1, x12 +# CHECK: msr pmovsset_el0, x12 +# CHECK: msr mair_el1, x12 +# CHECK: msr mair_el2, x12 +# CHECK: msr mair_el3, x12 +# CHECK: msr amair_el1, x12 +# CHECK: msr amair_el2, x12 +# CHECK: msr amair_el3, x12 +# CHECK: msr vbar_el1, x12 +# CHECK: msr vbar_el2, x12 +# CHECK: msr vbar_el3, x12 +# CHECK: msr rmr_el1, x12 +# CHECK: msr rmr_el2, x12 +# CHECK: msr rmr_el3, x12 +# CHECK: msr tpidr_el0, x12 +# CHECK: msr tpidr_el2, x12 +# CHECK: msr tpidr_el3, x12 +# CHECK: msr tpidrro_el0, x12 +# CHECK: msr tpidr_el1, x12 +# CHECK: msr cntfrq_el0, x12 +# CHECK: msr cntvoff_el2, x12 +# CHECK: msr cntkctl_el1, x12 +# CHECK: msr cnthctl_el2, x12 +# CHECK: msr cntp_tval_el0, x12 +# CHECK: msr cnthp_tval_el2, x12 +# CHECK: msr cntps_tval_el1, x12 +# CHECK: msr cntp_ctl_el0, x12 +# CHECK: msr cnthp_ctl_el2, x12 +# CHECK: msr cntps_ctl_el1, x12 +# CHECK: msr cntp_cval_el0, x12 +# CHECK: msr cnthp_cval_el2, x12 +# CHECK: msr cntps_cval_el1, x12 +# CHECK: msr cntv_tval_el0, x12 +# CHECK: msr cntv_ctl_el0, x12 +# CHECK: msr cntv_cval_el0, x12 +# CHECK: msr pmevcntr0_el0, x12 +# CHECK: msr pmevcntr1_el0, x12 +# CHECK: msr pmevcntr2_el0, x12 +# CHECK: msr pmevcntr3_el0, x12 +# CHECK: msr pmevcntr4_el0, x12 +# CHECK: msr pmevcntr5_el0, x12 +# CHECK: msr pmevcntr6_el0, x12 +# CHECK: msr pmevcntr7_el0, x12 +# CHECK: msr pmevcntr8_el0, x12 +# CHECK: msr pmevcntr9_el0, x12 +# CHECK: msr pmevcntr10_el0, x12 +# CHECK: msr pmevcntr11_el0, x12 +# CHECK: msr pmevcntr12_el0, x12 +# CHECK: msr pmevcntr13_el0, x12 +# CHECK: msr pmevcntr14_el0, x12 +# CHECK: msr pmevcntr15_el0, x12 +# CHECK: msr pmevcntr16_el0, x12 +# CHECK: msr pmevcntr17_el0, x12 +# CHECK: msr pmevcntr18_el0, x12 +# CHECK: msr pmevcntr19_el0, x12 +# CHECK: msr pmevcntr20_el0, x12 +# CHECK: msr pmevcntr21_el0, x12 +# CHECK: msr pmevcntr22_el0, x12 +# CHECK: msr pmevcntr23_el0, x12 +# CHECK: msr pmevcntr24_el0, x12 +# CHECK: msr pmevcntr25_el0, x12 +# CHECK: msr pmevcntr26_el0, x12 +# CHECK: msr pmevcntr27_el0, x12 +# CHECK: msr pmevcntr28_el0, x12 +# CHECK: msr pmevcntr29_el0, x12 +# CHECK: msr pmevcntr30_el0, x12 +# CHECK: msr pmccfiltr_el0, x12 +# CHECK: msr pmevtyper0_el0, x12 +# CHECK: msr pmevtyper1_el0, x12 +# CHECK: msr pmevtyper2_el0, x12 +# CHECK: msr pmevtyper3_el0, x12 +# CHECK: msr pmevtyper4_el0, x12 +# CHECK: msr pmevtyper5_el0, x12 +# CHECK: msr pmevtyper6_el0, x12 +# CHECK: msr pmevtyper7_el0, x12 +# CHECK: msr pmevtyper8_el0, x12 +# CHECK: msr pmevtyper9_el0, x12 +# CHECK: msr pmevtyper10_el0, x12 +# CHECK: msr pmevtyper11_el0, x12 +# CHECK: msr pmevtyper12_el0, x12 +# CHECK: msr pmevtyper13_el0, x12 +# CHECK: msr pmevtyper14_el0, x12 +# CHECK: msr pmevtyper15_el0, x12 +# CHECK: msr pmevtyper16_el0, x12 +# CHECK: msr pmevtyper17_el0, x12 +# CHECK: msr pmevtyper18_el0, x12 +# CHECK: msr pmevtyper19_el0, x12 +# CHECK: msr pmevtyper20_el0, x12 +# CHECK: msr pmevtyper21_el0, x12 +# CHECK: msr pmevtyper22_el0, x12 +# CHECK: msr pmevtyper23_el0, x12 +# CHECK: msr pmevtyper24_el0, x12 +# CHECK: msr pmevtyper25_el0, x12 +# CHECK: msr pmevtyper26_el0, x12 +# CHECK: msr pmevtyper27_el0, x12 +# CHECK: msr pmevtyper28_el0, x12 +# CHECK: msr pmevtyper29_el0, x12 +# CHECK: msr pmevtyper30_el0, x12 +# CHECK: mrs x9, teecr32_el1 +# CHECK: mrs x9, osdtrrx_el1 +# CHECK: mrs x9, mdccsr_el0 +# CHECK: mrs x9, mdccint_el1 +# CHECK: mrs x9, mdscr_el1 +# CHECK: mrs x9, osdtrtx_el1 +# CHECK: mrs x9, dbgdtr_el0 +# CHECK: mrs x9, dbgdtrrx_el0 +# CHECK: mrs x9, oseccr_el1 +# CHECK: mrs x9, dbgvcr32_el2 +# CHECK: mrs x9, dbgbvr0_el1 +# CHECK: mrs x9, dbgbvr1_el1 +# CHECK: mrs x9, dbgbvr2_el1 +# CHECK: mrs x9, dbgbvr3_el1 +# CHECK: mrs x9, dbgbvr4_el1 +# CHECK: mrs x9, dbgbvr5_el1 +# CHECK: mrs x9, dbgbvr6_el1 +# CHECK: mrs x9, dbgbvr7_el1 +# CHECK: mrs x9, dbgbvr8_el1 +# CHECK: mrs x9, dbgbvr9_el1 +# CHECK: mrs x9, dbgbvr10_el1 +# CHECK: mrs x9, dbgbvr11_el1 +# CHECK: mrs x9, dbgbvr12_el1 +# CHECK: mrs x9, dbgbvr13_el1 +# CHECK: mrs x9, dbgbvr14_el1 +# CHECK: mrs x9, dbgbvr15_el1 +# CHECK: mrs x9, dbgbcr0_el1 +# CHECK: mrs x9, dbgbcr1_el1 +# CHECK: mrs x9, dbgbcr2_el1 +# CHECK: mrs x9, dbgbcr3_el1 +# CHECK: mrs x9, dbgbcr4_el1 +# CHECK: mrs x9, dbgbcr5_el1 +# CHECK: mrs x9, dbgbcr6_el1 +# CHECK: mrs x9, dbgbcr7_el1 +# CHECK: mrs x9, dbgbcr8_el1 +# CHECK: mrs x9, dbgbcr9_el1 +# CHECK: mrs x9, dbgbcr10_el1 +# CHECK: mrs x9, dbgbcr11_el1 +# CHECK: mrs x9, dbgbcr12_el1 +# CHECK: mrs x9, dbgbcr13_el1 +# CHECK: mrs x9, dbgbcr14_el1 +# CHECK: mrs x9, dbgbcr15_el1 +# CHECK: mrs x9, dbgwvr0_el1 +# CHECK: mrs x9, dbgwvr1_el1 +# CHECK: mrs x9, dbgwvr2_el1 +# CHECK: mrs x9, dbgwvr3_el1 +# CHECK: mrs x9, dbgwvr4_el1 +# CHECK: mrs x9, dbgwvr5_el1 +# CHECK: mrs x9, dbgwvr6_el1 +# CHECK: mrs x9, dbgwvr7_el1 +# CHECK: mrs x9, dbgwvr8_el1 +# CHECK: mrs x9, dbgwvr9_el1 +# CHECK: mrs x9, dbgwvr10_el1 +# CHECK: mrs x9, dbgwvr11_el1 +# CHECK: mrs x9, dbgwvr12_el1 +# CHECK: mrs x9, dbgwvr13_el1 +# CHECK: mrs x9, dbgwvr14_el1 +# CHECK: mrs x9, dbgwvr15_el1 +# CHECK: mrs x9, dbgwcr0_el1 +# CHECK: mrs x9, dbgwcr1_el1 +# CHECK: mrs x9, dbgwcr2_el1 +# CHECK: mrs x9, dbgwcr3_el1 +# CHECK: mrs x9, dbgwcr4_el1 +# CHECK: mrs x9, dbgwcr5_el1 +# CHECK: mrs x9, dbgwcr6_el1 +# CHECK: mrs x9, dbgwcr7_el1 +# CHECK: mrs x9, dbgwcr8_el1 +# CHECK: mrs x9, dbgwcr9_el1 +# CHECK: mrs x9, dbgwcr10_el1 +# CHECK: mrs x9, dbgwcr11_el1 +# CHECK: mrs x9, dbgwcr12_el1 +# CHECK: mrs x9, dbgwcr13_el1 +# CHECK: mrs x9, dbgwcr14_el1 +# CHECK: mrs x9, dbgwcr15_el1 +# CHECK: mrs x9, mdrar_el1 +# CHECK: mrs x9, teehbr32_el1 +# CHECK: mrs x9, oslsr_el1 +# CHECK: mrs x9, osdlr_el1 +# CHECK: mrs x9, dbgprcr_el1 +# CHECK: mrs x9, dbgclaimset_el1 +# CHECK: mrs x9, dbgclaimclr_el1 +# CHECK: mrs x9, dbgauthstatus_el1 +# CHECK: mrs x9, midr_el1 +# CHECK: mrs x9, ccsidr_el1 +# CHECK: mrs x9, csselr_el1 +# CHECK: mrs x9, vpidr_el2 +# CHECK: mrs x9, clidr_el1 +# CHECK: mrs x9, ctr_el0 +# CHECK: mrs x9, mpidr_el1 +# CHECK: mrs x9, vmpidr_el2 +# CHECK: mrs x9, revidr_el1 +# CHECK: mrs x9, aidr_el1 +# CHECK: mrs x9, dczid_el0 +# CHECK: mrs x9, id_pfr0_el1 +# CHECK: mrs x9, id_pfr1_el1 +# CHECK: mrs x9, id_dfr0_el1 +# CHECK: mrs x9, id_afr0_el1 +# CHECK: mrs x9, id_mmfr0_el1 +# CHECK: mrs x9, id_mmfr1_el1 +# CHECK: mrs x9, id_mmfr2_el1 +# CHECK: mrs x9, id_mmfr3_el1 +# CHECK: mrs x9, id_isar0_el1 +# CHECK: mrs x9, id_isar1_el1 +# CHECK: mrs x9, id_isar2_el1 +# CHECK: mrs x9, id_isar3_el1 +# CHECK: mrs x9, id_isar4_el1 +# CHECK: mrs x9, id_isar5_el1 +# CHECK: mrs x9, mvfr0_el1 +# CHECK: mrs x9, mvfr1_el1 +# CHECK: mrs x9, mvfr2_el1 +# CHECK: mrs x9, id_aa64pfr0_el1 +# CHECK: mrs x9, id_aa64pfr1_el1 +# CHECK: mrs x9, id_aa64dfr0_el1 +# CHECK: mrs x9, id_aa64dfr1_el1 +# CHECK: mrs x9, id_aa64afr0_el1 +# CHECK: mrs x9, id_aa64afr1_el1 +# CHECK: mrs x9, id_aa64isar0_el1 +# CHECK: mrs x9, id_aa64isar1_el1 +# CHECK: mrs x9, id_aa64mmfr0_el1 +# CHECK: mrs x9, id_aa64mmfr1_el1 +# CHECK: mrs x9, sctlr_el1 +# CHECK: mrs x9, sctlr_el2 +# CHECK: mrs x9, sctlr_el3 +# CHECK: mrs x9, actlr_el1 +# CHECK: mrs x9, actlr_el2 +# CHECK: mrs x9, actlr_el3 +# CHECK: mrs x9, cpacr_el1 +# CHECK: mrs x9, hcr_el2 +# CHECK: mrs x9, scr_el3 +# CHECK: mrs x9, mdcr_el2 +# CHECK: mrs x9, sder32_el3 +# CHECK: mrs x9, cptr_el2 +# CHECK: mrs x9, cptr_el3 +# CHECK: mrs x9, hstr_el2 +# CHECK: mrs x9, hacr_el2 +# CHECK: mrs x9, mdcr_el3 +# CHECK: mrs x9, ttbr0_el1 +# CHECK: mrs x9, ttbr0_el2 +# CHECK: mrs x9, ttbr0_el3 +# CHECK: mrs x9, ttbr1_el1 +# CHECK: mrs x9, tcr_el1 +# CHECK: mrs x9, tcr_el2 +# CHECK: mrs x9, tcr_el3 +# CHECK: mrs x9, vttbr_el2 +# CHECK: mrs x9, vtcr_el2 +# CHECK: mrs x9, dacr32_el2 +# CHECK: mrs x9, spsr_el1 +# CHECK: mrs x9, spsr_el2 +# CHECK: mrs x9, spsr_el3 +# CHECK: mrs x9, elr_el1 +# CHECK: mrs x9, elr_el2 +# CHECK: mrs x9, elr_el3 +# CHECK: mrs x9, sp_el0 +# CHECK: mrs x9, sp_el1 +# CHECK: mrs x9, sp_el2 +# CHECK: mrs x9, spsel +# CHECK: mrs x9, nzcv +# CHECK: mrs x9, daif +# CHECK: mrs x9, currentel +# CHECK: mrs x9, spsr_irq +# CHECK: mrs x9, spsr_abt +# CHECK: mrs x9, spsr_und +# CHECK: mrs x9, spsr_fiq +# CHECK: mrs x9, fpcr +# CHECK: mrs x9, fpsr +# CHECK: mrs x9, dspsr_el0 +# CHECK: mrs x9, dlr_el0 +# CHECK: mrs x9, ifsr32_el2 +# CHECK: mrs x9, afsr0_el1 +# CHECK: mrs x9, afsr0_el2 +# CHECK: mrs x9, afsr0_el3 +# CHECK: mrs x9, afsr1_el1 +# CHECK: mrs x9, afsr1_el2 +# CHECK: mrs x9, afsr1_el3 +# CHECK: mrs x9, esr_el1 +# CHECK: mrs x9, esr_el2 +# CHECK: mrs x9, esr_el3 +# CHECK: mrs x9, fpexc32_el2 +# CHECK: mrs x9, far_el1 +# CHECK: mrs x9, far_el2 +# CHECK: mrs x9, far_el3 +# CHECK: mrs x9, hpfar_el2 +# CHECK: mrs x9, par_el1 +# CHECK: mrs x9, pmcr_el0 +# CHECK: mrs x9, pmcntenset_el0 +# CHECK: mrs x9, pmcntenclr_el0 +# CHECK: mrs x9, pmovsclr_el0 +# CHECK: mrs x9, pmselr_el0 +# CHECK: mrs x9, pmceid0_el0 +# CHECK: mrs x9, pmceid1_el0 +# CHECK: mrs x9, pmccntr_el0 +# CHECK: mrs x9, pmxevtyper_el0 +# CHECK: mrs x9, pmxevcntr_el0 +# CHECK: mrs x9, pmuserenr_el0 +# CHECK: mrs x9, pmintenset_el1 +# CHECK: mrs x9, pmintenclr_el1 +# CHECK: mrs x9, pmovsset_el0 +# CHECK: mrs x9, mair_el1 +# CHECK: mrs x9, mair_el2 +# CHECK: mrs x9, mair_el3 +# CHECK: mrs x9, amair_el1 +# CHECK: mrs x9, amair_el2 +# CHECK: mrs x9, amair_el3 +# CHECK: mrs x9, vbar_el1 +# CHECK: mrs x9, vbar_el2 +# CHECK: mrs x9, vbar_el3 +# CHECK: mrs x9, rvbar_el1 +# CHECK: mrs x9, rvbar_el2 +# CHECK: mrs x9, rvbar_el3 +# CHECK: mrs x9, rmr_el1 +# CHECK: mrs x9, rmr_el2 +# CHECK: mrs x9, rmr_el3 +# CHECK: mrs x9, isr_el1 +# CHECK: mrs x9, contextidr_el1 +# CHECK: mrs x9, tpidr_el0 +# CHECK: mrs x9, tpidr_el2 +# CHECK: mrs x9, tpidr_el3 +# CHECK: mrs x9, tpidrro_el0 +# CHECK: mrs x9, tpidr_el1 +# CHECK: mrs x9, cntfrq_el0 +# CHECK: mrs x9, cntpct_el0 +# CHECK: mrs x9, cntvct_el0 +# CHECK: mrs x9, cntvoff_el2 +# CHECK: mrs x9, cntkctl_el1 +# CHECK: mrs x9, cnthctl_el2 +# CHECK: mrs x9, cntp_tval_el0 +# CHECK: mrs x9, cnthp_tval_el2 +# CHECK: mrs x9, cntps_tval_el1 +# CHECK: mrs x9, cntp_ctl_el0 +# CHECK: mrs x9, cnthp_ctl_el2 +# CHECK: mrs x9, cntps_ctl_el1 +# CHECK: mrs x9, cntp_cval_el0 +# CHECK: mrs x9, cnthp_cval_el2 +# CHECK: mrs x9, cntps_cval_el1 +# CHECK: mrs x9, cntv_tval_el0 +# CHECK: mrs x9, cntv_ctl_el0 +# CHECK: mrs x9, cntv_cval_el0 +# CHECK: mrs x9, pmevcntr0_el0 +# CHECK: mrs x9, pmevcntr1_el0 +# CHECK: mrs x9, pmevcntr2_el0 +# CHECK: mrs x9, pmevcntr3_el0 +# CHECK: mrs x9, pmevcntr4_el0 +# CHECK: mrs x9, pmevcntr5_el0 +# CHECK: mrs x9, pmevcntr6_el0 +# CHECK: mrs x9, pmevcntr7_el0 +# CHECK: mrs x9, pmevcntr8_el0 +# CHECK: mrs x9, pmevcntr9_el0 +# CHECK: mrs x9, pmevcntr10_el0 +# CHECK: mrs x9, pmevcntr11_el0 +# CHECK: mrs x9, pmevcntr12_el0 +# CHECK: mrs x9, pmevcntr13_el0 +# CHECK: mrs x9, pmevcntr14_el0 +# CHECK: mrs x9, pmevcntr15_el0 +# CHECK: mrs x9, pmevcntr16_el0 +# CHECK: mrs x9, pmevcntr17_el0 +# CHECK: mrs x9, pmevcntr18_el0 +# CHECK: mrs x9, pmevcntr19_el0 +# CHECK: mrs x9, pmevcntr20_el0 +# CHECK: mrs x9, pmevcntr21_el0 +# CHECK: mrs x9, pmevcntr22_el0 +# CHECK: mrs x9, pmevcntr23_el0 +# CHECK: mrs x9, pmevcntr24_el0 +# CHECK: mrs x9, pmevcntr25_el0 +# CHECK: mrs x9, pmevcntr26_el0 +# CHECK: mrs x9, pmevcntr27_el0 +# CHECK: mrs x9, pmevcntr28_el0 +# CHECK: mrs x9, pmevcntr29_el0 +# CHECK: mrs x9, pmevcntr30_el0 +# CHECK: mrs x9, pmccfiltr_el0 +# CHECK: mrs x9, pmevtyper0_el0 +# CHECK: mrs x9, pmevtyper1_el0 +# CHECK: mrs x9, pmevtyper2_el0 +# CHECK: mrs x9, pmevtyper3_el0 +# CHECK: mrs x9, pmevtyper4_el0 +# CHECK: mrs x9, pmevtyper5_el0 +# CHECK: mrs x9, pmevtyper6_el0 +# CHECK: mrs x9, pmevtyper7_el0 +# CHECK: mrs x9, pmevtyper8_el0 +# CHECK: mrs x9, pmevtyper9_el0 +# CHECK: mrs x9, pmevtyper10_el0 +# CHECK: mrs x9, pmevtyper11_el0 +# CHECK: mrs x9, pmevtyper12_el0 +# CHECK: mrs x9, pmevtyper13_el0 +# CHECK: mrs x9, pmevtyper14_el0 +# CHECK: mrs x9, pmevtyper15_el0 +# CHECK: mrs x9, pmevtyper16_el0 +# CHECK: mrs x9, pmevtyper17_el0 +# CHECK: mrs x9, pmevtyper18_el0 +# CHECK: mrs x9, pmevtyper19_el0 +# CHECK: mrs x9, pmevtyper20_el0 +# CHECK: mrs x9, pmevtyper21_el0 +# CHECK: mrs x9, pmevtyper22_el0 +# CHECK: mrs x9, pmevtyper23_el0 +# CHECK: mrs x9, pmevtyper24_el0 +# CHECK: mrs x9, pmevtyper25_el0 +# CHECK: mrs x9, pmevtyper26_el0 +# CHECK: mrs x9, pmevtyper27_el0 +# CHECK: mrs x9, pmevtyper28_el0 +# CHECK: mrs x9, pmevtyper29_el0 +# CHECK: mrs x9, pmevtyper30_el0 + +0xc 0x0 0x12 0xd5 +0x4c 0x0 0x10 0xd5 +0xc 0x2 0x10 0xd5 +0x4c 0x2 0x10 0xd5 +0x4c 0x3 0x10 0xd5 +0xc 0x4 0x13 0xd5 +0xc 0x5 0x13 0xd5 +0x4c 0x6 0x10 0xd5 +0xc 0x7 0x14 0xd5 +0x8c 0x0 0x10 0xd5 +0x8c 0x1 0x10 0xd5 +0x8c 0x2 0x10 0xd5 +0x8c 0x3 0x10 0xd5 +0x8c 0x4 0x10 0xd5 +0x8c 0x5 0x10 0xd5 +0x8c 0x6 0x10 0xd5 +0x8c 0x7 0x10 0xd5 +0x8c 0x8 0x10 0xd5 +0x8c 0x9 0x10 0xd5 +0x8c 0xa 0x10 0xd5 +0x8c 0xb 0x10 0xd5 +0x8c 0xc 0x10 0xd5 +0x8c 0xd 0x10 0xd5 +0x8c 0xe 0x10 0xd5 +0x8c 0xf 0x10 0xd5 +0xac 0x0 0x10 0xd5 +0xac 0x1 0x10 0xd5 +0xac 0x2 0x10 0xd5 +0xac 0x3 0x10 0xd5 +0xac 0x4 0x10 0xd5 +0xac 0x5 0x10 0xd5 +0xac 0x6 0x10 0xd5 +0xac 0x7 0x10 0xd5 +0xac 0x8 0x10 0xd5 +0xac 0x9 0x10 0xd5 +0xac 0xa 0x10 0xd5 +0xac 0xb 0x10 0xd5 +0xac 0xc 0x10 0xd5 +0xac 0xd 0x10 0xd5 +0xac 0xe 0x10 0xd5 +0xac 0xf 0x10 0xd5 +0xcc 0x0 0x10 0xd5 +0xcc 0x1 0x10 0xd5 +0xcc 0x2 0x10 0xd5 +0xcc 0x3 0x10 0xd5 +0xcc 0x4 0x10 0xd5 +0xcc 0x5 0x10 0xd5 +0xcc 0x6 0x10 0xd5 +0xcc 0x7 0x10 0xd5 +0xcc 0x8 0x10 0xd5 +0xcc 0x9 0x10 0xd5 +0xcc 0xa 0x10 0xd5 +0xcc 0xb 0x10 0xd5 +0xcc 0xc 0x10 0xd5 +0xcc 0xd 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0xd5 +0x29 0x9e 0x38 0xd5 +0x49 0x9e 0x38 0xd5 +0x69 0x9e 0x3b 0xd5 +0x9 0xa2 0x38 0xd5 +0x9 0xa2 0x3c 0xd5 +0x9 0xa2 0x3e 0xd5 +0x9 0xa3 0x38 0xd5 +0x9 0xa3 0x3c 0xd5 +0x9 0xa3 0x3e 0xd5 +0x9 0xc0 0x38 0xd5 +0x9 0xc0 0x3c 0xd5 +0x9 0xc0 0x3e 0xd5 +0x29 0xc0 0x38 0xd5 +0x29 0xc0 0x3c 0xd5 +0x29 0xc0 0x3e 0xd5 +0x49 0xc0 0x38 0xd5 +0x49 0xc0 0x3c 0xd5 +0x49 0xc0 0x3e 0xd5 +0x9 0xc1 0x38 0xd5 +0x29 0xd0 0x38 0xd5 +0x49 0xd0 0x3b 0xd5 +0x49 0xd0 0x3c 0xd5 +0x49 0xd0 0x3e 0xd5 +0x69 0xd0 0x3b 0xd5 +0x89 0xd0 0x38 0xd5 +0x9 0xe0 0x3b 0xd5 +0x29 0xe0 0x3b 0xd5 +0x49 0xe0 0x3b 0xd5 +0x69 0xe0 0x3c 0xd5 +0x9 0xe1 0x38 0xd5 +0x9 0xe1 0x3c 0xd5 +0x9 0xe2 0x3b 0xd5 +0x9 0xe2 0x3c 0xd5 +0x9 0xe2 0x3f 0xd5 +0x29 0xe2 0x3b 0xd5 +0x29 0xe2 0x3c 0xd5 +0x29 0xe2 0x3f 0xd5 +0x49 0xe2 0x3b 0xd5 +0x49 0xe2 0x3c 0xd5 +0x49 0xe2 0x3f 0xd5 +0x9 0xe3 0x3b 0xd5 +0x29 0xe3 0x3b 0xd5 +0x49 0xe3 0x3b 0xd5 +0x9 0xe8 0x3b 0xd5 +0x29 0xe8 0x3b 0xd5 +0x49 0xe8 0x3b 0xd5 +0x69 0xe8 0x3b 0xd5 +0x89 0xe8 0x3b 0xd5 +0xa9 0xe8 0x3b 0xd5 +0xc9 0xe8 0x3b 0xd5 +0xe9 0xe8 0x3b 0xd5 +0x9 0xe9 0x3b 0xd5 +0x29 0xe9 0x3b 0xd5 +0x49 0xe9 0x3b 0xd5 +0x69 0xe9 0x3b 0xd5 +0x89 0xe9 0x3b 0xd5 +0xa9 0xe9 0x3b 0xd5 +0xc9 0xe9 0x3b 0xd5 +0xe9 0xe9 0x3b 0xd5 +0x9 0xea 0x3b 0xd5 +0x29 0xea 0x3b 0xd5 +0x49 0xea 0x3b 0xd5 +0x69 0xea 0x3b 0xd5 +0x89 0xea 0x3b 0xd5 +0xa9 0xea 0x3b 0xd5 +0xc9 0xea 0x3b 0xd5 +0xe9 0xea 0x3b 0xd5 +0x9 0xeb 0x3b 0xd5 +0x29 0xeb 0x3b 0xd5 +0x49 0xeb 0x3b 0xd5 +0x69 0xeb 0x3b 0xd5 +0x89 0xeb 0x3b 0xd5 +0xa9 0xeb 0x3b 0xd5 +0xc9 0xeb 0x3b 0xd5 +0xe9 0xef 0x3b 0xd5 +0x9 0xec 0x3b 0xd5 +0x29 0xec 0x3b 0xd5 +0x49 0xec 0x3b 0xd5 +0x69 0xec 0x3b 0xd5 +0x89 0xec 0x3b 0xd5 +0xa9 0xec 0x3b 0xd5 +0xc9 0xec 0x3b 0xd5 +0xe9 0xec 0x3b 0xd5 +0x9 0xed 0x3b 0xd5 +0x29 0xed 0x3b 0xd5 +0x49 0xed 0x3b 0xd5 +0x69 0xed 0x3b 0xd5 +0x89 0xed 0x3b 0xd5 +0xa9 0xed 0x3b 0xd5 +0xc9 0xed 0x3b 0xd5 +0xe9 0xed 0x3b 0xd5 +0x9 0xee 0x3b 0xd5 +0x29 0xee 0x3b 0xd5 +0x49 0xee 0x3b 0xd5 +0x69 0xee 0x3b 0xd5 +0x89 0xee 0x3b 0xd5 +0xa9 0xee 0x3b 0xd5 +0xc9 0xee 0x3b 0xd5 +0xe9 0xee 0x3b 0xd5 +0x9 0xef 0x3b 0xd5 +0x29 0xef 0x3b 0xd5 +0x49 0xef 0x3b 0xd5 +0x69 0xef 0x3b 0xd5 +0x89 0xef 0x3b 0xd5 +0xa9 0xef 0x3b 0xd5 +0xc9 0xef 0x3b 0xd5 + +# CHECK: mrs x12, s3_7_c15_c1_5 +# CHECK: mrs x13, s3_2_c11_c15_7 +# CHECK: msr s3_0_c15_c0_0, x12 +# CHECK: msr s3_7_c11_c13_7, x5 +0xac 0xf1 0x3f 0xd5 +0xed 0xbf 0x3a 0xd5 +0x0c 0xf0 0x18 0xd5 +0xe5 0xbd 0x1f 0xd5 + +#------------------------------------------------------------------------------ +# Test and branch (immediate) +#------------------------------------------------------------------------------ + +# CHECK: tbz x12, #62, #0 +# CHECK: tbz x12, #62, #4 +# CHECK: tbz x12, #62, #-32768 +# CHECK: tbnz x12, #60, #32764 +0x0c 0x00 0xf0 0xb6 +0x2c 0x00 0xf0 0xb6 +0x0c 0x00 0xf4 0xb6 +0xec 0xff 0xe3 0xb7 + +#------------------------------------------------------------------------------ +# Unconditional branch (immediate) +#------------------------------------------------------------------------------ + +# CHECK: b #4 +# CHECK: b #-4 +# CHECK: b #134217724 +0x01 0x00 0x00 0x14 +0xff 0xff 0xff 0x17 +0xff 0xff 0xff 0x15 + +#------------------------------------------------------------------------------ +# Unconditional branch (register) +#------------------------------------------------------------------------------ + +# CHECK: br x20 +# CHECK: blr xzr +# CHECK: ret x10 +0x80 0x2 0x1f 0xd6 +0xe0 0x3 0x3f 0xd6 +0x40 0x1 0x5f 0xd6 + +# CHECK: ret +# CHECK: eret +# CHECK: drps +0xc0 0x3 0x5f 0xd6 +0xe0 0x3 0x9f 0xd6 +0xe0 0x3 0xbf 0xd6 + diff --git a/test/MC/Disassembler/AArch64/basic-a64-undefined.txt b/test/MC/Disassembler/AArch64/basic-a64-undefined.txt new file mode 100644 index 0000000..a17579c --- /dev/null +++ b/test/MC/Disassembler/AArch64/basic-a64-undefined.txt @@ -0,0 +1,43 @@ +# These spawn another process so they're rather expensive. Not many. + +# Instructions notionally in the add/sub (extended register) sheet, but with +# invalid shift amount or "opt" field. +# RUN: echo "0x00 0x10 0xa0 0x0b" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s +# RUN: echo "0x00 0x10 0x60 0x0b" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s +# RUN: echo "0x00 0x14 0x20 0x0b" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s + +# Instructions notionally in the add/sub (immediate) sheet, but with +# invalid "shift" field. +# RUN: echo "0xdf 0x3 0x80 0x91" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s +# RUN: echo "0xed 0x8e 0xc4 0x31" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s +# RUN: echo "0x62 0xfc 0xbf 0x11" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s +# RUN: echo "0x3 0xff 0xff 0x91" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s + +# Instructions notionally in the load/store (unsigned immediate) sheet. +# Only unallocated (int-register) variants are: opc=0b11, size=0b10, 0b11 +# RUN: echo "0xd7 0xfc 0xff 0xb9" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s +# RUN: echo "0xd7 0xfc 0xcf 0xf9" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s + +# Instructions notionally in the floating-point <-> fixed-point conversion +# Scale field is 64-<imm> and <imm> should be 1-32 for a 32-bit int register. +# RUN: echo "0x23 0x01 0x18 0x1e" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s +# RUN: echo "0x23 0x25 0x42 0x1e" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s + +# Instructions notionally in the logical (shifted register) sheet, but with out +# of range shift: w-registers can only have 0-31. +# RUN: echo "0x00 0x80 0x00 0x0a" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s + +# Instructions notionally in the move wide (immediate) sheet, but with out +# of range shift: w-registers can only have 0 or 16. +# RUN: echo "0x00 0x00 0xc0 0x12" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s +# RUN: echo "0x12 0x34 0xe0 0x52" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s + +# Data-processing instructions are undefined when S=1 and for the 0b0000111 value in opcode:sf +# RUN: echo "0x00 0x00 0xc0 0x5f" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s +# RUN: echo "0x56 0x0c 0xc0 0x5a" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s + +# Data-processing instructions (2 source) are undefined for a value of 0001xx:0:x or 0011xx:0:x for opcode:S:sf +# RUN: echo "0x00 0x30 0xc1 0x1a" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s +# RUN: echo "0x00 0x10 0xc1 0x1a" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s + +# CHECK: invalid instruction encoding diff --git a/test/MC/Disassembler/AArch64/basic-a64-unpredictable.txt b/test/MC/Disassembler/AArch64/basic-a64-unpredictable.txt new file mode 100644 index 0000000..adb8f75 --- /dev/null +++ b/test/MC/Disassembler/AArch64/basic-a64-unpredictable.txt @@ -0,0 +1,96 @@ +# RUN: llvm-mc -triple=aarch64 -disassemble < %s 2>&1 | FileCheck %s + +#------------------------------------------------------------------------------ +# Load-store exclusive +#------------------------------------------------------------------------------ + +#ldxp x14, x14, [sp] +0xee 0x3b 0x7f 0xc8 +#CHECK: warning: potentially undefined instruction encoding +#CHECK-NEXT: 0xee 0x3b 0x7f 0xc8 + +#ldaxp w19, w19, [x1] +0x33 0xcc 0x7f 0x88 +#CHECK: warning: potentially undefined instruction encoding +#CHECK-NEXT: 0x33 0xcc 0x7f 0x88 + +#------------------------------------------------------------------------------ +# Load-store register (immediate post-indexed) +#------------------------------------------------------------------------------ + +0x63 0x44 0x40 0xf8 +#CHECK: warning: potentially undefined instruction encoding +#CHECK-NEXT: 0x63 0x44 0x40 0xf8 + +0x42 0x14 0xc0 0x38 +#CHECK: warning: potentially undefined instruction encoding +#CHECK-NEXT: 0x42 0x14 0xc0 0x38 + +#------------------------------------------------------------------------------ +# Load-store register (immediate pre-indexed) +#------------------------------------------------------------------------------ + +0x63 0x4c 0x40 0xf8 +#CHECK: warning: potentially undefined instruction encoding +#CHECK-NEXT: 0x63 0x4c 0x40 0xf8 + +0x42 0x1c 0xc0 0x38 +#CHECK: warning: potentially undefined instruction encoding +#CHECK-NEXT: 0x42 0x1c 0xc0 0x38 + +#------------------------------------------------------------------------------ +# Load-store register pair (offset) +#------------------------------------------------------------------------------ + +# Unpredictable if Rt == Rt2 on a load. + +0xe3 0x0f 0x40 0xa9 +# CHECK: warning: potentially undefined instruction encoding +# CHECK-NEXT: 0xe3 0x0f 0x40 0xa9 +# CHECK-NEXT: ^ + +0xe2 0x8b 0x41 0x69 +# CHECK: warning: potentially undefined instruction encoding +# CHECK-NEXT: 0xe2 0x8b 0x41 0x69 +# CHECK-NEXT: ^ + +0x82 0x88 0x40 0x2d +# CHECK: warning: potentially undefined instruction encoding +# CHECK-NEXT: 0x82 0x88 0x40 0x2d +# CHECK-NEXT: ^ + +#------------------------------------------------------------------------------ +# Load-store register pair (post-indexed) +#------------------------------------------------------------------------------ + +# Unpredictable if Rt == Rt2 on a load. + +0xe3 0x0f 0xc0 0xa8 +# CHECK: warning: potentially undefined instruction encoding +# CHECK-NEXT: 0xe3 0x0f 0xc0 0xa8 +# CHECK-NEXT: ^ + +0xe2 0x8b 0xc1 0x68 +# CHECK: warning: potentially undefined instruction encoding +# CHECK-NEXT: 0xe2 0x8b 0xc1 0x68 +# CHECK-NEXT: ^ + +0x82 0x88 0xc0 0x2c +# CHECK: warning: potentially undefined instruction encoding +# CHECK-NEXT: 0x82 0x88 0xc0 0x2c +# CHECK-NEXT: ^ + +# Also unpredictable if writeback clashes with either transfer register + +0x63 0x94 0xc0 0xa8 +# CHECK: warning: potentially undefined instruction encoding +# CHECK-NEXT: 0x63 0x94 0xc0 0xa8 + +0x69 0x2d 0x81 0xa8 +# CHECK: warning: potentially undefined instruction encoding +# CHECK-NEXT: 0x69 0x2d 0x81 0xa8 + +0x29 0xad 0xc0 0x28 +# CHECK: warning: potentially undefined instruction encoding +# CHECK-NEXT: 0x29 0xad 0xc0 0x28 + diff --git a/test/MC/Disassembler/AArch64/gicv3-regs.txt b/test/MC/Disassembler/AArch64/gicv3-regs.txt new file mode 100644 index 0000000..4351f64 --- /dev/null +++ b/test/MC/Disassembler/AArch64/gicv3-regs.txt @@ -0,0 +1,222 @@ +# RUN: llvm-mc -triple aarch64-none-linux-gnu -disassemble < %s | FileCheck %s + +0x8 0xcc 0x38 0xd5 +# CHECK: mrs x8, icc_iar1_el1 +0x1a 0xc8 0x38 0xd5 +# CHECK: mrs x26, icc_iar0_el1 +0x42 0xcc 0x38 0xd5 +# CHECK: mrs x2, icc_hppir1_el1 +0x51 0xc8 0x38 0xd5 +# CHECK: mrs x17, icc_hppir0_el1 +0x7d 0xcb 0x38 0xd5 +# CHECK: mrs x29, icc_rpr_el1 +0x24 0xcb 0x3c 0xd5 +# CHECK: mrs x4, ich_vtr_el2 +0x78 0xcb 0x3c 0xd5 +# CHECK: mrs x24, ich_eisr_el2 +0xa9 0xcb 0x3c 0xd5 +# CHECK: mrs x9, ich_elsr_el2 +0x78 0xcc 0x38 0xd5 +# CHECK: mrs x24, icc_bpr1_el1 +0x6e 0xc8 0x38 0xd5 +# CHECK: mrs x14, icc_bpr0_el1 +0x13 0x46 0x38 0xd5 +# CHECK: mrs x19, icc_pmr_el1 +0x97 0xcc 0x38 0xd5 +# CHECK: mrs x23, icc_ctlr_el1 +0x94 0xcc 0x3e 0xd5 +# CHECK: mrs x20, icc_ctlr_el3 +0xbc 0xcc 0x38 0xd5 +# CHECK: mrs x28, icc_sre_el1 +0xb9 0xc9 0x3c 0xd5 +# CHECK: mrs x25, icc_sre_el2 +0xa8 0xcc 0x3e 0xd5 +# CHECK: mrs x8, icc_sre_el3 +0xd6 0xcc 0x38 0xd5 +# CHECK: mrs x22, icc_igrpen0_el1 +0xe5 0xcc 0x38 0xd5 +# CHECK: mrs x5, icc_igrpen1_el1 +0xe7 0xcc 0x3e 0xd5 +# CHECK: mrs x7, icc_igrpen1_el3 +0x16 0xcd 0x38 0xd5 +# CHECK: mrs x22, icc_seien_el1 +0x84 0xc8 0x38 0xd5 +# CHECK: mrs x4, icc_ap0r0_el1 +0xab 0xc8 0x38 0xd5 +# CHECK: mrs x11, icc_ap0r1_el1 +0xdb 0xc8 0x38 0xd5 +# CHECK: mrs x27, icc_ap0r2_el1 +0xf5 0xc8 0x38 0xd5 +# CHECK: mrs x21, icc_ap0r3_el1 +0x2 0xc9 0x38 0xd5 +# CHECK: mrs x2, icc_ap1r0_el1 +0x35 0xc9 0x38 0xd5 +# CHECK: mrs x21, icc_ap1r1_el1 +0x4a 0xc9 0x38 0xd5 +# CHECK: mrs x10, icc_ap1r2_el1 +0x7b 0xc9 0x38 0xd5 +# CHECK: mrs x27, icc_ap1r3_el1 +0x14 0xc8 0x3c 0xd5 +# CHECK: mrs x20, ich_ap0r0_el2 +0x35 0xc8 0x3c 0xd5 +# CHECK: mrs x21, ich_ap0r1_el2 +0x45 0xc8 0x3c 0xd5 +# CHECK: mrs x5, ich_ap0r2_el2 +0x64 0xc8 0x3c 0xd5 +# CHECK: mrs x4, ich_ap0r3_el2 +0xf 0xc9 0x3c 0xd5 +# CHECK: mrs x15, ich_ap1r0_el2 +0x2c 0xc9 0x3c 0xd5 +# CHECK: mrs x12, ich_ap1r1_el2 +0x5b 0xc9 0x3c 0xd5 +# CHECK: mrs x27, ich_ap1r2_el2 +0x74 0xc9 0x3c 0xd5 +# CHECK: mrs x20, ich_ap1r3_el2 +0xa 0xcb 0x3c 0xd5 +# CHECK: mrs x10, ich_hcr_el2 +0x5b 0xcb 0x3c 0xd5 +# CHECK: mrs x27, ich_misr_el2 +0xe6 0xcb 0x3c 0xd5 +# CHECK: mrs x6, ich_vmcr_el2 +0x93 0xc9 0x3c 0xd5 +# CHECK: mrs x19, ich_vseir_el2 +0x3 0xcc 0x3c 0xd5 +# CHECK: mrs x3, ich_lr0_el2 +0x21 0xcc 0x3c 0xd5 +# CHECK: mrs x1, ich_lr1_el2 +0x56 0xcc 0x3c 0xd5 +# CHECK: mrs x22, ich_lr2_el2 +0x75 0xcc 0x3c 0xd5 +# CHECK: mrs x21, ich_lr3_el2 +0x86 0xcc 0x3c 0xd5 +# CHECK: mrs x6, ich_lr4_el2 +0xaa 0xcc 0x3c 0xd5 +# CHECK: mrs x10, ich_lr5_el2 +0xcb 0xcc 0x3c 0xd5 +# CHECK: mrs x11, ich_lr6_el2 +0xec 0xcc 0x3c 0xd5 +# CHECK: mrs x12, ich_lr7_el2 +0x0 0xcd 0x3c 0xd5 +# CHECK: mrs x0, ich_lr8_el2 +0x35 0xcd 0x3c 0xd5 +# CHECK: mrs x21, ich_lr9_el2 +0x4d 0xcd 0x3c 0xd5 +# CHECK: mrs x13, ich_lr10_el2 +0x7a 0xcd 0x3c 0xd5 +# CHECK: mrs x26, ich_lr11_el2 +0x81 0xcd 0x3c 0xd5 +# CHECK: mrs x1, ich_lr12_el2 +0xa8 0xcd 0x3c 0xd5 +# CHECK: mrs x8, ich_lr13_el2 +0xc2 0xcd 0x3c 0xd5 +# CHECK: mrs x2, ich_lr14_el2 +0xe8 0xcd 0x3c 0xd5 +# CHECK: mrs x8, ich_lr15_el2 +0x3b 0xcc 0x18 0xd5 +# CHECK: msr icc_eoir1_el1, x27 +0x25 0xc8 0x18 0xd5 +# CHECK: msr icc_eoir0_el1, x5 +0x2d 0xcb 0x18 0xd5 +# CHECK: msr icc_dir_el1, x13 +0xb5 0xcb 0x18 0xd5 +# CHECK: msr icc_sgi1r_el1, x21 +0xd9 0xcb 0x18 0xd5 +# CHECK: msr icc_asgi1r_el1, x25 +0xfc 0xcb 0x18 0xd5 +# CHECK: msr icc_sgi0r_el1, x28 +0x67 0xcc 0x18 0xd5 +# CHECK: msr icc_bpr1_el1, x7 +0x69 0xc8 0x18 0xd5 +# CHECK: msr icc_bpr0_el1, x9 +0x1d 0x46 0x18 0xd5 +# CHECK: msr icc_pmr_el1, x29 +0x98 0xcc 0x18 0xd5 +# CHECK: msr icc_ctlr_el1, x24 +0x80 0xcc 0x1e 0xd5 +# CHECK: msr icc_ctlr_el3, x0 +0xa2 0xcc 0x18 0xd5 +# CHECK: msr icc_sre_el1, x2 +0xa5 0xc9 0x1c 0xd5 +# CHECK: msr icc_sre_el2, x5 +0xaa 0xcc 0x1e 0xd5 +# CHECK: msr icc_sre_el3, x10 +0xd6 0xcc 0x18 0xd5 +# CHECK: msr icc_igrpen0_el1, x22 +0xeb 0xcc 0x18 0xd5 +# CHECK: msr icc_igrpen1_el1, x11 +0xe8 0xcc 0x1e 0xd5 +# CHECK: msr icc_igrpen1_el3, x8 +0x4 0xcd 0x18 0xd5 +# CHECK: msr icc_seien_el1, x4 +0x9b 0xc8 0x18 0xd5 +# CHECK: msr icc_ap0r0_el1, x27 +0xa5 0xc8 0x18 0xd5 +# CHECK: msr icc_ap0r1_el1, x5 +0xd4 0xc8 0x18 0xd5 +# CHECK: msr icc_ap0r2_el1, x20 +0xe0 0xc8 0x18 0xd5 +# CHECK: msr icc_ap0r3_el1, x0 +0x2 0xc9 0x18 0xd5 +# CHECK: msr icc_ap1r0_el1, x2 +0x3d 0xc9 0x18 0xd5 +# CHECK: msr icc_ap1r1_el1, x29 +0x57 0xc9 0x18 0xd5 +# CHECK: msr icc_ap1r2_el1, x23 +0x6b 0xc9 0x18 0xd5 +# CHECK: msr icc_ap1r3_el1, x11 +0x2 0xc8 0x1c 0xd5 +# CHECK: msr ich_ap0r0_el2, x2 +0x3b 0xc8 0x1c 0xd5 +# CHECK: msr ich_ap0r1_el2, x27 +0x47 0xc8 0x1c 0xd5 +# CHECK: msr ich_ap0r2_el2, x7 +0x61 0xc8 0x1c 0xd5 +# CHECK: msr ich_ap0r3_el2, x1 +0x7 0xc9 0x1c 0xd5 +# CHECK: msr ich_ap1r0_el2, x7 +0x2c 0xc9 0x1c 0xd5 +# CHECK: msr ich_ap1r1_el2, x12 +0x4e 0xc9 0x1c 0xd5 +# CHECK: msr ich_ap1r2_el2, x14 +0x6d 0xc9 0x1c 0xd5 +# CHECK: msr ich_ap1r3_el2, x13 +0x1 0xcb 0x1c 0xd5 +# CHECK: msr ich_hcr_el2, x1 +0x4a 0xcb 0x1c 0xd5 +# CHECK: msr ich_misr_el2, x10 +0xf8 0xcb 0x1c 0xd5 +# CHECK: msr ich_vmcr_el2, x24 +0x9d 0xc9 0x1c 0xd5 +# CHECK: msr ich_vseir_el2, x29 +0x1a 0xcc 0x1c 0xd5 +# CHECK: msr ich_lr0_el2, x26 +0x29 0xcc 0x1c 0xd5 +# CHECK: msr ich_lr1_el2, x9 +0x52 0xcc 0x1c 0xd5 +# CHECK: msr ich_lr2_el2, x18 +0x7a 0xcc 0x1c 0xd5 +# CHECK: msr ich_lr3_el2, x26 +0x96 0xcc 0x1c 0xd5 +# CHECK: msr ich_lr4_el2, x22 +0xba 0xcc 0x1c 0xd5 +# CHECK: msr ich_lr5_el2, x26 +0xdb 0xcc 0x1c 0xd5 +# CHECK: msr ich_lr6_el2, x27 +0xe8 0xcc 0x1c 0xd5 +# CHECK: msr ich_lr7_el2, x8 +0x11 0xcd 0x1c 0xd5 +# CHECK: msr ich_lr8_el2, x17 +0x33 0xcd 0x1c 0xd5 +# CHECK: msr ich_lr9_el2, x19 +0x51 0xcd 0x1c 0xd5 +# CHECK: msr ich_lr10_el2, x17 +0x65 0xcd 0x1c 0xd5 +# CHECK: msr ich_lr11_el2, x5 +0x9d 0xcd 0x1c 0xd5 +# CHECK: msr ich_lr12_el2, x29 +0xa2 0xcd 0x1c 0xd5 +# CHECK: msr ich_lr13_el2, x2 +0xcd 0xcd 0x1c 0xd5 +# CHECK: msr ich_lr14_el2, x13 +0xfb 0xcd 0x1c 0xd5 +# CHECK: msr ich_lr15_el2, x27 diff --git a/test/MC/Disassembler/AArch64/ldp-offset-predictable.txt b/test/MC/Disassembler/AArch64/ldp-offset-predictable.txt new file mode 100644 index 0000000..7ff495f --- /dev/null +++ b/test/MC/Disassembler/AArch64/ldp-offset-predictable.txt @@ -0,0 +1,7 @@ +# RUN: llvm-mc -triple=aarch64 -disassemble < %s 2>&1 | FileCheck %s + +# Stores are OK. +0xe0 0x83 0x00 0xa9 +# CHECK-NOT: potentially undefined instruction encoding +# CHECK: stp x0, x0, [sp, #8] + diff --git a/test/MC/Disassembler/AArch64/ldp-postind.predictable.txt b/test/MC/Disassembler/AArch64/ldp-postind.predictable.txt new file mode 100644 index 0000000..775660b --- /dev/null +++ b/test/MC/Disassembler/AArch64/ldp-postind.predictable.txt @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple=aarch64 -disassemble < %s 2>&1 | FileCheck %s + +# None of these instructions should be classified as unpredictable: + +# CHECK-NOT: potentially undefined instruction encoding + +# Stores from duplicated registers should be fine. +0xe3 0x0f 0x80 0xa8 +# CHECK: stp x3, x3, [sp], #0 + +# d5 != x5 so "ldp d5, d6, [x5], #24" is fine. +0xa5 0x98 0xc1 0x6c +# CHECK: ldp d5, d6, [x5], #24 + +# xzr != sp so "stp xzr, xzr, [sp], #8" is fine. +0xff 0xff 0x80 0xa8 +# CHECK: stp xzr, xzr, [sp], #8 diff --git a/test/MC/Disassembler/AArch64/ldp-preind.predictable.txt b/test/MC/Disassembler/AArch64/ldp-preind.predictable.txt new file mode 100644 index 0000000..48ea817 --- /dev/null +++ b/test/MC/Disassembler/AArch64/ldp-preind.predictable.txt @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple=aarch64 -disassemble < %s 2>&1 | FileCheck %s + +# None of these instructions should be classified as unpredictable: + +# CHECK-NOT: potentially undefined instruction encoding + +# Stores from duplicated registers should be fine. +0xe3 0x0f 0x80 0xa9 +# CHECK: stp x3, x3, [sp, #0]! + +# d5 != x5 so "ldp d5, d6, [x5, #24]!" is fine. +0xa5 0x98 0xc1 0x6d +# CHECK: ldp d5, d6, [x5, #24]! + +# xzr != sp so "stp xzr, xzr, [sp, #8]!" is fine. +0xff 0xff 0x80 0xa9 +# CHECK: stp xzr, xzr, [sp, #8]! diff --git a/test/MC/Disassembler/AArch64/lit.local.cfg b/test/MC/Disassembler/AArch64/lit.local.cfg new file mode 100644 index 0000000..f9df30e --- /dev/null +++ b/test/MC/Disassembler/AArch64/lit.local.cfg @@ -0,0 +1,6 @@ +config.suffixes = ['.txt'] + +targets = set(config.root.targets_to_build.split()) +if not 'AArch64' in targets: + config.unsupported = True + diff --git a/test/MC/Disassembler/AArch64/trace-regs.txt b/test/MC/Disassembler/AArch64/trace-regs.txt new file mode 100644 index 0000000..10c5937 --- /dev/null +++ b/test/MC/Disassembler/AArch64/trace-regs.txt @@ -0,0 +1,736 @@ +# RUN: llvm-mc -triple aarch64-none-linux-gnu -disassemble < %s | FileCheck %s + +0x8 0x3 0x31 0xd5 +# CHECK: mrs x8, trcstatr +0xc9 0x0 0x31 0xd5 +# CHECK: mrs x9, trcidr8 +0xcb 0x1 0x31 0xd5 +# CHECK: mrs x11, trcidr9 +0xd9 0x2 0x31 0xd5 +# CHECK: mrs x25, trcidr10 +0xc7 0x3 0x31 0xd5 +# CHECK: mrs x7, trcidr11 +0xc7 0x4 0x31 0xd5 +# CHECK: mrs x7, trcidr12 +0xc6 0x5 0x31 0xd5 +# CHECK: mrs x6, trcidr13 +0xfb 0x8 0x31 0xd5 +# CHECK: mrs x27, trcidr0 +0xfd 0x9 0x31 0xd5 +# CHECK: mrs x29, trcidr1 +0xe4 0xa 0x31 0xd5 +# CHECK: mrs x4, trcidr2 +0xe8 0xb 0x31 0xd5 +# CHECK: mrs x8, trcidr3 +0xef 0xc 0x31 0xd5 +# CHECK: mrs x15, trcidr4 +0xf4 0xd 0x31 0xd5 +# CHECK: mrs x20, trcidr5 +0xe6 0xe 0x31 0xd5 +# CHECK: mrs x6, trcidr6 +0xe6 0xf 0x31 0xd5 +# CHECK: mrs x6, trcidr7 +0x98 0x11 0x31 0xd5 +# CHECK: mrs x24, trcoslsr +0x92 0x15 0x31 0xd5 +# CHECK: mrs x18, trcpdsr +0xdc 0x7a 0x31 0xd5 +# CHECK: mrs x28, trcdevaff0 +0xc5 0x7b 0x31 0xd5 +# CHECK: mrs x5, trcdevaff1 +0xc5 0x7d 0x31 0xd5 +# CHECK: mrs x5, trclsr +0xcb 0x7e 0x31 0xd5 +# CHECK: mrs x11, trcauthstatus +0xcd 0x7f 0x31 0xd5 +# CHECK: mrs x13, trcdevarch +0xf2 0x72 0x31 0xd5 +# CHECK: mrs x18, trcdevid +0xf6 0x73 0x31 0xd5 +# CHECK: mrs x22, trcdevtype +0xee 0x74 0x31 0xd5 +# CHECK: mrs x14, trcpidr4 +0xe5 0x75 0x31 0xd5 +# CHECK: mrs x5, trcpidr5 +0xe5 0x76 0x31 0xd5 +# CHECK: mrs x5, trcpidr6 +0xe9 0x77 0x31 0xd5 +# CHECK: mrs x9, trcpidr7 +0xef 0x78 0x31 0xd5 +# CHECK: mrs x15, trcpidr0 +0xe6 0x79 0x31 0xd5 +# CHECK: mrs x6, trcpidr1 +0xeb 0x7a 0x31 0xd5 +# CHECK: mrs x11, trcpidr2 +0xf4 0x7b 0x31 0xd5 +# CHECK: mrs x20, trcpidr3 +0xf1 0x7c 0x31 0xd5 +# CHECK: mrs x17, trccidr0 +0xe2 0x7d 0x31 0xd5 +# CHECK: mrs x2, trccidr1 +0xf4 0x7e 0x31 0xd5 +# CHECK: mrs x20, trccidr2 +0xe4 0x7f 0x31 0xd5 +# CHECK: mrs x4, trccidr3 +0xb 0x1 0x31 0xd5 +# CHECK: mrs x11, trcprgctlr +0x17 0x2 0x31 0xd5 +# CHECK: mrs x23, trcprocselr +0xd 0x4 0x31 0xd5 +# CHECK: mrs x13, trcconfigr +0x17 0x6 0x31 0xd5 +# CHECK: mrs x23, trcauxctlr +0x9 0x8 0x31 0xd5 +# CHECK: mrs x9, trceventctl0r +0x10 0x9 0x31 0xd5 +# CHECK: mrs x16, trceventctl1r +0x4 0xb 0x31 0xd5 +# CHECK: mrs x4, trcstallctlr +0xe 0xc 0x31 0xd5 +# CHECK: mrs x14, trctsctlr +0x18 0xd 0x31 0xd5 +# CHECK: mrs x24, trcsyncpr +0x1c 0xe 0x31 0xd5 +# CHECK: mrs x28, trcccctlr +0xf 0xf 0x31 0xd5 +# CHECK: mrs x15, trcbbctlr +0x21 0x0 0x31 0xd5 +# CHECK: mrs x1, trctraceidr +0x34 0x1 0x31 0xd5 +# CHECK: mrs x20, trcqctlr +0x42 0x0 0x31 0xd5 +# CHECK: mrs x2, trcvictlr +0x4c 0x1 0x31 0xd5 +# CHECK: mrs x12, trcviiectlr +0x50 0x2 0x31 0xd5 +# CHECK: mrs x16, trcvissctlr +0x48 0x3 0x31 0xd5 +# CHECK: mrs x8, trcvipcssctlr +0x5b 0x8 0x31 0xd5 +# CHECK: mrs x27, trcvdctlr +0x49 0x9 0x31 0xd5 +# CHECK: mrs x9, trcvdsacctlr +0x40 0xa 0x31 0xd5 +# CHECK: mrs x0, trcvdarcctlr +0x8d 0x0 0x31 0xd5 +# CHECK: mrs x13, trcseqevr0 +0x8b 0x1 0x31 0xd5 +# CHECK: mrs x11, trcseqevr1 +0x9a 0x2 0x31 0xd5 +# CHECK: mrs x26, trcseqevr2 +0x8e 0x6 0x31 0xd5 +# CHECK: mrs x14, trcseqrstevr +0x84 0x7 0x31 0xd5 +# CHECK: mrs x4, trcseqstr +0x91 0x8 0x31 0xd5 +# CHECK: mrs x17, trcextinselr +0xb5 0x0 0x31 0xd5 +# CHECK: mrs x21, trccntrldvr0 +0xaa 0x1 0x31 0xd5 +# CHECK: mrs x10, trccntrldvr1 +0xb4 0x2 0x31 0xd5 +# CHECK: mrs x20, trccntrldvr2 +0xa5 0x3 0x31 0xd5 +# CHECK: mrs x5, trccntrldvr3 +0xb1 0x4 0x31 0xd5 +# CHECK: mrs x17, trccntctlr0 +0xa1 0x5 0x31 0xd5 +# CHECK: mrs x1, trccntctlr1 +0xb1 0x6 0x31 0xd5 +# CHECK: mrs x17, trccntctlr2 +0xa6 0x7 0x31 0xd5 +# CHECK: mrs x6, trccntctlr3 +0xbc 0x8 0x31 0xd5 +# CHECK: mrs x28, trccntvr0 +0xb7 0x9 0x31 0xd5 +# CHECK: mrs x23, trccntvr1 +0xa9 0xa 0x31 0xd5 +# CHECK: mrs x9, trccntvr2 +0xa6 0xb 0x31 0xd5 +# CHECK: mrs x6, trccntvr3 +0xf8 0x0 0x31 0xd5 +# CHECK: mrs x24, trcimspec0 +0xf8 0x1 0x31 0xd5 +# CHECK: mrs x24, trcimspec1 +0xef 0x2 0x31 0xd5 +# CHECK: mrs x15, trcimspec2 +0xea 0x3 0x31 0xd5 +# CHECK: mrs x10, trcimspec3 +0xfd 0x4 0x31 0xd5 +# CHECK: mrs x29, trcimspec4 +0xf2 0x5 0x31 0xd5 +# CHECK: mrs x18, trcimspec5 +0xfd 0x6 0x31 0xd5 +# CHECK: mrs x29, trcimspec6 +0xe2 0x7 0x31 0xd5 +# CHECK: mrs x2, trcimspec7 +0x8 0x12 0x31 0xd5 +# CHECK: mrs x8, trcrsctlr2 +0x0 0x13 0x31 0xd5 +# CHECK: mrs x0, trcrsctlr3 +0xc 0x14 0x31 0xd5 +# CHECK: mrs x12, trcrsctlr4 +0x1a 0x15 0x31 0xd5 +# CHECK: mrs x26, trcrsctlr5 +0x1d 0x16 0x31 0xd5 +# CHECK: mrs x29, trcrsctlr6 +0x11 0x17 0x31 0xd5 +# CHECK: mrs x17, trcrsctlr7 +0x0 0x18 0x31 0xd5 +# CHECK: mrs x0, trcrsctlr8 +0x1 0x19 0x31 0xd5 +# CHECK: mrs x1, trcrsctlr9 +0x11 0x1a 0x31 0xd5 +# CHECK: mrs x17, trcrsctlr10 +0x15 0x1b 0x31 0xd5 +# CHECK: mrs x21, trcrsctlr11 +0x1 0x1c 0x31 0xd5 +# CHECK: mrs x1, trcrsctlr12 +0x8 0x1d 0x31 0xd5 +# CHECK: mrs x8, trcrsctlr13 +0x18 0x1e 0x31 0xd5 +# CHECK: mrs x24, trcrsctlr14 +0x0 0x1f 0x31 0xd5 +# CHECK: mrs x0, trcrsctlr15 +0x22 0x10 0x31 0xd5 +# CHECK: mrs x2, trcrsctlr16 +0x3d 0x11 0x31 0xd5 +# CHECK: mrs x29, trcrsctlr17 +0x36 0x12 0x31 0xd5 +# CHECK: mrs x22, trcrsctlr18 +0x26 0x13 0x31 0xd5 +# CHECK: mrs x6, trcrsctlr19 +0x3a 0x14 0x31 0xd5 +# CHECK: mrs x26, trcrsctlr20 +0x3a 0x15 0x31 0xd5 +# CHECK: mrs x26, trcrsctlr21 +0x24 0x16 0x31 0xd5 +# CHECK: mrs x4, trcrsctlr22 +0x2c 0x17 0x31 0xd5 +# CHECK: mrs x12, trcrsctlr23 +0x21 0x18 0x31 0xd5 +# CHECK: mrs x1, trcrsctlr24 +0x20 0x19 0x31 0xd5 +# CHECK: mrs x0, trcrsctlr25 +0x31 0x1a 0x31 0xd5 +# CHECK: mrs x17, trcrsctlr26 +0x28 0x1b 0x31 0xd5 +# CHECK: mrs x8, trcrsctlr27 +0x2a 0x1c 0x31 0xd5 +# CHECK: mrs x10, trcrsctlr28 +0x39 0x1d 0x31 0xd5 +# CHECK: mrs x25, trcrsctlr29 +0x2c 0x1e 0x31 0xd5 +# CHECK: mrs x12, trcrsctlr30 +0x2b 0x1f 0x31 0xd5 +# CHECK: mrs x11, trcrsctlr31 +0x52 0x10 0x31 0xd5 +# CHECK: mrs x18, trcssccr0 +0x4c 0x11 0x31 0xd5 +# CHECK: mrs x12, trcssccr1 +0x43 0x12 0x31 0xd5 +# CHECK: mrs x3, trcssccr2 +0x42 0x13 0x31 0xd5 +# CHECK: mrs x2, trcssccr3 +0x55 0x14 0x31 0xd5 +# CHECK: mrs x21, trcssccr4 +0x4a 0x15 0x31 0xd5 +# CHECK: mrs x10, trcssccr5 +0x56 0x16 0x31 0xd5 +# CHECK: mrs x22, trcssccr6 +0x57 0x17 0x31 0xd5 +# CHECK: mrs x23, trcssccr7 +0x57 0x18 0x31 0xd5 +# CHECK: mrs x23, trcsscsr0 +0x53 0x19 0x31 0xd5 +# CHECK: mrs x19, trcsscsr1 +0x59 0x1a 0x31 0xd5 +# CHECK: mrs x25, trcsscsr2 +0x51 0x1b 0x31 0xd5 +# CHECK: mrs x17, trcsscsr3 +0x53 0x1c 0x31 0xd5 +# CHECK: mrs x19, trcsscsr4 +0x4b 0x1d 0x31 0xd5 +# CHECK: mrs x11, trcsscsr5 +0x45 0x1e 0x31 0xd5 +# CHECK: mrs x5, trcsscsr6 +0x49 0x1f 0x31 0xd5 +# CHECK: mrs x9, trcsscsr7 +0x9a 0x14 0x31 0xd5 +# CHECK: mrs x26, trcpdcr +0x8 0x20 0x31 0xd5 +# CHECK: mrs x8, trcacvr0 +0xf 0x22 0x31 0xd5 +# CHECK: mrs x15, trcacvr1 +0x13 0x24 0x31 0xd5 +# CHECK: mrs x19, trcacvr2 +0x8 0x26 0x31 0xd5 +# CHECK: mrs x8, trcacvr3 +0x1c 0x28 0x31 0xd5 +# CHECK: mrs x28, trcacvr4 +0x3 0x2a 0x31 0xd5 +# CHECK: mrs x3, trcacvr5 +0x19 0x2c 0x31 0xd5 +# CHECK: mrs x25, trcacvr6 +0x18 0x2e 0x31 0xd5 +# CHECK: mrs x24, trcacvr7 +0x26 0x20 0x31 0xd5 +# CHECK: mrs x6, trcacvr8 +0x23 0x22 0x31 0xd5 +# CHECK: mrs x3, trcacvr9 +0x38 0x24 0x31 0xd5 +# CHECK: mrs x24, trcacvr10 +0x23 0x26 0x31 0xd5 +# CHECK: mrs x3, trcacvr11 +0x2c 0x28 0x31 0xd5 +# CHECK: mrs x12, trcacvr12 +0x29 0x2a 0x31 0xd5 +# CHECK: mrs x9, trcacvr13 +0x2e 0x2c 0x31 0xd5 +# CHECK: mrs x14, trcacvr14 +0x23 0x2e 0x31 0xd5 +# CHECK: mrs x3, trcacvr15 +0x55 0x20 0x31 0xd5 +# CHECK: mrs x21, trcacatr0 +0x5a 0x22 0x31 0xd5 +# CHECK: mrs x26, trcacatr1 +0x48 0x24 0x31 0xd5 +# CHECK: mrs x8, trcacatr2 +0x56 0x26 0x31 0xd5 +# CHECK: mrs x22, trcacatr3 +0x46 0x28 0x31 0xd5 +# CHECK: mrs x6, trcacatr4 +0x5d 0x2a 0x31 0xd5 +# CHECK: mrs x29, trcacatr5 +0x45 0x2c 0x31 0xd5 +# CHECK: mrs x5, trcacatr6 +0x52 0x2e 0x31 0xd5 +# CHECK: mrs x18, trcacatr7 +0x62 0x20 0x31 0xd5 +# CHECK: mrs x2, trcacatr8 +0x73 0x22 0x31 0xd5 +# CHECK: mrs x19, trcacatr9 +0x6d 0x24 0x31 0xd5 +# CHECK: mrs x13, trcacatr10 +0x79 0x26 0x31 0xd5 +# CHECK: mrs x25, trcacatr11 +0x72 0x28 0x31 0xd5 +# CHECK: mrs x18, trcacatr12 +0x7d 0x2a 0x31 0xd5 +# CHECK: mrs x29, trcacatr13 +0x69 0x2c 0x31 0xd5 +# CHECK: mrs x9, trcacatr14 +0x72 0x2e 0x31 0xd5 +# CHECK: mrs x18, trcacatr15 +0x9d 0x20 0x31 0xd5 +# CHECK: mrs x29, trcdvcvr0 +0x8f 0x24 0x31 0xd5 +# CHECK: mrs x15, trcdvcvr1 +0x8f 0x28 0x31 0xd5 +# CHECK: mrs x15, trcdvcvr2 +0x8f 0x2c 0x31 0xd5 +# CHECK: mrs x15, trcdvcvr3 +0xb3 0x20 0x31 0xd5 +# CHECK: mrs x19, trcdvcvr4 +0xb6 0x24 0x31 0xd5 +# CHECK: mrs x22, trcdvcvr5 +0xbb 0x28 0x31 0xd5 +# CHECK: mrs x27, trcdvcvr6 +0xa1 0x2c 0x31 0xd5 +# CHECK: mrs x1, trcdvcvr7 +0xdd 0x20 0x31 0xd5 +# CHECK: mrs x29, trcdvcmr0 +0xc9 0x24 0x31 0xd5 +# CHECK: mrs x9, trcdvcmr1 +0xc1 0x28 0x31 0xd5 +# CHECK: mrs x1, trcdvcmr2 +0xc2 0x2c 0x31 0xd5 +# CHECK: mrs x2, trcdvcmr3 +0xe5 0x20 0x31 0xd5 +# CHECK: mrs x5, trcdvcmr4 +0xf5 0x24 0x31 0xd5 +# CHECK: mrs x21, trcdvcmr5 +0xe5 0x28 0x31 0xd5 +# CHECK: mrs x5, trcdvcmr6 +0xe1 0x2c 0x31 0xd5 +# CHECK: mrs x1, trcdvcmr7 +0x15 0x30 0x31 0xd5 +# CHECK: mrs x21, trccidcvr0 +0x18 0x32 0x31 0xd5 +# CHECK: mrs x24, trccidcvr1 +0x18 0x34 0x31 0xd5 +# CHECK: mrs x24, trccidcvr2 +0xc 0x36 0x31 0xd5 +# CHECK: mrs x12, trccidcvr3 +0xa 0x38 0x31 0xd5 +# CHECK: mrs x10, trccidcvr4 +0x9 0x3a 0x31 0xd5 +# CHECK: mrs x9, trccidcvr5 +0x6 0x3c 0x31 0xd5 +# CHECK: mrs x6, trccidcvr6 +0x14 0x3e 0x31 0xd5 +# CHECK: mrs x20, trccidcvr7 +0x34 0x30 0x31 0xd5 +# CHECK: mrs x20, trcvmidcvr0 +0x34 0x32 0x31 0xd5 +# CHECK: mrs x20, trcvmidcvr1 +0x3a 0x34 0x31 0xd5 +# CHECK: mrs x26, trcvmidcvr2 +0x21 0x36 0x31 0xd5 +# CHECK: mrs x1, trcvmidcvr3 +0x2e 0x38 0x31 0xd5 +# CHECK: mrs x14, trcvmidcvr4 +0x3b 0x3a 0x31 0xd5 +# CHECK: mrs x27, trcvmidcvr5 +0x3d 0x3c 0x31 0xd5 +# CHECK: mrs x29, trcvmidcvr6 +0x31 0x3e 0x31 0xd5 +# CHECK: mrs x17, trcvmidcvr7 +0x4a 0x30 0x31 0xd5 +# CHECK: mrs x10, trccidcctlr0 +0x44 0x31 0x31 0xd5 +# CHECK: mrs x4, trccidcctlr1 +0x49 0x32 0x31 0xd5 +# CHECK: mrs x9, trcvmidcctlr0 +0x4b 0x33 0x31 0xd5 +# CHECK: mrs x11, trcvmidcctlr1 +0x96 0x70 0x31 0xd5 +# CHECK: mrs x22, trcitctrl +0xd7 0x78 0x31 0xd5 +# CHECK: mrs x23, trcclaimset +0xce 0x79 0x31 0xd5 +# CHECK: mrs x14, trcclaimclr +0x9c 0x10 0x11 0xd5 +# CHECK: msr trcoslar, x28 +0xce 0x7c 0x11 0xd5 +# CHECK: msr trclar, x14 +0xa 0x1 0x11 0xd5 +# CHECK: msr trcprgctlr, x10 +0x1b 0x2 0x11 0xd5 +# CHECK: msr trcprocselr, x27 +0x18 0x4 0x11 0xd5 +# CHECK: msr trcconfigr, x24 +0x8 0x6 0x11 0xd5 +# CHECK: msr trcauxctlr, x8 +0x10 0x8 0x11 0xd5 +# CHECK: msr trceventctl0r, x16 +0x1b 0x9 0x11 0xd5 +# CHECK: msr trceventctl1r, x27 +0x1a 0xb 0x11 0xd5 +# CHECK: msr trcstallctlr, x26 +0x0 0xc 0x11 0xd5 +# CHECK: msr trctsctlr, x0 +0xe 0xd 0x11 0xd5 +# CHECK: msr trcsyncpr, x14 +0x8 0xe 0x11 0xd5 +# CHECK: msr trcccctlr, x8 +0x6 0xf 0x11 0xd5 +# CHECK: msr trcbbctlr, x6 +0x37 0x0 0x11 0xd5 +# CHECK: msr trctraceidr, x23 +0x25 0x1 0x11 0xd5 +# CHECK: msr trcqctlr, x5 +0x40 0x0 0x11 0xd5 +# CHECK: msr trcvictlr, x0 +0x40 0x1 0x11 0xd5 +# CHECK: msr trcviiectlr, x0 +0x41 0x2 0x11 0xd5 +# CHECK: msr trcvissctlr, x1 +0x40 0x3 0x11 0xd5 +# CHECK: msr trcvipcssctlr, x0 +0x47 0x8 0x11 0xd5 +# CHECK: msr trcvdctlr, x7 +0x52 0x9 0x11 0xd5 +# CHECK: msr trcvdsacctlr, x18 +0x58 0xa 0x11 0xd5 +# CHECK: msr trcvdarcctlr, x24 +0x9c 0x0 0x11 0xd5 +# CHECK: msr trcseqevr0, x28 +0x95 0x1 0x11 0xd5 +# CHECK: msr trcseqevr1, x21 +0x90 0x2 0x11 0xd5 +# CHECK: msr trcseqevr2, x16 +0x90 0x6 0x11 0xd5 +# CHECK: msr trcseqrstevr, x16 +0x99 0x7 0x11 0xd5 +# CHECK: msr trcseqstr, x25 +0x9d 0x8 0x11 0xd5 +# CHECK: msr trcextinselr, x29 +0xb4 0x0 0x11 0xd5 +# CHECK: msr trccntrldvr0, x20 +0xb4 0x1 0x11 0xd5 +# CHECK: msr trccntrldvr1, x20 +0xb6 0x2 0x11 0xd5 +# CHECK: msr trccntrldvr2, x22 +0xac 0x3 0x11 0xd5 +# CHECK: msr trccntrldvr3, x12 +0xb4 0x4 0x11 0xd5 +# CHECK: msr trccntctlr0, x20 +0xa4 0x5 0x11 0xd5 +# CHECK: msr trccntctlr1, x4 +0xa8 0x6 0x11 0xd5 +# CHECK: msr trccntctlr2, x8 +0xb0 0x7 0x11 0xd5 +# CHECK: msr trccntctlr3, x16 +0xa5 0x8 0x11 0xd5 +# CHECK: msr trccntvr0, x5 +0xbb 0x9 0x11 0xd5 +# CHECK: msr trccntvr1, x27 +0xb5 0xa 0x11 0xd5 +# CHECK: msr trccntvr2, x21 +0xa8 0xb 0x11 0xd5 +# CHECK: msr trccntvr3, x8 +0xe6 0x0 0x11 0xd5 +# CHECK: msr trcimspec0, x6 +0xfb 0x1 0x11 0xd5 +# CHECK: msr trcimspec1, x27 +0xf7 0x2 0x11 0xd5 +# CHECK: msr trcimspec2, x23 +0xef 0x3 0x11 0xd5 +# CHECK: msr trcimspec3, x15 +0xed 0x4 0x11 0xd5 +# CHECK: msr trcimspec4, x13 +0xf9 0x5 0x11 0xd5 +# CHECK: msr trcimspec5, x25 +0xf3 0x6 0x11 0xd5 +# CHECK: msr trcimspec6, x19 +0xfb 0x7 0x11 0xd5 +# CHECK: msr trcimspec7, x27 +0x4 0x12 0x11 0xd5 +# CHECK: msr trcrsctlr2, x4 +0x0 0x13 0x11 0xd5 +# CHECK: msr trcrsctlr3, x0 +0x15 0x14 0x11 0xd5 +# CHECK: msr trcrsctlr4, x21 +0x8 0x15 0x11 0xd5 +# CHECK: msr trcrsctlr5, x8 +0x14 0x16 0x11 0xd5 +# CHECK: msr trcrsctlr6, x20 +0xb 0x17 0x11 0xd5 +# CHECK: msr trcrsctlr7, x11 +0x12 0x18 0x11 0xd5 +# CHECK: msr trcrsctlr8, x18 +0x18 0x19 0x11 0xd5 +# CHECK: msr trcrsctlr9, x24 +0xf 0x1a 0x11 0xd5 +# CHECK: msr trcrsctlr10, x15 +0x15 0x1b 0x11 0xd5 +# CHECK: msr trcrsctlr11, x21 +0x4 0x1c 0x11 0xd5 +# CHECK: msr trcrsctlr12, x4 +0x1c 0x1d 0x11 0xd5 +# CHECK: msr trcrsctlr13, x28 +0x3 0x1e 0x11 0xd5 +# CHECK: msr trcrsctlr14, x3 +0x14 0x1f 0x11 0xd5 +# CHECK: msr trcrsctlr15, x20 +0x2c 0x10 0x11 0xd5 +# CHECK: msr trcrsctlr16, x12 +0x31 0x11 0x11 0xd5 +# CHECK: msr trcrsctlr17, x17 +0x2a 0x12 0x11 0xd5 +# CHECK: msr trcrsctlr18, x10 +0x2b 0x13 0x11 0xd5 +# CHECK: msr trcrsctlr19, x11 +0x23 0x14 0x11 0xd5 +# CHECK: msr trcrsctlr20, x3 +0x32 0x15 0x11 0xd5 +# CHECK: msr trcrsctlr21, x18 +0x3a 0x16 0x11 0xd5 +# CHECK: msr trcrsctlr22, x26 +0x25 0x17 0x11 0xd5 +# CHECK: msr trcrsctlr23, x5 +0x39 0x18 0x11 0xd5 +# CHECK: msr trcrsctlr24, x25 +0x25 0x19 0x11 0xd5 +# CHECK: msr trcrsctlr25, x5 +0x24 0x1a 0x11 0xd5 +# CHECK: msr trcrsctlr26, x4 +0x34 0x1b 0x11 0xd5 +# CHECK: msr trcrsctlr27, x20 +0x25 0x1c 0x11 0xd5 +# CHECK: msr trcrsctlr28, x5 +0x2a 0x1d 0x11 0xd5 +# CHECK: msr trcrsctlr29, x10 +0x38 0x1e 0x11 0xd5 +# CHECK: msr trcrsctlr30, x24 +0x34 0x1f 0x11 0xd5 +# CHECK: msr trcrsctlr31, x20 +0x57 0x10 0x11 0xd5 +# CHECK: msr trcssccr0, x23 +0x5b 0x11 0x11 0xd5 +# CHECK: msr trcssccr1, x27 +0x5b 0x12 0x11 0xd5 +# CHECK: msr trcssccr2, x27 +0x46 0x13 0x11 0xd5 +# CHECK: msr trcssccr3, x6 +0x43 0x14 0x11 0xd5 +# CHECK: msr trcssccr4, x3 +0x4c 0x15 0x11 0xd5 +# CHECK: msr trcssccr5, x12 +0x47 0x16 0x11 0xd5 +# CHECK: msr trcssccr6, x7 +0x46 0x17 0x11 0xd5 +# CHECK: msr trcssccr7, x6 +0x54 0x18 0x11 0xd5 +# CHECK: msr trcsscsr0, x20 +0x51 0x19 0x11 0xd5 +# CHECK: msr trcsscsr1, x17 +0x4b 0x1a 0x11 0xd5 +# CHECK: msr trcsscsr2, x11 +0x44 0x1b 0x11 0xd5 +# CHECK: msr trcsscsr3, x4 +0x4e 0x1c 0x11 0xd5 +# CHECK: msr trcsscsr4, x14 +0x56 0x1d 0x11 0xd5 +# CHECK: msr trcsscsr5, x22 +0x43 0x1e 0x11 0xd5 +# CHECK: msr trcsscsr6, x3 +0x4b 0x1f 0x11 0xd5 +# CHECK: msr trcsscsr7, x11 +0x83 0x14 0x11 0xd5 +# CHECK: msr trcpdcr, x3 +0x6 0x20 0x11 0xd5 +# CHECK: msr trcacvr0, x6 +0x14 0x22 0x11 0xd5 +# CHECK: msr trcacvr1, x20 +0x19 0x24 0x11 0xd5 +# CHECK: msr trcacvr2, x25 +0x1 0x26 0x11 0xd5 +# CHECK: msr trcacvr3, x1 +0x1c 0x28 0x11 0xd5 +# CHECK: msr trcacvr4, x28 +0xf 0x2a 0x11 0xd5 +# CHECK: msr trcacvr5, x15 +0x19 0x2c 0x11 0xd5 +# CHECK: msr trcacvr6, x25 +0xc 0x2e 0x11 0xd5 +# CHECK: msr trcacvr7, x12 +0x25 0x20 0x11 0xd5 +# CHECK: msr trcacvr8, x5 +0x39 0x22 0x11 0xd5 +# CHECK: msr trcacvr9, x25 +0x2d 0x24 0x11 0xd5 +# CHECK: msr trcacvr10, x13 +0x2a 0x26 0x11 0xd5 +# CHECK: msr trcacvr11, x10 +0x33 0x28 0x11 0xd5 +# CHECK: msr trcacvr12, x19 +0x2a 0x2a 0x11 0xd5 +# CHECK: msr trcacvr13, x10 +0x33 0x2c 0x11 0xd5 +# CHECK: msr trcacvr14, x19 +0x22 0x2e 0x11 0xd5 +# CHECK: msr trcacvr15, x2 +0x4f 0x20 0x11 0xd5 +# CHECK: msr trcacatr0, x15 +0x4d 0x22 0x11 0xd5 +# CHECK: msr trcacatr1, x13 +0x48 0x24 0x11 0xd5 +# CHECK: msr trcacatr2, x8 +0x41 0x26 0x11 0xd5 +# CHECK: msr trcacatr3, x1 +0x4b 0x28 0x11 0xd5 +# CHECK: msr trcacatr4, x11 +0x48 0x2a 0x11 0xd5 +# CHECK: msr trcacatr5, x8 +0x58 0x2c 0x11 0xd5 +# CHECK: msr trcacatr6, x24 +0x46 0x2e 0x11 0xd5 +# CHECK: msr trcacatr7, x6 +0x77 0x20 0x11 0xd5 +# CHECK: msr trcacatr8, x23 +0x65 0x22 0x11 0xd5 +# CHECK: msr trcacatr9, x5 +0x6b 0x24 0x11 0xd5 +# CHECK: msr trcacatr10, x11 +0x6b 0x26 0x11 0xd5 +# CHECK: msr trcacatr11, x11 +0x63 0x28 0x11 0xd5 +# CHECK: msr trcacatr12, x3 +0x7c 0x2a 0x11 0xd5 +# CHECK: msr trcacatr13, x28 +0x79 0x2c 0x11 0xd5 +# CHECK: msr trcacatr14, x25 +0x64 0x2e 0x11 0xd5 +# CHECK: msr trcacatr15, x4 +0x86 0x20 0x11 0xd5 +# CHECK: msr trcdvcvr0, x6 +0x83 0x24 0x11 0xd5 +# CHECK: msr trcdvcvr1, x3 +0x85 0x28 0x11 0xd5 +# CHECK: msr trcdvcvr2, x5 +0x8b 0x2c 0x11 0xd5 +# CHECK: msr trcdvcvr3, x11 +0xa9 0x20 0x11 0xd5 +# CHECK: msr trcdvcvr4, x9 +0xae 0x24 0x11 0xd5 +# CHECK: msr trcdvcvr5, x14 +0xaa 0x28 0x11 0xd5 +# CHECK: msr trcdvcvr6, x10 +0xac 0x2c 0x11 0xd5 +# CHECK: msr trcdvcvr7, x12 +0xc8 0x20 0x11 0xd5 +# CHECK: msr trcdvcmr0, x8 +0xc8 0x24 0x11 0xd5 +# CHECK: msr trcdvcmr1, x8 +0xd6 0x28 0x11 0xd5 +# CHECK: msr trcdvcmr2, x22 +0xd6 0x2c 0x11 0xd5 +# CHECK: msr trcdvcmr3, x22 +0xe5 0x20 0x11 0xd5 +# CHECK: msr trcdvcmr4, x5 +0xf0 0x24 0x11 0xd5 +# CHECK: msr trcdvcmr5, x16 +0xfb 0x28 0x11 0xd5 +# CHECK: msr trcdvcmr6, x27 +0xf5 0x2c 0x11 0xd5 +# CHECK: msr trcdvcmr7, x21 +0x8 0x30 0x11 0xd5 +# CHECK: msr trccidcvr0, x8 +0x6 0x32 0x11 0xd5 +# CHECK: msr trccidcvr1, x6 +0x9 0x34 0x11 0xd5 +# CHECK: msr trccidcvr2, x9 +0x8 0x36 0x11 0xd5 +# CHECK: msr trccidcvr3, x8 +0x3 0x38 0x11 0xd5 +# CHECK: msr trccidcvr4, x3 +0x15 0x3a 0x11 0xd5 +# CHECK: msr trccidcvr5, x21 +0xc 0x3c 0x11 0xd5 +# CHECK: msr trccidcvr6, x12 +0x7 0x3e 0x11 0xd5 +# CHECK: msr trccidcvr7, x7 +0x24 0x30 0x11 0xd5 +# CHECK: msr trcvmidcvr0, x4 +0x23 0x32 0x11 0xd5 +# CHECK: msr trcvmidcvr1, x3 +0x29 0x34 0x11 0xd5 +# CHECK: msr trcvmidcvr2, x9 +0x31 0x36 0x11 0xd5 +# CHECK: msr trcvmidcvr3, x17 +0x2e 0x38 0x11 0xd5 +# CHECK: msr trcvmidcvr4, x14 +0x2c 0x3a 0x11 0xd5 +# CHECK: msr trcvmidcvr5, x12 +0x2a 0x3c 0x11 0xd5 +# CHECK: msr trcvmidcvr6, x10 +0x23 0x3e 0x11 0xd5 +# CHECK: msr trcvmidcvr7, x3 +0x4e 0x30 0x11 0xd5 +# CHECK: msr trccidcctlr0, x14 +0x56 0x31 0x11 0xd5 +# CHECK: msr trccidcctlr1, x22 +0x48 0x32 0x11 0xd5 +# CHECK: msr trcvmidcctlr0, x8 +0x4f 0x33 0x11 0xd5 +# CHECK: msr trcvmidcctlr1, x15 +0x81 0x70 0x11 0xd5 +# CHECK: msr trcitctrl, x1 +0xc7 0x78 0x11 0xd5 +# CHECK: msr trcclaimset, x7 +0xdd 0x79 0x11 0xd5 +# CHECK: msr trcclaimclr, x29 + + diff --git a/test/MC/Disassembler/ARM/hex-immediates.txt b/test/MC/Disassembler/ARM/hex-immediates.txt new file mode 100644 index 0000000..2634d7e --- /dev/null +++ b/test/MC/Disassembler/ARM/hex-immediates.txt @@ -0,0 +1,5 @@ +# RUN: llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 -hdis < %s | FileCheck %s +# CHECK: ldr r4, [pc, #0x20] +0x08 0x4c +# CHECK: sub sp, #0x84 +0xa1 0xb0 diff --git a/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt b/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt index 2d2a628..99da8ce 100644 --- a/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt @@ -7,7 +7,7 @@ # ------------------------------------------------------------------------------------------------- # # A8.6.391 VST1 (multiple single elements) -# This encoding looks like: vst1.8 {d0,d1,d2}, [r0, :128] +# This encoding looks like: vst1.8 {d0,d1,d2}, [r0:128] # But bits 5-4 for the alignment of 128 encoded as align = 0b10, is available only if <list> # contains two or four registers. rdar://11220250 0x00 0xf9 0x2f 0x06 diff --git a/test/MC/Disassembler/ARM/neon-tests.txt b/test/MC/Disassembler/ARM/neon-tests.txt index a7b6b1c..65e9954 100644 --- a/test/MC/Disassembler/ARM/neon-tests.txt +++ b/test/MC/Disassembler/ARM/neon-tests.txt @@ -21,10 +21,10 @@ # CHECK: vld4.8 {d4, d6, d8, d10}, [r2] 0x0f 0x41 0x22 0xf4 -# CHECK: vld1.32 {d3[], d4[]}, [r0, :32]! +# CHECK: vld1.32 {d3[], d4[]}, [r0:32]! 0xbd 0x3c 0xa0 0xf4 -# CHECK: vld4.16 {d3[], d5[], d7[], d9[]}, [r0, :64]! +# CHECK: vld4.16 {d3[], d5[], d7[], d9[]}, [r0:64]! 0x7d 0x3f 0xa0 0xf4 # CHECK: vorr d0, d15, d15 @@ -75,7 +75,7 @@ # CHECK: vbic.i32 q2, #0xa900 0x79 0x43 0x82 0xf3 -# CHECK: vst2.32 {d16, d18}, [r2, :64], r2 +# CHECK: vst2.32 {d16, d18}, [r2:64], r2 0x92 0x9 0x42 0xf4 # CHECK: vmov.s8 r0, d8[1] diff --git a/test/MC/Disassembler/ARM/neon.txt b/test/MC/Disassembler/ARM/neon.txt index 649424a..cd5f418 100644 --- a/test/MC/Disassembler/ARM/neon.txt +++ b/test/MC/Disassembler/ARM/neon.txt @@ -1638,7 +1638,7 @@ 0x1f 0x07 0x60 0xf4 -# CHECK: vld1.8 {d16}, [r0, :64] +# CHECK: vld1.8 {d16}, [r0:64] 0x4f 0x07 0x60 0xf4 # CHECK: vld1.16 {d16}, [r0] 0x8f 0x07 0x60 0xf4 @@ -1646,37 +1646,37 @@ 0xcf 0x07 0x60 0xf4 # CHECK: vld1.64 {d16}, [r0] 0x1f 0x0a 0x60 0xf4 -# CHECK: vld1.8 {d16, d17}, [r0, :64] +# CHECK: vld1.8 {d16, d17}, [r0:64] 0x6f 0x0a 0x60 0xf4 -# CHECK: vld1.16 {d16, d17}, [r0, :128] +# CHECK: vld1.16 {d16, d17}, [r0:128] 0x8f 0x0a 0x60 0xf4 # CHECK: vld1.32 {d16, d17}, [r0] 0xcf 0x0a 0x60 0xf4 # CHECK: vld1.64 {d16, d17}, [r0] 0x1f 0x08 0x60 0xf4 -# CHECK: vld2.8 {d16, d17}, [r0, :64] +# CHECK: vld2.8 {d16, d17}, [r0:64] 0x6f 0x08 0x60 0xf4 -# CHECK: vld2.16 {d16, d17}, [r0, :128] +# CHECK: vld2.16 {d16, d17}, [r0:128] 0x8f 0x08 0x60 0xf4 # CHECK: vld2.32 {d16, d17}, [r0] 0x1f 0x03 0x60 0xf4 -# CHECK: vld2.8 {d16, d17, d18, d19}, [r0, :64] +# CHECK: vld2.8 {d16, d17, d18, d19}, [r0:64] 0x6f 0x03 0x60 0xf4 -# CHECK: vld2.16 {d16, d17, d18, d19}, [r0, :128] +# CHECK: vld2.16 {d16, d17, d18, d19}, [r0:128] 0xbf 0x03 0x60 0xf4 -# CHECK: vld2.32 {d16, d17, d18, d19}, [r0, :256] +# CHECK: vld2.32 {d16, d17, d18, d19}, [r0:256] 0x1f 0x04 0x60 0xf4 -# CHECK: vld3.8 {d16, d17, d18}, [r0, :64] +# CHECK: vld3.8 {d16, d17, d18}, [r0:64] 0x4f 0x04 0x60 0xf4 # CHECK: vld3.16 {d16, d17, d18}, [r0] 0x8f 0x04 0x60 0xf4 # CHECK: vld3.32 {d16, d17, d18}, [r0] 0x1d 0x05 0x60 0xf4 -# CHECK: vld3.8 {d16, d18, d20}, [r0, :64]! +# CHECK: vld3.8 {d16, d18, d20}, [r0:64]! 0x1d 0x15 0x60 0xf4 -# CHECK: vld3.8 {d17, d19, d21}, [r0, :64]! +# CHECK: vld3.8 {d17, d19, d21}, [r0:64]! 0x4d 0x05 0x60 0xf4 # CHECK: vld3.16 {d16, d18, d20}, [r0]! 0x4d 0x15 0x60 0xf4 @@ -1687,15 +1687,15 @@ # CHECK: vld3.32 {d17, d19, d21}, [r0]! 0x1f 0x00 0x60 0xf4 -# CHECK: vld4.8 {d16, d17, d18, d19}, [r0, :64] +# CHECK: vld4.8 {d16, d17, d18, d19}, [r0:64] 0x6f 0x00 0x60 0xf4 -# CHECK: vld4.16 {d16, d17, d18, d19}, [r0, :128] +# CHECK: vld4.16 {d16, d17, d18, d19}, [r0:128] 0xbf 0x00 0x60 0xf4 -# CHECK: vld4.32 {d16, d17, d18, d19}, [r0, :256] +# CHECK: vld4.32 {d16, d17, d18, d19}, [r0:256] 0x3d 0x01 0x60 0xf4 -# CHECK: vld4.8 {d16, d18, d20, d22}, [r0, :256]! +# CHECK: vld4.8 {d16, d18, d20, d22}, [r0:256]! 0x3d 0x11 0x60 0xf4 -# CHECK: vld4.8 {d17, d19, d21, d23}, [r0, :256]! +# CHECK: vld4.8 {d17, d19, d21, d23}, [r0:256]! 0x4d 0x01 0x60 0xf4 # CHECK: vld4.16 {d16, d18, d20, d22}, [r0]! 0x4d 0x11 0x60 0xf4 @@ -1708,20 +1708,20 @@ 0x6f 0x00 0xe0 0xf4 # CHECK: vld1.8 {d16[3]}, [r0] 0x9f 0x04 0xe0 0xf4 -# CHECK: vld1.16 {d16[2]}, [r0, :16] +# CHECK: vld1.16 {d16[2]}, [r0:16] 0xbf 0x08 0xe0 0xf4 -# CHECK: vld1.32 {d16[1]}, [r0, :32] +# CHECK: vld1.32 {d16[1]}, [r0:32] 0x3f 0x01 0xe0 0xf4 -# CHECK: vld2.8 {d16[1], d17[1]}, [r0, :16] +# CHECK: vld2.8 {d16[1], d17[1]}, [r0:16] 0x5f 0x05 0xe0 0xf4 -# CHECK: vld2.16 {d16[1], d17[1]}, [r0, :32] +# CHECK: vld2.16 {d16[1], d17[1]}, [r0:32] 0x8f 0x09 0xe0 0xf4 # CHECK: vld2.32 {d16[1], d17[1]}, [r0] 0x6f 0x15 0xe0 0xf4 # CHECK: vld2.16 {d17[1], d19[1]}, [r0] 0x5f 0x19 0xe0 0xf4 -# CHECK: vld2.32 {d17[0], d19[0]}, [r0, :64] +# CHECK: vld2.32 {d17[0], d19[0]}, [r0:64] 0x2f 0x02 0xe0 0xf4 # CHECK: vld3.8 {d16[1], d17[1], d18[1]}, [r0] @@ -1754,44 +1754,44 @@ 0xa5 0x0e 0xa4 0xf4 0x3f 0x03 0xe0 0xf4 -# CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] +# CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0:32] 0x4f 0x07 0xe0 0xf4 # CHECK: vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] 0xaf 0x0b 0xe0 0xf4 -# CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128] +# CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0:128] 0x7f 0x07 0xe0 0xf4 -# CHECK: vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r0, :64] +# CHECK: vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r0:64] 0x4f 0x1b 0xe0 0xf4 # CHECK: vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] 0x0f 0x0f 0xa4 0xf4 # CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4] 0x3f 0x0f 0xa4 0xf4 -# CHECK: vld4.8 {d0[], d2[], d4[], d6[]}, [r4, :32] +# CHECK: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:32] 0x1d 0x0f 0xa4 0xf4 -# CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4, :32]! +# CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:32]! 0x35 0x0f 0xa4 0xf4 -# CHECK: vld4.8 {d0[], d2[], d4[], d6[]}, [r4, :32], r5 +# CHECK: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:32], r5 0x4f 0x0f 0xa4 0xf4 # CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4] 0x7f 0x0f 0xa4 0xf4 -# CHECK: vld4.16 {d0[], d2[], d4[], d6[]}, [r4, :64] +# CHECK: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:64] 0x5d 0x0f 0xa4 0xf4 -# CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4, :64]! +# CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:64]! 0x75 0x0f 0xa4 0xf4 -# CHECK: vld4.16 {d0[], d2[], d4[], d6[]}, [r4, :64], r5 +# CHECK: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:64], r5 0x8f 0x0f 0xa4 0xf4 # CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4] 0xbf 0x0f 0xa4 0xf4 -# CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4, :64] +# CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:64] 0xdd 0x0f 0xa4 0xf4 -# CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4, :128]! +# CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:128]! 0xf5 0x0f 0xa4 0xf4 -# CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4, :128], r5 +# CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:128], r5 0x1f 0x07 0x40 0xf4 -# CHECK: vst1.8 {d16}, [r0, :64] +# CHECK: vst1.8 {d16}, [r0:64] 0x4f 0x07 0x40 0xf4 # CHECK: vst1.16 {d16}, [r0] 0x8f 0x07 0x40 0xf4 @@ -1799,37 +1799,37 @@ 0xcf 0x07 0x40 0xf4 # CHECK: vst1.64 {d16}, [r0] 0x1f 0x0a 0x40 0xf4 -# CHECK: vst1.8 {d16, d17}, [r0, :64] +# CHECK: vst1.8 {d16, d17}, [r0:64] 0x6f 0x0a 0x40 0xf4 -# CHECK: vst1.16 {d16, d17}, [r0, :128] +# CHECK: vst1.16 {d16, d17}, [r0:128] 0x8f 0x0a 0x40 0xf4 # CHECK: vst1.32 {d16, d17}, [r0] 0xcf 0x0a 0x40 0xf4 # CHECK: vst1.64 {d16, d17}, [r0] 0x1f 0x08 0x40 0xf4 -# CHECK: vst2.8 {d16, d17}, [r0, :64] +# CHECK: vst2.8 {d16, d17}, [r0:64] 0x6f 0x08 0x40 0xf4 -# CHECK: vst2.16 {d16, d17}, [r0, :128] +# CHECK: vst2.16 {d16, d17}, [r0:128] 0x8f 0x08 0x40 0xf4 # CHECK: vst2.32 {d16, d17}, [r0] 0x1f 0x03 0x40 0xf4 -# CHECK: vst2.8 {d16, d17, d18, d19}, [r0, :64] +# CHECK: vst2.8 {d16, d17, d18, d19}, [r0:64] 0x6f 0x03 0x40 0xf4 -# CHECK: vst2.16 {d16, d17, d18, d19}, [r0, :128] +# CHECK: vst2.16 {d16, d17, d18, d19}, [r0:128] 0xbf 0x03 0x40 0xf4 -# CHECK: vst2.32 {d16, d17, d18, d19}, [r0, :256] +# CHECK: vst2.32 {d16, d17, d18, d19}, [r0:256] 0x1f 0x04 0x40 0xf4 -# CHECK: vst3.8 {d16, d17, d18}, [r0, :64] +# CHECK: vst3.8 {d16, d17, d18}, [r0:64] 0x4f 0x04 0x40 0xf4 # CHECK: vst3.16 {d16, d17, d18}, [r0] 0x8f 0x04 0x40 0xf4 # CHECK: vst3.32 {d16, d17, d18}, [r0] 0x1d 0x05 0x40 0xf4 -# CHECK: vst3.8 {d16, d18, d20}, [r0, :64]! +# CHECK: vst3.8 {d16, d18, d20}, [r0:64]! 0x1d 0x15 0x40 0xf4 -# CHECK: vst3.8 {d17, d19, d21}, [r0, :64]! +# CHECK: vst3.8 {d17, d19, d21}, [r0:64]! 0x4d 0x05 0x40 0xf4 # CHECK: vst3.16 {d16, d18, d20}, [r0]! 0x4d 0x15 0x40 0xf4 @@ -1840,13 +1840,13 @@ # CHECK: vst3.32 {d17, d19, d21}, [r0]! 0x1f 0x00 0x40 0xf4 -# CHECK: vst4.8 {d16, d17, d18, d19}, [r0, :64] +# CHECK: vst4.8 {d16, d17, d18, d19}, [r0:64] 0x6f 0x00 0x40 0xf4 -# CHECK: vst4.16 {d16, d17, d18, d19}, [r0, :128] +# CHECK: vst4.16 {d16, d17, d18, d19}, [r0:128] 0x3d 0x01 0x40 0xf4 -# CHECK: vst4.8 {d16, d18, d20, d22}, [r0, :256]! +# CHECK: vst4.8 {d16, d18, d20, d22}, [r0:256]! 0x3d 0x11 0x40 0xf4 -# CHECK: vst4.8 {d17, d19, d21, d23}, [r0, :256]! +# CHECK: vst4.8 {d17, d19, d21, d23}, [r0:256]! 0x4d 0x01 0x40 0xf4 # CHECK: vst4.16 {d16, d18, d20, d22}, [r0]! 0x4d 0x11 0x40 0xf4 @@ -1857,15 +1857,15 @@ # CHECK: vst4.32 {d17, d19, d21, d23}, [r0]! 0x3f 0x01 0xc0 0xf4 -# CHECK: vst2.8 {d16[1], d17[1]}, [r0, :16] +# CHECK: vst2.8 {d16[1], d17[1]}, [r0:16] 0x5f 0x05 0xc0 0xf4 -# CHECK: vst2.16 {d16[1], d17[1]}, [r0, :32] +# CHECK: vst2.16 {d16[1], d17[1]}, [r0:32] 0x8f 0x09 0xc0 0xf4 # CHECK: vst2.32 {d16[1], d17[1]}, [r0] 0x6f 0x15 0xc0 0xf4 # CHECK: vst2.16 {d17[1], d19[1]}, [r0] 0x5f 0x19 0xc0 0xf4 -# CHECK: vst2.32 {d17[0], d19[0]}, [r0, :64] +# CHECK: vst2.32 {d17[0], d19[0]}, [r0:64] 0x2f 0x02 0xc0 0xf4 # CHECK: vst3.8 {d16[1], d17[1], d18[1]}, [r0] @@ -1879,13 +1879,13 @@ # CHECK: vst3.32 {d16[0], d18[0], d20[0]}, [r0] 0x3f 0x03 0xc0 0xf4 -# CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] +# CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0:32] 0x4f 0x07 0xc0 0xf4 # CHECK: vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] 0xaf 0x0b 0xc0 0xf4 -# CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128] +# CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0:128] 0xff 0x17 0xc0 0xf4 -# CHECK: vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0, :64] +# CHECK: vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0:64] 0x4f 0x1b 0xc0 0xf4 # CHECK: vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] @@ -1920,11 +1920,11 @@ # CHECK: vcvttmi.f32.f16 s2, s19 0x1d 0x76 0x66 0xf4 -# CHECK: vld1.8 {d23, d24, d25}, [r6, :64]! +# CHECK: vld1.8 {d23, d24, d25}, [r6:64]! 0x9d 0x62 0x6f 0xf4 -# CHECK: vld1.32 {d22, d23, d24, d25}, [pc, :64]! +# CHECK: vld1.32 {d22, d23, d24, d25}, [pc:64]! 0x9d 0xaa 0x41 0xf4 -# CHECK: vst1.32 {d26, d27}, [r1, :64]! +# CHECK: vst1.32 {d26, d27}, [r1:64]! 0x10 0x0f 0x83 0xf2 0x50 0x0f 0x83 0xf2 diff --git a/test/MC/Disassembler/ARM/neont-VLD-reencoding.txt b/test/MC/Disassembler/ARM/neont-VLD-reencoding.txt index e53739e..6506143 100644 --- a/test/MC/Disassembler/ARM/neont-VLD-reencoding.txt +++ b/test/MC/Disassembler/ARM/neont-VLD-reencoding.txt @@ -28,13 +28,13 @@ 0xa0 0xf9 0xd0 0x04 # CHECK: vld1.16 {d0[0]}, [r0], r0 @ encoding: [0xa0,0xf9,0x00,0x04] -# CHECK: vld1.16 {d0[0]}, [r0, :16], r0 @ encoding: [0xa0,0xf9,0x10,0x04] +# CHECK: vld1.16 {d0[0]}, [r0:16], r0 @ encoding: [0xa0,0xf9,0x10,0x04] # CHECK: vld1.16 {d0[1]}, [r0], r0 @ encoding: [0xa0,0xf9,0x40,0x04] -# CHECK: vld1.16 {d0[1]}, [r0, :16], r0 @ encoding: [0xa0,0xf9,0x50,0x04] +# CHECK: vld1.16 {d0[1]}, [r0:16], r0 @ encoding: [0xa0,0xf9,0x50,0x04] # CHECK: vld1.16 {d0[2]}, [r0], r0 @ encoding: [0xa0,0xf9,0x80,0x04] -# CHECK: vld1.16 {d0[2]}, [r0, :16], r0 @ encoding: [0xa0,0xf9,0x90,0x04] +# CHECK: vld1.16 {d0[2]}, [r0:16], r0 @ encoding: [0xa0,0xf9,0x90,0x04] # CHECK: vld1.16 {d0[3]}, [r0], r0 @ encoding: [0xa0,0xf9,0xc0,0x04] -# CHECK: vld1.16 {d0[3]}, [r0, :16], r0 @ encoding: [0xa0,0xf9,0xd0,0x04] +# CHECK: vld1.16 {d0[3]}, [r0:16], r0 @ encoding: [0xa0,0xf9,0xd0,0x04] 0xa0 0xf9 0x00 0x08 0xa0 0xf9 0x30 0x08 @@ -42,20 +42,20 @@ 0xa0 0xf9 0xb0 0x08 # CHECK: vld1.32 {d0[0]}, [r0], r0 @ encoding: [0xa0,0xf9,0x00,0x08] -# CHECK: vld1.32 {d0[0]}, [r0, :32], r0 @ encoding: [0xa0,0xf9,0x30,0x08] +# CHECK: vld1.32 {d0[0]}, [r0:32], r0 @ encoding: [0xa0,0xf9,0x30,0x08] # CHECK: vld1.32 {d0[1]}, [r0], r0 @ encoding: [0xa0,0xf9,0x80,0x08] -# CHECK: vld1.32 {d0[1]}, [r0, :32], r0 @ encoding: [0xa0,0xf9,0xb0,0x08] +# CHECK: vld1.32 {d0[1]}, [r0:32], r0 @ encoding: [0xa0,0xf9,0xb0,0x08] 0xa0 0xf9 0x1f 0x04 0xa0 0xf9 0x8f 0x00 -# CHECK: vld1.16 {d0[0]}, [r0, :16] @ encoding: [0xa0,0xf9,0x1f,0x04] +# CHECK: vld1.16 {d0[0]}, [r0:16] @ encoding: [0xa0,0xf9,0x1f,0x04] # CHECK: vld1.8 {d0[4]}, [r0] @ encoding: [0xa0,0xf9,0x8f,0x00] 0xa0 0xf9 0x1d 0x04 0xa0 0xf9 0x8d 0x00 -# CHECK: vld1.16 {d0[0]}, [r0, :16]! @ encoding: [0xa0,0xf9,0x1d,0x04] +# CHECK: vld1.16 {d0[0]}, [r0:16]! @ encoding: [0xa0,0xf9,0x1d,0x04] # CHECK: vld1.8 {d0[4]}, [r0]! @ encoding: [0xa0,0xf9,0x8d,0x00] 0xa5 0xf9 0x10 0x04 @@ -63,15 +63,15 @@ 0xae 0xf9 0x1a 0x04 0xa5 0xf9 0x1a 0x94 -# CHECK: vld1.16 {d0[0]}, [r5, :16], r0 @ encoding: [0xa5,0xf9,0x10,0x04] -# CHECK: vld1.16 {d0[0]}, [r5, :16], r10 @ encoding: [0xa5,0xf9,0x1a,0x04] -# CHECK: vld1.16 {d0[0]}, [lr, :16], r10 @ encoding: [0xae,0xf9,0x1a,0x04] -# CHECK: vld1.16 {d9[0]}, [r5, :16], r10 @ encoding: [0xa5,0xf9,0x1a,0x94] +# CHECK: vld1.16 {d0[0]}, [r5:16], r0 @ encoding: [0xa5,0xf9,0x10,0x04] +# CHECK: vld1.16 {d0[0]}, [r5:16], r10 @ encoding: [0xa5,0xf9,0x1a,0x04] +# CHECK: vld1.16 {d0[0]}, [lr:16], r10 @ encoding: [0xae,0xf9,0x1a,0x04] +# CHECK: vld1.16 {d9[0]}, [r5:16], r10 @ encoding: [0xa5,0xf9,0x1a,0x94] 0xa0 0xf9 0x20 0x0b 0xa0 0xf9 0x20 0x07 0xa0 0xf9 0x20 0x03 -# CHECK: vld4.32 {d0[0], d1[0], d2[0], d3[0]}, [r0, :128], r0 @ encoding: [0xa0,0xf9,0x20,0x0b] +# CHECK: vld4.32 {d0[0], d1[0], d2[0], d3[0]}, [r0:128], r0 @ encoding: [0xa0,0xf9,0x20,0x0b] # CHECK: vld4.16 {d0[0], d2[0], d4[0], d6[0]}, [r0], r0 @ encoding: [0xa0,0xf9,0x20,0x07] # CHECK: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r0], r0 @ encoding: [0xa0,0xf9,0x20,0x03] diff --git a/test/MC/Disassembler/ARM/neont-VST-reencoding.txt b/test/MC/Disassembler/ARM/neont-VST-reencoding.txt index eb3722c..5119d92 100644 --- a/test/MC/Disassembler/ARM/neont-VST-reencoding.txt +++ b/test/MC/Disassembler/ARM/neont-VST-reencoding.txt @@ -28,13 +28,13 @@ 0xc9 0xf9 0xd9 0x94 # CHECK: vst1.16 {d0[0]}, [r0], r0 @ encoding: [0x80,0xf9,0x00,0x04] -# CHECK: vst1.16 {d16[0]}, [r3, :16], r3 @ encoding: [0xc3,0xf9,0x13,0x04] +# CHECK: vst1.16 {d16[0]}, [r3:16], r3 @ encoding: [0xc3,0xf9,0x13,0x04] # CHECK: vst1.16 {d16[1]}, [r4], r3 @ encoding: [0xc4,0xf9,0x43,0x04] -# CHECK: vst1.16 {d16[1]}, [r5, :16], r5 @ encoding: [0xc5,0xf9,0x55,0x04] +# CHECK: vst1.16 {d16[1]}, [r5:16], r5 @ encoding: [0xc5,0xf9,0x55,0x04] # CHECK: vst1.16 {d16[2]}, [r6], r5 @ encoding: [0xc6,0xf9,0x85,0x04] -# CHECK: vst1.16 {d23[2]}, [r7, :16], r5 @ encoding: [0xc7,0xf9,0x95,0x74] +# CHECK: vst1.16 {d23[2]}, [r7:16], r5 @ encoding: [0xc7,0xf9,0x95,0x74] # CHECK: vst1.16 {d24[3]}, [r8], r7 @ encoding: [0xc8,0xf9,0xc7,0x84] -# CHECK: vst1.16 {d25[3]}, [r9, :16], r9 @ encoding: [0xc9,0xf9,0xd9,0x94] +# CHECK: vst1.16 {d25[3]}, [r9:16], r9 @ encoding: [0xc9,0xf9,0xd9,0x94] 0x8a 0xf9 0x01 0xa8 0xcb 0xf9 0x32 0x18 @@ -42,20 +42,20 @@ 0xcd 0xf9 0xb4 0x28 # CHECK: vst1.32 {d10[0]}, [r10], r1 @ encoding: [0x8a,0xf9,0x01,0xa8] -# CHECK: vst1.32 {d17[0]}, [r11, :32], r2 @ encoding: [0xcb,0xf9,0x32,0x18] +# CHECK: vst1.32 {d17[0]}, [r11:32], r2 @ encoding: [0xcb,0xf9,0x32,0x18] # CHECK: vst1.32 {d11[1]}, [r12], r3 @ encoding: [0x8c,0xf9,0x83,0xb8] -# CHECK: vst1.32 {d18[1]}, [sp, :32], r4 @ encoding: [0xcd,0xf9,0xb4,0x28] +# CHECK: vst1.32 {d18[1]}, [sp:32], r4 @ encoding: [0xcd,0xf9,0xb4,0x28] 0x81 0xf9 0x1f 0x44 0x82 0xf9 0x8f 0x30 -# CHECK: vst1.16 {d4[0]}, [r1, :16] @ encoding: [0x81,0xf9,0x1f,0x44] +# CHECK: vst1.16 {d4[0]}, [r1:16] @ encoding: [0x81,0xf9,0x1f,0x44] # CHECK: vst1.8 {d3[4]}, [r2] @ encoding: [0x82,0xf9,0x8f,0x30] 0x83 0xf9 0x1d 0x24 0x84 0xf9 0x8d 0x10 -# CHECK: vst1.16 {d2[0]}, [r3, :16]! @ encoding: [0x83,0xf9,0x1d,0x24] +# CHECK: vst1.16 {d2[0]}, [r3:16]! @ encoding: [0x83,0xf9,0x1d,0x24] # CHECK: vst1.8 {d1[4]}, [r4]! @ encoding: [0x84,0xf9,0x8d,0x10] 0x85 0xf9 0x10 0x04 @@ -63,15 +63,15 @@ 0x8e 0xf9 0x1a 0x84 0x85 0xf9 0x1a 0x94 -# CHECK: vst1.16 {d0[0]}, [r5, :16], r0 @ encoding: [0x85,0xf9,0x10,0x04] -# CHECK: vst1.16 {d7[0]}, [r5, :16], r10 @ encoding: [0x85,0xf9,0x1a,0x74] -# CHECK: vst1.16 {d8[0]}, [lr, :16], r10 @ encoding: [0x8e,0xf9,0x1a,0x84] -# CHECK: vst1.16 {d9[0]}, [r5, :16], r10 @ encoding: [0x85,0xf9,0x1a,0x94] +# CHECK: vst1.16 {d0[0]}, [r5:16], r0 @ encoding: [0x85,0xf9,0x10,0x04] +# CHECK: vst1.16 {d7[0]}, [r5:16], r10 @ encoding: [0x85,0xf9,0x1a,0x74] +# CHECK: vst1.16 {d8[0]}, [lr:16], r10 @ encoding: [0x8e,0xf9,0x1a,0x84] +# CHECK: vst1.16 {d9[0]}, [r5:16], r10 @ encoding: [0x85,0xf9,0x1a,0x94] 0x81 0xf9 0x24 0x0b 0x82 0xf9 0x25 0x07 0x83 0xf9 0x26 0x03 -# CHECK: vst4.32 {d0[0], d1[0], d2[0], d3[0]}, [r1, :128], r4 @ encoding: [0x81,0xf9,0x24,0x0b] +# CHECK: vst4.32 {d0[0], d1[0], d2[0], d3[0]}, [r1:128], r4 @ encoding: [0x81,0xf9,0x24,0x0b] # CHECK: vst4.16 {d0[0], d2[0], d4[0], d6[0]}, [r2], r5 @ encoding: [0x82,0xf9,0x25,0x07] # CHECK: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r3], r6 @ encoding: [0x83,0xf9,0x26,0x03] diff --git a/test/MC/Disassembler/ARM/neont2.txt b/test/MC/Disassembler/ARM/neont2.txt index 7d7010f..3374578 100644 --- a/test/MC/Disassembler/ARM/neont2.txt +++ b/test/MC/Disassembler/ARM/neont2.txt @@ -1379,7 +1379,7 @@ # CHECK: vtbx.8 d20, {d16, d17, d18, d19}, d21 0x60 0xf9 0x1f 0x07 -# CHECK: vld1.8 {d16}, [r0, :64] +# CHECK: vld1.8 {d16}, [r0:64] 0x60 0xf9 0x4f 0x07 # CHECK: vld1.16 {d16}, [r0] 0x60 0xf9 0x8f 0x07 @@ -1387,37 +1387,37 @@ 0x60 0xf9 0xcf 0x07 # CHECK: vld1.64 {d16}, [r0] 0x60 0xf9 0x1f 0x0a -# CHECK: vld1.8 {d16, d17}, [r0, :64] +# CHECK: vld1.8 {d16, d17}, [r0:64] 0x60 0xf9 0x6f 0x0a -# CHECK: vld1.16 {d16, d17}, [r0, :128] +# CHECK: vld1.16 {d16, d17}, [r0:128] 0x60 0xf9 0x8f 0x0a # CHECK: vld1.32 {d16, d17}, [r0] 0x60 0xf9 0xcf 0x0a # CHECK: vld1.64 {d16, d17}, [r0] 0x60 0xf9 0x1f 0x08 -# CHECK: vld2.8 {d16, d17}, [r0, :64] +# CHECK: vld2.8 {d16, d17}, [r0:64] 0x60 0xf9 0x6f 0x08 -# CHECK: vld2.16 {d16, d17}, [r0, :128] +# CHECK: vld2.16 {d16, d17}, [r0:128] 0x60 0xf9 0x8f 0x08 # CHECK: vld2.32 {d16, d17}, [r0] 0x60 0xf9 0x1f 0x03 -# CHECK: vld2.8 {d16, d17, d18, d19}, [r0, :64] +# CHECK: vld2.8 {d16, d17, d18, d19}, [r0:64] 0x60 0xf9 0x6f 0x03 -# CHECK: vld2.16 {d16, d17, d18, d19}, [r0, :128] +# CHECK: vld2.16 {d16, d17, d18, d19}, [r0:128] 0x60 0xf9 0xbf 0x03 -# CHECK: vld2.32 {d16, d17, d18, d19}, [r0, :256] +# CHECK: vld2.32 {d16, d17, d18, d19}, [r0:256] 0x60 0xf9 0x1f 0x04 -# CHECK: vld3.8 {d16, d17, d18}, [r0, :64] +# CHECK: vld3.8 {d16, d17, d18}, [r0:64] 0x60 0xf9 0x4f 0x04 # CHECK: vld3.16 {d16, d17, d18}, [r0] 0x60 0xf9 0x8f 0x04 # CHECK: vld3.32 {d16, d17, d18}, [r0] 0x60 0xf9 0x1d 0x05 -# CHECK: vld3.8 {d16, d18, d20}, [r0, :64]! +# CHECK: vld3.8 {d16, d18, d20}, [r0:64]! 0x60 0xf9 0x1d 0x15 -# CHECK: vld3.8 {d17, d19, d21}, [r0, :64]! +# CHECK: vld3.8 {d17, d19, d21}, [r0:64]! 0x60 0xf9 0x4d 0x05 # CHECK: vld3.16 {d16, d18, d20}, [r0]! 0x60 0xf9 0x4d 0x15 @@ -1428,15 +1428,15 @@ # CHECK: vld3.32 {d17, d19, d21}, [r0]! 0x60 0xf9 0x1f 0x00 -# CHECK: vld4.8 {d16, d17, d18, d19}, [r0, :64] +# CHECK: vld4.8 {d16, d17, d18, d19}, [r0:64] 0x60 0xf9 0x6f 0x00 -# CHECK: vld4.16 {d16, d17, d18, d19}, [r0, :128] +# CHECK: vld4.16 {d16, d17, d18, d19}, [r0:128] 0x60 0xf9 0xbf 0x00 -# CHECK: vld4.32 {d16, d17, d18, d19}, [r0, :256] +# CHECK: vld4.32 {d16, d17, d18, d19}, [r0:256] 0x60 0xf9 0x3d 0x01 -# CHECK: vld4.8 {d16, d18, d20, d22}, [r0, :256]! +# CHECK: vld4.8 {d16, d18, d20, d22}, [r0:256]! 0x60 0xf9 0x3d 0x11 -# CHECK: vld4.8 {d17, d19, d21, d23}, [r0, :256]! +# CHECK: vld4.8 {d17, d19, d21, d23}, [r0:256]! 0x60 0xf9 0x4d 0x01 # CHECK: vld4.16 {d16, d18, d20, d22}, [r0]! 0x60 0xf9 0x4d 0x11 @@ -1449,20 +1449,20 @@ 0xe0 0xf9 0x6f 0x00 # CHECK: vld1.8 {d16[3]}, [r0] 0xe0 0xf9 0x9f 0x04 -# CHECK: vld1.16 {d16[2]}, [r0, :16] +# CHECK: vld1.16 {d16[2]}, [r0:16] 0xe0 0xf9 0xbf 0x08 -# CHECK: vld1.32 {d16[1]}, [r0, :32] +# CHECK: vld1.32 {d16[1]}, [r0:32] 0xe0 0xf9 0x3f 0x01 -# CHECK: vld2.8 {d16[1], d17[1]}, [r0, :16] +# CHECK: vld2.8 {d16[1], d17[1]}, [r0:16] 0xe0 0xf9 0x5f 0x05 -# CHECK: vld2.16 {d16[1], d17[1]}, [r0, :32] +# CHECK: vld2.16 {d16[1], d17[1]}, [r0:32] 0xe0 0xf9 0x8f 0x09 # CHECK: vld2.32 {d16[1], d17[1]}, [r0] 0xe0 0xf9 0x6f 0x15 # CHECK: vld2.16 {d17[1], d19[1]}, [r0] 0xe0 0xf9 0x5f 0x19 -# CHECK: vld2.32 {d17[0], d19[0]}, [r0, :64] +# CHECK: vld2.32 {d17[0], d19[0]}, [r0:64] 0xe0 0xf9 0x2f 0x02 # CHECK: vld3.8 {d16[1], d17[1], d18[1]}, [r0] @@ -1495,43 +1495,43 @@ # CHECK: vld3.32 {d0[], d2[], d4[]}, [r4], r5 0xe0 0xf9 0x3f 0x03 -# CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] +# CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0:32] 0xe0 0xf9 0x4f 0x07 # CHECK: vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] 0xe0 0xf9 0xaf 0x0b -# CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128] +# CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0:128] 0xe0 0xf9 0x7f 0x07 -# CHECK: vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r0, :64] +# CHECK: vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r0:64] 0xe0 0xf9 0x4f 0x1b # CHECK: vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] 0xa4 0xf9 0x0f 0x0f # CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4] 0xa4 0xf9 0x3f 0x0f -# CHECK: vld4.8 {d0[], d2[], d4[], d6[]}, [r4, :32] +# CHECK: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:32] 0xa4 0xf9 0x1d 0x0f -# CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4, :32]! +# CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:32]! 0xa4 0xf9 0x35 0x0f -# CHECK: vld4.8 {d0[], d2[], d4[], d6[]}, [r4, :32], r5 +# CHECK: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:32], r5 0xa4 0xf9 0x4f 0x0f # CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4] 0xa4 0xf9 0x7f 0x0f -# CHECK: vld4.16 {d0[], d2[], d4[], d6[]}, [r4, :64] +# CHECK: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:64] 0xa4 0xf9 0x5d 0x0f -# CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4, :64]! +# CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:64]! 0xa4 0xf9 0x75 0x0f -# CHECK: vld4.16 {d0[], d2[], d4[], d6[]}, [r4, :64], r5 +# CHECK: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:64], r5 0xa4 0xf9 0x8f 0x0f # CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4] 0xa4 0xf9 0xbf 0x0f -# CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4, :64] +# CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:64] 0xa4 0xf9 0xdd 0x0f -# CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4, :128]! +# CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:128]! 0xa4 0xf9 0xf5 0x0f -# CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4, :128], r5 +# CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:128], r5 0x40 0xf9 0x1f 0x07 -# CHECK: vst1.8 {d16}, [r0, :64] +# CHECK: vst1.8 {d16}, [r0:64] 0x40 0xf9 0x4f 0x07 # CHECK: vst1.16 {d16}, [r0] 0x40 0xf9 0x8f 0x07 @@ -1539,37 +1539,37 @@ 0x40 0xf9 0xcf 0x07 # CHECK: vst1.64 {d16}, [r0] 0x40 0xf9 0x1f 0x0a -# CHECK: vst1.8 {d16, d17}, [r0, :64] +# CHECK: vst1.8 {d16, d17}, [r0:64] 0x40 0xf9 0x6f 0x0a -# CHECK: vst1.16 {d16, d17}, [r0, :128] +# CHECK: vst1.16 {d16, d17}, [r0:128] 0x40 0xf9 0x8f 0x0a # CHECK: vst1.32 {d16, d17}, [r0] 0x40 0xf9 0xcf 0x0a # CHECK: vst1.64 {d16, d17}, [r0] 0x40 0xf9 0x1f 0x08 -# CHECK: vst2.8 {d16, d17}, [r0, :64] +# CHECK: vst2.8 {d16, d17}, [r0:64] 0x40 0xf9 0x6f 0x08 -# CHECK: vst2.16 {d16, d17}, [r0, :128] +# CHECK: vst2.16 {d16, d17}, [r0:128] 0x40 0xf9 0x8f 0x08 # CHECK: vst2.32 {d16, d17}, [r0] 0x40 0xf9 0x1f 0x03 -# CHECK: vst2.8 {d16, d17, d18, d19}, [r0, :64] +# CHECK: vst2.8 {d16, d17, d18, d19}, [r0:64] 0x40 0xf9 0x6f 0x03 -# CHECK: vst2.16 {d16, d17, d18, d19}, [r0, :128] +# CHECK: vst2.16 {d16, d17, d18, d19}, [r0:128] 0x40 0xf9 0xbf 0x03 -# CHECK: vst2.32 {d16, d17, d18, d19}, [r0, :256] +# CHECK: vst2.32 {d16, d17, d18, d19}, [r0:256] 0x40 0xf9 0x1f 0x04 -# CHECK: vst3.8 {d16, d17, d18}, [r0, :64] +# CHECK: vst3.8 {d16, d17, d18}, [r0:64] 0x40 0xf9 0x4f 0x04 # CHECK: vst3.16 {d16, d17, d18}, [r0] 0x40 0xf9 0x8f 0x04 # CHECK: vst3.32 {d16, d17, d18}, [r0] 0x40 0xf9 0x1d 0x05 -# CHECK: vst3.8 {d16, d18, d20}, [r0, :64]! +# CHECK: vst3.8 {d16, d18, d20}, [r0:64]! 0x40 0xf9 0x1d 0x15 -# CHECK: vst3.8 {d17, d19, d21}, [r0, :64]! +# CHECK: vst3.8 {d17, d19, d21}, [r0:64]! 0x40 0xf9 0x4d 0x05 # CHECK: vst3.16 {d16, d18, d20}, [r0]! 0x40 0xf9 0x4d 0x15 @@ -1580,13 +1580,13 @@ # CHECK: vst3.32 {d17, d19, d21}, [r0]! 0x40 0xf9 0x1f 0x00 -# CHECK: vst4.8 {d16, d17, d18, d19}, [r0, :64] +# CHECK: vst4.8 {d16, d17, d18, d19}, [r0:64] 0x40 0xf9 0x6f 0x00 -# CHECK: vst4.16 {d16, d17, d18, d19}, [r0, :128] +# CHECK: vst4.16 {d16, d17, d18, d19}, [r0:128] 0x40 0xf9 0x3d 0x01 -# CHECK: vst4.8 {d16, d18, d20, d22}, [r0, :256]! +# CHECK: vst4.8 {d16, d18, d20, d22}, [r0:256]! 0x40 0xf9 0x3d 0x11 -# CHECK: vst4.8 {d17, d19, d21, d23}, [r0, :256]! +# CHECK: vst4.8 {d17, d19, d21, d23}, [r0:256]! 0x40 0xf9 0x4d 0x01 # CHECK: vst4.16 {d16, d18, d20, d22}, [r0]! 0x40 0xf9 0x4d 0x11 @@ -1597,15 +1597,15 @@ # CHECK: vst4.32 {d17, d19, d21, d23}, [r0]! 0xc0 0xf9 0x3f 0x01 -# CHECK: vst2.8 {d16[1], d17[1]}, [r0, :16] +# CHECK: vst2.8 {d16[1], d17[1]}, [r0:16] 0xc0 0xf9 0x5f 0x05 -# CHECK: vst2.16 {d16[1], d17[1]}, [r0, :32] +# CHECK: vst2.16 {d16[1], d17[1]}, [r0:32] 0xc0 0xf9 0x8f 0x09 # CHECK: vst2.32 {d16[1], d17[1]}, [r0] 0xc0 0xf9 0x6f 0x15 # CHECK: vst2.16 {d17[1], d19[1]}, [r0] 0xc0 0xf9 0x5f 0x19 -# CHECK: vst2.32 {d17[0], d19[0]}, [r0, :64] +# CHECK: vst2.32 {d17[0], d19[0]}, [r0:64] 0xc0 0xf9 0x2f 0x02 # CHECK: vst3.8 {d16[1], d17[1], d18[1]}, [r0] @@ -1619,26 +1619,26 @@ # CHECK: vst3.32 {d16[0], d18[0], d20[0]}, [r0] 0xc0 0xf9 0x3f 0x03 -# CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] +# CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0:32] 0xc0 0xf9 0x4f 0x07 # CHECK: vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] 0xc0 0xf9 0xaf 0x0b -# CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128] +# CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0:128] 0xc0 0xf9 0xff 0x17 -# CHECK: vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0, :64] +# CHECK: vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0:64] 0xc0 0xf9 0x4f 0x1b # CHECK: vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] 0x63 0xf9 0x37 0xc9 -# CHECK: vld2.8 {d28, d30}, [r3, :256], r7 +# CHECK: vld2.8 {d28, d30}, [r3:256], r7 # rdar://10798451 0xe7 0xf9 0x32 0x1d -# CHECK vld2.8 {d17[], d19[]}, [r7, :16], r2 +# CHECK vld2.8 {d17[], d19[]}, [r7:16], r2 0xe7 0xf9 0x3d 0x1d -# CHECK vld2.8 {d17[], d19[]}, [r7, :16]! +# CHECK vld2.8 {d17[], d19[]}, [r7:16]! 0xe7 0xf9 0x3f 0x1d -# CHECK vld2.8 {d17[], d19[]}, [r7, :16] +# CHECK vld2.8 {d17[], d19[]}, [r7:16] # rdar://11034702 0x04 0xf9 0x0d 0x87 @@ -2046,9 +2046,9 @@ # rdar://10798451 0xe7 0xf9 0x32 0x1d -# CHECK: vld2.8 {d17[], d19[]}, [r7, :16], r2 +# CHECK: vld2.8 {d17[], d19[]}, [r7:16], r2 0xe7 0xf9 0x3d 0x1d -# CHECK: vld2.8 {d17[], d19[]}, [r7, :16]! +# CHECK: vld2.8 {d17[], d19[]}, [r7:16]! 0xe7 0xf9 0x3f 0x1d -# CHECK: vld2.8 {d17[], d19[]}, [r7, :16] +# CHECK: vld2.8 {d17[], d19[]}, [r7:16] diff --git a/test/MC/Disassembler/ARM/thumb2.txt b/test/MC/Disassembler/ARM/thumb2.txt index 45dace3..31f75b3 100644 --- a/test/MC/Disassembler/ARM/thumb2.txt +++ b/test/MC/Disassembler/ARM/thumb2.txt @@ -254,9 +254,12 @@ #------------------------------------------------------------------------------ # CHECK: cbnz r7, #6 # CHECK: cbnz r7, #12 +# CHECK: cbz r4, #64 0x1f 0xb9 0x37 0xb9 +0x04 0xb3 + #------------------------------------------------------------------------------ # CDP/CDP2 @@ -554,6 +557,7 @@ # CHECK: ldr.w r8, [r8, r2, lsl #2] # CHECK: ldr.w r7, [sp, r2, lsl #1] # CHECK: ldr.w r7, [sp, r2] +# CHECK: ldr pc, [sp], #12 # CHECK: ldr r2, [r4, #255]! # CHECK: ldr r8, [sp, #4]! # CHECK: ldr lr, [sp, #-4]! @@ -567,6 +571,7 @@ 0x58 0xf8 0x22 0x80 0x5d 0xf8 0x12 0x70 0x5d 0xf8 0x02 0x70 +0x5d 0xf8 0x0c 0xfb 0x54 0xf8 0xff 0x2f 0x5d 0xf8 0x04 0x8f 0x5d 0xf8 0x04 0xed diff --git a/test/MC/Disassembler/ARM/unpredictable-BFI.txt b/test/MC/Disassembler/ARM/unpredictable-BFI.txt new file mode 100644 index 0000000..a98f859c --- /dev/null +++ b/test/MC/Disassembler/ARM/unpredictable-BFI.txt @@ -0,0 +1,11 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | FileCheck %s + +# rdar://11437956 + +# CHECK: warning: invalid instruction encoding +# CHECK: 0x90 0x00 0xc0 0xe7 +0x90 0x00 0xc0 0xe7 + +# CHECK: warning: invalid instruction encoding +# CHECK: 0x90 0x01 0xc0 0xe7 +0x90 0x01 0xc0 0xe7 diff --git a/test/MC/Disassembler/Mips/mips32.txt b/test/MC/Disassembler/Mips/mips32.txt index a193319..7022486 100644 --- a/test/MC/Disassembler/Mips/mips32.txt +++ b/test/MC/Disassembler/Mips/mips32.txt @@ -404,3 +404,9 @@ # CHECK: xori $9, $6, 17767 0x38 0xc9 0x45 0x67 + +# CHECK: .set push +# CHECK: .set mips32r2 +# CHECK: rdhwr $5, $29 +# CHECK: .set pop +0x7c 0x05 0xe8 0x3b diff --git a/test/MC/Disassembler/Mips/mips32_le.txt b/test/MC/Disassembler/Mips/mips32_le.txt index 08b3672..48fa8e2 100644 --- a/test/MC/Disassembler/Mips/mips32_le.txt +++ b/test/MC/Disassembler/Mips/mips32_le.txt @@ -404,3 +404,9 @@ # CHECK: xori $9, $6, 17767 0x67 0x45 0xc9 0x38 + +# CHECK: .set push +# CHECK: .set mips32r2 +# CHECK: rdhwr $5, $29 +# CHECK: .set pop +0x3b 0xe8 0x05 0x7c diff --git a/test/MC/Disassembler/Mips/mips64.txt b/test/MC/Disassembler/Mips/mips64.txt index 0a88c40..38b1377 100644 --- a/test/MC/Disassembler/Mips/mips64.txt +++ b/test/MC/Disassembler/Mips/mips64.txt @@ -1,67 +1,67 @@ -# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux | FileCheck %s
-# CHECK: .section __TEXT,__text,regular,pure_instructions
-# CHECK: daddiu $11, $26, 31949
-0x67 0x4b 0x7c 0xcd
-
-# CHECK: daddu $26, $1, $11
-0x00 0x2b 0xd0 0x2d
-
-# CHECK: ddiv $zero, $26, $22
-0x03 0x56 0x00 0x1e
-
-# CHECK: ddivu $zero, $9, $24
-0x01 0x38 0x00 0x1f
-
-# CHECK: dmfc1 $2, $f14
-0x44 0x22 0x70 0x00
-
-# CHECK: dmtc1 $23, $f5
-0x44 0xb7 0x28 0x00
-
-# CHECK: dmult $11, $26
-0x01 0x7a 0x00 0x1c
-
-# CHECK: dmultu $23, $13
-0x02 0xed 0x00 0x1d
-
-# CHECK: dsll $3, $24, 17
-0x00 0x18 0x1c 0x78
-
-# CHECK: dsllv $gp, $27, $24
-0x03 0x1b 0xe0 0x14
-
-# CHECK: dsra $1, $1, 30
-0x00 0x01 0x0f 0xbb
-
-# CHECK: dsrav $1, $1, $fp
-0x03 0xc1 0x08 0x17
-
-# CHECK: dsrl $10, $gp, 24
-0x00 0x1c 0x56 0x3a
-
-# CHECK: dsrlv $gp, $10, $23
-0x02 0xea 0xe0 0x16
-
-# CHECK: dsubu $gp, $27, $24
-0x03 0x78 0xe0 0x2f
-
-# CHECK: lw $27, -15155($1)
-0x8c 0x3b 0xc4 0xcd
-
-# CHECK: lui $1, 1
-0x3c 0x01 0x00 0x01
-
-# CHECK: lwu $3, -1746($3)
-0x9c 0x63 0xf9 0x2e
-
-# CHECK: lui $ra, 1
-0x3c 0x1f 0x00 0x01
-
-# CHECK: sw $26, -15159($1)
-0xac 0x3a 0xc4 0xc9
-
-# CHECK: ld $26, 3958($zero)
-0xdc 0x1a 0x0f 0x76
-
-# CHECK: sd $6, 17767($zero)
-0xfc 0x06 0x45 0x67
+# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux | FileCheck %s +# CHECK: .section __TEXT,__text,regular,pure_instructions +# CHECK: daddiu $11, $26, 31949 +0x67 0x4b 0x7c 0xcd + +# CHECK: daddu $26, $1, $11 +0x00 0x2b 0xd0 0x2d + +# CHECK: ddiv $zero, $26, $22 +0x03 0x56 0x00 0x1e + +# CHECK: ddivu $zero, $9, $24 +0x01 0x38 0x00 0x1f + +# CHECK: dmfc1 $2, $f14 +0x44 0x22 0x70 0x00 + +# CHECK: dmtc1 $23, $f5 +0x44 0xb7 0x28 0x00 + +# CHECK: dmult $11, $26 +0x01 0x7a 0x00 0x1c + +# CHECK: dmultu $23, $13 +0x02 0xed 0x00 0x1d + +# CHECK: dsll $3, $24, 17 +0x00 0x18 0x1c 0x78 + +# CHECK: dsllv $gp, $27, $24 +0x03 0x1b 0xe0 0x14 + +# CHECK: dsra $1, $1, 30 +0x00 0x01 0x0f 0xbb + +# CHECK: dsrav $1, $1, $fp +0x03 0xc1 0x08 0x17 + +# CHECK: dsrl $10, $gp, 24 +0x00 0x1c 0x56 0x3a + +# CHECK: dsrlv $gp, $10, $23 +0x02 0xea 0xe0 0x16 + +# CHECK: dsubu $gp, $27, $24 +0x03 0x78 0xe0 0x2f + +# CHECK: lw $27, -15155($1) +0x8c 0x3b 0xc4 0xcd + +# CHECK: lui $1, 1 +0x3c 0x01 0x00 0x01 + +# CHECK: lwu $3, -1746($3) +0x9c 0x63 0xf9 0x2e + +# CHECK: lui $ra, 1 +0x3c 0x1f 0x00 0x01 + +# CHECK: sw $26, -15159($1) +0xac 0x3a 0xc4 0xc9 + +# CHECK: ld $26, 3958($zero) +0xdc 0x1a 0x0f 0x76 + +# CHECK: sd $6, 17767($zero) +0xfc 0x06 0x45 0x67 diff --git a/test/MC/Disassembler/Mips/mips64_le.txt b/test/MC/Disassembler/Mips/mips64_le.txt index fe8faff..a7ef0e4 100644 --- a/test/MC/Disassembler/Mips/mips64_le.txt +++ b/test/MC/Disassembler/Mips/mips64_le.txt @@ -1,67 +1,67 @@ -# RUN: llvm-mc --disassemble %s -triple=mips64el-unknown-linux | FileCheck %s
-# CHECK: .section __TEXT,__text,regular,pure_instructions
-# CHECK: daddiu $11, $26, 31949
-0xcd 0x7c 0x4b 0x67
-
-# CHECK: daddu $26, $1, $11
-0x2d 0xd0 0x2b 0x00
-
-# CHECK: ddiv $zero, $26, $22
-0x1e 0x00 0x56 0x03
-
-# CHECK: ddivu $zero, $9, $24
-0x1f 0x00 0x38 0x01
-
-# CHECK: dmfc1 $2, $f14
-0x00 0x70 0x22 0x44
-
-# CHECK: dmtc1 $23, $f5
-0x00 0x28 0xb7 0x44
-
-# CHECK: dmult $11, $26
-0x1c 0x00 0x7a 0x01
-
-# CHECK: dmultu $23, $13
-0x1d 0x00 0xed 0x02
-
-# CHECK: dsll $3, $24, 17
-0x78 0x1c 0x18 0x00
-
-# CHECK: dsllv $gp, $27, $24
-0x14 0xe0 0x1b 0x03
-
-# CHECK: dsra $1, $1, 30
-0xbb 0x0f 0x01 0x00
-
-# CHECK: dsrav $1, $1, $fp
-0x17 0x08 0xc1 0x03
-
-# CHECK: dsrl $10, $gp, 24
-0x3a 0x56 0x1c 0x00
-
-# CHECK: dsrlv $gp, $10, $23
-0x16 0xe0 0xea 0x02
-
-# CHECK: dsubu $gp, $27, $24
-0x2f 0xe0 0x78 0x03
-
-# CHECK: lw $27, -15155($1)
-0xcd 0xc4 0x3b 0x8c
-
-# CHECK: lui $1, 1
-0x01 0x00 0x01 0x3c
-
-# CHECK: lwu $3, -1746($3)
-0x2e 0xf9 0x63 0x9c
-
-# CHECK: lui $ra, 1
-0x01 0x00 0x1f 0x3c
-
-# CHECK: sw $26, -15159($1)
-0xc9 0xc4 0x3a 0xac
-
-# CHECK: ld $26, 3958($zero)
-0x76 0x0f 0x1a 0xdc
-
-# CHECK: sd $6, 17767($zero)
-0x67 0x45 0x06 0xfc
+# RUN: llvm-mc --disassemble %s -triple=mips64el-unknown-linux | FileCheck %s +# CHECK: .section __TEXT,__text,regular,pure_instructions +# CHECK: daddiu $11, $26, 31949 +0xcd 0x7c 0x4b 0x67 + +# CHECK: daddu $26, $1, $11 +0x2d 0xd0 0x2b 0x00 + +# CHECK: ddiv $zero, $26, $22 +0x1e 0x00 0x56 0x03 + +# CHECK: ddivu $zero, $9, $24 +0x1f 0x00 0x38 0x01 + +# CHECK: dmfc1 $2, $f14 +0x00 0x70 0x22 0x44 + +# CHECK: dmtc1 $23, $f5 +0x00 0x28 0xb7 0x44 + +# CHECK: dmult $11, $26 +0x1c 0x00 0x7a 0x01 + +# CHECK: dmultu $23, $13 +0x1d 0x00 0xed 0x02 + +# CHECK: dsll $3, $24, 17 +0x78 0x1c 0x18 0x00 + +# CHECK: dsllv $gp, $27, $24 +0x14 0xe0 0x1b 0x03 + +# CHECK: dsra $1, $1, 30 +0xbb 0x0f 0x01 0x00 + +# CHECK: dsrav $1, $1, $fp +0x17 0x08 0xc1 0x03 + +# CHECK: dsrl $10, $gp, 24 +0x3a 0x56 0x1c 0x00 + +# CHECK: dsrlv $gp, $10, $23 +0x16 0xe0 0xea 0x02 + +# CHECK: dsubu $gp, $27, $24 +0x2f 0xe0 0x78 0x03 + +# CHECK: lw $27, -15155($1) +0xcd 0xc4 0x3b 0x8c + +# CHECK: lui $1, 1 +0x01 0x00 0x01 0x3c + +# CHECK: lwu $3, -1746($3) +0x2e 0xf9 0x63 0x9c + +# CHECK: lui $ra, 1 +0x01 0x00 0x1f 0x3c + +# CHECK: sw $26, -15159($1) +0xc9 0xc4 0x3a 0xac + +# CHECK: ld $26, 3958($zero) +0x76 0x0f 0x1a 0xdc + +# CHECK: sd $6, 17767($zero) +0x67 0x45 0x06 0xfc diff --git a/test/MC/Disassembler/Mips/mips64r2.txt b/test/MC/Disassembler/Mips/mips64r2.txt index 2dfde0d..0b421fc 100644 --- a/test/MC/Disassembler/Mips/mips64r2.txt +++ b/test/MC/Disassembler/Mips/mips64r2.txt @@ -1,91 +1,91 @@ -# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux -mattr +mips64r2 | FileCheck %s
-# CHECK: .section __TEXT,__text,regular,pure_instructions
-# CHECK: daddiu $11, $26, 31949
-0x67 0x4b 0x7c 0xcd
-
-# CHECK: daddu $26, $1, $11
-0x00 0x2b 0xd0 0x2d
-
-# CHECK: ddiv $zero, $26, $22
-0x03 0x56 0x00 0x1e
-
-# CHECK: ddivu $zero, $9, $24
-0x01 0x38 0x00 0x1f
-
-# CHECK: dmfc1 $2, $f14
-0x44 0x22 0x70 0x00
-
-# CHECK: dmtc1 $23, $f5
-0x44 0xb7 0x28 0x00
-
-# CHECK: dmult $11, $26
-0x01 0x7a 0x00 0x1c
-
-# CHECK: dmultu $23, $13
-0x02 0xed 0x00 0x1d
-
-# CHECK: dsll $3, $24, 17
-0x00 0x18 0x1c 0x78
-
-# CHECK: dsllv $gp, $27, $24
-0x03 0x1b 0xe0 0x14
-
-# CHECK: dsra $1, $1, 30
-0x00 0x01 0x0f 0xbb
-
-# CHECK: dsrav $1, $1, $fp
-0x03 0xc1 0x08 0x17
-
-# CHECK: dsrl $10, $gp, 24
-0x00 0x1c 0x56 0x3a
-
-# CHECK: dsrlv $gp, $10, $23
-0x02 0xea 0xe0 0x16
-
-# CHECK: dsubu $gp, $27, $24
-0x03 0x78 0xe0 0x2f
-
-# CHECK: lw $27, -15155($1)
-0x8c 0x3b 0xc4 0xcd
-
-# CHECK: lui $1, 1
-0x3c 0x01 0x00 0x01
-
-# CHECK: lwu $3, -1746($3)
-0x9c 0x63 0xf9 0x2e
-
-# CHECK: lui $ra, 1
-0x3c 0x1f 0x00 0x01
-
-# CHECK: sw $26, -15159($1)
-0xac 0x3a 0xc4 0xc9
-
-# CHECK: ld $26, 3958($zero)
-0xdc 0x1a 0x0f 0x76
-
-# CHECK: sd $6, 17767($zero)
-0xfc 0x06 0x45 0x67
-
-# CHECK: dclo $9, $24
-0x73 0x09 0x48 0x25
-
-# CHECK: dclz $26, $9
-0x71 0x3a 0xd0 0x24
-
-# CHECK: dext $7, $gp, 29, 31
-0x7f 0x87 0xf7 0x43
-
-# CHECK: dins $20, $gp, 15, 1
-0x7f 0x94 0x7b 0xc7
-
-# CHECK: dsbh $7, $gp
-0x7c 0x1c 0x38 0xa4
-
-# CHECK: dshd $3, $14
-0x7c 0x0e 0x19 0x64
-
-# CHECK: drotr $20, $27, 6
-0x00 0x3b 0xa1 0xba
-
-# CHECK: drotrv $24, $23, $5
-0x00 0xb7 0xc0 0x56
+# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux -mattr +mips64r2 | FileCheck %s +# CHECK: .section __TEXT,__text,regular,pure_instructions +# CHECK: daddiu $11, $26, 31949 +0x67 0x4b 0x7c 0xcd + +# CHECK: daddu $26, $1, $11 +0x00 0x2b 0xd0 0x2d + +# CHECK: ddiv $zero, $26, $22 +0x03 0x56 0x00 0x1e + +# CHECK: ddivu $zero, $9, $24 +0x01 0x38 0x00 0x1f + +# CHECK: dmfc1 $2, $f14 +0x44 0x22 0x70 0x00 + +# CHECK: dmtc1 $23, $f5 +0x44 0xb7 0x28 0x00 + +# CHECK: dmult $11, $26 +0x01 0x7a 0x00 0x1c + +# CHECK: dmultu $23, $13 +0x02 0xed 0x00 0x1d + +# CHECK: dsll $3, $24, 17 +0x00 0x18 0x1c 0x78 + +# CHECK: dsllv $gp, $27, $24 +0x03 0x1b 0xe0 0x14 + +# CHECK: dsra $1, $1, 30 +0x00 0x01 0x0f 0xbb + +# CHECK: dsrav $1, $1, $fp +0x03 0xc1 0x08 0x17 + +# CHECK: dsrl $10, $gp, 24 +0x00 0x1c 0x56 0x3a + +# CHECK: dsrlv $gp, $10, $23 +0x02 0xea 0xe0 0x16 + +# CHECK: dsubu $gp, $27, $24 +0x03 0x78 0xe0 0x2f + +# CHECK: lw $27, -15155($1) +0x8c 0x3b 0xc4 0xcd + +# CHECK: lui $1, 1 +0x3c 0x01 0x00 0x01 + +# CHECK: lwu $3, -1746($3) +0x9c 0x63 0xf9 0x2e + +# CHECK: lui $ra, 1 +0x3c 0x1f 0x00 0x01 + +# CHECK: sw $26, -15159($1) +0xac 0x3a 0xc4 0xc9 + +# CHECK: ld $26, 3958($zero) +0xdc 0x1a 0x0f 0x76 + +# CHECK: sd $6, 17767($zero) +0xfc 0x06 0x45 0x67 + +# CHECK: dclo $9, $24 +0x73 0x09 0x48 0x25 + +# CHECK: dclz $26, $9 +0x71 0x3a 0xd0 0x24 + +# CHECK: dext $7, $gp, 29, 31 +0x7f 0x87 0xf7 0x43 + +# CHECK: dins $20, $gp, 15, 1 +0x7f 0x94 0x7b 0xc7 + +# CHECK: dsbh $7, $gp +0x7c 0x1c 0x38 0xa4 + +# CHECK: dshd $3, $14 +0x7c 0x0e 0x19 0x64 + +# CHECK: drotr $20, $27, 6 +0x00 0x3b 0xa1 0xba + +# CHECK: drotrv $24, $23, $5 +0x00 0xb7 0xc0 0x56 diff --git a/test/MC/Disassembler/Mips/mips64r2_le.txt b/test/MC/Disassembler/Mips/mips64r2_le.txt index 620d9eb..c1d326f 100644 --- a/test/MC/Disassembler/Mips/mips64r2_le.txt +++ b/test/MC/Disassembler/Mips/mips64r2_le.txt @@ -1,91 +1,91 @@ -# RUN: llvm-mc --disassemble %s -triple=mips64el-unknown-linux -mattr +mips64r2 | FileCheck %s
-# CHECK: .section __TEXT,__text,regular,pure_instructions
-# CHECK: daddiu $11, $26, 31949
-0xcd 0x7c 0x4b 0x67
-
-# CHECK: daddu $26, $1, $11
-0x2d 0xd0 0x2b 0x00
-
-# CHECK: ddiv $zero, $26, $22
-0x1e 0x00 0x56 0x03
-
-# CHECK: ddivu $zero, $9, $24
-0x1f 0x00 0x38 0x01
-
-# CHECK: dmfc1 $2, $f14
-0x00 0x70 0x22 0x44
-
-# CHECK: dmtc1 $23, $f5
-0x00 0x28 0xb7 0x44
-
-# CHECK: dmult $11, $26
-0x1c 0x00 0x7a 0x01
-
-# CHECK: dmultu $23, $13
-0x1d 0x00 0xed 0x02
-
-# CHECK: dsll $3, $24, 17
-0x78 0x1c 0x18 0x00
-
-# CHECK: dsllv $gp, $27, $24
-0x14 0xe0 0x1b 0x03
-
-# CHECK: dsra $1, $1, 30
-0xbb 0x0f 0x01 0x00
-
-# CHECK: dsrav $1, $1, $fp
-0x17 0x08 0xc1 0x03
-
-# CHECK: dsrl $10, $gp, 24
-0x3a 0x56 0x1c 0x00
-
-# CHECK: dsrlv $gp, $10, $23
-0x16 0xe0 0xea 0x02
-
-# CHECK: dsubu $gp, $27, $24
-0x2f 0xe0 0x78 0x03
-
-# CHECK: lw $27, -15155($1)
-0xcd 0xc4 0x3b 0x8c
-
-# CHECK: lui $1, 1
-0x01 0x00 0x01 0x3c
-
-# CHECK: lwu $3, -1746($3)
-0x2e 0xf9 0x63 0x9c
-
-# CHECK: lui $ra, 1
-0x01 0x00 0x1f 0x3c
-
-# CHECK: sw $26, -15159($1)
-0xc9 0xc4 0x3a 0xac
-
-# CHECK: ld $26, 3958($zero)
-0x76 0x0f 0x1a 0xdc
-
-# CHECK: sd $6, 17767($zero)
-0x67 0x45 0x06 0xfc
-
-# CHECK: dclo $9, $24
-0x25 0x48 0x09 0x73
-
-# CHECK: dclz $26, $9
-0x24 0xd0 0x3a 0x71
-
-# CHECK: dext $7, $gp, 29, 31
-0x43 0xf7 0x87 0x7f
-
-# CHECK: dins $20, $gp, 15, 1
-0xc7 0x7b 0x94 0x7f
-
-# CHECK: dsbh $7, $gp
-0xa4 0x38 0x1c 0x7c
-
-# CHECK: dshd $3, $14
-0x64 0x19 0x0e 0x7c
-
-# CHECK: drotr $20, $27, 6
-0xba 0xa1 0x3b 0x00
-
-# CHECK: drotrv $24, $23, $5
-0x56 0xc0 0xb7 0x00
+# RUN: llvm-mc --disassemble %s -triple=mips64el-unknown-linux -mattr +mips64r2 | FileCheck %s +# CHECK: .section __TEXT,__text,regular,pure_instructions +# CHECK: daddiu $11, $26, 31949 +0xcd 0x7c 0x4b 0x67 + +# CHECK: daddu $26, $1, $11 +0x2d 0xd0 0x2b 0x00 + +# CHECK: ddiv $zero, $26, $22 +0x1e 0x00 0x56 0x03 + +# CHECK: ddivu $zero, $9, $24 +0x1f 0x00 0x38 0x01 + +# CHECK: dmfc1 $2, $f14 +0x00 0x70 0x22 0x44 + +# CHECK: dmtc1 $23, $f5 +0x00 0x28 0xb7 0x44 + +# CHECK: dmult $11, $26 +0x1c 0x00 0x7a 0x01 + +# CHECK: dmultu $23, $13 +0x1d 0x00 0xed 0x02 + +# CHECK: dsll $3, $24, 17 +0x78 0x1c 0x18 0x00 + +# CHECK: dsllv $gp, $27, $24 +0x14 0xe0 0x1b 0x03 + +# CHECK: dsra $1, $1, 30 +0xbb 0x0f 0x01 0x00 + +# CHECK: dsrav $1, $1, $fp +0x17 0x08 0xc1 0x03 + +# CHECK: dsrl $10, $gp, 24 +0x3a 0x56 0x1c 0x00 + +# CHECK: dsrlv $gp, $10, $23 +0x16 0xe0 0xea 0x02 + +# CHECK: dsubu $gp, $27, $24 +0x2f 0xe0 0x78 0x03 + +# CHECK: lw $27, -15155($1) +0xcd 0xc4 0x3b 0x8c + +# CHECK: lui $1, 1 +0x01 0x00 0x01 0x3c + +# CHECK: lwu $3, -1746($3) +0x2e 0xf9 0x63 0x9c + +# CHECK: lui $ra, 1 +0x01 0x00 0x1f 0x3c + +# CHECK: sw $26, -15159($1) +0xc9 0xc4 0x3a 0xac + +# CHECK: ld $26, 3958($zero) +0x76 0x0f 0x1a 0xdc + +# CHECK: sd $6, 17767($zero) +0x67 0x45 0x06 0xfc + +# CHECK: dclo $9, $24 +0x25 0x48 0x09 0x73 + +# CHECK: dclz $26, $9 +0x24 0xd0 0x3a 0x71 + +# CHECK: dext $7, $gp, 29, 31 +0x43 0xf7 0x87 0x7f + +# CHECK: dins $20, $gp, 15, 1 +0xc7 0x7b 0x94 0x7f + +# CHECK: dsbh $7, $gp +0xa4 0x38 0x1c 0x7c + +# CHECK: dshd $3, $14 +0x64 0x19 0x0e 0x7c + +# CHECK: drotr $20, $27, 6 +0xba 0xa1 0x3b 0x00 + +# CHECK: drotrv $24, $23, $5 +0x56 0xc0 0xb7 0x00 diff --git a/test/MC/Disassembler/X86/enhanced.txt b/test/MC/Disassembler/X86/enhanced.txt deleted file mode 100644 index deff735..0000000 --- a/test/MC/Disassembler/X86/enhanced.txt +++ /dev/null @@ -1,10 +0,0 @@ -# RUN: llvm-mc --edis %s -triple=x86_64-apple-darwin9 2>&1 | FileCheck %s - -# CHECK: [o:jne][w: ][0-p:-][0-l:10=10] <br> 0:[RIP/112](pc)=18446744073709551606 -0x0f 0x85 0xf6 0xff 0xff 0xff -# CHECK: [o:movq][w: ][1-r:%gs=r64][1-p::][1-l:8=8][p:,][w: ][0-r:%rcx=r109] <mov> 0:[RCX/109]=0 1:[GS/64]=8 -0x65 0x48 0x8b 0x0c 0x25 0x08 0x00 0x00 0x00 -# CHECK: [o:xorps][w: ][2-r:%xmm1=r130][p:,][w: ][0-r:%xmm2=r131] 0:[XMM2/131]=0 1:[XMM2/131]=0 2:[XMM1/130]=0 -0x0f 0x57 0xd1 -# CHECK: [o:andps][w: ][2-r:%xmm1=r130][p:,][w: ][0-r:%xmm2=r131] 0:[XMM2/131]=0 1:[XMM2/131]=0 2:[XMM1/130]=0 -0x0f 0x54 0xd1 diff --git a/test/MC/Disassembler/X86/hex-immediates.txt b/test/MC/Disassembler/X86/hex-immediates.txt new file mode 100644 index 0000000..80d2448 --- /dev/null +++ b/test/MC/Disassembler/X86/hex-immediates.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --hdis %s -triple=x86_64-apple-darwin9 2>&1 | FileCheck %s + +# CHECK: movabsq $0x7fffffffffffffff, %rcx +0x48 0xb9 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x7f +# CHECK: leaq 0x3e2(%rip), %rdi +0x48 0x8d 0x3d 0xe2 0x03 0x00 0x00 +# CHECK: subq $0x40, %rsp +0x48 0x83 0xec 0x40 +# CHECK: leal (,%r14,4), %eax +0x42 0x8d 0x04 0xb5 0x00 0x00 0x00 0x00 diff --git a/test/MC/Disassembler/X86/intel-syntax-32.txt b/test/MC/Disassembler/X86/intel-syntax-32.txt new file mode 100644 index 0000000..08bae6e --- /dev/null +++ b/test/MC/Disassembler/X86/intel-syntax-32.txt @@ -0,0 +1,13 @@ +# RUN: llvm-mc --disassemble %s -triple=i386 --output-asm-variant=1 | FileCheck %s + +# CHECK: sgdt +0x0f 0x01 0x00 + +# CHECK: sidt +0x0f 0x01 0x08 + +# CHECK: lgdt +0x0f 0x01 0x10 + +# CHECK: lidt +0x0f 0x01 0x18 diff --git a/test/MC/Disassembler/X86/simple-tests.txt b/test/MC/Disassembler/X86/simple-tests.txt index 672d239..9827a18 100644 --- a/test/MC/Disassembler/X86/simple-tests.txt +++ b/test/MC/Disassembler/X86/simple-tests.txt @@ -120,13 +120,13 @@ # CHECK: vandps (%rdx), %xmm1, %xmm7 0xc5 0xf0 0x54 0x3a -# CHECK: vcvtss2sil %xmm0, %eax +# CHECK: vcvtss2si %xmm0, %eax 0xc5 0xfa 0x2d 0xc0 -# CHECK: vcvtsd2sil %xmm0, %eax +# CHECK: vcvtsd2si %xmm0, %eax 0xc5 0xfb 0x2d 0xc0 -# CHECK: vcvtsd2siq %xmm0, %rax +# CHECK: vcvtsd2si %xmm0, %rax 0xc4 0xe1 0xfb 0x2d 0xc0 # CHECK: vmaskmovpd %xmm0, %xmm1, (%rax) @@ -437,10 +437,10 @@ # CHECK: vroundsd $0, %xmm0, %xmm0, %xmm0 0xc4 0xe3 0x7d 0x0b 0xc0 0x00 -# CHECK: vcvtsd2sil %xmm0, %eax +# CHECK: vcvtsd2si %xmm0, %eax 0xc4 0xe1 0x7f 0x2d 0xc0 -# CHECK: vcvtsd2siq %xmm0, %rax +# CHECK: vcvtsd2si %xmm0, %rax 0xc4 0xe1 0xff 0x2d 0xc0 # CHECK: vucomisd %xmm1, %xmm0 @@ -753,3 +753,18 @@ # CHECK: lock # CHECK-NEXT: xaddq %rcx, %rbx 0xf0 0x48 0x0f 0xc1 0xcb + +# rdar://13493622 lldb doesn't print the x86 rep/repne prefix when disassembling +# CHECK: repne +# CHECK-NEXT: movsd +0xf2 0xa5 +# CHECK: repne +# CHECK-NEXT: movsq +0xf2 0x48 0xa5 +# CHECK: repne +# CHECK-NEXT: movb $0, (%rax) +0xf2 0xc6 0x0 0x0 +# CHECK: rep +# CHECK-NEXT: lock +# CHECK-NEXT: incl (%rax) +0xf3 0xf0 0xff 0x00 diff --git a/test/MC/Disassembler/X86/x86-32.txt b/test/MC/Disassembler/X86/x86-32.txt index 899657b..76d67d3 100644 --- a/test/MC/Disassembler/X86/x86-32.txt +++ b/test/MC/Disassembler/X86/x86-32.txt @@ -156,13 +156,13 @@ # CHECK: vandps (%edx), %xmm1, %xmm7 0xc5 0xf0 0x54 0x3a -# CHECK: vcvtss2sil %xmm0, %eax +# CHECK: vcvtss2si %xmm0, %eax 0xc5 0xfa 0x2d 0xc0 -# CHECK: vcvtsd2sil %xmm0, %eax +# CHECK: vcvtsd2si %xmm0, %eax 0xc5 0xfb 0x2d 0xc0 -# CHECK: vcvtsd2sil %xmm0, %eax +# CHECK: vcvtsd2si %xmm0, %eax 0xc4 0xe1 0x7b 0x2d 0xc0 # CHECK: vmaskmovpd %xmm0, %xmm1, (%eax) @@ -460,10 +460,10 @@ # CHECK: vroundsd $0, %xmm0, %xmm0, %xmm0 0xc4 0xe3 0x7d 0x0b 0xc0 0x00 -# CHECK: vcvtsd2sil %xmm0, %eax +# CHECK: vcvtsd2si %xmm0, %eax 0xc4 0xe1 0x7f 0x2d 0xc0 -# CHECK: vcvtsd2sil %xmm0, %eax +# CHECK: vcvtsd2si %xmm0, %eax 0xc4 0xe1 0xff 0x2d 0xc0 # CHECK: vucomisd %xmm1, %xmm0 @@ -630,3 +630,21 @@ # CHECK: movntss %xmm0, (%edi) 0xf3 0x0f 0x2b 0x07 + +# CHECK: prefetch (%eax) +0x0f 0x0d 0x00 + +# CHECK: prefetchw (%eax) +0x0f 0x0d 0x08 + +# CHECK: adcxl %eax, %eax +0x66 0x0f 0x38 0xf6 0xc0 + +# CHECK: adcxl (%eax), %eax +0x66 0x0f 0x38 0xf6 0x00 + +# CHECK: adoxl %eax, %eax +0xf3 0x0f 0x38 0xf6 0xc0 + +# CHECK: adoxl (%eax), %eax +0xf3 0x0f 0x38 0xf6 0x00 diff --git a/test/MC/Disassembler/X86/x86-64.txt b/test/MC/Disassembler/X86/x86-64.txt index df449a4..5de1d59 100644 --- a/test/MC/Disassembler/X86/x86-64.txt +++ b/test/MC/Disassembler/X86/x86-64.txt @@ -2,64 +2,64 @@ # Coverage -# CHECK: vcmptrue_usps +# CHECK: vcmptrue_usps 0xc5 0x04 0xc2 0xc7 0x1f -# CHECK: vcmptrue_uspd +# CHECK: vcmptrue_uspd 0xc5 0x05 0xc2 0xc7 0x1f -# CHECK: vcmptrue_usss +# CHECK: vcmptrue_usss 0xc5 0x06 0xc2 0xc7 0x1f -# CHECK: vcmptrue_ussd +# CHECK: vcmptrue_ussd 0xc5 0x07 0xc2 0xc7 0x1f -# CHECK: vcmpeq_uqps +# CHECK: vcmpeq_uqps 0xc5 0x04 0xc2 0xc7 0x08 -# CHECK: vcmpeq_uqpd +# CHECK: vcmpeq_uqpd 0xc5 0x05 0xc2 0xc7 0x08 -# CHECK: vcmpeq_uqss +# CHECK: vcmpeq_uqss 0xc5 0x06 0xc2 0xc7 0x08 -# CHECK: vcmpeq_uqsd +# CHECK: vcmpeq_uqsd 0xc5 0x07 0xc2 0xc7 0x08 -# CHECK: vcmpeqps +# CHECK: vcmpeqps 0xc5 0x04 0xc2 0xc7 0x00 -# CHECK: vcmpeqpd +# CHECK: vcmpeqpd 0xc5 0x05 0xc2 0xc7 0x00 -# CHECK: vcmpeqss +# CHECK: vcmpeqss 0xc5 0x06 0xc2 0xc7 0x00 -# CHECK: vcmpeqsd +# CHECK: vcmpeqsd 0xc5 0x07 0xc2 0xc7 0x00 -# CHECK: cmpeqps +# CHECK: cmpeqps 0x0f 0xc2 0xc7 0x00 -# CHECK: cmpeqpd +# CHECK: cmpeqpd 0x66 0x0f 0xc2 0xc7 0x00 -# CHECK: cmpeqss +# CHECK: cmpeqss 0xf3 0x0f 0xc2 0xc7 0x00 -# CHECK: cmpeqsd +# CHECK: cmpeqsd 0xf2 0x0f 0xc2 0xc7 0x00 -# CHECK: cmpordps +# CHECK: cmpordps 0x0f 0xc2 0xc7 0x07 -# CHECK: cmpordpd +# CHECK: cmpordpd 0x66 0x0f 0xc2 0xc7 0x07 -# CHECK: cmpordss +# CHECK: cmpordss 0xf3 0x0f 0xc2 0xc7 0x07 -# CHECK: cmpordsd +# CHECK: cmpordsd 0xf2 0x0f 0xc2 0xc7 0x07 # CHECK: extrq $2, $3, %xmm0 @@ -79,3 +79,36 @@ # CHECK: movntss %xmm0, (%rdi) 0xf3 0x0f 0x2b 0x07 + +# CHECK: adcxl %eax, %eax +0x66 0x0f 0x38 0xf6 0xc0 + +# CHECK: adcxl (%rax), %eax +0x66 0x0f 0x38 0xf6 0x00 + +# CHECK: adcxq %rax, %rax +0x66 0x48 0x0f 0x38 0xf6 0xc0 + +# CHECK: adcxq (%rax), %rax +0x66 0x48 0x0f 0x38 0xf6 0x00 + +# CHECK: adoxl %eax, %eax +0xf3 0x0f 0x38 0xf6 0xc0 + +# CHECK: adoxl (%rax), %eax +0xf3 0x0f 0x38 0xf6 0x00 + +# CHECK: adoxq %rax, %rax +0xf3 0x48 0x0f 0x38 0xf6 0xc0 + +# CHECK: adoxq (%rax), %rax +0xf3 0x48 0x0f 0x38 0xf6 0x00 + +# CHECK: xbegin 53 +0xc7 0xf8 0x35 0x00 0x00 0x00 + +# CHECK: xend +0x0f 0x01 0xd5 + +# CHECK: xabort $13 +0xc6 0xf8 0x0d diff --git a/test/MC/Disassembler/XCore/lit.local.cfg b/test/MC/Disassembler/XCore/lit.local.cfg new file mode 100644 index 0000000..15b6583 --- /dev/null +++ b/test/MC/Disassembler/XCore/lit.local.cfg @@ -0,0 +1,5 @@ +config.suffixes = ['.txt'] + +targets = set(config.root.targets_to_build.split()) +if not 'XCore' in targets: + config.unsupported = True diff --git a/test/MC/Disassembler/XCore/xcore.txt b/test/MC/Disassembler/XCore/xcore.txt new file mode 100644 index 0000000..99e54e9 --- /dev/null +++ b/test/MC/Disassembler/XCore/xcore.txt @@ -0,0 +1,695 @@ +# RUN: llvm-mc --disassemble %s -triple=xcore-xmos-elf | FileCheck %s +# CHECK: .section __TEXT,__text,regular,pure_instructions + +# 0r instructions + +# CHECK: clre +0xed 0x07 + +# CHECK: get r11, id +0xee 0x17 + +# CHECK: get r11, ed +0xfe 0x0f + +# CHECK: get r11, et +0xff 0x0f + +# CHECK: ssync +0xee 0x07 + +# CHECK: waiteu +0xec 0x07 + +# CHECK: dcall +0xfc 0x07 + +# CHECK: dentsp +0xec 0x17 + +# CHECK: drestsp +0xed 0x17 + +# CHECK: dret +0xfe 0x07 + +# CHECK: freet +0xef 0x07 + +# CHECK: get r11, kep +0xef 0x17 + +# CHECK: get r11, ksp +0xfc 0x17 + +# CHECK: kret +0xfd 0x07 + +# CHECK: ldw et, sp[4] +0xfe 0x17 + +# CHECK: ldw sed, sp[3] +0xfd 0x17 + +# CHECK: ldw spc, sp[1] +0xec 0x0f + +# CHECK: ldw ssr, sp[2] +0xee 0x0f + +# CHECK: set kep, r11 +0xff 0x07 + +# CHECK: stw et, sp[4] +0xfd 0x0f + +# CHECK: stw sed, sp[3] +0xfc 0x0f + +# CHECK: stw spc, sp[1] +0xed 0x0f + +# CHECK: stw ssr, sp[2] +0xef 0x0f + +# 1r instructions + +# CHECK: msync res[r0] +0xf0 0x1f + +# CHECK: mjoin res[r1] +0xf1 0x17 + +# CHECK: bau r2 +0xf2 0x27 + +# CHECK: set sp, r3 +0xf3 0x2f + +# CHECK: ecallt r4 +0xf4 0x4f + +# CHECK: ecallf r5 +0xe5 0x4f + +# CHECK: bla r6 +0xe6 0x27 + +# CHECK: bru r8 +0xe8 0x2f + +# CHECK: syncr res[r7] +0xf7 0x87 + +# CHECK: freer res[r8] +0xe8 0x17 + +# CHECK: setv res[r9], r11 +0xf9 0x47 + +# CHECK: setev res[r10], r11 +0xfa 0x3f + +# CHECK: eeu res[r11] +0xfb 0x07 + +# CHECK: set dp, r5 +0xe5 0x37 + +# CHECK: set cp, r0 +0xf0 0x37 + +# CHECK: dgetreg r11 +0xeb 0x3f + +# CHECK: edu res[r8] +0xe8 0x07 + +# CHECK: kcall r2 +0xe2 0x47 + +# CHECK: waitef r10 +0xfa 0x0f + +# CHECK: waitet r7 +0xe7 0x0f + +# CHECK: start t[r4] +0xe4 0x1f + +# CHECK: clrpt res[r9] +0xe9 0x87 + +# 2r instructions + +# CHECK: not r1, r8 +0x24 0x8f + +# CHECK: neg r7, r6 +0xce 0x97 + +# CHECK: andnot r10, r11 +0xab 0x2f + +# CHECK: mkmsk r11, r0 +0x4c 0xa7 + +# CHECK: getts r8, res[r1] +0x41 0x3f + +# CHECK: setpt res[r2], r3 +0xde 0x3e + +# CHECK: outct res[r1], r2 +0xc6 0x4e + +# CHECK: outt res[r5], r4 +0xd1 0x0f + +# CHECK: out res[r9], r10 +0xa9 0xaf + +# CHECK: outshr res[r0], r2 +0xd8 0xae + +# CHECK: inct r7, res[r4] +0xdc 0x87 + +# CHECK: int r8, res[r3] +0x53 0x8f + +# CHECK: in r10, res[r0] +0x48 0xb7 + +# CHECK: inshr r4, res[r2] +0x12 0xb7 + +# CHECK: chkct res[r6], r0 +0x08 0xcf + +# CHECK: testct r8, res[r3] +0x53 0xbf + +# CHECK: testwct r2, res[r9] +0x39 0xc7 + +# CHECK: setd res[r3], r4 +0x13 0x17 + +# CHECK: getst r7, res[r1] +0x1d 0x07 + +# CHECK: init t[r1]:sp, r2 +0xc9 0x16 + +# CHECK: init t[r10]:pc, r1 +0x26 0x07 + +# CHECK: init t[r2]:cp, r10 +0x4a 0x1f + +# CHECK: init t[r2]:dp, r3 +0xce 0x0e + +# CHECK: setpsc res[r8], r2 +0x28 0xc7 + +# CHECK: zext r3, r8 +0x2c 0x47 + +# CHECK: sext r9, r1 +0x45 0x37 + +# CHECK: tsetmr r7, r3 +0x1f 0x1f + +# CHECK: eef r1, res[r6] +0x96 0x2f + +# CHECK: eet r11, res[r0] +0x5c 0x27 + +# rus instructions + +# CHECK: chkct res[r1], 8 +0x34 0xcf + +# CHECK: getr r11, 2 +0x4e 0x87 + +# CHECK: mkmsk r4, 24 +0x72 0xa7 + +# CHECK: outct res[r3], 0 +0xdc 0x4e + +# CHECK: sext r8, 16 +0xb1 0x37 + +# CHECK: zext r2, 32 +0xd8 0x46 + +# CHECK: peek r0, res[r5] +0x81 0xbf + +# CHECK: endin r10, res[r1] +0x59 0x97 + +# l2r instructions + +# CHECK: bitrev r1, r10 +0x26 0xff 0xec 0x07 + +# CHECK: byterev r4, r1 +0x11 0xff 0xec 0x07 + +# CHECK: clz r11, r10 +0xae 0xff 0xec 0x0f + +# CHECK: get r3, ps[r6] +0x9e 0xff 0xec 0x17 + +# CHECK: setc res[r5], r9 +0x75 0xff 0xec 0x2f + +# CHECK: init t[r2]:lr, r1 +0xc6 0xfe 0xec 0x17 + +# CHECK: setclk res[r2], r1 +0xd6 0xfe 0xec 0x0f + +# CHECK: set ps[r9], r10 +0xa9 0xff 0xec 0x1f + +# CHECK: setrdy res[r3], r1 +0xc7 0xfe 0xec 0x2f + +# CHECK: settw res[r7], r2 +0x9b 0xff 0xec 0x27 + +# CHECK: getd r8, res[r3] +0x53 0xff 0xec 0x1f + +# CHECK: getn r10, res[r11] +0xbb 0xff 0xec 0x37 + +# CHECK: testlcl r2, res[r0] +0xc8 0xfe 0xec 0x27 + +# CHECK: setn res[r9], r7 +0x6d 0xff 0xec 0x37 + +# 3r instructions + +# CHECK: add r1, r2, r3 +0x1b 0x10 + +# CHECK: and r11, r10, r9 +0xb9 0x3e + +# CHECK: eq r6, r1, r2 +0x66 0x30 + +# CHECK: ld16s r8, r3[r4] +0xcc 0x82 + +# CHECK: ld8u r9, r1[r10] +0x16 0x8d + +# CHECK: ldw r9, r4[r5] +0x91 0x4b + +# CHECK: lss r7, r3, r0 +0x7c 0xc0 + +# CHECK: lsu r5, r8, r6 +0x12 0xcc + +# CHECK: or r1, r3, r2 +0x1e 0x40 + +# CHECK: shl r8, r2, r4 +0xc8 0x22 + +# CHECK: shr r9, r7, r1 +0x5d 0x29 + +# CHECK: sub r4, r2, r5 +0x89 0x1a + +# CHECK: set t[r0]:r1, r2 +0x18 0xb8 + +# 2rus instructions + +# CHECK: add r10, r2, 5 +0xe9 0x92 + +# CHECK: eq r2, r1, 0 +0x24 0xb0 + +# CHECK: ldw r5, r6[1] +0x19 0x09 + +# CHECK: shl r6, r5, 24 +0xa6 0xa5 + +# CHECK: shr r3, r8, 5 +0xf1 0xab + +# CHECK: stw r3, r2[0] +0x38 0x00 + +# CHECK: sub r2, r4, 11 +0x63 0x9d + +# l3r instructions + +# CHECK: ashr r5, r1, r11 +0xd7 0xfc 0xec 0x17 + +# CHECK: crc32 r5, r6, r1 +0x19 0xf9 0xec 0xaf + +# CHECK: divu r9, r1, r3 +0x97 0xf8 0xec 0x4f + +# CHECK: divs r6, r7, r2 +0x2e 0xf9 0xec 0x47 + +# CHECK: lda16 r11, r2[r1] +0xb9 0xf8 0xec 0x2f + +# CHECK: lda16 r9, r3[-r11] +0x1f 0xfd 0xec 0x37 + +# CHECK: ldaw r9, r1[r2] +0x96 0xf8 0xec 0x1f + +# CHECK: ldaw r8, r7[-r11] +0xcf 0xfd 0xec 0x27 + +# CHECK: mul r0, r4, r2 +0xc2 0xf8 0xec 0x3f + +# CHECK: remu r1, r2, r3 +0x1b 0xf8 0xec 0xcf + +# CHECK: rems r11, r10, r9 +0xb9 0xfe 0xec 0xc7 + +# CHECK: st16 r5, r3[r8] +0xdc 0xfc 0xec 0x87 + +# CHECK: st8 r9, r1[r3] +0x97 0xf8 0xec 0x8f + +# CHECK: stw r7, r10[r1] +0xf9 0xf9 0xec 0x07 + +# CHECK: xor r4, r3, r9 +0xcd 0xfc 0xec 0x0f + +# l2rus instructions + +# CHECK: ashr r5, r1, 3 +0x57 0xf8 0xec 0x97 + +# CHECK: ldaw r11, r10[6] +0x7a 0xfc 0xec 0x9f + +# CHECK: ldaw r8, r2[-9] +0x09 0xfd 0xec 0xa7 + +# CHECK: inpw r6, res[r1], 8 +0xe4 0xfc 0xee 0x97 + +# CHECK: outpw res[r3], r0, 2 +0x0e 0xf8 0xed 0x97 + +# ru6 / lru6 instructions + +# CHECK: bt r6, -5 +0x85 0x75 + +# CHECK: bt r10, -451 +0x07 0xf0 0x83 0x76 + +# CHECK: bt r8, 10 +0x0a 0x72 + +# CHECK: bt r1, 6451 +0x64 0xf0 0x73 0x70 + +# CHECK: bf r5, 8 +0x48 0x79 + +# CHECK: bf r6, 65 +0x01 0xf0 0x81 0x79 + +# CHECK: bf r1, 53 +0x75 0x78 + +# CHECK: bf r10, 101 +0x01 0xf0 0xa5 0x7a + +# CHECK: ldaw r11, dp[63] +0xff 0x62 + +# CHECK: ldaw r1, dp[456] +0x07 0xf0 0x48 0x60 + +# CHECK: ldaw cp, dp[5] +0x05 0x63 + +# CHECK: ldaw sp, dp[9929] +0x9b 0xf0 0x89 0x63 + +# CHECK: ldaw r3, sp[2] +0xc2 0x64 + +# CHECK: ldaw r8, sp[65535] +0xff 0xf3 0x3f 0x66 + +# CHECK: ldaw sp, sp[41] +0xa9 0x67 + +# CHECK: ldaw sp, sp[13121] +0xcd 0xf0 0x81 0x67 + +# CHECK: ldc r3, 30 +0xde 0x68 + +# CHECK: ldc r11, 1000 +0x0f 0xf0 0xe8 0x6a + +# CHECK: ldc sp, 0 +0x80 0x6b + +# CHECK: ldc lr, 81 +0x01 0xf0 0xd1 0x6b + +# CHECK: ldw r0, cp[4] +0x04 0x6c + +# CHECK: ldw r1, cp[32345] +0xf9 0xf1 0x59 0x6c + +# CHECK: ldw cp, cp[8] +0x08 0x6f + +# CHECK: ldw sp, cp[10222] +0x9f 0xf0 0xae 0x6f + +# CHECK: ldw r10, dp[16] +0x90 0x5a + +# CHECK: ldw r10, dp[76] +0x01 0xf0 0x8c 0x5a + +# CHECK: ldw lr, dp[8] +0xc8 0x5b + +# CHECK: ldw dp, dp[33221] +0x07 0xf2 0x45 0x5b + +# CHECK: ldw r8, sp[51] +0x33 0x5e + +# CHECK: ldw r8, sp[1225] +0x13 0xf0 0x09 0x5e + +# CHECK: ldw cp, sp[31] +0x1f 0x5f + +# CHECK: ldw sp, sp[1000] +0x0f 0xf0 0xa8 0x5f + +# CHECK: setc res[r5], 36 +0x64 0xe9 + +# CHECK: setc res[r2], 40312 +0x75 0xf2 0xb8 0xe8 + +# CHECK: stw r8, dp[14] +0x0e 0x52 + +# CHECK: stw r9, dp[654] +0x0a 0xf0 0x4e 0x52 + +# CHECK: stw lr, dp[23] +0xd7 0x53 + +# CHECK: stw sp, dp[44442] +0xb6 0xf2 0x9a 0x53 + +# CHECK: stw r1, sp[32] +0x60 0x54 + +# CHECK: stw r0, sp[8761] +0x88 0xf0 0x39 0x54 + +# CHECK: stw cp, sp[63] +0x3f 0x57 + +# CHECK: stw lr, sp[4391] +0x44 0xf0 0xe7 0x57 + +# u6 / lu6 instructions + +# CHECK: bu -20 +0x14 0x77 + +# CHECK: bu -1000 +0x0f 0xf0 0x28 0x77 + +# CHECK: bu 24 +0x18 0x73 + +# CHECK: bu 2231 +0x22 0xf0 0x37 0x73 + +# CHECK: extsp 9 +0x89 0x77 + +# CHECK: extsp 5721 +0x59 0xf0 0x99 0x77 + +# CHECK: clrsr 60 +0x3c 0x7b + +# CHECK: clrsr 64391 +0xee 0xf3 0x07 0x7b + +# CHECK: entsp 1 +0x41 0x77 + +# CHECK: entsp 70 +0x01 0xf0 0x46 0x77 + +# CHECK: ldaw r11, cp[5] +0x45 0x7f + +# CHECK: ldaw r11, cp[33000] +0x03 0xf2 0x68 0x7f + +# CHECK: retsp 40 +0xe8 0x77 + +# CHECK: retsp 52010 +0x2c 0xf3 0xea 0x77 + +# CHECK: setsr 42 +0x6a 0x7b + +# CHECK: setsr 21863 +0x55 0xf1 0x67 0x7b + +# CHECK: extdp 4 +0x84 0x73 + +# CHECK: extdp 554 +0x08 0xf0 0xaa 0x73 + +# CHECK: blat 9 +0x49 0x73 + +# CHECK: blat 61212 +0xbc 0xf3 0x5c 0x73 + +# CHECK: getsr r11, 54 +0x36 0x7f + +# CHECK: getsr r11, 442 +0x06 0xf0 0x3a 0x7f + +# CHECK: kcall 11 +0xcb 0x73 + +# CHECK: kcall 4001 +0x3e 0xf0 0xe1 0x73 + +# CHECK: kentsp 22 +0x96 0x7b + +# CHECK: kentsp 8793 +0x89 0xf0 0x99 0x7b + +# CHECK: krestsp 0 +0xc0 0x7b + +# CHECK: krestsp 55312 +0x60 0xf3 0xd0 0x7b + +# u10 / lu10 instructions + +# CHECK: ldap r11, 40 +0x28 0xd8 + +# CHECK: ldap r11, 53112 +0x33 0xf0 0x78 0xdb + +# CHECK: bl 8 +0x08 0xd0 + +# CHECK: bl 38631 +0x25 0xf0 0xe7 0xd2 + +# CHECK: bla cp[500] +0xf4 0xe1 + +# CHECK: bla cp[413742] +0x94 0xf1 0x2e 0xe0 + +# CHECK: ldw r11, cp[132] +0x84 0xe4 + +# CHECK: ldw r11, cp[102741] +0x64 0xf0 0x55 0xe5 + +# l6r instructions + +# CHECK: lmul r11, r0, r2, r5, r8, r10 +0xf9 0xfa 0x02 0x06 + +# l5r instructions + +# CHECK: ladd r10, r2, r5, r1, r7 +0xe5 0xf8 0xfb 0x06 + +# CHECK: ldivu r5, r6, r3, r9, r8 +0x54 0xfe 0x0b 0x07 + +# CHECK: lsub r1, r8, r7, r11, r5 +0xcf 0xfd 0x85 0x0f + +# l4r instructions + +# CHECK: crc8 r6, r3, r4, r11 +0x73 0xfd 0xe6 0x07 + +# CHECK: maccs r11, r8, r2, r4 +0xf8 0xfa 0xe8 0x0f + +# CHECK: maccu r0, r2, r5, r8 +0x44 0xfd 0xf2 0x07 |
