diff options
Diffstat (limited to 'test/MC/Disassembler/ARM')
25 files changed, 1003 insertions, 66 deletions
diff --git a/test/MC/Disassembler/ARM/arm-tests.txt b/test/MC/Disassembler/ARM/arm-tests.txt index 69a094d..ce1446b 100644 --- a/test/MC/Disassembler/ARM/arm-tests.txt +++ b/test/MC/Disassembler/ARM/arm-tests.txt @@ -201,7 +201,7 @@ 0x20 0x51 0x17 0xe6 # CHECK: strdeq r2, r3, [r0], -r8 -0xf8 0x24 0x00 0x00 +0xf8 0x20 0x00 0x00 # CHECK: ldrdeq r2, r3, [r0], -r12 0xdc 0x24 0x00 0x00 @@ -215,7 +215,7 @@ # CHECK: vldmdb r2!, {s7, s8, s9, s10, s11} 0x05 0x3a 0x72 0xed -# CHECK: vldr.32 s23, [r2, #660] +# CHECK: vldr s23, [r2, #660] 0xa5 0xba 0xd2 0xed # CHECK: strtvc r5, [r3], r0, lsr #20 @@ -317,3 +317,7 @@ # CHECK: stc2l p0, c0, [r2], #-96 0x18 0x0 0x62 0xfc + +# CHECK: ldmgt sp!, {r9} +0x00 0x02 0xbd 0xc8 + diff --git a/test/MC/Disassembler/ARM/dg.exp b/test/MC/Disassembler/ARM/dg.exp deleted file mode 100644 index fc2f17a..0000000 --- a/test/MC/Disassembler/ARM/dg.exp +++ /dev/null @@ -1,6 +0,0 @@ -load_lib llvm.exp - -if { [llvm_supports_target ARM] } { - RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{txt}]] -} - diff --git a/test/MC/Disassembler/ARM/fp-encoding.txt b/test/MC/Disassembler/ARM/fp-encoding.txt index f3e0261..9095b84 100644 --- a/test/MC/Disassembler/ARM/fp-encoding.txt +++ b/test/MC/Disassembler/ARM/fp-encoding.txt @@ -152,46 +152,46 @@ # CHECK: vmov r0, r1, d16 0x00 0x1b 0xd0 0xed -# CHECK: vldr.64 d17, [r0] +# CHECK: vldr d17, [r0] 0x08 0x1b 0x92 0xed 0x08 0x1b 0x12 0xed -# CHECK: vldr.64 d1, [r2, #32] -# CHECK: vldr.64 d1, [r2, #-32] +# CHECK: vldr d1, [r2, #32] +# CHECK: vldr d1, [r2, #-32] 0x00 0x2b 0x93 0xed -# CHECK: vldr.64 d2, [r3] +# CHECK: vldr d2, [r3] 0x00 0x3b 0x9f 0xed -# CHECK: vldr.64 d3, [pc] +# CHECK: vldr d3, [pc] 0x00 0x6a 0xd0 0xed -# CHECK: vldr.32 s13, [r0] +# CHECK: vldr s13, [r0] 0x08 0x0a 0xd2 0xed 0x08 0x0a 0x52 0xed -# CHECK: vldr.32 s1, [r2, #32] -# CHECK: vldr.32 s1, [r2, #-32] +# CHECK: vldr s1, [r2, #32] +# CHECK: vldr s1, [r2, #-32] 0x00 0x1a 0x93 0xed -# CHECK: vldr.32 s2, [r3] +# CHECK: vldr s2, [r3] 0x00 0x2a 0xdf 0xed -# CHECK: vldr.32 s5, [pc] +# CHECK: vldr s5, [pc] 0x00 0x4b 0x81 0xed 0x06 0x4b 0x81 0xed 0x06 0x4b 0x01 0xed -# CHECK: vstr.64 d4, [r1] -# CHECK: vstr.64 d4, [r1, #24] -# CHECK: vstr.64 d4, [r1, #-24] +# CHECK: vstr d4, [r1] +# CHECK: vstr d4, [r1, #24] +# CHECK: vstr d4, [r1, #-24] 0x00 0x2a 0x81 0xed 0x06 0x2a 0x81 0xed 0x06 0x2a 0x01 0xed -# CHECK: vstr.32 s4, [r1] -# CHECK: vstr.32 s4, [r1, #24] -# CHECK: vstr.32 s4, [r1, #-24] +# CHECK: vstr s4, [r1] +# CHECK: vstr s4, [r1, #24] +# CHECK: vstr s4, [r1, #-24] 0x0c 0x2b 0x91 0xec 0x06 0x1a 0x91 0xec diff --git a/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt b/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt index 6fdb55e..8146b5c 100644 --- a/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt @@ -1,4 +1,4 @@ # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {potentially undefined instruction encoding} # invalid (imod, M, iflags) combination -0x93 0x1c 0x02 0xf1 +0x93 0x00 0x02 0xf1 diff --git a/test/MC/Disassembler/ARM/invalid-IT-CC15.txt b/test/MC/Disassembler/ARM/invalid-IT-CC15.txt new file mode 100644 index 0000000..17e25ea --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-IT-CC15.txt @@ -0,0 +1,18 @@ +# RUN: llvm-mc --disassemble %s -triple=thumbv7-unknown-unknown |& grep und +# rdar://10841671 + +0xe3 0xbf +0xdf 0xed 0x61 0x3b +0x71 0xee 0xe0 0x1b +0x72 0xee 0xa3 0x2b +0xdf 0xed 0x60 0x0b + +# This is test is dealing with a undefined condition code value of 15 in the +# above sequence of junk bytes and not allowing the disassembler to abort on +# printing the final instruction in this list. +# +# ittte al +# vldr d19, [pc, #388] +# vsub.f64 d17, d17, d16 +# vadd.f64 d18, d18, d19 +# vldr<und> d16, [pc, #384] diff --git a/test/MC/Disassembler/ARM/invalid-LDRT-arm.txt b/test/MC/Disassembler/ARM/invalid-LDRT-arm.txt deleted file mode 100644 index 067dcb3..0000000 --- a/test/MC/Disassembler/ARM/invalid-LDRT-arm.txt +++ /dev/null @@ -1,12 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} - -# Opcode=0 Name=PHI Format=(42) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 0| 0: 1: 1: 0| 0: 0: 1: 1| 0: 1: 1: 1| 0: 1: 0: 1| 0: 0: 0: 1| 0: 0: 0: 1| 0: 0: 0: 0| -# ------------------------------------------------------------------------------------------------- -# -# The bytes have Inst{4} = 1, so it's not an LDRT Encoding A2 instruction. -0x10 0x51 0x37 0xe6 - - diff --git a/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt b/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt new file mode 100644 index 0000000..8ff3a2b --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt @@ -0,0 +1,13 @@ +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=1839 Name=VST1d8Twb_register Format=ARM_FORMAT_NLdSt(30) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 1: 0: 0: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 1: 1: 0| 0: 0: 1: 0| 1: 1: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# A8.6.391 VST1 (multiple single elements) +# This encoding looks like: vst1.8 {d0,d1,d2}, [r0, :128] +# But bits 5-4 for the alignment of 128 encoded as align = 0b10, is available only if <list> +# contains two or four registers. rdar://11220250 +0x00 0xf9 0x2f 0x06 diff --git a/test/MC/Disassembler/ARM/ldrd-armv4.txt b/test/MC/Disassembler/ARM/ldrd-armv4.txt new file mode 100644 index 0000000..bb87ade --- /dev/null +++ b/test/MC/Disassembler/ARM/ldrd-armv4.txt @@ -0,0 +1,15 @@ +# RUN: llvm-mc --disassemble %s -triple=armv4-linux-gnueabi |& FileCheck %s -check-prefix=V4 +# RUN: llvm-mc --disassemble %s -triple=armv5te-linux-gnueabi |& FileCheck %s -check-prefix=V5TE + +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| X: X: X: 1| X: X: X: X| 1: 1: X: 1| X: X: X: X| +# ------------------------------------------------------------------------------------------------- +# +# A8.6.68 LDRD (register) +# if Rt{0} = 1 then UNDEFINED; + +# V4: invalid instruction encoding +# V5TE: ldrd +0xd0 0x10 0x00 0x01 + diff --git a/test/MC/Disassembler/ARM/lit.local.cfg b/test/MC/Disassembler/ARM/lit.local.cfg new file mode 100644 index 0000000..22a76e5 --- /dev/null +++ b/test/MC/Disassembler/ARM/lit.local.cfg @@ -0,0 +1,6 @@ +config.suffixes = ['.txt'] + +targets = set(config.root.targets_to_build.split()) +if not 'ARM' in targets: + config.unsupported = True + diff --git a/test/MC/Disassembler/ARM/neon-tests.txt b/test/MC/Disassembler/ARM/neon-tests.txt index 1e03deb..f44c2a0 100644 --- a/test/MC/Disassembler/ARM/neon-tests.txt +++ b/test/MC/Disassembler/ARM/neon-tests.txt @@ -30,7 +30,7 @@ # CHECK: vorr d0, d15, d15 0x1f 0x01 0x2f 0xf2 -# CHECK: vmov.i64 q6, #0xFF00FF00FF +# CHECK: vmov.i64 q6, #0xff00ff00ff 0x75 0xce 0x81 0xf2 # CHECK: vmvn.i32 d0, #0x0 @@ -69,10 +69,10 @@ # CHECK: vpop {d8} 0x02 0x8b 0xbd 0xec -# CHECK: vorr.i32 q15, #0x4F0000 +# CHECK: vorr.i32 q15, #0x4f0000 0x5f 0xe5 0xc4 0xf2 -# CHECK: vbic.i32 q2, #0xA900 +# CHECK: vbic.i32 q2, #0xa900 0x79 0x43 0x82 0xf3 # CHECK: vst2.32 {d16, d18}, [r2, :64], r2 diff --git a/test/MC/Disassembler/ARM/neon.txt b/test/MC/Disassembler/ARM/neon.txt index 5d2df93..58fe20e 100644 --- a/test/MC/Disassembler/ARM/neon.txt +++ b/test/MC/Disassembler/ARM/neon.txt @@ -307,9 +307,9 @@ 0xf2 0x01 0x50 0xf2 # CHECK: vbic q8, q8, q9 0x3f 0x07 0xc7 0xf3 -# CHECK: vbic.i32 d16, #0xFF000000 +# CHECK: vbic.i32 d16, #0xff000000 0x7f 0x07 0xc7 0xf3 -# CHECK: vbic.i32 q8, #0xFF000000 +# CHECK: vbic.i32 q8, #0xff000000 0xb0 0x01 0x71 0xf2 # CHECK: vorn d16, d17, d16 @@ -587,11 +587,11 @@ 0x10 0x06 0xc2 0xf2 # CHECK: vmov.i32 d16, #0x20000000 0x10 0x0c 0xc2 0xf2 -# CHECK: vmov.i32 d16, #0x20FF +# CHECK: vmov.i32 d16, #0x20ff 0x10 0x0d 0xc2 0xf2 -# CHECK: vmov.i32 d16, #0x20FFFF +# CHECK: vmov.i32 d16, #0x20ffff 0x33 0x0e 0xc1 0xf3 -# CHECK: vmov.i64 d16, #0xFF0000FF0000FFFF +# CHECK: vmov.i64 d16, #0xff0000ff0000ffff 0x58 0x0e 0xc0 0xf2 # CHECK: vmov.i8 q8, #0x8 0x50 0x08 0xc1 0xf2 @@ -607,11 +607,11 @@ 0x50 0x06 0xc2 0xf2 # CHECK: vmov.i32 q8, #0x20000000 0x50 0x0c 0xc2 0xf2 -# CHECK: vmov.i32 q8, #0x20FF +# CHECK: vmov.i32 q8, #0x20ff 0x50 0x0d 0xc2 0xf2 -# CHECK: vmov.i32 q8, #0x20FFFF +# CHECK: vmov.i32 q8, #0x20ffff 0x73 0x0e 0xc1 0xf3 -# CHECK: vmov.i64 q8, #0xFF0000FF0000FFFF +# CHECK: vmov.i64 q8, #0xff0000ff0000ffff 0x30 0x08 0xc1 0xf2 # CHECK: vmvn.i16 d16, #0x10 0x30 0x0a 0xc1 0xf2 @@ -625,9 +625,9 @@ 0x30 0x06 0xc2 0xf2 # CHECK: vmvn.i32 d16, #0x20000000 0x30 0x0c 0xc2 0xf2 -# CHECK: vmvn.i32 d16, #0x20FF +# CHECK: vmvn.i32 d16, #0x20ff 0x30 0x0d 0xc2 0xf2 -# CHECK: vmvn.i32 d16, #0x20FFFF +# CHECK: vmvn.i32 d16, #0x20ffff 0x30 0x0a 0xc8 0xf2 # CHECK: vmovl.s8 q8, d16 0x30 0x0a 0xd0 0xf2 @@ -1856,3 +1856,390 @@ 0xe9 0x1a 0xb2 0x4e # CHECK: vcvttmi.f32.f16 s2, s19 + +0x1d 0x76 0x66 0xf4 +# CHECK: vld1.8 {d23, d24, d25}, [r6, :64]! +0x9d 0x62 0x6f 0xf4 +# CHECK: vld1.32 {d22, d23, d24, d25}, [pc, :64]! +0x9d 0xaa 0x41 0xf4 +# CHECK: vst1.32 {d26, d27}, [r1, :64]! + +0x10 0x0f 0x83 0xf2 +0x50 0x0f 0x83 0xf2 +# CHECK: vmov.f32 d0, #1.600000e+01 +# CHECK: vmov.f32 q0, #1.600000e+01 + +# rdar://10798451 +0xe7 0xf9 0x32 0x1d +# CHECK vld2.8 {d17[], d19[]}, [r7, :16], r2 +0xe7 0xf9 0x3d 0x1d +# CHECK vld2.8 {d17[], d19[]}, [r7, :16]! +0xe7 0xf9 0x3f 0x1d +# CHECK vld2.8 {d17[], d19[]}, [r7, :16] + +# rdar://11034702 +0x0d 0x87 0x04 0xf4 +# CHECK: vst1.8 {d8}, [r4]! +0x4d 0x87 0x04 0xf4 +# CHECK: vst1.16 {d8}, [r4]! +0x8d 0x87 0x04 0xf4 +# CHECK: vst1.32 {d8}, [r4]! +0xcd 0x87 0x04 0xf4 +# CHECK: vst1.64 {d8}, [r4]! +0x06 0x87 0x04 0xf4 +# CHECK: vst1.8 {d8}, [r4], r6 +0x46 0x87 0x04 0xf4 +# CHECK: vst1.16 {d8}, [r4], r6 +0x86 0x87 0x04 0xf4 +# CHECK: vst1.32 {d8}, [r4], r6 +0xc6 0x87 0x04 0xf4 +# CHECK: vst1.64 {d8}, [r4], r6 + +0x0d 0x8a 0x04 0xf4 +# CHECK: vst1.8 {d8, d9}, [r4]! +0x4d 0x8a 0x04 0xf4 +# CHECK: vst1.16 {d8, d9}, [r4]! +0x8d 0x8a 0x04 0xf4 +# CHECK: vst1.32 {d8, d9}, [r4]! +0xcd 0x8a 0x04 0xf4 +# CHECK: vst1.64 {d8, d9}, [r4]! +0x06 0x8a 0x04 0xf4 +# CHECK: vst1.8 {d8, d9}, [r4], r6 +0x46 0x8a 0x04 0xf4 +# CHECK: vst1.16 {d8, d9}, [r4], r6 +0x86 0x8a 0x04 0xf4 +# CHECK: vst1.32 {d8, d9}, [r4], r6 +0xc6 0x8a 0x04 0xf4 +# CHECK: vst1.64 {d8, d9}, [r4], r6 + +0x0d 0x86 0x04 0xf4 +# CHECK: vst1.8 {d8, d9, d10}, [r4]! +0x4d 0x86 0x04 0xf4 +# CHECK: vst1.16 {d8, d9, d10}, [r4]! +0x8d 0x86 0x04 0xf4 +# CHECK: vst1.32 {d8, d9, d10}, [r4]! +0xcd 0x86 0x04 0xf4 +# CHECK: vst1.64 {d8, d9, d10}, [r4]! +0x06 0x86 0x04 0xf4 +# CHECK: vst1.8 {d8, d9, d10}, [r4], r6 +0x46 0x86 0x04 0xf4 +# CHECK: vst1.16 {d8, d9, d10}, [r4], r6 +0x86 0x86 0x04 0xf4 +# CHECK: vst1.32 {d8, d9, d10}, [r4], r6 +0xc6 0x86 0x04 0xf4 +# CHECK: vst1.64 {d8, d9, d10}, [r4], r6 + +0x0d 0x82 0x04 0xf4 +# CHECK: vst1.8 {d8, d9, d10, d11}, [r4]! +0x4d 0x82 0x04 0xf4 +# CHECK: vst1.16 {d8, d9, d10, d11}, [r4]! +0x8d 0x82 0x04 0xf4 +# CHECK: vst1.32 {d8, d9, d10, d11}, [r4]! +0xcd 0x82 0x04 0xf4 +# CHECK: vst1.64 {d8, d9, d10, d11}, [r4]! +0x06 0x82 0x04 0xf4 +# CHECK: vst1.8 {d8, d9, d10, d11}, [r4], r6 +0x46 0x82 0x04 0xf4 +# CHECK: vst1.16 {d8, d9, d10, d11}, [r4], r6 +0x86 0x82 0x04 0xf4 +# CHECK: vst1.32 {d8, d9, d10, d11}, [r4], r6 +0xc6 0x82 0x04 0xf4 +# CHECK: vst1.64 {d8, d9, d10, d11}, [r4], r6 + +0x0d 0x88 0x04 0xf4 +# CHECK: vst2.8 {d8, d9}, [r4]! +0x4d 0x88 0x04 0xf4 +# CHECK: vst2.16 {d8, d9}, [r4]! +0x8d 0x88 0x04 0xf4 +# CHECK: vst2.32 {d8, d9}, [r4]! +0x06 0x88 0x04 0xf4 +# CHECK: vst2.8 {d8, d9}, [r4], r6 +0x46 0x88 0x04 0xf4 +# CHECK: vst2.16 {d8, d9}, [r4], r6 +0x86 0x88 0x04 0xf4 +# CHECK: vst2.32 {d8, d9}, [r4], r6 + +0x0d 0x89 0x04 0xf4 +# CHECK: vst2.8 {d8, d10}, [r4]! +0x4d 0x89 0x04 0xf4 +# CHECK: vst2.16 {d8, d10}, [r4]! +0x8d 0x89 0x04 0xf4 +# CHECK: vst2.32 {d8, d10}, [r4]! +0x06 0x89 0x04 0xf4 +# CHECK: vst2.8 {d8, d10}, [r4], r6 +0x46 0x89 0x04 0xf4 +# CHECK: vst2.16 {d8, d10}, [r4], r6 +0x86 0x89 0x04 0xf4 +# CHECK: vst2.32 {d8, d10}, [r4], r6 + +0x0d 0x84 0x04 0xf4 +# CHECK: vst3.8 {d8, d9, d10}, [r4]! +0x4d 0x84 0x04 0xf4 +# CHECK: vst3.16 {d8, d9, d10}, [r4]! +0x8d 0x84 0x04 0xf4 +# CHECK: vst3.32 {d8, d9, d10}, [r4]! +0x06 0x85 0x04 0xf4 +# CHECK: vst3.8 {d8, d10, d12}, [r4], r6 +0x46 0x85 0x04 0xf4 +# CHECK: vst3.16 {d8, d10, d12}, [r4], r6 +0x86 0x85 0x04 0xf4 +# CHECK: vst3.32 {d8, d10, d12}, [r4], r6 + +0x0d 0x80 0x04 0xf4 +# CHECK: vst4.8 {d8, d9, d10, d11}, [r4]! +0x4d 0x80 0x04 0xf4 +# CHECK: vst4.16 {d8, d9, d10, d11}, [r4]! +0x8d 0x80 0x04 0xf4 +# CHECK: vst4.32 {d8, d9, d10, d11}, [r4]! +0x06 0x81 0x04 0xf4 +# CHECK: vst4.8 {d8, d10, d12, d14}, [r4], r6 +0x46 0x81 0x04 0xf4 +# CHECK: vst4.16 {d8, d10, d12, d14}, [r4], r6 +0x86 0x81 0x04 0xf4 +# CHECK: vst4.32 {d8, d10, d12, d14}, [r4], r6 + +0x4f 0x8a 0x04 0xf4 +# CHECK: vst1.16 {d8, d9}, [r4] +0x8f 0x8a 0x04 0xf4 +# CHECK: vst1.32 {d8, d9}, [r4] +0xcf 0x8a 0x04 0xf4 +# CHECK: vst1.64 {d8, d9}, [r4] +0x0f 0x8a 0x04 0xf4 +# CHECK: vst1.8 {d8, d9}, [r4] + +0x4f 0x88 0x04 0xf4 +# CHECK: vst2.16 {d8, d9}, [r4] +0x8f 0x88 0x04 0xf4 +# CHECK: vst2.32 {d8, d9}, [r4] +0x0f 0x88 0x04 0xf4 +# CHECK: vst2.8 {d8, d9}, [r4] + +0x4d 0x88 0x04 0xf4 +# CHECK: vst2.16 {d8, d9}, [r4]! +0x46 0x88 0x04 0xf4 +# CHECK: vst2.16 {d8, d9}, [r4], r6 +0x8d 0x88 0x04 0xf4 +# CHECK: vst2.32 {d8, d9}, [r4]! +0x86 0x88 0x04 0xf4 +# CHECK: vst2.32 {d8, d9}, [r4], r6 +0x0d 0x88 0x04 0xf4 +# CHECK: vst2.8 {d8, d9}, [r4]! +0x06 0x88 0x04 0xf4 +# CHECK: vst2.8 {d8, d9}, [r4], r6 + +0x4f 0x89 0x04 0xf4 +# CHECK: vst2.16 {d8, d10}, [r4] +0x8f 0x89 0x04 0xf4 +# CHECK: vst2.32 {d8, d10}, [r4] +0x0f 0x89 0x04 0xf4 +# CHECK: vst2.8 {d8, d10}, [r4] + +0x0f 0x84 0x04 0xf4 +# CHECK: vst3.8 {d8, d9, d10}, [r4] +0x4f 0x84 0x04 0xf4 +# CHECK: vst3.16 {d8, d9, d10}, [r4] +0x8f 0x84 0x04 0xf4 +# CHECK: vst3.32 {d8, d9, d10}, [r4] + +0x0f 0x80 0x04 0xf4 +# CHECK: vst4.8 {d8, d9, d10, d11}, [r4] +0x4f 0x80 0x04 0xf4 +# CHECK: vst4.16 {d8, d9, d10, d11}, [r4] +0x8f 0x80 0x04 0xf4 +# CHECK: vst4.32 {d8, d9, d10, d11}, [r4] + +0x0f 0x85 0x04 0xf4 +# CHECK: vst3.8 {d8, d10, d12}, [r4] +0x4f 0x85 0x04 0xf4 +# CHECK: vst3.16 {d8, d10, d12}, [r4] +0x8f 0x85 0x04 0xf4 +# CHECK: vst3.32 {d8, d10, d12}, [r4] + +0x0f 0x81 0x04 0xf4 +# CHECK: vst4.8 {d8, d10, d12, d14}, [r4] +0x4f 0x81 0x04 0xf4 +# CHECK: vst4.16 {d8, d10, d12, d14}, [r4] +0x8f 0x81 0x04 0xf4 +# CHECK: vst4.32 {d8, d10, d12, d14}, [r4] + +# rdar://11204059 +0x0d 0x87 0x24 0xf4 +# CHECK: vld1.8 {d8}, [r4]! +0x4d 0x87 0x24 0xf4 +# CHECK: vld1.16 {d8}, [r4]! +0x8d 0x87 0x24 0xf4 +# CHECK: vld1.32 {d8}, [r4]! +0xcd 0x87 0x24 0xf4 +# CHECK: vld1.64 {d8}, [r4]! +0x06 0x87 0x24 0xf4 +# CHECK: vld1.8 {d8}, [r4], r6 +0x46 0x87 0x24 0xf4 +# CHECK: vld1.16 {d8}, [r4], r6 +0x86 0x87 0x24 0xf4 +# CHECK: vld1.32 {d8}, [r4], r6 +0xc6 0x87 0x24 0xf4 +# CHECK: vld1.64 {d8}, [r4], r6 +0x0d 0x8a 0x24 0xf4 +# CHECK: vld1.8 {d8, d9}, [r4]! +0x4d 0x8a 0x24 0xf4 +# CHECK: vld1.16 {d8, d9}, [r4]! +0x8d 0x8a 0x24 0xf4 +# CHECK: vld1.32 {d8, d9}, [r4]! +0xcd 0x8a 0x24 0xf4 +# CHECK: vld1.64 {d8, d9}, [r4]! +0x06 0x8a 0x24 0xf4 +# CHECK: vld1.8 {d8, d9}, [r4], r6 +0x46 0x8a 0x24 0xf4 +# CHECK: vld1.16 {d8, d9}, [r4], r6 +0x86 0x8a 0x24 0xf4 +# CHECK: vld1.32 {d8, d9}, [r4], r6 +0xc6 0x8a 0x24 0xf4 +# CHECK: vld1.64 {d8, d9}, [r4], r6 +0x0d 0x86 0x24 0xf4 +# CHECK: vld1.8 {d8, d9, d10}, [r4]! +0x4d 0x86 0x24 0xf4 +# CHECK: vld1.16 {d8, d9, d10}, [r4]! +0x8d 0x86 0x24 0xf4 +# CHECK: vld1.32 {d8, d9, d10}, [r4]! +0xcd 0x86 0x24 0xf4 +# CHECK: vld1.64 {d8, d9, d10}, [r4]! +0x06 0x86 0x24 0xf4 +# CHECK: vld1.8 {d8, d9, d10}, [r4], r6 +0x46 0x86 0x24 0xf4 +# CHECK: vld1.16 {d8, d9, d10}, [r4], r6 +0x86 0x86 0x24 0xf4 +# CHECK: vld1.32 {d8, d9, d10}, [r4], r6 +0xc6 0x86 0x24 0xf4 +# CHECK: vld1.64 {d8, d9, d10}, [r4], r6 +0x0d 0x82 0x24 0xf4 +# CHECK: vld1.8 {d8, d9, d10, d11}, [r4]! +0x4d 0x82 0x24 0xf4 +# CHECK: vld1.16 {d8, d9, d10, d11}, [r4]! +0x8d 0x82 0x24 0xf4 +# CHECK: vld1.32 {d8, d9, d10, d11}, [r4]! +0xcd 0x82 0x24 0xf4 +# CHECK: vld1.64 {d8, d9, d10, d11}, [r4]! +0x06 0x82 0x24 0xf4 +# CHECK: vld1.8 {d8, d9, d10, d11}, [r4], r6 +0x46 0x82 0x24 0xf4 +# CHECK: vld1.16 {d8, d9, d10, d11}, [r4], r6 +0x86 0x82 0x24 0xf4 +# CHECK: vld1.32 {d8, d9, d10, d11}, [r4], r6 +0xc6 0x82 0x24 0xf4 +# CHECK: vld1.64 {d8, d9, d10, d11}, [r4], r6 +0x0d 0x88 0x24 0xf4 +# CHECK: vld2.8 {d8, d9}, [r4]! +0x4d 0x88 0x24 0xf4 +# CHECK: vld2.16 {d8, d9}, [r4]! +0x8d 0x88 0x24 0xf4 +# CHECK: vld2.32 {d8, d9}, [r4]! +0x06 0x88 0x24 0xf4 +# CHECK: vld2.8 {d8, d9}, [r4], r6 +0x46 0x88 0x24 0xf4 +# CHECK: vld2.16 {d8, d9}, [r4], r6 +0x86 0x88 0x24 0xf4 +# CHECK: vld2.32 {d8, d9}, [r4], r6 +0x0d 0x89 0x24 0xf4 +# CHECK: vld2.8 {d8, d10}, [r4]! +0x4d 0x89 0x24 0xf4 +# CHECK: vld2.16 {d8, d10}, [r4]! +0x8d 0x89 0x24 0xf4 +# CHECK: vld2.32 {d8, d10}, [r4]! +0x06 0x89 0x24 0xf4 +# CHECK: vld2.8 {d8, d10}, [r4], r6 +0x46 0x89 0x24 0xf4 +# CHECK: vld2.16 {d8, d10}, [r4], r6 +0x86 0x89 0x24 0xf4 +# CHECK: vld2.32 {d8, d10}, [r4], r6 +0x0d 0x84 0x24 0xf4 +# CHECK: vld3.8 {d8, d9, d10}, [r4]! +0x4d 0x84 0x24 0xf4 +# CHECK: vld3.16 {d8, d9, d10}, [r4]! +0x8d 0x84 0x24 0xf4 +# CHECK: vld3.32 {d8, d9, d10}, [r4]! +0x06 0x85 0x24 0xf4 +# CHECK: vld3.8 {d8, d10, d12}, [r4], r6 +0x46 0x85 0x24 0xf4 +# CHECK: vld3.16 {d8, d10, d12}, [r4], r6 +0x86 0x85 0x24 0xf4 +# CHECK: vld3.32 {d8, d10, d12}, [r4], r6 +0x0d 0x80 0x24 0xf4 +# CHECK: vld4.8 {d8, d9, d10, d11}, [r4]! +0x4d 0x80 0x24 0xf4 +# CHECK: vld4.16 {d8, d9, d10, d11}, [r4]! +0x8d 0x80 0x24 0xf4 +# CHECK: vld4.32 {d8, d9, d10, d11}, [r4]! +0x06 0x81 0x24 0xf4 +# CHECK: vld4.8 {d8, d10, d12, d14}, [r4], r6 +0x46 0x81 0x24 0xf4 +# CHECK: vld4.16 {d8, d10, d12, d14}, [r4], r6 +0x86 0x81 0x24 0xf4 +# CHECK: vld4.32 {d8, d10, d12, d14}, [r4], r6 +0x4f 0x8a 0x24 0xf4 +# CHECK: vld1.16 {d8, d9}, [r4] +0x8f 0x8a 0x24 0xf4 +# CHECK: vld1.32 {d8, d9}, [r4] +0xcf 0x8a 0x24 0xf4 +# CHECK: vld1.64 {d8, d9}, [r4] +0x0f 0x8a 0x24 0xf4 +# CHECK: vld1.8 {d8, d9}, [r4] +0x4f 0x88 0x24 0xf4 +# CHECK: vld2.16 {d8, d9}, [r4] +0x8f 0x88 0x24 0xf4 +# CHECK: vld2.32 {d8, d9}, [r4] +0x0f 0x88 0x24 0xf4 +# CHECK: vld2.8 {d8, d9}, [r4] +0x4d 0x88 0x24 0xf4 +# CHECK: vld2.16 {d8, d9}, [r4]! +0x46 0x88 0x24 0xf4 +# CHECK: vld2.16 {d8, d9}, [r4], r6 +0x8d 0x88 0x24 0xf4 +# CHECK: vld2.32 {d8, d9}, [r4]! +0x86 0x88 0x24 0xf4 +# CHECK: vld2.32 {d8, d9}, [r4], r6 +0x0d 0x88 0x24 0xf4 +# CHECK: vld2.8 {d8, d9}, [r4]! +0x06 0x88 0x24 0xf4 +# CHECK: vld2.8 {d8, d9}, [r4], r6 +0x4f 0x89 0x24 0xf4 +# CHECK: vld2.16 {d8, d10}, [r4] +0x8f 0x89 0x24 0xf4 +# CHECK: vld2.32 {d8, d10}, [r4] +0x0f 0x89 0x24 0xf4 +# CHECK: vld2.8 {d8, d10}, [r4] +0x4d 0x83 0x24 0xf4 +# CHECK: vld2.16 {d8, d9, d10, d11}, [r4]! +0x46 0x83 0x24 0xf4 +# CHECK: vld2.16 {d8, d9, d10, d11}, [r4], r6 +0x8d 0x83 0x24 0xf4 +# CHECK: vld2.32 {d8, d9, d10, d11}, [r4]! +0x86 0x83 0x24 0xf4 +# CHECK: vld2.32 {d8, d9, d10, d11}, [r4], r6 +0x0d 0x83 0x24 0xf4 +# CHECK: vld2.8 {d8, d9, d10, d11}, [r4]! +0x06 0x83 0x24 0xf4 +# CHECK: vld2.8 {d8, d9, d10, d11}, [r4], r6 +0x0f 0x84 0x24 0xf4 +# CHECK: vld3.8 {d8, d9, d10}, [r4] +0x4f 0x84 0x24 0xf4 +# CHECK: vld3.16 {d8, d9, d10}, [r4] +0x8f 0x84 0x24 0xf4 +# CHECK: vld3.32 {d8, d9, d10}, [r4] +0x0f 0x80 0x24 0xf4 +# CHECK: vld4.8 {d8, d9, d10, d11}, [r4] +0x4f 0x80 0x24 0xf4 +# CHECK: vld4.16 {d8, d9, d10, d11}, [r4] +0x8f 0x80 0x24 0xf4 +# CHECK: vld4.32 {d8, d9, d10, d11}, [r4] +0x0f 0x85 0x24 0xf4 +# CHECK: vld3.8 {d8, d10, d12}, [r4] +0x4f 0x85 0x24 0xf4 +# CHECK: vld3.16 {d8, d10, d12}, [r4] +0x8f 0x85 0x24 0xf4 +# CHECK: vld3.32 {d8, d10, d12}, [r4] +0x0f 0x81 0x24 0xf4 +# CHECK: vld4.8 {d8, d10, d12, d14}, [r4] +0x4f 0x81 0x24 0xf4 +# CHECK: vld4.16 {d8, d10, d12, d14}, [r4] +0x8f 0x81 0x24 0xf4 +# CHECK: vld4.32 {d8, d10, d12, d14}, [r4] diff --git a/test/MC/Disassembler/ARM/neont2.txt b/test/MC/Disassembler/ARM/neont2.txt index 577703c..efe7e60 100644 --- a/test/MC/Disassembler/ARM/neont2.txt +++ b/test/MC/Disassembler/ARM/neont2.txt @@ -301,9 +301,9 @@ 0x50 0xef 0xf2 0x01 # CHECK: vbic q8, q8, q9 0xc7 0xff 0x3f 0x07 -# CHECK: vbic.i32 d16, #0xFF000000 +# CHECK: vbic.i32 d16, #0xff000000 0xc7 0xff 0x7f 0x07 -# CHECK: vbic.i32 q8, #0xFF000000 +# CHECK: vbic.i32 q8, #0xff000000 0x71 0xef 0xb0 0x01 # CHECK: vorn d16, d17, d16 @@ -486,11 +486,11 @@ 0xc2 0xef 0x10 0x06 # CHECK: vmov.i32 d16, #0x20000000 0xc2 0xef 0x10 0x0c -# CHECK: vmov.i32 d16, #0x20FF +# CHECK: vmov.i32 d16, #0x20ff 0xc2 0xef 0x10 0x0d -# CHECK: vmov.i32 d16, #0x20FFFF +# CHECK: vmov.i32 d16, #0x20ffff 0xc1 0xff 0x33 0x0e -# CHECK: vmov.i64 d16, #0xFF0000FF0000FFFF +# CHECK: vmov.i64 d16, #0xff0000ff0000ffff 0xc0 0xef 0x58 0x0e # CHECK: vmov.i8 q8, #0x8 0xc1 0xef 0x50 0x08 @@ -506,11 +506,11 @@ 0xc2 0xef 0x50 0x06 # CHECK: vmov.i32 q8, #0x20000000 0xc2 0xef 0x50 0x0c -# CHECK: vmov.i32 q8, #0x20FF +# CHECK: vmov.i32 q8, #0x20ff 0xc2 0xef 0x50 0x0d -# CHECK: vmov.i32 q8, #0x20FFFF +# CHECK: vmov.i32 q8, #0x20ffff 0xc1 0xff 0x73 0x0e -# CHECK: vmov.i64 q8, #0xFF0000FF0000FFFF +# CHECK: vmov.i64 q8, #0xff0000ff0000ffff 0xc1 0xef 0x30 0x08 # CHECK: vmvn.i16 d16, #0x10 0xc1 0xef 0x30 0x0a @@ -524,9 +524,9 @@ 0xc2 0xef 0x30 0x06 # CHECK: vmvn.i32 d16, #0x20000000 0xc2 0xef 0x30 0x0c -# CHECK: vmvn.i32 d16, #0x20FF +# CHECK: vmvn.i32 d16, #0x20ff 0xc2 0xef 0x30 0x0d -# CHECK: vmvn.i32 d16, #0x20FFFF +# CHECK: vmvn.i32 d16, #0x20ffff 0xc8 0xef 0x30 0x0a # CHECK: vmovl.s8 q8, d16 0xd0 0xef 0x30 0x0a @@ -1584,3 +1584,379 @@ # CHECK: vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0, :64] 0xc0 0xf9 0x4f 0x1b # CHECK: vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] + +0x63 0xf9 0x37 0xc9 +# CHECK: vld2.8 {d28, d30}, [r3, :256], r7 + +# rdar://10798451 +0xe7 0xf9 0x32 0x1d +# CHECK vld2.8 {d17[], d19[]}, [r7, :16], r2 +0xe7 0xf9 0x3d 0x1d +# CHECK vld2.8 {d17[], d19[]}, [r7, :16]! +0xe7 0xf9 0x3f 0x1d +# CHECK vld2.8 {d17[], d19[]}, [r7, :16] + +# rdar://11034702 +0x04 0xf9 0x0d 0x87 +# CHECK: vst1.8 {d8}, [r4]! +0x04 0xf9 0x4d 0x87 +# CHECK: vst1.16 {d8}, [r4]! +0x04 0xf9 0x8d 0x87 +# CHECK: vst1.32 {d8}, [r4]! +0x04 0xf9 0xcd 0x87 +# CHECK: vst1.64 {d8}, [r4]! +0x04 0xf9 0x06 0x87 +# CHECK: vst1.8 {d8}, [r4], r6 +0x04 0xf9 0x46 0x87 +# CHECK: vst1.16 {d8}, [r4], r6 +0x04 0xf9 0x86 0x87 +# CHECK: vst1.32 {d8}, [r4], r6 +0x04 0xf9 0xc6 0x87 +# CHECK: vst1.64 {d8}, [r4], r6 + +0x04 0xf9 0x0d 0x8a +# CHECK: vst1.8 {d8, d9}, [r4]! +0x04 0xf9 0x4d 0x8a +# CHECK: vst1.16 {d8, d9}, [r4]! +0x04 0xf9 0x8d 0x8a +# CHECK: vst1.32 {d8, d9}, [r4]! +0x04 0xf9 0xcd 0x8a +# CHECK: vst1.64 {d8, d9}, [r4]! +0x04 0xf9 0x06 0x8a +# CHECK: vst1.8 {d8, d9}, [r4], r6 +0x04 0xf9 0x46 0x8a +# CHECK: vst1.16 {d8, d9}, [r4], r6 +0x04 0xf9 0x86 0x8a +# CHECK: vst1.32 {d8, d9}, [r4], r6 +0x04 0xf9 0xc6 0x8a +# CHECK: vst1.64 {d8, d9}, [r4], r6 + +0x04 0xf9 0x0d 0x86 +# CHECK: vst1.8 {d8, d9, d10}, [r4]! +0x04 0xf9 0x4d 0x86 +# CHECK: vst1.16 {d8, d9, d10}, [r4]! +0x04 0xf9 0x8d 0x86 +# CHECK: vst1.32 {d8, d9, d10}, [r4]! +0x04 0xf9 0xcd 0x86 +# CHECK: vst1.64 {d8, d9, d10}, [r4]! +0x04 0xf9 0x06 0x86 +# CHECK: vst1.8 {d8, d9, d10}, [r4], r6 +0x04 0xf9 0x46 0x86 +# CHECK: vst1.16 {d8, d9, d10}, [r4], r6 +0x04 0xf9 0x86 0x86 +# CHECK: vst1.32 {d8, d9, d10}, [r4], r6 +0x04 0xf9 0xc6 0x86 +# CHECK: vst1.64 {d8, d9, d10}, [r4], r6 + +0x04 0xf9 0x0d 0x82 +# CHECK: vst1.8 {d8, d9, d10, d11}, [r4]! +0x04 0xf9 0x4d 0x82 +# CHECK: vst1.16 {d8, d9, d10, d11}, [r4]! +0x04 0xf9 0x8d 0x82 +# CHECK: vst1.32 {d8, d9, d10, d11}, [r4]! +0x04 0xf9 0xcd 0x82 +# CHECK: vst1.64 {d8, d9, d10, d11}, [r4]! +0x04 0xf9 0x06 0x82 +# CHECK: vst1.8 {d8, d9, d10, d11}, [r4], r6 +0x04 0xf9 0x46 0x82 +# CHECK: vst1.16 {d8, d9, d10, d11}, [r4], r6 +0x04 0xf9 0x86 0x82 +# CHECK: vst1.32 {d8, d9, d10, d11}, [r4], r6 +0x04 0xf9 0xc6 0x82 +# CHECK: vst1.64 {d8, d9, d10, d11}, [r4], r6 + +0x04 0xf9 0x0d 0x88 +# CHECK: vst2.8 {d8, d9}, [r4]! +0x04 0xf9 0x4d 0x88 +# CHECK: vst2.16 {d8, d9}, [r4]! +0x04 0xf9 0x8d 0x88 +# CHECK: vst2.32 {d8, d9}, [r4]! +0x04 0xf9 0x06 0x88 +# CHECK: vst2.8 {d8, d9}, [r4], r6 +0x04 0xf9 0x46 0x88 +# CHECK: vst2.16 {d8, d9}, [r4], r6 +0x04 0xf9 0x86 0x88 +# CHECK: vst2.32 {d8, d9}, [r4], r6 + +0x04 0xf9 0x0d 0x89 +# CHECK: vst2.8 {d8, d10}, [r4]! +0x04 0xf9 0x4d 0x89 +# CHECK: vst2.16 {d8, d10}, [r4]! +0x04 0xf9 0x8d 0x89 +# CHECK: vst2.32 {d8, d10}, [r4]! +0x04 0xf9 0x06 0x89 +# CHECK: vst2.8 {d8, d10}, [r4], r6 +0x04 0xf9 0x46 0x89 +# CHECK: vst2.16 {d8, d10}, [r4], r6 +0x04 0xf9 0x86 0x89 +# CHECK: vst2.32 {d8, d10}, [r4], r6 + +0x04 0xf9 0x0d 0x84 +# CHECK: vst3.8 {d8, d9, d10}, [r4]! +0x04 0xf9 0x4d 0x84 +# CHECK: vst3.16 {d8, d9, d10}, [r4]! +0x04 0xf9 0x8d 0x84 +# CHECK: vst3.32 {d8, d9, d10}, [r4]! +0x04 0xf9 0x06 0x85 +# CHECK: vst3.8 {d8, d10, d12}, [r4], r6 +0x04 0xf9 0x46 0x85 +# CHECK: vst3.16 {d8, d10, d12}, [r4], r6 +0x04 0xf9 0x86 0x85 +# CHECK: vst3.32 {d8, d10, d12}, [r4], r6 + +0x04 0xf9 0x0d 0x80 +# CHECK: vst4.8 {d8, d9, d10, d11}, [r4]! +0x04 0xf9 0x4d 0x80 +# CHECK: vst4.16 {d8, d9, d10, d11}, [r4]! +0x04 0xf9 0x8d 0x80 +# CHECK: vst4.32 {d8, d9, d10, d11}, [r4]! +0x04 0xf9 0x06 0x81 +# CHECK: vst4.8 {d8, d10, d12, d14}, [r4], r6 +0x04 0xf9 0x46 0x81 +# CHECK: vst4.16 {d8, d10, d12, d14}, [r4], r6 +0x04 0xf9 0x86 0x81 +# CHECK: vst4.32 {d8, d10, d12, d14}, [r4], r6 + +0x04 0xf9 0x4f 0x8a +# CHECK: vst1.16 {d8, d9}, [r4] +0x04 0xf9 0x8f 0x8a +# CHECK: vst1.32 {d8, d9}, [r4] +0x04 0xf9 0xcf 0x8a +# CHECK: vst1.64 {d8, d9}, [r4] +0x04 0xf9 0x0f 0x8a +# CHECK: vst1.8 {d8, d9}, [r4] +0x04 0xf9 0x4f 0x88 +# CHECK: vst2.16 {d8, d9}, [r4] +0x04 0xf9 0x8f 0x88 +# CHECK: vst2.32 {d8, d9}, [r4] +0x04 0xf9 0x0f 0x88 +# CHECK: vst2.8 {d8, d9}, [r4] +0x04 0xf9 0x4d 0x88 +# CHECK: vst2.16 {d8, d9}, [r4]! +0x04 0xf9 0x46 0x88 +# CHECK: vst2.16 {d8, d9}, [r4], r6 +0x04 0xf9 0x8d 0x88 +# CHECK: vst2.32 {d8, d9}, [r4]! +0x04 0xf9 0x86 0x88 +# CHECK: vst2.32 {d8, d9}, [r4], r6 +0x04 0xf9 0x0d 0x88 +# CHECK: vst2.8 {d8, d9}, [r4]! +0x04 0xf9 0x06 0x88 +# CHECK: vst2.8 {d8, d9}, [r4], r6 + +0x04 0xf9 0x4f 0x89 +# CHECK: vst2.16 {d8, d10}, [r4] +0x04 0xf9 0x8f 0x89 +# CHECK: vst2.32 {d8, d10}, [r4] +0x04 0xf9 0x0f 0x89 +# CHECK: vst2.8 {d8, d10}, [r4] + +0x04 0xf9 0x0f 0x84 +# CHECK: vst3.8 {d8, d9, d10}, [r4] +0x04 0xf9 0x4f 0x84 +# CHECK: vst3.16 {d8, d9, d10}, [r4] +0x04 0xf9 0x8f 0x84 +# CHECK: vst3.32 {d8, d9, d10}, [r4] + +0x04 0xf9 0x0f 0x80 +# CHECK: vst4.8 {d8, d9, d10, d11}, [r4] +0x04 0xf9 0x4f 0x80 +# CHECK: vst4.16 {d8, d9, d10, d11}, [r4] +0x04 0xf9 0x8f 0x80 +# CHECK: vst4.32 {d8, d9, d10, d11}, [r4] + +0x04 0xf9 0x0f 0x85 +# CHECK: vst3.8 {d8, d10, d12}, [r4] +0x04 0xf9 0x4f 0x85 +# CHECK: vst3.16 {d8, d10, d12}, [r4] +0x04 0xf9 0x8f 0x85 +# CHECK: vst3.32 {d8, d10, d12}, [r4] + +0x04 0xf9 0x0f 0x81 +# CHECK: vst4.8 {d8, d10, d12, d14}, [r4] +0x04 0xf9 0x4f 0x81 +# CHECK: vst4.16 {d8, d10, d12, d14}, [r4] +0x04 0xf9 0x8f 0x81 +# CHECK: vst4.32 {d8, d10, d12, d14}, [r4] + +# rdar://11204059 +0x24 0xf9 0x0d 0x87 +# CHECK: vld1.8 {d8}, [r4]! +0x24 0xf9 0x4d 0x87 +# CHECK: vld1.16 {d8}, [r4]! +0x24 0xf9 0x8d 0x87 +# CHECK: vld1.32 {d8}, [r4]! +0x24 0xf9 0xcd 0x87 +# CHECK: vld1.64 {d8}, [r4]! +0x24 0xf9 0x06 0x87 +# CHECK: vld1.8 {d8}, [r4], r6 +0x24 0xf9 0x46 0x87 +# CHECK: vld1.16 {d8}, [r4], r6 +0x24 0xf9 0x86 0x87 +# CHECK: vld1.32 {d8}, [r4], r6 +0x24 0xf9 0xc6 0x87 +# CHECK: vld1.64 {d8}, [r4], r6 +0x24 0xf9 0x0d 0x8a +# CHECK: vld1.8 {d8, d9}, [r4]! +0x24 0xf9 0x4d 0x8a +# CHECK: vld1.16 {d8, d9}, [r4]! +0x24 0xf9 0x8d 0x8a +# CHECK: vld1.32 {d8, d9}, [r4]! +0x24 0xf9 0xcd 0x8a +# CHECK: vld1.64 {d8, d9}, [r4]! +0x24 0xf9 0x06 0x8a +# CHECK: vld1.8 {d8, d9}, [r4], r6 +0x24 0xf9 0x46 0x8a +# CHECK: vld1.16 {d8, d9}, [r4], r6 +0x24 0xf9 0x86 0x8a +# CHECK: vld1.32 {d8, d9}, [r4], r6 +0x24 0xf9 0xc6 0x8a +# CHECK: vld1.64 {d8, d9}, [r4], r6 +0x24 0xf9 0x0d 0x86 +# CHECK: vld1.8 {d8, d9, d10}, [r4]! +0x24 0xf9 0x4d 0x86 +# CHECK: vld1.16 {d8, d9, d10}, [r4]! +0x24 0xf9 0x8d 0x86 +# CHECK: vld1.32 {d8, d9, d10}, [r4]! +0x24 0xf9 0xcd 0x86 +# CHECK: vld1.64 {d8, d9, d10}, [r4]! +0x24 0xf9 0x06 0x86 +# CHECK: vld1.8 {d8, d9, d10}, [r4], r6 +0x24 0xf9 0x46 0x86 +# CHECK: vld1.16 {d8, d9, d10}, [r4], r6 +0x24 0xf9 0x86 0x86 +# CHECK: vld1.32 {d8, d9, d10}, [r4], r6 +0x24 0xf9 0xc6 0x86 +# CHECK: vld1.64 {d8, d9, d10}, [r4], r6 +0x24 0xf9 0x0d 0x82 +# CHECK: vld1.8 {d8, d9, d10, d11}, [r4]! +0x24 0xf9 0x4d 0x82 +# CHECK: vld1.16 {d8, d9, d10, d11}, [r4]! +0x24 0xf9 0x8d 0x82 +# CHECK: vld1.32 {d8, d9, d10, d11}, [r4]! +0x24 0xf9 0xcd 0x82 +# CHECK: vld1.64 {d8, d9, d10, d11}, [r4]! +0x24 0xf9 0x06 0x82 +# CHECK: vld1.8 {d8, d9, d10, d11}, [r4], r6 +0x24 0xf9 0x46 0x82 +# CHECK: vld1.16 {d8, d9, d10, d11}, [r4], r6 +0x24 0xf9 0x86 0x82 +# CHECK: vld1.32 {d8, d9, d10, d11}, [r4], r6 +0x24 0xf9 0xc6 0x82 +# CHECK: vld1.64 {d8, d9, d10, d11}, [r4], r6 +0x24 0xf9 0x0d 0x88 +# CHECK: vld2.8 {d8, d9}, [r4]! +0x24 0xf9 0x4d 0x88 +# CHECK: vld2.16 {d8, d9}, [r4]! +0x24 0xf9 0x8d 0x88 +# CHECK: vld2.32 {d8, d9}, [r4]! +0x24 0xf9 0x06 0x88 +# CHECK: vld2.8 {d8, d9}, [r4], r6 +0x24 0xf9 0x46 0x88 +# CHECK: vld2.16 {d8, d9}, [r4], r6 +0x24 0xf9 0x86 0x88 +# CHECK: vld2.32 {d8, d9}, [r4], r6 +0x24 0xf9 0x0d 0x89 +# CHECK: vld2.8 {d8, d10}, [r4]! +0x24 0xf9 0x4d 0x89 +# CHECK: vld2.16 {d8, d10}, [r4]! +0x24 0xf9 0x8d 0x89 +# CHECK: vld2.32 {d8, d10}, [r4]! +0x24 0xf9 0x06 0x89 +# CHECK: vld2.8 {d8, d10}, [r4], r6 +0x24 0xf9 0x46 0x89 +# CHECK: vld2.16 {d8, d10}, [r4], r6 +0x24 0xf9 0x86 0x89 +# CHECK: vld2.32 {d8, d10}, [r4], r6 +0x24 0xf9 0x0d 0x84 +# CHECK: vld3.8 {d8, d9, d10}, [r4]! +0x24 0xf9 0x4d 0x84 +# CHECK: vld3.16 {d8, d9, d10}, [r4]! +0x24 0xf9 0x8d 0x84 +# CHECK: vld3.32 {d8, d9, d10}, [r4]! +0x24 0xf9 0x06 0x85 +# CHECK: vld3.8 {d8, d10, d12}, [r4], r6 +0x24 0xf9 0x46 0x85 +# CHECK: vld3.16 {d8, d10, d12}, [r4], r6 +0x24 0xf9 0x86 0x85 +# CHECK: vld3.32 {d8, d10, d12}, [r4], r6 +0x24 0xf9 0x0d 0x80 +# CHECK: vld4.8 {d8, d9, d10, d11}, [r4]! +0x24 0xf9 0x4d 0x80 +# CHECK: vld4.16 {d8, d9, d10, d11}, [r4]! +0x24 0xf9 0x8d 0x80 +# CHECK: vld4.32 {d8, d9, d10, d11}, [r4]! +0x24 0xf9 0x06 0x81 +# CHECK: vld4.8 {d8, d10, d12, d14}, [r4], r6 +0x24 0xf9 0x46 0x81 +# CHECK: vld4.16 {d8, d10, d12, d14}, [r4], r6 +0x24 0xf9 0x86 0x81 +# CHECK: vld4.32 {d8, d10, d12, d14}, [r4], r6 +0x24 0xf9 0x4f 0x8a +# CHECK: vld1.16 {d8, d9}, [r4] +0x24 0xf9 0x8f 0x8a +# CHECK: vld1.32 {d8, d9}, [r4] +0x24 0xf9 0xcf 0x8a +# CHECK: vld1.64 {d8, d9}, [r4] +0x24 0xf9 0x0f 0x8a +# CHECK: vld1.8 {d8, d9}, [r4] +0x24 0xf9 0x4f 0x88 +# CHECK: vld2.16 {d8, d9}, [r4] +0x24 0xf9 0x8f 0x88 +# CHECK: vld2.32 {d8, d9}, [r4] +0x24 0xf9 0x0f 0x88 +# CHECK: vld2.8 {d8, d9}, [r4] +0x24 0xf9 0x4d 0x88 +# CHECK: vld2.16 {d8, d9}, [r4]! +0x24 0xf9 0x46 0x88 +# CHECK: vld2.16 {d8, d9}, [r4], r6 +0x24 0xf9 0x8d 0x88 +# CHECK: vld2.32 {d8, d9}, [r4]! +0x24 0xf9 0x86 0x88 +# CHECK: vld2.32 {d8, d9}, [r4], r6 +0x24 0xf9 0x0d 0x88 +# CHECK: vld2.8 {d8, d9}, [r4]! +0x24 0xf9 0x06 0x88 +# CHECK: vld2.8 {d8, d9}, [r4], r6 +0x24 0xf9 0x4f 0x89 +# CHECK: vld2.16 {d8, d10}, [r4] +0x24 0xf9 0x8f 0x89 +# CHECK: vld2.32 {d8, d10}, [r4] +0x24 0xf9 0x0f 0x89 +# CHECK: vld2.8 {d8, d10}, [r4] +0x24 0xf9 0x4d 0x83 +# CHECK: vld2.16 {d8, d9, d10, d11}, [r4]! +0x24 0xf9 0x46 0x83 +# CHECK: vld2.16 {d8, d9, d10, d11}, [r4], r6 +0x24 0xf9 0x8d 0x83 +# CHECK: vld2.32 {d8, d9, d10, d11}, [r4]! +0x24 0xf9 0x86 0x83 +# CHECK: vld2.32 {d8, d9, d10, d11}, [r4], r6 +0x24 0xf9 0x0d 0x83 +# CHECK: vld2.8 {d8, d9, d10, d11}, [r4]! +0x24 0xf9 0x06 0x83 +# CHECK: vld2.8 {d8, d9, d10, d11}, [r4], r6 +0x24 0xf9 0x0f 0x84 +# CHECK: vld3.8 {d8, d9, d10}, [r4] +0x24 0xf9 0x4f 0x84 +# CHECK: vld3.16 {d8, d9, d10}, [r4] +0x24 0xf9 0x8f 0x84 +# CHECK: vld3.32 {d8, d9, d10}, [r4] +0x24 0xf9 0x0f 0x80 +# CHECK: vld4.8 {d8, d9, d10, d11}, [r4] +0x24 0xf9 0x4f 0x80 +# CHECK: vld4.16 {d8, d9, d10, d11}, [r4] +0x24 0xf9 0x8f 0x80 +# CHECK: vld4.32 {d8, d9, d10, d11}, [r4] +0x24 0xf9 0x0f 0x85 +# CHECK: vld3.8 {d8, d10, d12}, [r4] +0x24 0xf9 0x4f 0x85 +# CHECK: vld3.16 {d8, d10, d12}, [r4] +0x24 0xf9 0x8f 0x85 +# CHECK: vld3.32 {d8, d10, d12}, [r4] +0x24 0xf9 0x0f 0x81 +# CHECK: vld4.8 {d8, d10, d12, d14}, [r4] +0x24 0xf9 0x4f 0x81 +# CHECK: vld4.16 {d8, d10, d12, d14}, [r4] +0x24 0xf9 0x8f 0x81 +# CHECK: vld4.32 {d8, d10, d12, d14}, [r4] diff --git a/test/MC/Disassembler/ARM/unpredictable-ADC-arm.txt b/test/MC/Disassembler/ARM/unpredictable-ADC-arm.txt new file mode 100644 index 0000000..275bae2f --- /dev/null +++ b/test/MC/Disassembler/ARM/unpredictable-ADC-arm.txt @@ -0,0 +1,17 @@ +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s + +# CHECK: potentially undefined +# CHECK: 0x1f 0x12 0xb0 0x00 +0x1f 0x12 0xb0 0x00 + +# CHECK: potentially undefined +# CHECK: 0x13 0xf2 0xb0 0x00 +0x13 0xf2 0xb0 0x00 + +# CHECK: potentially undefined +# CHECK: 0x13 0x1f 0xb0 0x00 +0x13 0x1f 0xb0 0x00 + +# CHECK: potentially undefined +# CHECK: 0x13 0x12 0xbf 0x00 +0x13 0x12 0xbf 0x00 diff --git a/test/MC/Disassembler/ARM/unpredictable-ADDREXT3-arm.txt b/test/MC/Disassembler/ARM/unpredictable-ADDREXT3-arm.txt new file mode 100644 index 0000000..635b66e --- /dev/null +++ b/test/MC/Disassembler/ARM/unpredictable-ADDREXT3-arm.txt @@ -0,0 +1,16 @@ +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s + +# CHECK: potentially undefined +# CHECK: 0xd1 0xf1 0x5f 0x01 +0xd1 0xf1 0x5f 0x01 +# CHECK: potentially undefined +# CHECK: 0xf1 0xf1 0x5f 0x01 +0xf1 0xf1 0x5f 0x01 +# CHECK: potentially undefined +# CHECK: 0xf1 0xf1 0x5f 0x01 +0xf1 0xf1 0x5f 0x01 +# CHECK: potentially undefined +# CHECK: 0xd1 0xe1 0x4f 0x01 +0xd1 0xe1 0x4f 0x01 + + diff --git a/test/MC/Disassembler/ARM/unpredictable-LDR-arm.txt b/test/MC/Disassembler/ARM/unpredictable-LDR-arm.txt new file mode 100644 index 0000000..ed5e350 --- /dev/null +++ b/test/MC/Disassembler/ARM/unpredictable-LDR-arm.txt @@ -0,0 +1,22 @@ +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s + +# CHECK: potentially undefined +# CHECK: 0xff 0x00 0xb9 0x00 +0xff 0x00 0xb9 0x00 + +# CHECK: potentially undefined +# CHECK: 0xfb 0xf0 0xb9 0x00 +0xfb 0xf0 0xb9 0x00 + +# CHECK: potentially undefined +# CHECK: 0xfb 0x01 0xb9 0x00 +0xfb 0x01 0xb9 0x00 + +# CHECK: potentially undefined +# CHECK: 0xfb 0x00 0xbf 0x00 +0xfb 0x00 0xbf 0x00 + +# CHECK: potentially undefined +# CHECK: 0xfb 0x90 0xb9 0x00 +0xfb 0x90 0xb9 0x00 + diff --git a/test/MC/Disassembler/ARM/invalid-LDRD-arm.txt b/test/MC/Disassembler/ARM/unpredictable-LDRD-arm.txt index f8f23ed..a8f54f7 100644 --- a/test/MC/Disassembler/ARM/invalid-LDRD-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-LDRD-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # ------------------------------------------------------------------------------------------------- @@ -7,4 +7,7 @@ # # A8.6.68 LDRD (register) # if Rt{0} = 1 then UNDEFINED; + +# CHECK: potentially undefined +# CHECK: 0xd0 0x10 0x00 0x00 0xd0 0x10 0x00 0x00 diff --git a/test/MC/Disassembler/ARM/invalid-LSL-regform.txt b/test/MC/Disassembler/ARM/unpredictable-LSL-regform.txt index 6a1f11f..f7d6bc6 100644 --- a/test/MC/Disassembler/ARM/invalid-LSL-regform.txt +++ b/test/MC/Disassembler/ARM/unpredictable-LSL-regform.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s # Opcode=196 Name=MOVs Format=ARM_FORMAT_DPSOREGFRM(5) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 @@ -8,4 +8,6 @@ # # A8.6.89 LSL (register) # if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; + +# CHECK: warning: potentially undefined instruction encoding 0x12 0xf1 0xa0 0xe1 diff --git a/test/MC/Disassembler/ARM/unpredictable-MUL-arm.txt b/test/MC/Disassembler/ARM/unpredictable-MUL-arm.txt new file mode 100644 index 0000000..3db86cc --- /dev/null +++ b/test/MC/Disassembler/ARM/unpredictable-MUL-arm.txt @@ -0,0 +1,17 @@ +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s + +# CHECK: potentially undefined +# CHECK: 0x93 0x12 0x01 0x00 +0x93 0x12 0x01 0x00 + +# CHECK: potentially undefined +# CHECK: 0x92 0x0f 0x01 0x00 +0x92 0x0f 0x01 0x00 + +# CHECK: potentially undefined +# CHECK: 0x9f 0x02 0x01 0x00 +0x9f 0x02 0x01 0x00 + +# CHECK: potentially undefined +# CHECK: 0x92 0x01 0x0f 0x00 +0x92 0x01 0x0f 0x00 diff --git a/test/MC/Disassembler/ARM/invalid-RSC-arm.txt b/test/MC/Disassembler/ARM/unpredictable-RSC-arm.txt index 096b909..5b13610 100644 --- a/test/MC/Disassembler/ARM/invalid-RSC-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-RSC-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s # Opcode=261 Name=RSCrs Format=ARM_FORMAT_DPSOREGFRM(5) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 @@ -6,4 +6,6 @@ # | 0: 0: 1: 1| 0: 0: 0: 0| 1: 1: 1: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 0: 0: 0| 0: 1: 0: 1| 1: 1: 1: 1| # ------------------------------------------------------------------------------------------------- # if d == 15 || n == 15 || m == 15 || s == 15 then UNPREDICTABLE; + +# CHECK: warning: potentially undefined instruction encoding 0x5f 0xf8 0xe4 0x30 diff --git a/test/MC/Disassembler/ARM/unpredictable-SHADD16-arm.txt b/test/MC/Disassembler/ARM/unpredictable-SHADD16-arm.txt new file mode 100644 index 0000000..8ec49ca --- /dev/null +++ b/test/MC/Disassembler/ARM/unpredictable-SHADD16-arm.txt @@ -0,0 +1,7 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s + +# CHECK: warning: potentially undefined +# CHECK: shadd16 r5, r7, r0 +0x10 0x51 0x37 0xe6 + + diff --git a/test/MC/Disassembler/ARM/invalid-SSAT-arm.txt b/test/MC/Disassembler/ARM/unpredictable-SSAT-arm.txt index b236f8e..874378e 100644 --- a/test/MC/Disassembler/ARM/invalid-SSAT-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-SSAT-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s # Opcode=322 Name=SSAT Format=ARM_FORMAT_SATFRM(13) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 @@ -8,4 +8,6 @@ # # A8.6.183 SSAT # if d == 15 || n == 15 then UNPREDICTABLE; + +# CHECK:warning: potentially undefined instruction encoding 0x1a 0xf4 0xa0 0xe6 diff --git a/test/MC/Disassembler/ARM/invalid-STRBrs-arm.txt b/test/MC/Disassembler/ARM/unpredictable-STRBrs-arm.txt index d3998bd..fef6125 100644 --- a/test/MC/Disassembler/ARM/invalid-STRBrs-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-STRBrs-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s # Opcode=355 Name=STRBrs Format=ARM_FORMAT_STFRM(7) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 @@ -7,4 +7,6 @@ # ------------------------------------------------------------------------------------------------- # # if t == 15 then UNPREDICTABLE + +# CHECK: warning: potentially undefined instruction encoding 0x00 0xf0 0xcf 0xe7 diff --git a/test/MC/Disassembler/ARM/invalid-UQADD8-arm.txt b/test/MC/Disassembler/ARM/unpredictable-UQADD8-arm.txt index fb3e711..4c4c9ab 100644 --- a/test/MC/Disassembler/ARM/invalid-UQADD8-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-UQADD8-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s # Opcode=426 Name=UQADD8 Format=ARM_FORMAT_DPFRM(4) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 @@ -10,3 +10,7 @@ # # if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; 0x9f 0x5f 0x66 0xe6 + +# CHECK: warning: potentially undefined +# CHECK: uqadd8 r5, r6, pc + diff --git a/test/MC/Disassembler/ARM/unpredictables-thumb.txt b/test/MC/Disassembler/ARM/unpredictables-thumb.txt new file mode 100644 index 0000000..e7645f0 --- /dev/null +++ b/test/MC/Disassembler/ARM/unpredictables-thumb.txt @@ -0,0 +1,5 @@ +# RUN: llvm-mc --disassemble %s -triple=thumbv7 |& FileCheck %s + +0x01 0x47 +# CHECK: 3:1: warning: potentially undefined +# CHECK: bx r0 diff --git a/test/MC/Disassembler/ARM/vfp4.txt b/test/MC/Disassembler/ARM/vfp4.txt new file mode 100644 index 0000000..4f2c732 --- /dev/null +++ b/test/MC/Disassembler/ARM/vfp4.txt @@ -0,0 +1,37 @@ +# RUN: llvm-mc < %s -triple thumbv7-unknown-unknown --disassemble -mattr=+neon,+vfp4 | FileCheck %s + +# CHECK: vfma.f64 d16, d18, d17 +0xe2 0xee 0xa1 0x0b + +# CHECK: vfma.f32 s2, s4, s0 +0xa2 0xee 0x00 0x1a + +# CHECK: vfma.f32 d16, d18, d17 +0x42 0xef 0xb1 0x0c + +# CHECK: vfma.f32 q2, q4, q0 +0x08 0xef 0x50 0x4c + +# CHECK: vfnms.f64 d16, d18, d17 +0xd2 0xee 0xa1 0x0b + +# CHECK: vfnms.f32 s2, s4, s0 +0x92 0xee 0x00 0x1a + +# CHECK: vfms.f64 d16, d18, d17 +0xe2 0xee 0xe1 0x0b + +# CHECK: vfms.f32 s2, s4, s0 +0xa2 0xee 0x40 0x1a + +# CHECK: vfms.f32 d16, d18, d17 +0x62 0xef 0xb1 0x0c + +# CHECK: vfms.f32 q2, q4, q0 +0x28 0xef 0x50 0x4c + +# CHECK: vfnma.f64 d16, d18, d17 +0xd2 0xee 0xe1 0x0b + +# CHECK: vfnma.f32 s2, s4, s0 +0x92 0xee 0x40 0x1a |
