diff options
Diffstat (limited to 'test/MC/Disassembler/ARM')
74 files changed, 413 insertions, 128 deletions
diff --git a/test/MC/Disassembler/ARM/arm-tests.txt b/test/MC/Disassembler/ARM/arm-tests.txt index 471076a..0c9aaab 100644 --- a/test/MC/Disassembler/ARM/arm-tests.txt +++ b/test/MC/Disassembler/ARM/arm-tests.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=armv7-apple-darwin9 -mattr +mp | FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=armv7-apple-darwin9 -mcpu=cortex-a9-mp | FileCheck %s # CHECK: addpl r4, pc, #318767104 0x4c 0x45 0x8f 0x52 diff --git a/test/MC/Disassembler/ARM/basic-arm-instructions.txt b/test/MC/Disassembler/ARM/basic-arm-instructions.txt index fc7eda5..1100ce6 100644 --- a/test/MC/Disassembler/ARM/basic-arm-instructions.txt +++ b/test/MC/Disassembler/ARM/basic-arm-instructions.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc -triple=armv7-apple-darwin -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple=armv7-apple-darwin -mcpu=cortex-a8 -disassemble < %s | FileCheck %s #------------------------------------------------------------------------------ # ADC (immediate) @@ -169,9 +169,15 @@ #------------------------------------------------------------------------------ # CHECK: add r2, pc, #3 # CHECK: sub r2, pc, #3 +# CHECK: sub r1, pc, #0 +# CHECK: sub r1, pc, #301989888 +# CHECK: add r1, pc, #301989888 0x03 0x20 0x8f 0xe2 0x03 0x20 0x4f 0xe2 +0x00 0x10 0x4f 0xe2 +0x12 0x14 0x4f 0xe2 +0x12 0x14 0x8f 0xe2 #------------------------------------------------------------------------------ # AND @@ -469,47 +475,77 @@ #------------------------------------------------------------------------------ # DMB #------------------------------------------------------------------------------ -# CHECK: dmb sy -# CHECK: dmb st -# CHECK: dmb ish -# CHECK: dmb ishst -# CHECK: dmb nsh -# CHECK: dmb nshst -# CHECK: dmb osh + +# CHECK: dmb #0x0 +# CHECK: dmb #0x1 # CHECK: dmb oshst -# CHECK: dmb +# CHECK: dmb osh +# CHECK: dmb #0x4 +# CHECK: dmb #0x5 +# CHECK: dmb nshst +# CHECK: dmb nsh +# CHECK: dmb #0x8 +# CHECK: dmb #0x9 +# CHECK: dmb ishst +# CHECK: dmb ish +# CHECK: dmb #0xc +# CHECK: dmb #0xd +# CHECK: dmb st +# CHECK: dmb sy -0x5f 0xf0 0x7f 0xf5 -0x5e 0xf0 0x7f 0xf5 -0x5b 0xf0 0x7f 0xf5 -0x5a 0xf0 0x7f 0xf5 -0x57 0xf0 0x7f 0xf5 -0x56 0xf0 0x7f 0xf5 -0x53 0xf0 0x7f 0xf5 +0x50 0xf0 0x7f 0xf5 +0x51 0xf0 0x7f 0xf5 0x52 0xf0 0x7f 0xf5 +0x53 0xf0 0x7f 0xf5 +0x54 0xf0 0x7f 0xf5 +0x55 0xf0 0x7f 0xf5 +0x56 0xf0 0x7f 0xf5 +0x57 0xf0 0x7f 0xf5 +0x58 0xf0 0x7f 0xf5 +0x59 0xf0 0x7f 0xf5 +0x5a 0xf0 0x7f 0xf5 +0x5b 0xf0 0x7f 0xf5 +0x5c 0xf0 0x7f 0xf5 +0x5d 0xf0 0x7f 0xf5 +0x5e 0xf0 0x7f 0xf5 0x5f 0xf0 0x7f 0xf5 #------------------------------------------------------------------------------ # DSB #------------------------------------------------------------------------------ -# CHECK: dsb sy -# CHECK: dsb st -# CHECK: dsb ish -# CHECK: dsb ishst -# CHECK: dsb nsh -# CHECK: dsb nshst -# CHECK: dsb osh -# CHECK: dsb oshst -# CHECK: dsb -0x4f 0xf0 0x7f 0xf5 -0x4e 0xf0 0x7f 0xf5 -0x4b 0xf0 0x7f 0xf5 -0x4a 0xf0 0x7f 0xf5 -0x47 0xf0 0x7f 0xf5 -0x46 0xf0 0x7f 0xf5 -0x43 0xf0 0x7f 0xf5 +# CHECK: dsb #0x0 +# CHECK: dsb #0x1 +# CHECK: dsb oshst +# CHECK: dsb osh +# CHECK: dsb #0x4 +# CHECK: dsb #0x5 +# CHECK: dsb nshst +# CHECK: dsb nsh +# CHECK: dsb #0x8 +# CHECK: dsb #0x9 +# CHECK: dsb ishst +# CHECK: dsb ish +# CHECK: dsb #0xc +# CHECK: dsb #0xd +# CHECK: dsb st +# CHECK: dsb sy + +0x40 0xf0 0x7f 0xf5 +0x41 0xf0 0x7f 0xf5 0x42 0xf0 0x7f 0xf5 +0x43 0xf0 0x7f 0xf5 +0x44 0xf0 0x7f 0xf5 +0x45 0xf0 0x7f 0xf5 +0x46 0xf0 0x7f 0xf5 +0x47 0xf0 0x7f 0xf5 +0x48 0xf0 0x7f 0xf5 +0x49 0xf0 0x7f 0xf5 +0x4a 0xf0 0x7f 0xf5 +0x4b 0xf0 0x7f 0xf5 +0x4c 0xf0 0x7f 0xf5 +0x4d 0xf0 0x7f 0xf5 +0x4e 0xf0 0x7f 0xf5 0x4f 0xf0 0x7f 0xf5 #------------------------------------------------------------------------------ diff --git a/test/MC/Disassembler/ARM/fp-encoding.txt b/test/MC/Disassembler/ARM/fp-encoding.txt index 9095b84..8dedf80 100644 --- a/test/MC/Disassembler/ARM/fp-encoding.txt +++ b/test/MC/Disassembler/ARM/fp-encoding.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc -triple armv7-apple-darwin -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple armv7-apple-darwin -mcpu=cortex-a8 -disassemble < %s | FileCheck %s 0xa0 0x0b 0x71 0xee # CHECK: vadd.f64 d16, d17, d16 @@ -203,6 +203,33 @@ # CHECK: vstmia r1, {d2, d3, d4, d5, d6, d7} # CHECK: vstmia r1, {s2, s3, s4, s5, s6, s7} +0x05 0x9a 0xc0 0x0c +0x0c 0x0b 0xc7 0x0c +0x06 0x9a 0x93 0x0c +0x0a 0x5b 0xd2 0x0c +# CHECK: vstmiaeq r0, {s19, s20, s21, s22, s23} +# CHECK: vstmiaeq r7, {d16, d17, d18, d19, d20, d21} +# CHECK: vldmiaeq r3, {s18, s19, s20, s21, s22, s23} +# CHECK: vldmiaeq r2, {d21, d22, d23, d24, d25} + +0x04 0xca 0x6c 0x0d +0x06 0x1b 0x69 0x0d +0x03 0xaa 0x75 0x0d +0x08 0xeb 0x37 0x0d +# CHECK: vstmdbeq r12!, {s25, s26, s27, s28} +# CHECK: vstmdbeq r9!, {d17, d18, d19} +# CHECK: vldmdbeq r5!, {s21, s22, s23} +# CHECK: vldmdbeq r7!, {d14, d15, d16, d17} + +0x04 0x7a 0xa6 0x0c +0x0c 0xfb 0xa4 0x0c +0x03 0xaa 0xf8 0x0c +0x0a 0x3b 0xfb 0x0c +# CHECK: vstmiaeq r6!, {s14, s15, s16, s17} +# CHECK: vstmiaeq r4!, {d15, d16, d17, d18, d19, d20} +# CHECK: vldmiaeq r8!, {s21, s22, s23} +# CHECK: vldmiaeq r11!, {d19, d20, d21, d22, d23} + 0x40 0x0b 0xbd 0xee 0x60 0x0a 0xbd 0xee 0x40 0x0b 0xbc 0xee diff --git a/test/MC/Disassembler/ARM/invalid-BFI-arm.txt b/test/MC/Disassembler/ARM/invalid-BFI-arm.txt index a0d5944..f7acce9 100644 --- a/test/MC/Disassembler/ARM/invalid-BFI-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-BFI-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=60 Name=BFI Format=ARM_FORMAT_DPFRM(4) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-Bcc-thumb.txt b/test/MC/Disassembler/ARM/invalid-Bcc-thumb.txt index d2d424c..356c376 100644 --- a/test/MC/Disassembler/ARM/invalid-Bcc-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-Bcc-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=2249 Name=tBcc Format=ARM_FORMAT_THUMBFRM(25) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt b/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt index 10748e9..bc8b7e1 100644 --- a/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # invalid imod value (0b01) 0xc0 0x67 0x4 0xf1 diff --git a/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt b/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt index 8146b5c..842a52b 100644 --- a/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {potentially undefined instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "potentially undefined instruction encoding" # invalid (imod, M, iflags) combination 0x93 0x00 0x02 0xf1 diff --git a/test/MC/Disassembler/ARM/invalid-DMB-thumb.txt b/test/MC/Disassembler/ARM/invalid-DMB-thumb.txt index b441485..8396156 100644 --- a/test/MC/Disassembler/ARM/invalid-DMB-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-DMB-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=1908 Name=t2DMB Format=ARM_FORMAT_THUMBFRM(25) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-DSB-arm.txt b/test/MC/Disassembler/ARM/invalid-DSB-arm.txt index de042a97..2c6e6a7 100644 --- a/test/MC/Disassembler/ARM/invalid-DSB-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-DSB-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=102 Name=DSB Format=ARM_FORMAT_MISCFRM(26) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-IT-CBNZ-thumb.txt b/test/MC/Disassembler/ARM/invalid-IT-CBNZ-thumb.txt index 6174e92..4297c01 100644 --- a/test/MC/Disassembler/ARM/invalid-IT-CBNZ-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-IT-CBNZ-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 |& grep {potentially undefined instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "potentially undefined instruction encoding" # CBZ / CBNZ not allowed in IT block. diff --git a/test/MC/Disassembler/ARM/invalid-IT-CC15.txt b/test/MC/Disassembler/ARM/invalid-IT-CC15.txt index 17e25ea..733895d 100644 --- a/test/MC/Disassembler/ARM/invalid-IT-CC15.txt +++ b/test/MC/Disassembler/ARM/invalid-IT-CC15.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumbv7-unknown-unknown |& grep und +# RUN: llvm-mc --disassemble %s -triple=thumbv7-unknown-unknown 2>&1 | grep und # rdar://10841671 0xe3 0xbf diff --git a/test/MC/Disassembler/ARM/invalid-IT-thumb.txt b/test/MC/Disassembler/ARM/invalid-IT-thumb.txt index 9b571b3..1a8ff48 100644 --- a/test/MC/Disassembler/ARM/invalid-IT-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-IT-thumb.txt @@ -1,3 +1,3 @@ -# RUN: llvm-mc --disassemble %s -triple=thumbv7-unknown-unknown |& grep {potentially undefined instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumbv7-unknown-unknown 2>&1 | grep "potentially undefined instruction encoding" 0xff 0xbf 0x6b 0x80 0x00 0x75 diff --git a/test/MC/Disassembler/ARM/invalid-LDC-form-arm.txt b/test/MC/Disassembler/ARM/invalid-LDC-form-arm.txt index 0b0426b..6cff09e 100644 --- a/test/MC/Disassembler/ARM/invalid-LDC-form-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-LDC-form-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=0 Name=PHI Format=(42) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-LDM-thumb.txt b/test/MC/Disassembler/ARM/invalid-LDM-thumb.txt index a42b248..7d8c492 100644 --- a/test/MC/Disassembler/ARM/invalid-LDM-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-LDM-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 |& grep {potentially undefined instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "potentially undefined instruction encoding" # Writeback is not allowed is Rn is in the target register list. diff --git a/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt b/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt index 6b695b9..68d22de 100644 --- a/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {potentially undefined instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "potentially undefined instruction encoding" # Opcode=140 Name=LDRB_POST Format=ARM_FORMAT_LDFRM(6) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt b/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt index 7ea1b46..4df5309 100644 --- a/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=1930 Name=t2LDRD_PRE Format=ARM_FORMAT_THUMBFRM(25) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt b/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt index eef2c45..0cff28a 100644 --- a/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # XFAIL: * # LDR_PRE/POST has encoding Inst{4} = 0. diff --git a/test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt b/test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt index e42e0de..30cb727 100644 --- a/test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {potentially undefined instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "potentially undefined instruction encoding" # Opcode=165 Name=LDR_PRE Format=ARM_FORMAT_LDFRM(6) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-LDRrs-arm.txt b/test/MC/Disassembler/ARM/invalid-LDRrs-arm.txt index 23a0b85..7b7286a 100644 --- a/test/MC/Disassembler/ARM/invalid-LDRrs-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-LDRrs-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # LDR (register) has encoding Inst{4} = 0. 0xba 0xae 0x9f 0x57 diff --git a/test/MC/Disassembler/ARM/invalid-MCR-arm.txt b/test/MC/Disassembler/ARM/invalid-MCR-arm.txt index 8343d54..bb4b06c 100644 --- a/test/MC/Disassembler/ARM/invalid-MCR-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-MCR-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=171 Name=MCR Format=ARM_FORMAT_BRFRM(2) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-MOVTi16-arm.txt b/test/MC/Disassembler/ARM/invalid-MOVTi16-arm.txt index 235952f..528563a 100644 --- a/test/MC/Disassembler/ARM/invalid-MOVTi16-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-MOVTi16-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=185 Name=MOVTi16 Format=ARM_FORMAT_DPFRM(4) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-MOVr-arm.txt b/test/MC/Disassembler/ARM/invalid-MOVr-arm.txt index 01c1466..41ec53f 100644 --- a/test/MC/Disassembler/ARM/invalid-MOVr-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-MOVr-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=0 Name=PHI Format=(42) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt b/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt index 757d167..e5f2a5e 100644 --- a/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=196 Name=MOVs Format=ARM_FORMAT_DPSOREGFRM(5) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-MOVs-arm.txt b/test/MC/Disassembler/ARM/invalid-MOVs-arm.txt index ba48877..3f4c1e5 100644 --- a/test/MC/Disassembler/ARM/invalid-MOVs-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-MOVs-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=0 Name=PHI Format=(42) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-MRRC2-arm.txt b/test/MC/Disassembler/ARM/invalid-MRRC2-arm.txt index aaae6ce..c20ce54 100644 --- a/test/MC/Disassembler/ARM/invalid-MRRC2-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-MRRC2-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi 2>&1 | FileCheck %s # CHECK: invalid instruction encoding 0x00 0x1a 0x50 0xfc diff --git a/test/MC/Disassembler/ARM/invalid-MSRi-arm.txt b/test/MC/Disassembler/ARM/invalid-MSRi-arm.txt index 3765b1f..901667a 100644 --- a/test/MC/Disassembler/ARM/invalid-MSRi-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-MSRi-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=206 Name=MSRi Format=ARM_FORMAT_BRFRM(2) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-RFEorLDMIA-arm.txt b/test/MC/Disassembler/ARM/invalid-RFEorLDMIA-arm.txt index cffd86d..499aa86 100644 --- a/test/MC/Disassembler/ARM/invalid-RFEorLDMIA-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-RFEorLDMIA-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=134 Name=LDMIA Format=ARM_FORMAT_LDSTMULFRM(10) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-SBFX-arm.txt b/test/MC/Disassembler/ARM/invalid-SBFX-arm.txt index 9e16536..7bc97d5 100644 --- a/test/MC/Disassembler/ARM/invalid-SBFX-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-SBFX-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=271 Name=SBFX Format=ARM_FORMAT_DPFRM(4) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-SMLAD-arm.txt b/test/MC/Disassembler/ARM/invalid-SMLAD-arm.txt index 91f3d58..fe4f43a 100644 --- a/test/MC/Disassembler/ARM/invalid-SMLAD-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-SMLAD-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=284 Name=SMLAD Format=ARM_FORMAT_MULFRM(1) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-SRS-arm.txt b/test/MC/Disassembler/ARM/invalid-SRS-arm.txt index fc5c711..eedd05c 100644 --- a/test/MC/Disassembler/ARM/invalid-SRS-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-SRS-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=0 Name=PHI Format=(42) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-STMIA_UPD-thumb.txt b/test/MC/Disassembler/ARM/invalid-STMIA_UPD-thumb.txt index ca16724..3d5235d 100644 --- a/test/MC/Disassembler/ARM/invalid-STMIA_UPD-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-STMIA_UPD-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=2313 Name=tSTMIA_UPD Format=ARM_FORMAT_THUMBFRM(25) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-SXTB-arm.txt b/test/MC/Disassembler/ARM/invalid-SXTB-arm.txt index 400d44c..f67f38e 100644 --- a/test/MC/Disassembler/ARM/invalid-SXTB-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-SXTB-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=390 Name=SXTBr_rot Format=ARM_FORMAT_EXTFRM(14) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-UMAAL-arm.txt b/test/MC/Disassembler/ARM/invalid-UMAAL-arm.txt index c7cbd84..f57c48f 100644 --- a/test/MC/Disassembler/ARM/invalid-UMAAL-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-UMAAL-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=419 Name=UMAAL Format=ARM_FORMAT_MULFRM(1) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt b/test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt index 12da869..5ba7d61 100644 --- a/test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=armv7-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=armv7-unknown-unknwon -mcpu=cortex-a8 2>&1 | grep "invalid instruction encoding" # XFAIL: * # Opcode=737 Name=VLD1DUPq8_UPD Format=ARM_FORMAT_NLdSt(30) diff --git a/test/MC/Disassembler/ARM/invalid-VLD3DUPd32_UPD-thumb.txt b/test/MC/Disassembler/ARM/invalid-VLD3DUPd32_UPD-thumb.txt index bab32ca..58def05 100644 --- a/test/MC/Disassembler/ARM/invalid-VLD3DUPd32_UPD-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-VLD3DUPd32_UPD-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=871 Name=VLD3DUPd32_UPD Format=ARM_FORMAT_NLdSt(30) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-VLDMSDB_UPD-arm.txt b/test/MC/Disassembler/ARM/invalid-VLDMSDB_UPD-arm.txt index 887b983..54fcadb 100644 --- a/test/MC/Disassembler/ARM/invalid-VLDMSDB_UPD-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-VLDMSDB_UPD-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # core registers out of range 0xa5 0xba 0x72 0xed diff --git a/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt b/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt index a53f940..f961c64 100644 --- a/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=armv7-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=armv7-unknown-unknwon -mcpu=cortex-a8 2>&1 | grep "invalid instruction encoding" # XFAIL: * # Opcode=1225 Name=VQADDsv16i8 Format=ARM_FORMAT_N3Reg(37) diff --git a/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt b/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt index 8ff3a2b..2d2a628 100644 --- a/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=1839 Name=VST1d8Twb_register Format=ARM_FORMAT_NLdSt(30) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt b/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt index a12ca95..07a1c7a 100644 --- a/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=armv7-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=armv7-unknown-unknwon -mcpu=cortex-a8 2>&1 | grep "invalid instruction encoding" # XFAIL: * # Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30) diff --git a/test/MC/Disassembler/ARM/invalid-t2Bcc-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2Bcc-thumb.txt index df0a642..c9f1cf1 100644 --- a/test/MC/Disassembler/ARM/invalid-t2Bcc-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-t2Bcc-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=1894 Name=t2Bcc Format=ARM_FORMAT_THUMBFRM(25) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-t2LDRBT-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2LDRBT-thumb.txt index e1f841b8..eb415f7 100644 --- a/test/MC/Disassembler/ARM/invalid-t2LDRBT-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-t2LDRBT-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=1922 Name=t2LDRBT Format=ARM_FORMAT_THUMBFRM(25) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-t2LDREXD-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2LDREXD-thumb.txt index 7c0efab..6c13560 100644 --- a/test/MC/Disassembler/ARM/invalid-t2LDREXD-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-t2LDREXD-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "invalid instruction encoding" # XFAIL: * # Opcode=1934 Name=t2LDREXD Format=ARM_FORMAT_THUMBFRM(25) diff --git a/test/MC/Disassembler/ARM/invalid-t2LDRSHi12-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2LDRSHi12-thumb.txt index a63d121..7f84e08 100644 --- a/test/MC/Disassembler/ARM/invalid-t2LDRSHi12-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-t2LDRSHi12-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=1953 Name=t2LDRSHi12 Format=ARM_FORMAT_THUMBFRM(25) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-t2LDRSHi8-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2LDRSHi8-thumb.txt index f126ff0..e44cf95 100644 --- a/test/MC/Disassembler/ARM/invalid-t2LDRSHi8-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-t2LDRSHi8-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=1954 Name=t2LDRSHi8 Format=ARM_FORMAT_THUMBFRM(25) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-t2PUSH-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2PUSH-thumb.txt index b3daa9a..8c0d48b 100644 --- a/test/MC/Disassembler/ARM/invalid-t2PUSH-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-t2PUSH-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "invalid instruction encoding" # SP and PC are not allowed in the register list on STM instructions in Thumb2. diff --git a/test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt index 2198efc..64ba368 100644 --- a/test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "invalid instruction encoding" # XFAIL: * # Opcode=2124 Name=t2STRD_PRE Format=ARM_FORMAT_THUMBFRM(25) diff --git a/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt index 3f406d4..243c11d 100644 --- a/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "invalid instruction encoding" # XFAIL: * # Opcode=2127 Name=t2STREXB Format=ARM_FORMAT_THUMBFRM(25) diff --git a/test/MC/Disassembler/ARM/invalid-t2STREXD-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2STREXD-thumb.txt index 0f9a16e..7a7c4a5 100644 --- a/test/MC/Disassembler/ARM/invalid-t2STREXD-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-t2STREXD-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=2128 Name=t2STREXD Format=ARM_FORMAT_THUMBFRM(25) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-t2STR_POST-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2STR_POST-thumb.txt index 548ad05..2ad3e7d 100644 --- a/test/MC/Disassembler/ARM/invalid-t2STR_POST-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-t2STR_POST-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=2137 Name=t2STR_POST Format=ARM_FORMAT_THUMBFRM(25) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/ldrd-armv4.txt b/test/MC/Disassembler/ARM/ldrd-armv4.txt index bb87ade..f2fff3f 100644 --- a/test/MC/Disassembler/ARM/ldrd-armv4.txt +++ b/test/MC/Disassembler/ARM/ldrd-armv4.txt @@ -1,5 +1,5 @@ -# RUN: llvm-mc --disassemble %s -triple=armv4-linux-gnueabi |& FileCheck %s -check-prefix=V4 -# RUN: llvm-mc --disassemble %s -triple=armv5te-linux-gnueabi |& FileCheck %s -check-prefix=V5TE +# RUN: llvm-mc --disassemble %s -triple=armv4-linux-gnueabi 2>&1 | FileCheck %s -check-prefix=V4 +# RUN: llvm-mc --disassemble %s -triple=armv5te-linux-gnueabi 2>&1 | FileCheck %s -check-prefix=V5TE # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # ------------------------------------------------------------------------------------------------- diff --git a/test/MC/Disassembler/ARM/neon-tests.txt b/test/MC/Disassembler/ARM/neon-tests.txt index f44c2a0..a7b6b1c 100644 --- a/test/MC/Disassembler/ARM/neon-tests.txt +++ b/test/MC/Disassembler/ARM/neon-tests.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=armv7-apple-darwin9 | FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=armv7-apple-darwin9 -mcpu=cortex-a8 | FileCheck %s # CHECK: vbif q15, q7, q0 0x50 0xe1 0x7e 0xf3 diff --git a/test/MC/Disassembler/ARM/neon.txt b/test/MC/Disassembler/ARM/neon.txt index c5dbee3..649424a 100644 --- a/test/MC/Disassembler/ARM/neon.txt +++ b/test/MC/Disassembler/ARM/neon.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc -triple armv7-unknown-unknown -disassemble -mattr +fp16 < %s | FileCheck %s +# RUN: llvm-mc -triple armv7-unknown-unknown -mcpu=cortex-a9 -disassemble < %s | FileCheck %s 0x20 0x03 0xf1 0xf3 # CHECK: vabs.s8 d16, d16 @@ -1734,6 +1734,25 @@ 0xcf 0x1a 0xe0 0xf4 # CHECK: vld3.32 {d17[1], d19[1], d21[1]}, [r0] +# CHECK: vld3.8 {d0[], d1[], d2[]}, [r4] +0x0f 0x0e 0xa4 0xf4 +# CHECK: vld3.8 {d0[], d1[], d2[]}, [r4]! +0x0d 0x0e 0xa4 0xf4 +# CHECK: vld3.8 {d0[], d2[], d4[]}, [r4], r5 +0x25 0x0e 0xa4 0xf4 +# CHECK: vld3.16 {d0[], d2[], d4[]}, [r4] +0x6f 0x0e 0xa4 0xf4 +# CHECK: vld3.16 {d0[], d1[], d2[]}, [r4]! +0x4d 0x0e 0xa4 0xf4 +# CHECK: vld3.16 {d0[], d2[], d4[]}, [r4], r5 +0x65 0x0e 0xa4 0xf4 +# CHECK: vld3.32 {d0[], d1[], d2[]}, [r4] +0x8f 0x0e 0xa4 0xf4 +# CHECK: vld3.32 {d0[], d1[], d2[]}, [r4]! +0x8d 0x0e 0xa4 0xf4 +# CHECK: vld3.32 {d0[], d2[], d4[]}, [r4], r5 +0xa5 0x0e 0xa4 0xf4 + 0x3f 0x03 0xe0 0xf4 # CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] 0x4f 0x07 0xe0 0xf4 @@ -1745,6 +1764,30 @@ 0x4f 0x1b 0xe0 0xf4 # CHECK: vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] +0x0f 0x0f 0xa4 0xf4 +# CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4] +0x3f 0x0f 0xa4 0xf4 +# CHECK: vld4.8 {d0[], d2[], d4[], d6[]}, [r4, :32] +0x1d 0x0f 0xa4 0xf4 +# CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4, :32]! +0x35 0x0f 0xa4 0xf4 +# CHECK: vld4.8 {d0[], d2[], d4[], d6[]}, [r4, :32], r5 +0x4f 0x0f 0xa4 0xf4 +# CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4] +0x7f 0x0f 0xa4 0xf4 +# CHECK: vld4.16 {d0[], d2[], d4[], d6[]}, [r4, :64] +0x5d 0x0f 0xa4 0xf4 +# CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4, :64]! +0x75 0x0f 0xa4 0xf4 +# CHECK: vld4.16 {d0[], d2[], d4[], d6[]}, [r4, :64], r5 +0x8f 0x0f 0xa4 0xf4 +# CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4] +0xbf 0x0f 0xa4 0xf4 +# CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4, :64] +0xdd 0x0f 0xa4 0xf4 +# CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4, :128]! +0xf5 0x0f 0xa4 0xf4 +# CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4, :128], r5 0x1f 0x07 0x40 0xf4 @@ -1852,7 +1895,26 @@ # CHECK: vst4.8 {d0[0], d1[0], d2[0], d3[0]}, [r0]! 0x3d 0x2a 0x5e 0x6c -# CHECK: vmovvs r2, lr, s29, s30 +# CHECK: vmovvs r2, lr, s27, s28 + +0x31 0x1a 0x42 0xec +0x11 0x1a 0x42 0xec +0x31 0x1a 0x52 0xec +0x11 0x1a 0x52 0xec +# CHECK: vmov s3, s4, r1, r2 +# CHECK: vmov s2, s3, r1, r2 +# CHECK: vmov r1, r2, s3, s4 +# CHECK: vmov r1, r2, s2, s3 + +0x1f 0x1b 0x42 0xec +0x30 0x1b 0x42 0xec +0x1f 0x1b 0x52 0xec +0x30 0x1b 0x52 0xec +# CHECK: vmov d15, r1, r2 +# CHECK: vmov d16, r1, r2 +# CHECK: vmov r1, r2, d15 +# CHECK: vmov r1, r2, d16 + 0xe9 0x1a 0xb2 0x4e # CHECK: vcvttmi.f32.f16 s2, s19 @@ -1869,14 +1931,6 @@ # CHECK: vmov.f32 d0, #1.600000e+01 # CHECK: vmov.f32 q0, #1.600000e+01 -# rdar://10798451 -0xe7 0xf9 0x32 0x1d -# CHECK vld2.8 {d17[], d19[]}, [r7, :16], r2 -0xe7 0xf9 0x3d 0x1d -# CHECK vld2.8 {d17[], d19[]}, [r7, :16]! -0xe7 0xf9 0x3f 0x1d -# CHECK vld2.8 {d17[], d19[]}, [r7, :16] - # rdar://11034702 0x0d 0x87 0x04 0xf4 # CHECK: vst1.8 {d8}, [r4]! diff --git a/test/MC/Disassembler/ARM/neont2.txt b/test/MC/Disassembler/ARM/neont2.txt index 65cd230..7d7010f 100644 --- a/test/MC/Disassembler/ARM/neont2.txt +++ b/test/MC/Disassembler/ARM/neont2.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc -triple thumbv7-unknown-unknown -disassemble -mattr +fp16 < %s | FileCheck %s +# RUN: llvm-mc -triple thumbv7-unknown-unknown -mcpu=cortex-a9 -disassemble < %s | FileCheck %s 0xf1 0xff 0x20 0x03 # CHECK: vabs.s8 d16, d16 @@ -1475,6 +1475,25 @@ 0xe0 0xf9 0xcf 0x1a # CHECK: vld3.32 {d17[1], d19[1], d21[1]}, [r0] +0xa4 0xf9 0x0f 0x0e +# CHECK: vld3.8 {d0[], d1[], d2[]}, [r4] +0xa4 0xf9 0x0d 0x0e +# CHECK: vld3.8 {d0[], d1[], d2[]}, [r4]! +0xa4 0xf9 0x25 0x0e +# CHECK: vld3.8 {d0[], d2[], d4[]}, [r4], r5 +0xa4 0xf9 0x6f 0x0e +# CHECK: vld3.16 {d0[], d2[], d4[]}, [r4] +0xa4 0xf9 0x4d 0x0e +# CHECK: vld3.16 {d0[], d1[], d2[]}, [r4]! +0xa4 0xf9 0x65 0x0e +# CHECK: vld3.16 {d0[], d2[], d4[]}, [r4], r5 +0xa4 0xf9 0x8f 0x0e +# CHECK: vld3.32 {d0[], d1[], d2[]}, [r4] +0xa4 0xf9 0x8d 0x0e +# CHECK: vld3.32 {d0[], d1[], d2[]}, [r4]! +0xa4 0xf9 0xa5 0x0e +# CHECK: vld3.32 {d0[], d2[], d4[]}, [r4], r5 + 0xe0 0xf9 0x3f 0x03 # CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] 0xe0 0xf9 0x4f 0x07 @@ -1486,6 +1505,31 @@ 0xe0 0xf9 0x4f 0x1b # CHECK: vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] +0xa4 0xf9 0x0f 0x0f +# CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4] +0xa4 0xf9 0x3f 0x0f +# CHECK: vld4.8 {d0[], d2[], d4[], d6[]}, [r4, :32] +0xa4 0xf9 0x1d 0x0f +# CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4, :32]! +0xa4 0xf9 0x35 0x0f +# CHECK: vld4.8 {d0[], d2[], d4[], d6[]}, [r4, :32], r5 +0xa4 0xf9 0x4f 0x0f +# CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4] +0xa4 0xf9 0x7f 0x0f +# CHECK: vld4.16 {d0[], d2[], d4[], d6[]}, [r4, :64] +0xa4 0xf9 0x5d 0x0f +# CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4, :64]! +0xa4 0xf9 0x75 0x0f +# CHECK: vld4.16 {d0[], d2[], d4[], d6[]}, [r4, :64], r5 +0xa4 0xf9 0x8f 0x0f +# CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4] +0xa4 0xf9 0xbf 0x0f +# CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4, :64] +0xa4 0xf9 0xdd 0x0f +# CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4, :128]! +0xa4 0xf9 0xf5 0x0f +# CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4, :128], r5 + 0x40 0xf9 0x1f 0x07 # CHECK: vst1.8 {d16}, [r0, :64] 0x40 0xf9 0x4f 0x07 @@ -1998,3 +2042,13 @@ # CHECK: vld2.16 {d0[], d2[]}, [r3], r4 0xa3 0xf9 0xa4 0x0d # CHECK: vld2.32 {d0[], d2[]}, [r3], r4 + + +# rdar://10798451 +0xe7 0xf9 0x32 0x1d +# CHECK: vld2.8 {d17[], d19[]}, [r7, :16], r2 +0xe7 0xf9 0x3d 0x1d +# CHECK: vld2.8 {d17[], d19[]}, [r7, :16]! +0xe7 0xf9 0x3f 0x1d +# CHECK: vld2.8 {d17[], d19[]}, [r7, :16] + diff --git a/test/MC/Disassembler/ARM/thumb-tests.txt b/test/MC/Disassembler/ARM/thumb-tests.txt index 18b8f47..c08585a 100644 --- a/test/MC/Disassembler/ARM/thumb-tests.txt +++ b/test/MC/Disassembler/ARM/thumb-tests.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 -mattr +t2xtpk,+mp | FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 -mcpu=cortex-a9-mp | FileCheck %s # CHECK: add r5, sp, #68 0x11 0xad @@ -301,3 +301,11 @@ # CHECK: mrs r0, apsr 0xef 0xf3 0x00 0x80 + +# rdar://11313994 +# CHECK: blx #2313244 +0x34 0xf2 0x0e 0xee + +# rdar://11324693 +# CHECK: bl #-12303196 +0x44 0xf4 0x52 0xda diff --git a/test/MC/Disassembler/ARM/thumb1.txt b/test/MC/Disassembler/ARM/thumb1.txt index 17c4bad..5b70262 100644 --- a/test/MC/Disassembler/ARM/thumb1.txt +++ b/test/MC/Disassembler/ARM/thumb1.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc -triple=thumbv6-apple-darwin -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple=thumbv6-apple-darwin -disassemble -show-encoding < %s | FileCheck %s #------------------------------------------------------------------------------ # ADC (register) @@ -83,6 +83,15 @@ 0xb1 0x43 #------------------------------------------------------------------------------ +# B +#------------------------------------------------------------------------------ +# CHECK: bls #128 @ encoding: [0x40,0xd9] +# CHECK: beq #-256 @ encoding: [0x80,0xd0] + +0x40 0xd9 +0x80 0xd0 + +#------------------------------------------------------------------------------ # BKPT #------------------------------------------------------------------------------ # CHECK: bkpt #0 @@ -516,15 +525,3 @@ 0xd7 0xb2 0xa1 0xb2 - - -#------------------------------------------------------------------------------ -# WFE/WFI/YIELD -#------------------------------------------------------------------------------ -# CHECK: wfe -# CHECK: wfi -# CHECK: yield - -0x20 0xbf -0x30 0xbf -0x10 0xbf diff --git a/test/MC/Disassembler/ARM/thumb2.txt b/test/MC/Disassembler/ARM/thumb2.txt index ed8d988..42ebe58 100644 --- a/test/MC/Disassembler/ARM/thumb2.txt +++ b/test/MC/Disassembler/ARM/thumb2.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc -triple=thumbv7-apple-darwin -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 -disassemble < %s | FileCheck %s #------------------------------------------------------------------------------ # ADC (immediate) @@ -92,9 +92,11 @@ #------------------------------------------------------------------------------ # CHECK: subw r11, pc, #3270 # CHECK: subw r11, pc, #826 +# CHECK: subw r1, pc, #0 0xaf 0xf6 0xc6 0x4b 0xaf 0xf2 0x3a 0x3b +0xaf 0xf2 0x00 0x01 #------------------------------------------------------------------------------ # AND (immediate) @@ -344,23 +346,37 @@ #------------------------------------------------------------------------------ #CHECK: dmb sy #CHECK: dmb st +#CHECK: dmb #0xd +#CHECK: dmb #0xc #CHECK: dmb ish #CHECK: dmb ishst +#CHECK: dmb #0x9 +#CHECK: dmb #0x8 #CHECK: dmb nsh #CHECK: dmb nshst +#CHECK: dmb #0x5 +#CHECK: dmb #0x4 #CHECK: dmb osh #CHECK: dmb oshst -#CHECK: dmb +#CHECK: dmb #0x1 +#CHECK: dmb #0x0 0xbf 0xf3 0x5f 0x8f 0xbf 0xf3 0x5e 0x8f +0xbf 0xf3 0x5d 0x8f +0xbf 0xf3 0x5c 0x8f 0xbf 0xf3 0x5b 0x8f 0xbf 0xf3 0x5a 0x8f +0xbf 0xf3 0x59 0x8f +0xbf 0xf3 0x58 0x8f 0xbf 0xf3 0x57 0x8f 0xbf 0xf3 0x56 0x8f +0xbf 0xf3 0x55 0x8f +0xbf 0xf3 0x54 0x8f 0xbf 0xf3 0x53 0x8f 0xbf 0xf3 0x52 0x8f -0xbf 0xf3 0x5f 0x8f +0xbf 0xf3 0x51 0x8f +0xbf 0xf3 0x50 0x8f #------------------------------------------------------------------------------ @@ -368,21 +384,37 @@ #------------------------------------------------------------------------------ #CHECK: dsb sy #CHECK: dsb st +#CHECK: dsb #0xd +#CHECK: dsb #0xc #CHECK: dsb ish #CHECK: dsb ishst +#CHECK: dsb #0x9 +#CHECK: dsb #0x8 #CHECK: dsb nsh #CHECK: dsb nshst +#CHECK: dsb #0x5 +#CHECK: dsb #0x4 #CHECK: dsb osh #CHECK: dsb oshst +#CHECK: dsb #0x1 +#CHECK: dsb #0x0 0xbf 0xf3 0x4f 0x8f 0xbf 0xf3 0x4e 0x8f +0xbf 0xf3 0x4d 0x8f +0xbf 0xf3 0x4c 0x8f 0xbf 0xf3 0x4b 0x8f 0xbf 0xf3 0x4a 0x8f +0xbf 0xf3 0x49 0x8f +0xbf 0xf3 0x48 0x8f 0xbf 0xf3 0x47 0x8f 0xbf 0xf3 0x46 0x8f +0xbf 0xf3 0x45 0x8f +0xbf 0xf3 0x44 0x8f 0xbf 0xf3 0x43 0x8f 0xbf 0xf3 0x42 0x8f +0xbf 0xf3 0x41 0x8f +0xbf 0xf3 0x40 0x8f #------------------------------------------------------------------------------ @@ -609,6 +641,9 @@ # CHECK: ldrd r3, r5, [r6], #-8 # CHECK: ldrd r3, r5, [r6] # CHECK: ldrd r8, r1, [r3] +# CHECK: ldrd r0, r1, [r2], #-0 +# CHECK: ldrd r0, r1, [r2, #-0]! +# CHECK: ldrd r0, r1, [r2, #-0] 0xd6 0xe9 0x06 0x35 0xf6 0xe9 0x06 0x35 @@ -616,6 +651,9 @@ 0x76 0xe8 0x02 0x35 0xd6 0xe9 0x00 0x35 0xd3 0xe9 0x00 0x81 +0x72 0xe8 0x00 0x01 +0x72 0xe9 0x00 0x01 +0x52 0xe9 0x00 0x01 #------------------------------------------------------------------------------ @@ -1790,12 +1828,16 @@ # STRD (immediate) #------------------------------------------------------------------------------ # CHECK: strd r6, r3, [r5], #-8 -# CHECK: strd r8, r5, [r5]{{$}} +# CHECK: strd r8, r5, [r5], #-0 # CHECK: strd r7, r4, [r5], #-4 +# CHECK: strd r0, r1, [r2, #-0]! +# CHECK: strd r0, r1, [r2, #-0] 0x65 0xe8 0x02 0x63 0x65 0xe8 0x00 0x85 0x65 0xe8 0x01 0x74 +0x62 0xe9 0x00 0x01 +0x42 0xe9 0x00 0x01 #------------------------------------------------------------------------------ # STREX/STREXB/STREXH/STREXD diff --git a/test/MC/Disassembler/ARM/unpredictable-ADC-arm.txt b/test/MC/Disassembler/ARM/unpredictable-ADC-arm.txt index 275bae2f..d5c8cbb 100644 --- a/test/MC/Disassembler/ARM/unpredictable-ADC-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-ADC-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi 2>&1 | FileCheck %s # CHECK: potentially undefined # CHECK: 0x1f 0x12 0xb0 0x00 diff --git a/test/MC/Disassembler/ARM/unpredictable-ADDREXT3-arm.txt b/test/MC/Disassembler/ARM/unpredictable-ADDREXT3-arm.txt index 635b66e..d251eb4 100644 --- a/test/MC/Disassembler/ARM/unpredictable-ADDREXT3-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-ADDREXT3-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi 2>&1 | FileCheck %s # CHECK: potentially undefined # CHECK: 0xd1 0xf1 0x5f 0x01 diff --git a/test/MC/Disassembler/ARM/unpredictable-AExtI-arm.txt b/test/MC/Disassembler/ARM/unpredictable-AExtI-arm.txt new file mode 100644 index 0000000..d0cb520 --- /dev/null +++ b/test/MC/Disassembler/ARM/unpredictable-AExtI-arm.txt @@ -0,0 +1,62 @@ +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi 2>&1 | FileCheck %s -check-prefix=CHECK-WARN +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi 2>&1 | FileCheck %s + +# CHECK-WARN: potentially undefined +# CHECK-WARN: 0x74 0x03 0xaf 0x06 +# CHECK: sxtb +0x74 0x03 0xaf 0x06 + +# CHECK-WARN: potentially undefined +# CHECK-WARN: 0x74 0x3f 0xbf 0x06 +# CHECK: sxth +0x74 0x3f 0xbf 0x06 + +# CHECK-WARN: potentially undefined +# CHECK-WARN: 0x74 0x3f 0xa6 0x06 +# CHECK: sxtab +0x74 0x3f 0xa6 0x06 + +# CHECK-WARN: potentially undefined +# CHECK-WARN: 0x74 0x3f 0xb7 0x06 +# CHECK: sxtah +0x74 0x3f 0xb7 0x06 + +# CHECK-WARN: potentially undefined +# CHECK-WARN: 0x74 0x3f 0x8f 0x06 +# CHECK: sxtb16 +0x74 0x3f 0x8f 0x06 + +# CHECK-WARN: potentially undefined +# CHECK-WARN: 0x74 0x3f 0x86 0x06 +# CHECK: sxtab16 +0x74 0x3f 0x86 0x06 + +# CHECK-WARN: potentially undefined +# CHECK-WARN: 0x74 0x3f 0xef 0x06 +# CHECK: uxtb +0x74 0x3f 0xef 0x06 + +# CHECK-WARN: potentially undefined +# CHECK-WARN: 0x74 0x3f 0xff 0x06 +# CHECK: uxth +0x74 0x3f 0xff 0x06 + +# CHECK-WARN: potentially undefined +# CHECK-WARN: 0x74 0x3f 0xcf 0x06 +# CHECK: uxtb16 +0x74 0x3f 0xcf 0x06 + +# CHECK-WARN: potentially undefined +# CHECK-WARN: 0x74 0x3f 0xe4 0x06 +# CHECK: uxtab +0x74 0x3f 0xe4 0x06 + +# CHECK-WARN: potentially undefined +# CHECK-WARN: 0x74 0x3f 0xf2 0x06 +# CHECK: uxtah +0x74 0x3f 0xf2 0x06 + +# CHECK-WARN: potentially undefined +# CHECK-WARN: 0x74 0x3f 0xc4 0x06 +# CHECK: uxtab16 +0x74 0x3f 0xc4 0x06 diff --git a/test/MC/Disassembler/ARM/unpredictable-AI1cmp-arm.txt b/test/MC/Disassembler/ARM/unpredictable-AI1cmp-arm.txt index dac4390..554ae53 100644 --- a/test/MC/Disassembler/ARM/unpredictable-AI1cmp-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-AI1cmp-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi 2>&1 | FileCheck %s # CHECK: potentially undefined # CHECK: 0x01 0x10 0x50 0x03 diff --git a/test/MC/Disassembler/ARM/unpredictable-LDR-arm.txt b/test/MC/Disassembler/ARM/unpredictable-LDR-arm.txt index ed5e350..66073a8 100644 --- a/test/MC/Disassembler/ARM/unpredictable-LDR-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-LDR-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi 2>&1 | FileCheck %s # CHECK: potentially undefined # CHECK: 0xff 0x00 0xb9 0x00 diff --git a/test/MC/Disassembler/ARM/unpredictable-LDRD-arm.txt b/test/MC/Disassembler/ARM/unpredictable-LDRD-arm.txt index a8f54f7..572d844 100644 --- a/test/MC/Disassembler/ARM/unpredictable-LDRD-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-LDRD-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | FileCheck %s # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # ------------------------------------------------------------------------------------------------- diff --git a/test/MC/Disassembler/ARM/unpredictable-LSL-regform.txt b/test/MC/Disassembler/ARM/unpredictable-LSL-regform.txt index f7d6bc6..9c26953 100644 --- a/test/MC/Disassembler/ARM/unpredictable-LSL-regform.txt +++ b/test/MC/Disassembler/ARM/unpredictable-LSL-regform.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | FileCheck %s # Opcode=196 Name=MOVs Format=ARM_FORMAT_DPSOREGFRM(5) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/unpredictable-MRRC2-arm.txt b/test/MC/Disassembler/ARM/unpredictable-MRRC2-arm.txt index 26b286d..439aaed 100644 --- a/test/MC/Disassembler/ARM/unpredictable-MRRC2-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-MRRC2-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi 2>&1 | FileCheck %s # CHECK: potentially undefined # CHECK: 0x00 0x10 0x51 0xfc diff --git a/test/MC/Disassembler/ARM/unpredictable-MRS-arm.txt b/test/MC/Disassembler/ARM/unpredictable-MRS-arm.txt index 3e472cd..d785341 100644 --- a/test/MC/Disassembler/ARM/unpredictable-MRS-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-MRS-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | FileCheck %s # CHECK: warning: potentially undefined # CHECK: 0x00 0xf0 0x0f 0x01 diff --git a/test/MC/Disassembler/ARM/unpredictable-MUL-arm.txt b/test/MC/Disassembler/ARM/unpredictable-MUL-arm.txt index 3db86cc..472868f 100644 --- a/test/MC/Disassembler/ARM/unpredictable-MUL-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-MUL-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi 2>&1 | FileCheck %s # CHECK: potentially undefined # CHECK: 0x93 0x12 0x01 0x00 diff --git a/test/MC/Disassembler/ARM/unpredictable-RSC-arm.txt b/test/MC/Disassembler/ARM/unpredictable-RSC-arm.txt index 5b13610..fdfda6d 100644 --- a/test/MC/Disassembler/ARM/unpredictable-RSC-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-RSC-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | FileCheck %s # Opcode=261 Name=RSCrs Format=ARM_FORMAT_DPSOREGFRM(5) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/unpredictable-SEL-arm.txt b/test/MC/Disassembler/ARM/unpredictable-SEL-arm.txt new file mode 100644 index 0000000..a2a8770 --- /dev/null +++ b/test/MC/Disassembler/ARM/unpredictable-SEL-arm.txt @@ -0,0 +1,5 @@ +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi 2>&1 | FileCheck %s + +# CHECK: potentially undefined +# CHECK: 0xb4 0x38 0x80 0x06 +0xb4 0x38 0x80 0x06 diff --git a/test/MC/Disassembler/ARM/unpredictable-SHADD16-arm.txt b/test/MC/Disassembler/ARM/unpredictable-SHADD16-arm.txt index 8ec49ca..741d059 100644 --- a/test/MC/Disassembler/ARM/unpredictable-SHADD16-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-SHADD16-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | FileCheck %s # CHECK: warning: potentially undefined # CHECK: shadd16 r5, r7, r0 diff --git a/test/MC/Disassembler/ARM/unpredictable-SSAT-arm.txt b/test/MC/Disassembler/ARM/unpredictable-SSAT-arm.txt index 874378e..832aa3f 100644 --- a/test/MC/Disassembler/ARM/unpredictable-SSAT-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-SSAT-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | FileCheck %s # Opcode=322 Name=SSAT Format=ARM_FORMAT_SATFRM(13) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/unpredictable-STRBrs-arm.txt b/test/MC/Disassembler/ARM/unpredictable-STRBrs-arm.txt index fef6125..5e62802 100644 --- a/test/MC/Disassembler/ARM/unpredictable-STRBrs-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-STRBrs-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | FileCheck %s # Opcode=355 Name=STRBrs Format=ARM_FORMAT_STFRM(7) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/unpredictable-UQADD8-arm.txt b/test/MC/Disassembler/ARM/unpredictable-UQADD8-arm.txt index 4c4c9ab..85b52dd 100644 --- a/test/MC/Disassembler/ARM/unpredictable-UQADD8-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-UQADD8-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | FileCheck %s # Opcode=426 Name=UQADD8 Format=ARM_FORMAT_DPFRM(4) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/unpredictable-swp-arm.txt b/test/MC/Disassembler/ARM/unpredictable-swp-arm.txt index 64bb171..eef5d9f 100644 --- a/test/MC/Disassembler/ARM/unpredictable-swp-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-swp-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi 2>&1 | FileCheck %s # CHECK: potentially undefined # CHECK: 0x9f 0x10 0x03 0x01 diff --git a/test/MC/Disassembler/ARM/unpredictables-thumb.txt b/test/MC/Disassembler/ARM/unpredictables-thumb.txt index e7645f0..925dcd3 100644 --- a/test/MC/Disassembler/ARM/unpredictables-thumb.txt +++ b/test/MC/Disassembler/ARM/unpredictables-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumbv7 |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=thumbv7 2>&1 | FileCheck %s 0x01 0x47 # CHECK: 3:1: warning: potentially undefined |
