diff options
Diffstat (limited to 'test/MC/ARM')
65 files changed, 4937 insertions, 0 deletions
diff --git a/test/MC/ARM/arm_fixups.s b/test/MC/ARM/arm_fixups.s new file mode 100644 index 0000000..0dceb83 --- /dev/null +++ b/test/MC/ARM/arm_fixups.s @@ -0,0 +1,7 @@ +// RUN: llvm-mc -triple arm-unknown-unknown %s --show-encoding > %t +// RUN: FileCheck < %t %s + +// CHECK: bl _printf @ encoding: [A,A,A,0xeb] +// CHECK: @ fixup A - offset: 0, value: _printf, kind: fixup_arm_uncondbranch +bl _printf +
\ No newline at end of file diff --git a/test/MC/ARM/arm_instructions.s b/test/MC/ARM/arm_instructions.s new file mode 100644 index 0000000..fbec789 --- /dev/null +++ b/test/MC/ARM/arm_instructions.s @@ -0,0 +1,284 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding %s | FileCheck %s + +@ CHECK: nop +@ CHECK: encoding: [0x00,0xf0,0x20,0xe3] + nop + +@ CHECK: nopeq +@ CHECK: encoding: [0x00,0xf0,0x20,0x03] + nopeq + +@ CHECK: trap +@ CHECK: encoding: [0xfe,0xde,0xff,0xe7] + trap + +@ CHECK: bx lr +@ CHECK: encoding: [0x1e,0xff,0x2f,0xe1] + bx lr + +@ CHECK: vqdmull.s32 q8, d17, d16 +@ CHECK: encoding: [0xa0,0x0d,0xe1,0xf2] + vqdmull.s32 q8, d17, d16 + +@ CHECK: ldmia r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x92,0xe8] +@ CHECK: ldmib r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x92,0xe9] +@ CHECK: ldmda r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x12,0xe8] +@ CHECK: ldmdb r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x12,0xe9] + ldmia r2, {r1,r3-r6,sp} + ldmib r2, {r1,r3-r6,sp} + ldmda r2, {r1,r3-r6,sp} + ldmdb r2, {r1,r3-r6,sp} + +@ CHECK: stmia r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x82,0xe8] +@ CHECK: stmib r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x82,0xe9] +@ CHECK: stmda r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x02,0xe8] +@ CHECK: stmdb r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x02,0xe9] + stmia r2, {r1,r3-r6,sp} + stmib r2, {r1,r3-r6,sp} + stmda r2, {r1,r3-r6,sp} + stmdb r2, {r1,r3-r6,sp} + +@ CHECK: ldmia r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xb2,0xe8] +@ CHECK: ldmib r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xb2,0xe9] +@ CHECK: ldmda r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x32,0xe8] +@ CHECK: ldmdb r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x32,0xe9] + ldmia r2!, {r1,r3-r6,sp} + ldmib r2!, {r1,r3-r6,sp} + ldmda r2!, {r1,r3-r6,sp} + ldmdb r2!, {r1,r3-r6,sp} + +@ CHECK: stmia r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xa2,0xe8] +@ CHECK: stmib r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xa2,0xe9] +@ CHECK: stmda r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x22,0xe8] +@ CHECK: stmdb r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x22,0xe9] + stmia r2!, {r1,r3-r6,sp} + stmib r2!, {r1,r3-r6,sp} + stmda r2!, {r1,r3-r6,sp} + stmdb r2!, {r1,r3-r6,sp} + +@ CHECK: and r1, r2, r3 @ encoding: [0x03,0x10,0x02,0xe0] + and r1,r2,r3 + +@ FIXME: This is wrong, we are dropping the 's' for now. +@ CHECK-FIXME: ands r1, r2, r3 @ encoding: [0x03,0x10,0x12,0xe0] + ands r1,r2,r3 + +@ CHECK: eor r1, r2, r3 @ encoding: [0x03,0x10,0x22,0xe0] + eor r1,r2,r3 + +@ FIXME: This is wrong, we are dropping the 's' for now. +@ CHECK-FIXME: eors r1, r2, r3 @ encoding: [0x03,0x10,0x32,0xe0] + eors r1,r2,r3 + +@ CHECK: sub r1, r2, r3 @ encoding: [0x03,0x10,0x42,0xe0] + sub r1,r2,r3 + +@ FIXME: This is wrong, we are dropping the 's' for now. +@ CHECK-FIXME: subs r1, r2, r3 @ encoding: [0x03,0x10,0x52,0xe0] + subs r1,r2,r3 + +@ CHECK: add r1, r2, r3 @ encoding: [0x03,0x10,0x82,0xe0] + add r1,r2,r3 + +@ FIXME: This is wrong, we are dropping the 's' for now. +@ CHECK-FIXME: adds r1, r2, r3 @ encoding: [0x03,0x10,0x92,0xe0] + adds r1,r2,r3 + +@ CHECK: adc r1, r2, r3 @ encoding: [0x03,0x10,0xa2,0xe0] + adc r1,r2,r3 + +@ CHECK: sbc r1, r2, r3 @ encoding: [0x03,0x10,0xc2,0xe0] + sbc r1,r2,r3 + +@ CHECK: orr r1, r2, r3 @ encoding: [0x03,0x10,0x82,0xe1] + orr r1,r2,r3 + +@ FIXME: This is wrong, we are dropping the 's' for now. +@ CHECK-FIXME: orrs r1, r2, r3 @ encoding: [0x03,0x10,0x92,0xe1] + orrs r1,r2,r3 + +@ CHECK: bic r1, r2, r3 @ encoding: [0x03,0x10,0xc2,0xe1] + bic r1,r2,r3 + +@ FIXME: This is wrong, we are dropping the 's' for now. +@ CHECK-FIXME: bics r1, r2, r3 @ encoding: [0x03,0x10,0xd2,0xe1] + bics r1,r2,r3 + +@ CHECK: mov r1, r2 @ encoding: [0x02,0x10,0xa0,0xe1] + mov r1,r2 + +@ CHECK: mvn r1, r2 @ encoding: [0x02,0x10,0xe0,0xe1] + mvn r1,r2 + +@ FIXME: This is wrong, we are dropping the 's' for now. +@ CHECK-FIXME: mvns r1, r2 @ encoding: [0x02,0x10,0xf0,0xe1] + mvns r1,r2 + +@ CHECK: rsb r1, r2, r3 @ encoding: [0x03,0x10,0x62,0xe0] + rsb r1,r2,r3 + +@ CHECK: rsc r1, r2, r3 @ encoding: [0x03,0x10,0xe2,0xe0] + rsc r1,r2,r3 + +@ FIXME: This is broken, CCOut operands don't work correctly when their presence +@ may depend on flags. +@ CHECK-FIXME:: mlas r1, r2, r3, r4 @ encoding: [0x92,0x43,0x31,0xe0] +@ mlas r1,r2,r3,r4 + +@ CHECK: bfi r0, r0, #5, #7 @ encoding: [0x90,0x02,0xcb,0xe7] + bfi r0, r0, #5, #7 + +@ CHECK: bkpt #10 @ encoding: [0x7a,0x00,0x20,0xe1] + bkpt #10 + +@ CHECK: isb @ encoding: [0x6f,0xf0,0x7f,0xf5] + isb +@ CHECK: mrs r8, cpsr @ encoding: [0x00,0x80,0x0f,0xe1] + mrs r8, cpsr + +@ CHECK: mcr p7, #1, r5, c1, c1, #4 @ encoding: [0x91,0x57,0x21,0xee] + mcr p7, #1, r5, c1, c1, #4 +@ CHECK: mrc p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xee] + mrc p14, #0, r1, c1, c2, #4 +@ CHECK: mcrr p7, #1, r5, r4, c1 @ encoding: [0x11,0x57,0x44,0xec] + mcrr p7, #1, r5, r4, c1 +@ CHECK: mrrc p7, #1, r5, r4, c1 @ encoding: [0x11,0x57,0x54,0xec] + mrrc p7, #1, r5, r4, c1 + +@ CHECK: mcr2 p7, #1, r5, c1, c1, #4 @ encoding: [0x91,0x57,0x21,0xfe] + mcr2 p7, #1, r5, c1, c1, #4 +@ CHECK: mrc2 p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xfe] + mrc2 p14, #0, r1, c1, c2, #4 +@ CHECK: mcrr2 p7, #1, r5, r4, c1 @ encoding: [0x11,0x57,0x44,0xfc] + mcrr2 p7, #1, r5, r4, c1 +@ CHECK: mrrc2 p7, #1, r5, r4, c1 @ encoding: [0x11,0x57,0x54,0xfc] + mrrc2 p7, #1, r5, r4, c1 + +@ CHECK: cdp p7, #1, c1, c1, c1, #4 @ encoding: [0x81,0x17,0x11,0xee] + cdp p7, #1, c1, c1, c1, #4 +@ CHECK: cdp2 p7, #1, c1, c1, c1, #4 @ encoding: [0x81,0x17,0x11,0xfe] + cdp2 p7, #1, c1, c1, c1, #4 + +@ CHECK: clrex @ encoding: [0x1f,0xf0,0x7f,0xf5] + clrex + +@ CHECK: clz r9, r0 @ encoding: [0x10,0x9f,0x6f,0xe1] + clz r9, r0 + +@ CHECK: qadd r1, r2, r3 @ encoding: [0x52,0x10,0x03,0xe1] + qadd r1, r2, r3 + +@ CHECK: qsub r1, r2, r3 @ encoding: [0x52,0x10,0x23,0xe1] + qsub r1, r2, r3 + +@ CHECK: qdadd r1, r2, r3 @ encoding: [0x52,0x10,0x43,0xe1] + qdadd r1, r2, r3 + +@ CHECK: qdsub r1, r2, r3 @ encoding: [0x52,0x10,0x63,0xe1] + qdsub r1, r2, r3 + +@ CHECK: wfe @ encoding: [0x02,0xf0,0x20,0xe3] + wfe + +@ CHECK: wfi @ encoding: [0x03,0xf0,0x20,0xe3] + wfi + +@ CHECK: yield @ encoding: [0x01,0xf0,0x20,0xe3] + yield + +@ CHECK: nop @ encoding: [0x00,0xf0,0x20,0xe3] + nop + +@ CHECK: dmb sy @ encoding: [0x5f,0xf0,0x7f,0xf5] + dmb sy + +@ CHECK: dmb st @ encoding: [0x5e,0xf0,0x7f,0xf5] + dmb st + +@ CHECK: dmb ish @ encoding: [0x5b,0xf0,0x7f,0xf5] + dmb ish + +@ CHECK: dmb ishst @ encoding: [0x5a,0xf0,0x7f,0xf5] + dmb ishst + +@ CHECK: dmb nsh @ encoding: [0x57,0xf0,0x7f,0xf5] + dmb nsh + +@ CHECK: dmb nshst @ encoding: [0x56,0xf0,0x7f,0xf5] + dmb nshst + +@ CHECK: dmb osh @ encoding: [0x53,0xf0,0x7f,0xf5] + dmb osh + +@ CHECK: dmb oshst @ encoding: [0x52,0xf0,0x7f,0xf5] + dmb oshst + +@ CHECK: dsb sy @ encoding: [0x4f,0xf0,0x7f,0xf5] + dsb sy + +@ CHECK: dsb st @ encoding: [0x4e,0xf0,0x7f,0xf5] + dsb st + +@ CHECK: dsb ish @ encoding: [0x4b,0xf0,0x7f,0xf5] + dsb ish + +@ CHECK: dsb ishst @ encoding: [0x4a,0xf0,0x7f,0xf5] + dsb ishst + +@ CHECK: dsb nsh @ encoding: [0x47,0xf0,0x7f,0xf5] + dsb nsh + +@ CHECK: dsb nshst @ encoding: [0x46,0xf0,0x7f,0xf5] + dsb nshst + +@ CHECK: dsb osh @ encoding: [0x43,0xf0,0x7f,0xf5] + dsb osh + +@ CHECK: dsb oshst @ encoding: [0x42,0xf0,0x7f,0xf5] + dsb oshst + +@ CHECK: cpsie aif @ encoding: [0xc0,0x01,0x08,0xf1] + cpsie aif + +@ CHECK: cps #15 @ encoding: [0x0f,0x00,0x02,0xf1] + cps #15 + +@ CHECK: cpsie if, #10 @ encoding: [0xca,0x00,0x0a,0xf1] + cpsie if, #10 + +@ CHECK: msr cpsr_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1] + msr apsr, r0 + +@ CHECK: msr cpsr_s, r0 @ encoding: [0x00,0xf0,0x24,0xe1] + msr apsr_g, r0 + +@ CHECK: msr cpsr_f, r0 @ encoding: [0x00,0xf0,0x28,0xe1] + msr apsr_nzcvq, r0 + +@ CHECK: msr cpsr_fs, r0 @ encoding: [0x00,0xf0,0x2c,0xe1] + msr apsr_nzcvqg, r0 + +@ CHECK: msr cpsr_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1] + msr cpsr_fc, r0 + +@ CHECK: msr cpsr_c, r0 @ encoding: [0x00,0xf0,0x21,0xe1] + msr cpsr_c, r0 + +@ CHECK: msr cpsr_x, r0 @ encoding: [0x00,0xf0,0x22,0xe1] + msr cpsr_x, r0 + +@ CHECK: msr cpsr_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1] + msr cpsr_fc, r0 + +@ CHECK: msr cpsr_fsx, r0 @ encoding: [0x00,0xf0,0x2e,0xe1] + msr cpsr_fsx, r0 + +@ CHECK: msr spsr_fc, r0 @ encoding: [0x00,0xf0,0x69,0xe1] + msr spsr_fc, r0 + +@ CHECK: msr spsr_fsxc, r0 @ encoding: [0x00,0xf0,0x6f,0xe1] + msr spsr_fsxc, r0 + +@ CHECK: msr cpsr_fsxc, r0 @ encoding: [0x00,0xf0,0x2f,0xe1] + msr cpsr_fsxc, r0 + diff --git a/test/MC/ARM/arm_word_directive.s b/test/MC/ARM/arm_word_directive.s new file mode 100644 index 0000000..e782479 --- /dev/null +++ b/test/MC/ARM/arm_word_directive.s @@ -0,0 +1,6 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown %s | FileCheck %s + +@ CHECK: TEST0: +@ CHECK: .long 3 +TEST0: + .word 3 diff --git a/test/MC/ARM/dg.exp b/test/MC/ARM/dg.exp new file mode 100644 index 0000000..055fa25 --- /dev/null +++ b/test/MC/ARM/dg.exp @@ -0,0 +1,5 @@ +load_lib llvm.exp + +if { [llvm_supports_target ARM] } { + RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp,s}]] +} diff --git a/test/MC/ARM/elf-eflags-eabi.s b/test/MC/ARM/elf-eflags-eabi.s new file mode 100644 index 0000000..ea89eac --- /dev/null +++ b/test/MC/ARM/elf-eflags-eabi.s @@ -0,0 +1,13 @@ +@ RUN: llvm-mc %s -triple=armv7-linux-gnueabi -filetype=obj -o - | \ +@ RUN: elf-dump --dump-section-data | FileCheck -check-prefix=OBJ %s + .syntax unified + .text + .globl barf + .align 2 + .type barf,%function +barf: @ @barf +@ BB#0: @ %entry + b foo + +@@@ make sure the EF_ARM_EABIMASK comes out OK +@OBJ: 'e_flags', 0x05000000 diff --git a/test/MC/ARM/elf-movt.s b/test/MC/ARM/elf-movt.s new file mode 100644 index 0000000..0fe7c50 --- /dev/null +++ b/test/MC/ARM/elf-movt.s @@ -0,0 +1,39 @@ +@ RUN: llvm-mc %s -triple=armv7-linux-gnueabi | FileCheck -check-prefix=ASM %s +@ RUN: llvm-mc %s -triple=armv7-linux-gnueabi -filetype=obj -o - | \ +@ RUN: elf-dump --dump-section-data | FileCheck -check-prefix=OBJ %s + .syntax unified + .text + .globl barf + .align 2 + .type barf,%function +barf: @ @barf +@ BB#0: @ %entry + movw r0, :lower16:GOT-(.LPC0_2+8) + movt r0, :upper16:GOT-(.LPC0_2+16) +.LPC0_2: +@ ASM: movw r0, :lower16:(GOT-(.LPC0_2+8)) +@ ASM-NEXT: movt r0, :upper16:(GOT-(.LPC0_2+16)) + +@@ make sure that the text section fixups are sane too +@ OBJ: '.text' +@ OBJ-NEXT: 'sh_type', 0x00000001 +@ OBJ-NEXT: 'sh_flags', 0x00000006 +@ OBJ-NEXT: 'sh_addr', 0x00000000 +@ OBJ-NEXT: 'sh_offset', 0x00000034 +@ OBJ-NEXT: 'sh_size', 0x00000008 +@ OBJ-NEXT: 'sh_link', 0x00000000 +@ OBJ-NEXT: 'sh_info', 0x00000000 +@ OBJ-NEXT: 'sh_addralign', 0x00000004 +@ OBJ-NEXT: 'sh_entsize', 0x00000000 +@ OBJ-NEXT: '_section_data', 'f00f0fe3 ff0f4fe3' + +@ OBJ: Relocation 0x00000000 +@ OBJ-NEXT: 'r_offset', 0x00000000 +@ OBJ-NEXT: 'r_sym' +@ OBJ-NEXT: 'r_type', 0x0000002d + +@ OBJ: Relocation 0x00000001 +@ OBJ-NEXT: 'r_offset', 0x00000004 +@ OBJ-NEXT: 'r_sym' +@ OBJ-NEXT: 'r_type', 0x0000002e + diff --git a/test/MC/ARM/elf-reloc-01.ll b/test/MC/ARM/elf-reloc-01.ll new file mode 100644 index 0000000..6b83c95 --- /dev/null +++ b/test/MC/ARM/elf-reloc-01.ll @@ -0,0 +1,71 @@ +;; RUN: llc -mtriple=armv7-linux-gnueabi -O3 \ +;; RUN: -mcpu=cortex-a8 -mattr=-neon -mattr=+vfp2 -arm-reserve-r9 \ +;; RUN: -filetype=obj %s -o - | \ +;; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=OBJ %s + +;; FIXME: This file needs to be in .s form! +;; The args to llc are there to constrain the codegen only. +;; +;; Ensure no regression on ARM/gcc compatibility for +;; emitting explicit symbol relocs for nonexternal symbols +;; versus section symbol relocs (with offset) - +;; +;; Default llvm behavior is to emit as section symbol relocs nearly +;; everything that is not an undefined external. Unfortunately, this +;; diverges from what codesourcery ARM/gcc does! +;; +;; Tests that reloc to _MergedGlobals show up as explicit symbol reloc + + +target triple = "armv7-none-linux-gnueabi" + +@var_tls = thread_local global i32 1 +@var_tls_double = thread_local global double 1.000000e+00 +@var_static = internal global i32 1 +@var_static_double = internal global double 1.000000e+00 +@var_global = global i32 1 +@var_global_double = global double 1.000000e+00 + +declare i32 @mystrlen(i8* nocapture %s) nounwind + +declare void @myhextochar(i32 %n, i8* nocapture %buffer) + +declare void @__aeabi_read_tp() nounwind + +declare void @__nacl_read_tp() nounwind + +define i32 @main(i32 %argc, i8** nocapture %argv) nounwind { +entry: + switch i32 %argc, label %bb3 [ + i32 555, label %bb + i32 6666, label %bb2 + ] + +bb: ; preds = %entry + volatile store i32 11, i32* @var_tls, align 4 + volatile store double 2.200000e+01, double* @var_tls_double, align 8 + volatile store i32 33, i32* @var_static, align 4 + volatile store double 4.400000e+01, double* @var_static_double, align 8 + volatile store i32 55, i32* @var_global, align 4 + volatile store double 6.600000e+01, double* @var_global_double, align 8 + br label %bb3 + +bb2: ; preds = %entry + ret i32 add (i32 add (i32 add (i32 ptrtoint (i32* @var_tls to i32), i32 add (i32 ptrtoint (i32* @var_static to i32), i32 ptrtoint (i32* @var_global to i32))), i32 ptrtoint (double* @var_tls_double to i32)), i32 add (i32 ptrtoint (double* @var_static_double to i32), i32 ptrtoint (double* @var_global_double to i32))) + +bb3: ; preds = %bb, %entry + tail call void @exit(i32 55) noreturn nounwind + unreachable +} + +declare void @exit(i32) noreturn nounwind + + +;; OBJ: Symbol 0x00000002 +;; OBJ-NEXT: '_MergedGlobals' +;; OBJ-NEXT: 'st_value', 0x00000010 + +;; OBJ: Relocation 0x00000001 +;; OBJ-NEXT: 'r_offset', +;; OBJ-NEXT: 'r_sym', 0x00000002 +;; OBJ-NEXT: 'r_type', 0x0000002b diff --git a/test/MC/ARM/elf-reloc-02.ll b/test/MC/ARM/elf-reloc-02.ll new file mode 100644 index 0000000..132a477 --- /dev/null +++ b/test/MC/ARM/elf-reloc-02.ll @@ -0,0 +1,51 @@ +;; RUN: llc -mtriple=armv7-linux-gnueabi -O3 \ +;; RUN: -mcpu=cortex-a8 -mattr=-neon -mattr=+vfp2 -arm-reserve-r9 \ +;; RUN: -filetype=obj %s -o - | \ +;; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=OBJ %s + +;; FIXME: This file needs to be in .s form! +;; The args to llc are there to constrain the codegen only. +;; +;; Ensure no regression on ARM/gcc compatibility for +;; emitting explicit symbol relocs for nonexternal symbols +;; versus section symbol relocs (with offset) - +;; +;; Default llvm behavior is to emit as section symbol relocs nearly +;; everything that is not an undefined external. Unfortunately, this +;; diverges from what codesourcery ARM/gcc does! +;; +;; Tests that reloc to .L.str* show up as explicit symbols + +target triple = "armv7-none-linux-gnueabi" + +@.str = private constant [7 x i8] c"@null\0A\00", align 4 +@.str1 = private constant [8 x i8] c"@write\0A\00", align 4 +@.str2 = private constant [13 x i8] c"hello worldn\00", align 4 +@.str3 = private constant [7 x i8] c"@exit\0A\00", align 4 + +declare i32 @mystrlen(i8* nocapture %s) nounwind readonly + +declare void @myhextochar(i32 %n, i8* nocapture %buffer) nounwind + +define i32 @main() nounwind { +entry: + %0 = tail call i32 (...)* @write(i32 1, i8* getelementptr inbounds ([7 x i8]* @.str, i32 0, i32 0), i32 6) nounwind + %1 = tail call i32 (...)* @write(i32 1, i8* getelementptr inbounds ([8 x i8]* @.str1, i32 0, i32 0), i32 7) nounwind + %2 = tail call i32 (...)* @write(i32 1, i8* getelementptr inbounds ([13 x i8]* @.str2, i32 0, i32 0), i32 12) nounwind + %3 = tail call i32 (...)* @write(i32 1, i8* getelementptr inbounds ([7 x i8]* @.str3, i32 0, i32 0), i32 6) nounwind + tail call void @exit(i32 55) noreturn nounwind + unreachable +} + +declare i32 @write(...) + +declare void @exit(i32) noreturn nounwind + + +;; OBJ: Symbol 0x00000002 +;; OBJ-NEXT: '.L.str' + +;; OBJ: Relocation 0x00000000 +;; OBJ-NEXT: 'r_offset', +;; OBJ-NEXT: 'r_sym', 0x00000002 +;; OBJ-NEXT: 'r_type', 0x0000002b diff --git a/test/MC/ARM/elf-reloc-03.ll b/test/MC/ARM/elf-reloc-03.ll new file mode 100644 index 0000000..e052f39 --- /dev/null +++ b/test/MC/ARM/elf-reloc-03.ll @@ -0,0 +1,98 @@ +;; RUN: llc -mtriple=armv7-linux-gnueabi -O3 \ +;; RUN: -mcpu=cortex-a8 -mattr=-neon -mattr=+vfp2 -arm-reserve-r9 \ +;; RUN: -filetype=obj %s -o - | \ +;; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=OBJ %s + +;; FIXME: This file needs to be in .s form! +;; The args to llc are there to constrain the codegen only. +;; +;; Ensure no regression on ARM/gcc compatibility for +;; emitting explicit symbol relocs for nonexternal symbols +;; versus section symbol relocs (with offset) - +;; +;; Default llvm behavior is to emit as section symbol relocs nearly +;; everything that is not an undefined external. Unfortunately, this +;; diverges from what codesourcery ARM/gcc does! +;; +;; Verifies that internal constants appear as explict symbol relocs + + +target triple = "armv7-none-linux-gnueabi" + +@startval = global i32 5 +@vtable = internal constant [10 x i32 (...)*] [i32 (...)* bitcast (i32 ()* @foo0 to i32 (...)*), i32 (...)* bitcast (i32 ()* @foo1 to i32 (...)*), i32 (...)* bitcast (i32 ()* @foo2 to i32 (...)*), i32 (...)* bitcast (i32 ()* @foo3 to i32 (...)*), i32 (...)* bitcast (i32 ()* @foo4 to i32 (...)*), i32 (...)* bitcast (i32 ()* @foo5 to i32 (...)*), i32 (...)* bitcast (i32 ()* @foo6 to i32 (...)*), i32 (...)* bitcast (i32 ()* @foo7 to i32 (...)*), i32 (...)* bitcast (i32 ()* @foo8 to i32 (...)*), i32 (...)* bitcast (i32 ()* @foo9 to i32 (...)*)] + +declare i32 @mystrlen(i8* nocapture %s) nounwind readonly + +declare void @myhextochar(i32 %n, i8* nocapture %buffer) nounwind + +define internal i32 @foo0() nounwind readnone { +entry: + ret i32 0 +} + +define internal i32 @foo1() nounwind readnone { +entry: + ret i32 1 +} + +define internal i32 @foo2() nounwind readnone { +entry: + ret i32 2 +} + +define internal i32 @foo3() nounwind readnone { +entry: + ret i32 3 +} + +define internal i32 @foo4() nounwind readnone { +entry: + ret i32 4 +} + +define internal i32 @foo5() nounwind readnone { +entry: + ret i32 55 +} + +define internal i32 @foo6() nounwind readnone { +entry: + ret i32 6 +} + +define internal i32 @foo7() nounwind readnone { +entry: + ret i32 7 +} + +define internal i32 @foo8() nounwind readnone { +entry: + ret i32 8 +} + +define internal i32 @foo9() nounwind readnone { +entry: + ret i32 9 +} + +define i32 @main() nounwind { +entry: + %0 = load i32* @startval, align 4 + %1 = getelementptr inbounds [10 x i32 (...)*]* @vtable, i32 0, i32 %0 + %2 = load i32 (...)** %1, align 4 + %3 = tail call i32 (...)* %2() nounwind + tail call void @exit(i32 %3) noreturn nounwind + unreachable +} + +declare void @exit(i32) noreturn nounwind + + +;; OBJ: Symbol 0x0000000c +;; OBJ-NEXT: 'vtable' + +;; OBJ: Relocation 0x00000001 +;; OBJ-NEXT: 'r_offset', +;; OBJ-NEXT: 'r_sym', 0x0000000c +;; OBJ-NEXT: 'r_type', 0x0000002b diff --git a/test/MC/ARM/hilo-16bit-relocations.s b/test/MC/ARM/hilo-16bit-relocations.s new file mode 100644 index 0000000..7d6b498 --- /dev/null +++ b/test/MC/ARM/hilo-16bit-relocations.s @@ -0,0 +1,20 @@ +@ RUN: llvm-mc %s -triple armv7-apple-darwin | FileCheck %s +@ RUN: llvm-mc %s -triple armv7-apple-darwin | FileCheck %s + +_t: + movw r0, :lower16:(L_foo$non_lazy_ptr - (L1 + 8)) + movt r0, :upper16:(L_foo$non_lazy_ptr - (L1 + 8)) +L1: + +@ CHECK: movw r0, :lower16:(L_foo$non_lazy_ptr-(L1+8)) +@ CHECK: movt r0, :upper16:(L_foo$non_lazy_ptr-(L1+8)) + + .comm _foo,4,2 + + .section __DATA,__nl_symbol_ptr,non_lazy_symbol_pointers + .align 2 +L_foo$non_lazy_ptr: + .indirect_symbol _foo + .long 0 + +.subsections_via_symbols diff --git a/test/MC/ARM/neon-abs-encoding.s b/test/MC/ARM/neon-abs-encoding.s new file mode 100644 index 0000000..398f2db --- /dev/null +++ b/test/MC/ARM/neon-abs-encoding.s @@ -0,0 +1,31 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s + +@ CHECK: vabs.s8 d16, d16 @ encoding: [0x20,0x03,0xf1,0xf3] + vabs.s8 d16, d16 +@ CHECK: vabs.s16 d16, d16 @ encoding: [0x20,0x03,0xf5,0xf3] + vabs.s16 d16, d16 +@ CHECK: vabs.s32 d16, d16 @ encoding: [0x20,0x03,0xf9,0xf3] + vabs.s32 d16, d16 +@ CHECK: vabs.f32 d16, d16 @ encoding: [0x20,0x07,0xf9,0xf3] + vabs.f32 d16, d16 +@ CHECK: vabs.s8 q8, q8 @ encoding: [0x60,0x03,0xf1,0xf3] + vabs.s8 q8, q8 +@ CHECK: vabs.s16 q8, q8 @ encoding: [0x60,0x03,0xf5,0xf3] + vabs.s16 q8, q8 +@ CHECK: vabs.s32 q8, q8 @ encoding: [0x60,0x03,0xf9,0xf3] + vabs.s32 q8, q8 +@ CHECK: vabs.f32 q8, q8 @ encoding: [0x60,0x07,0xf9,0xf3] + vabs.f32 q8, q8 + +@ CHECK: vqabs.s8 d16, d16 @ encoding: [0x20,0x07,0xf0,0xf3] + vqabs.s8 d16, d16 +@ CHECK: vqabs.s16 d16, d16 @ encoding: [0x20,0x07,0xf4,0xf3] + vqabs.s16 d16, d16 +@ CHECK: vqabs.s32 d16, d16 @ encoding: [0x20,0x07,0xf8,0xf3] + vqabs.s32 d16, d16 +@ CHECK: vqabs.s8 q8, q8 @ encoding: [0x60,0x07,0xf0,0xf3] + vqabs.s8 q8, q8 +@ CHECK: vqabs.s16 q8, q8 @ encoding: [0x60,0x07,0xf4,0xf3] + vqabs.s16 q8, q8 +@ CHECK: vqabs.s32 q8, q8 @ encoding: [0x60,0x07,0xf8,0xf3] + vqabs.s32 q8, q8 diff --git a/test/MC/ARM/neon-absdiff-encoding.s b/test/MC/ARM/neon-absdiff-encoding.s new file mode 100644 index 0000000..f43ea65 --- /dev/null +++ b/test/MC/ARM/neon-absdiff-encoding.s @@ -0,0 +1,82 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s + +@ CHECK: vabd.s8 d16, d16, d17 @ encoding: [0xa1,0x07,0x40,0xf2] + vabd.s8 d16, d16, d17 +@ CHECK: vabd.s16 d16, d16, d17 @ encoding: [0xa1,0x07,0x50,0xf2] + vabd.s16 d16, d16, d17 +@ CHECK: vabd.s32 d16, d16, d17 @ encoding: [0xa1,0x07,0x60,0xf2] + vabd.s32 d16, d16, d17 +@ CHECK: vabd.u8 d16, d16, d17 @ encoding: [0xa1,0x07,0x40,0xf3] + vabd.u8 d16, d16, d17 +@ CHECK: vabd.u16 d16, d16, d17 @ encoding: [0xa1,0x07,0x50,0xf3] + vabd.u16 d16, d16, d17 + @ CHECK: vabd.u32 d16, d16, d17 @ encoding: [0xa1,0x07,0x60,0xf3] + vabd.u32 d16, d16, d17 +@ CHECK: vabd.f32 d16, d16, d17 @ encoding: [0xa1,0x0d,0x60,0xf3] + vabd.f32 d16, d16, d17 +@ CHECK: vabd.s8 q8, q8, q9 @ encoding: [0xe2,0x07,0x40,0xf2] + vabd.s8 q8, q8, q9 +@ CHECK: vabd.s16 q8, q8, q9 @ encoding: [0xe2,0x07,0x50,0xf2] + vabd.s16 q8, q8, q9 +@ CHECK: vabd.s32 q8, q8, q9 @ encoding: [0xe2,0x07,0x60,0xf2] + vabd.s32 q8, q8, q9 +@ CHECK: vabd.u8 q8, q8, q9 @ encoding: [0xe2,0x07,0x40,0xf3] + vabd.u8 q8, q8, q9 +@ CHECK: vabd.u16 q8, q8, q9 @ encoding: [0xe2,0x07,0x50,0xf3] + vabd.u16 q8, q8, q9 +@ CHECK: vabd.u32 q8, q8, q9 @ encoding: [0xe2,0x07,0x60,0xf3] + vabd.u32 q8, q8, q9 +@ CHECK: vabd.f32 q8, q8, q9 @ encoding: [0xe2,0x0d,0x60,0xf3] + vabd.f32 q8, q8, q9 + +@ CHECK: vabdl.s8 q8, d16, d17 @ encoding: [0xa1,0x07,0xc0,0xf2] + vabdl.s8 q8, d16, d17 +@ CHECK: vabdl.s16 q8, d16, d17 @ encoding: [0xa1,0x07,0xd0,0xf2] + vabdl.s16 q8, d16, d17 +@ CHECK: vabdl.s32 q8, d16, d17 @ encoding: [0xa1,0x07,0xe0,0xf2] + vabdl.s32 q8, d16, d17 +@ CHECK: vabdl.u8 q8, d16, d17 @ encoding: [0xa1,0x07,0xc0,0xf3] + vabdl.u8 q8, d16, d17 +@ CHECK: vabdl.u16 q8, d16, d17 @ encoding: [0xa1,0x07,0xd0,0xf3] + vabdl.u16 q8, d16, d17 +@ CHECK: vabdl.u32 q8, d16, d17 @ encoding: [0xa1,0x07,0xe0,0xf3] + vabdl.u32 q8, d16, d17 + +@ CHECK: vaba.s8 d16, d18, d17 @ encoding: [0xb1,0x07,0x42,0xf2] + vaba.s8 d16, d18, d17 +@ CHECK: vaba.s16 d16, d18, d17 @ encoding: [0xb1,0x07,0x52,0xf2] + vaba.s16 d16, d18, d17 +@ CHECK: vaba.s32 d16, d18, d17 @ encoding: [0xb1,0x07,0x62,0xf2] + vaba.s32 d16, d18, d17 +@ CHECK: vaba.u8 d16, d18, d17 @ encoding: [0xb1,0x07,0x42,0xf3] + vaba.u8 d16, d18, d17 +@ CHECK: vaba.u16 d16, d18, d17 @ encoding: [0xb1,0x07,0x52,0xf3] + vaba.u16 d16, d18, d17 +@ CHECK: vaba.u32 d16, d18, d17 @ encoding: [0xb1,0x07,0x62,0xf3] + vaba.u32 d16, d18, d17 +@ CHECK: vaba.s8 q9, q8, q10 @ encoding: [0xf4,0x27,0x40,0xf2] + vaba.s8 q9, q8, q10 +@ CHECK: vaba.s16 q9, q8, q10 @ encoding: [0xf4,0x27,0x50,0xf2] + vaba.s16 q9, q8, q10 +@ CHECK: vaba.s32 q9, q8, q10 @ encoding: [0xf4,0x27,0x60,0xf2] + vaba.s32 q9, q8, q10 +@ CHECK: vaba.u8 q9, q8, q10 @ encoding: [0xf4,0x27,0x40,0xf3] + vaba.u8 q9, q8, q10 +@ CHECK: vaba.u16 q9, q8, q10 @ encoding: [0xf4,0x27,0x50,0xf3] + vaba.u16 q9, q8, q10 +@ CHECK: vaba.u32 q9, q8, q10 @ encoding: [0xf4,0x27,0x60,0xf3] + vaba.u32 q9, q8, q10 + +@ CHECK: vabal.s8 q8, d19, d18 @ encoding: [0xa2,0x05,0xc3,0xf2] + vabal.s8 q8, d19, d18 +@ CHECK: vabal.s16 q8, d19, d18 @ encoding: [0xa2,0x05,0xd3,0xf2] + vabal.s16 q8, d19, d18 +@ CHECK: vabal.s32 q8, d19, d18 @ encoding: [0xa2,0x05,0xe3,0xf2] + vabal.s32 q8, d19, d18 +@ CHECK: vabal.u8 q8, d19, d18 @ encoding: [0xa2,0x05,0xc3,0xf3] + vabal.u8 q8, d19, d18 +@ CHECK: vabal.u16 q8, d19, d18 @ encoding: [0xa2,0x05,0xd3,0xf3] + vabal.u16 q8, d19, d18 +@ CHECK: vabal.u32 q8, d19, d18 @ encoding: [0xa2,0x05,0xe3,0xf3] + vabal.u32 q8, d19, d18 + diff --git a/test/MC/ARM/neon-add-encoding.s b/test/MC/ARM/neon-add-encoding.s new file mode 100644 index 0000000..e425397 --- /dev/null +++ b/test/MC/ARM/neon-add-encoding.s @@ -0,0 +1,137 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple armv7-apple-darwin -show-encoding < %s | FileCheck %s + + +@ CHECK: vadd.i8 d16, d17, d16 @ encoding: [0xa0,0x08,0x41,0xf2] + vadd.i8 d16, d17, d16 +@ CHECK: vadd.i16 d16, d17, d16 @ encoding: [0xa0,0x08,0x51,0xf2] + vadd.i16 d16, d17, d16 +@ CHECK: vadd.i64 d16, d17, d16 @ encoding: [0xa0,0x08,0x71,0xf2] + vadd.i64 d16, d17, d16 +@ CHECK: vadd.i32 d16, d17, d16 @ encoding: [0xa0,0x08,0x61,0xf2] + vadd.i32 d16, d17, d16 +@ CHECK: vadd.f32 d16, d16, d17 @ encoding: [0xa1,0x0d,0x40,0xf2] + vadd.f32 d16, d16, d17 +@ CHECK: vadd.f32 q8, q8, q9 @ encoding: [0xe2,0x0d,0x40,0xf2] + vadd.f32 q8, q8, q9 + +@ CHECK: vaddl.s8 q8, d17, d16 @ encoding: [0xa0,0x00,0xc1,0xf2] + vaddl.s8 q8, d17, d16 +@ CHECK: vaddl.s16 q8, d17, d16 @ encoding: [0xa0,0x00,0xd1,0xf2] + vaddl.s16 q8, d17, d16 +@ CHECK: vaddl.s32 q8, d17, d16 @ encoding: [0xa0,0x00,0xe1,0xf2] + vaddl.s32 q8, d17, d16 +@ CHECK: vaddl.u8 q8, d17, d16 @ encoding: [0xa0,0x00,0xc1,0xf3] + vaddl.u8 q8, d17, d16 +@ CHECK: vaddl.u16 q8, d17, d16 @ encoding: [0xa0,0x00,0xd1,0xf3] + vaddl.u16 q8, d17, d16 +@ CHECK: vaddl.u32 q8, d17, d16 @ encoding: [0xa0,0x00,0xe1,0xf3] + vaddl.u32 q8, d17, d16 + +@ CHECK: vaddw.s8 q8, q8, d18 @ encoding: [0xa2,0x01,0xc0,0xf2] + vaddw.s8 q8, q8, d18 +@ CHECK: vaddw.s16 q8, q8, d18 @ encoding: [0xa2,0x01,0xd0,0xf2] + vaddw.s16 q8, q8, d18 +@ CHECK: vaddw.s32 q8, q8, d18 @ encoding: [0xa2,0x01,0xe0,0xf2] + vaddw.s32 q8, q8, d18 +@ CHECK: vaddw.u8 q8, q8, d18 @ encoding: [0xa2,0x01,0xc0,0xf3] + vaddw.u8 q8, q8, d18 +@ CHECK: vaddw.u16 q8, q8, d18 @ encoding: [0xa2,0x01,0xd0,0xf3] + vaddw.u16 q8, q8, d18 +@ CHECK: vaddw.u32 q8, q8, d18 @ encoding: [0xa2,0x01,0xe0,0xf3] + vaddw.u32 q8, q8, d18 + +@ CHECK: vhadd.s8 d16, d16, d17 @ encoding: [0xa1,0x00,0x40,0xf2] + vhadd.s8 d16, d16, d17 +@ CHECK: vhadd.s16 d16, d16, d17 @ encoding: [0xa1,0x00,0x50,0xf2] + vhadd.s16 d16, d16, d17 +@ CHECK: vhadd.s32 d16, d16, d17 @ encoding: [0xa1,0x00,0x60,0xf2] + vhadd.s32 d16, d16, d17 +@ CHECK: vhadd.u8 d16, d16, d17 @ encoding: [0xa1,0x00,0x40,0xf3] + vhadd.u8 d16, d16, d17 +@ CHECK: vhadd.u16 d16, d16, d17 @ encoding: [0xa1,0x00,0x50,0xf3] + vhadd.u16 d16, d16, d17 +@ CHECK: vhadd.u32 d16, d16, d17 @ encoding: [0xa1,0x00,0x60,0xf3] + vhadd.u32 d16, d16, d17 +@ CHECK: vhadd.s8 q8, q8, q9 @ encoding: [0xe2,0x00,0x40,0xf2] + vhadd.s8 q8, q8, q9 +@ CHECK: vhadd.s16 q8, q8, q9 @ encoding: [0xe2,0x00,0x50,0xf2] + vhadd.s16 q8, q8, q9 +@ CHECK: vhadd.s32 q8, q8, q9 @ encoding: [0xe2,0x00,0x60,0xf2] + vhadd.s32 q8, q8, q9 + @ CHECK: vhadd.u8 q8, q8, q9 @ encoding: [0xe2,0x00,0x40,0xf3] + vhadd.u8 q8, q8, q9 +@ CHECK: vhadd.u16 q8, q8, q9 @ encoding: [0xe2,0x00,0x50,0xf3] + vhadd.u16 q8, q8, q9 +@ CHECK: vhadd.u32 q8, q8, q9 @ encoding: [0xe2,0x00,0x60,0xf3] + vhadd.u32 q8, q8, q9 + +@ CHECK: vrhadd.s8 d16, d16, d17 @ encoding: [0xa1,0x01,0x40,0xf2] + vrhadd.s8 d16, d16, d17 +@ CHECK: vrhadd.s16 d16, d16, d17 @ encoding: [0xa1,0x01,0x50,0xf2] + vrhadd.s16 d16, d16, d17 +@ CHECK: vrhadd.s32 d16, d16, d17 @ encoding: [0xa1,0x01,0x60,0xf2] + vrhadd.s32 d16, d16, d17 +@ CHECK: vrhadd.u8 d16, d16, d17 @ encoding: [0xa1,0x01,0x40,0xf3] + vrhadd.u8 d16, d16, d17 +@ CHECK: vrhadd.u16 d16, d16, d17 @ encoding: [0xa1,0x01,0x50,0xf3] + vrhadd.u16 d16, d16, d17 +@ CHECK: vrhadd.u32 d16, d16, d17 @ encoding: [0xa1,0x01,0x60,0xf3] + vrhadd.u32 d16, d16, d17 +@ CHECK: vrhadd.s8 q8, q8, q9 @ encoding: [0xe2,0x01,0x40,0xf2] + vrhadd.s8 q8, q8, q9 +@ CHECK: vrhadd.s16 q8, q8, q9 @ encoding: [0xe2,0x01,0x50,0xf2] + vrhadd.s16 q8, q8, q9 +@ CHECK: vrhadd.s32 q8, q8, q9 @ encoding: [0xe2,0x01,0x60,0xf2] + vrhadd.s32 q8, q8, q9 +@ CHECK: vrhadd.u8 q8, q8, q9 @ encoding: [0xe2,0x01,0x40,0xf3] + vrhadd.u8 q8, q8, q9 +@ CHECK: vrhadd.u16 q8, q8, q9 @ encoding: [0xe2,0x01,0x50,0xf3] + vrhadd.u16 q8, q8, q9 +@ CHECK: vrhadd.u32 q8, q8, q9 @ encoding: [0xe2,0x01,0x60,0xf3] + vrhadd.u32 q8, q8, q9 + +@ CHECK: vqadd.s8 d16, d16, d17 @ encoding: [0xb1,0x00,0x40,0xf2] + vqadd.s8 d16, d16, d17 +@ CHECK: vqadd.s16 d16, d16, d17 @ encoding: [0xb1,0x00,0x50,0xf2] + vqadd.s16 d16, d16, d17 +@ CHECK: vqadd.s32 d16, d16, d17 @ encoding: [0xb1,0x00,0x60,0xf2] + vqadd.s32 d16, d16, d17 +@ CHECK: vqadd.s64 d16, d16, d17 @ encoding: [0xb1,0x00,0x70,0xf2] + vqadd.s64 d16, d16, d17 +@ CHECK: vqadd.u8 d16, d16, d17 @ encoding: [0xb1,0x00,0x40,0xf3] + vqadd.u8 d16, d16, d17 +@ CHECK: vqadd.u16 d16, d16, d17 @ encoding: [0xb1,0x00,0x50,0xf3] + vqadd.u16 d16, d16, d17 +@ CHECK: vqadd.u32 d16, d16, d17 @ encoding: [0xb1,0x00,0x60,0xf3] + vqadd.u32 d16, d16, d17 +@ CHECK: vqadd.u64 d16, d16, d17 @ encoding: [0xb1,0x00,0x70,0xf3] + vqadd.u64 d16, d16, d17 +@ CHECK: vqadd.s8 q8, q8, q9 @ encoding: [0xf2,0x00,0x40,0xf2] + vqadd.s8 q8, q8, q9 +@ CHECK: vqadd.s16 q8, q8, q9 @ encoding: [0xf2,0x00,0x50,0xf2] + vqadd.s16 q8, q8, q9 +@ CHECK: vqadd.s32 q8, q8, q9 @ encoding: [0xf2,0x00,0x60,0xf2] + vqadd.s32 q8, q8, q9 +@ CHECK: vqadd.s64 q8, q8, q9 @ encoding: [0xf2,0x00,0x70,0xf2] + vqadd.s64 q8, q8, q9 +@ CHECK: vqadd.u8 q8, q8, q9 @ encoding: [0xf2,0x00,0x40,0xf3] + vqadd.u8 q8, q8, q9 +@ CHECK: vqadd.u16 q8, q8, q9 @ encoding: [0xf2,0x00,0x50,0xf3] + vqadd.u16 q8, q8, q9 +@ CHECK: vqadd.u32 q8, q8, q9 @ encoding: [0xf2,0x00,0x60,0xf3] + vqadd.u32 q8, q8, q9 +@ CHECK: vqadd.u64 q8, q8, q9 @ encoding: [0xf2,0x00,0x70,0xf3] + vqadd.u64 q8, q8, q9 + +@ CHECK: vaddhn.i16 d16, q8, q9 @ encoding: [0xa2,0x04,0xc0,0xf2] + vaddhn.i16 d16, q8, q9 +@ CHECK: vaddhn.i32 d16, q8, q9 @ encoding: [0xa2,0x04,0xd0,0xf2] + vaddhn.i32 d16, q8, q9 +@ CHECK: vaddhn.i64 d16, q8, q9 @ encoding: [0xa2,0x04,0xe0,0xf2] + vaddhn.i64 d16, q8, q9 +@ CHECK: vraddhn.i16 d16, q8, q9 @ encoding: [0xa2,0x04,0xc0,0xf3] + vraddhn.i16 d16, q8, q9 +@ CHECK: vraddhn.i32 d16, q8, q9 @ encoding: [0xa2,0x04,0xd0,0xf3] + vraddhn.i32 d16, q8, q9 +@ CHECK: vraddhn.i64 d16, q8, q9 @ encoding: [0xa2,0x04,0xe0,0xf3] + vraddhn.i64 d16, q8, q9 diff --git a/test/MC/ARM/neon-bitcount-encoding.s b/test/MC/ARM/neon-bitcount-encoding.s new file mode 100644 index 0000000..2c9518b --- /dev/null +++ b/test/MC/ARM/neon-bitcount-encoding.s @@ -0,0 +1,31 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s + +@ CHECK: vcnt.8 d16, d16 @ encoding: [0x20,0x05,0xf0,0xf3] + vcnt.8 d16, d16 +@ CHECK: vcnt.8 q8, q8 @ encoding: [0x60,0x05,0xf0,0xf3] + vcnt.8 q8, q8 +@ CHECK: vclz.i8 d16, d16 @ encoding: [0xa0,0x04,0xf0,0xf3] + vclz.i8 d16, d16 +@ CHECK: vclz.i16 d16, d16 @ encoding: [0xa0,0x04,0xf4,0xf3] + vclz.i16 d16, d16 +@ CHECK: vclz.i32 d16, d16 @ encoding: [0xa0,0x04,0xf8,0xf3] + vclz.i32 d16, d16 +@ CHECK: vclz.i8 q8, q8 @ encoding: [0xe0,0x04,0xf0,0xf3] + vclz.i8 q8, q8 +@ CHECK: vclz.i16 q8, q8 @ encoding: [0xe0,0x04,0xf4,0xf3] + vclz.i16 q8, q8 +@ CHECK: vclz.i32 q8, q8 @ encoding: [0xe0,0x04,0xf8,0xf3] + vclz.i32 q8, q8 +@ CHECK: vcls.s8 d16, d16 @ encoding: [0x20,0x04,0xf0,0xf3] + vcls.s8 d16, d16 +@ CHECK: vcls.s16 d16, d16 @ encoding: [0x20,0x04,0xf4,0xf3] + vcls.s16 d16, d16 +@ CHECK: vcls.s32 d16, d16 @ encoding: [0x20,0x04,0xf8,0xf3] + vcls.s32 d16, d16 +@ CHECK: vcls.s8 q8, q8 @ encoding: [0x60,0x04,0xf0,0xf3] + vcls.s8 q8, q8 +@ CHECK: vcls.s16 q8, q8 @ encoding: [0x60,0x04,0xf4,0xf3] + vcls.s16 q8, q8 +@ CHECK: vcls.s32 q8, q8 @ encoding: [0x60,0x04,0xf8,0xf3] + vcls.s32 q8, q8 + diff --git a/test/MC/ARM/neon-bitwise-encoding.s b/test/MC/ARM/neon-bitwise-encoding.s new file mode 100644 index 0000000..8710923 --- /dev/null +++ b/test/MC/ARM/neon-bitwise-encoding.s @@ -0,0 +1,47 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s +@ XFAIL: * + +@ CHECK: vand d16, d17, d16 @ encoding: [0xb0,0x01,0x41,0xf2] + vand d16, d17, d16 +@ CHECK: vand q8, q8, q9 @ encoding: [0xf2,0x01,0x40,0xf2] + vand q8, q8, q9 + +@ CHECK: veor d16, d17, d16 @ encoding: [0xb0,0x01,0x41,0xf3] + veor d16, d17, d16 +@ CHECK: veor q8, q8, q9 @ encoding: [0xf2,0x01,0x40,0xf3] + veor q8, q8, q9 + +@ CHECK: vorr d16, d17, d16 @ encoding: [0xb0,0x01,0x61,0xf2] + vorr d16, d17, d16 +@ CHECK: vorr q8, q8, q9 @ encoding: [0xf2,0x01,0x60,0xf2] + vorr q8, q8, q9 +@ CHECK: vorr.i32 d16, #0x1000000 @ encoding: [0x11,0x07,0xc0,0xf2] + vorr.i32 d16, #0x1000000 +@ CHECK: vorr.i32 q8, #0x1000000 @ encoding: [0x51,0x07,0xc0,0xf2] + vorr.i32 q8, #0x1000000 +@ CHECK: vorr.i32 q8, #0x0 @ encoding: [0x50,0x01,0xc0,0xf2] + vorr.i32 q8, #0x0 + +@ CHECK: vbic d16, d17, d16 @ encoding: [0xb0,0x01,0x51,0xf2] + vbic d16, d17, d16 +@ CHECK: vbic q8, q8, q9 @ encoding: [0xf2,0x01,0x50,0xf2] + vbic q8, q8, q9 +@ CHECK: vbic.i32 d16, #0xFF000000 @ encoding: [0x3f,0x07,0xc7,0xf3] + vbic.i32 d16, #0xFF000000 +@ CHECK: vbic.i32 q8, #0xFF000000 @ encoding: [0x7f,0x07,0xc7,0xf3] + vbic.i32 q8, #0xFF000000 + +@ CHECK: vorn d16, d17, d16 @ encoding: [0xb0,0x01,0x71,0xf2] + vorn d16, d17, d16 +@ CHECK: vorn q8, q8, q9 @ encoding: [0xf2,0x01,0x70,0xf2] + vorn q8, q8, q9 + +@ CHECK: vmvn d16, d16 @ encoding: [0xa0,0x05,0xf0,0xf3] + vmvn d16, d16 +@ CHECK: vmvn q8, q8 @ encoding: [0xe0,0x05,0xf0,0xf3] + vmvn q8, q8 + +@ CHECK: vbsl d18, d17, d16 @ encoding: [0xb0,0x21,0x51,0xf3] + vbsl d18, d17, d16 +@ CHECK: vbsl q8, q10, q9 @ encoding: [0xf2,0x01,0x54,0xf3] + vbsl q8, q10, q9 diff --git a/test/MC/ARM/neon-cmp-encoding.s b/test/MC/ARM/neon-cmp-encoding.s new file mode 100644 index 0000000..6bfc549 --- /dev/null +++ b/test/MC/ARM/neon-cmp-encoding.s @@ -0,0 +1,115 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s +@ XFAIL: * + +@ FIXME: We cannot currently test the following instructions, which are +@ currently marked as for-disassembly only in the .td files: +@ - VCEQz +@ - VCGEz, VCLEz +@ - VCGTz, VCLTz + +@ CHECK: vceq.i8 d16, d16, d17 @ encoding: [0xb1,0x08,0x40,0xf3] + vceq.i8 d16, d16, d17 +@ CHECK: vceq.i16 d16, d16, d17 @ encoding: [0xb1,0x08,0x50,0xf3] + vceq.i16 d16, d16, d17 +@ CHECK: vceq.i32 d16, d16, d17 @ encoding: [0xb1,0x08,0x60,0xf3] + vceq.i32 d16, d16, d17 +@ CHECK: vceq.f32 d16, d16, d17 @ encoding: [0xa1,0x0e,0x40,0xf2] + vceq.f32 d16, d16, d17 +@ CHECK: vceq.i8 q8, q8, q9 @ encoding: [0xf2,0x08,0x40,0xf3] + vceq.i8 q8, q8, q9 +@ CHECK: vceq.i16 q8, q8, q9 @ encoding: [0xf2,0x08,0x50,0xf3] + vceq.i16 q8, q8, q9 +@ CHECK: vceq.i32 q8, q8, q9 @ encoding: [0xf2,0x08,0x60,0xf3] + vceq.i32 q8, q8, q9 +@ CHECK: vceq.f32 q8, q8, q9 @ encoding: [0xe2,0x0e,0x40,0xf2] + vceq.f32 q8, q8, q9 + +@ CHECK: vcge.s8 d16, d16, d17 @ encoding: [0xb1,0x03,0x40,0xf2] + vcge.s8 d16, d16, d17 +@ CHECK: vcge.s16 d16, d16, d17 @ encoding: [0xb1,0x03,0x50,0xf2] + vcge.s16 d16, d16, d17 +@ CHECK: vcge.s32 d16, d16, d17 @ encoding: [0xb1,0x03,0x60,0xf2] + vcge.s32 d16, d16, d17 +@ CHECK: vcge.u8 d16, d16, d17 @ encoding: [0xb1,0x03,0x40,0xf3] + vcge.u8 d16, d16, d17 +@ CHECK: vcge.u16 d16, d16, d17 @ encoding: [0xb1,0x03,0x50,0xf3] + vcge.u16 d16, d16, d17 +@ CHECK: vcge.u32 d16, d16, d17 @ encoding: [0xb1,0x03,0x60,0xf3] + vcge.u32 d16, d16, d17 +@ CHECK: vcge.f32 d16, d16, d17 @ encoding: [0xa1,0x0e,0x40,0xf3] + vcge.f32 d16, d16, d17 +@ CHECK: vcge.s8 q8, q8, q9 @ encoding: [0xf2,0x03,0x40,0xf2] + vcge.s8 q8, q8, q9 +@ CHECK: vcge.s16 q8, q8, q9 @ encoding: [0xf2,0x03,0x50,0xf2] + vcge.s16 q8, q8, q9 +@ CHECK: vcge.s32 q8, q8, q9 @ encoding: [0xf2,0x03,0x60,0xf2] + vcge.s32 q8, q8, q9 +@ CHECK: vcge.u8 q8, q8, q9 @ encoding: [0xf2,0x03,0x40,0xf3] + vcge.u8 q8, q8, q9 +@ CHECK: vcge.u16 q8, q8, q9 @ encoding: [0xf2,0x03,0x50,0xf3] + vcge.u16 q8, q8, q9 +@ CHECK: vcge.u32 q8, q8, q9 @ encoding: [0xf2,0x03,0x60,0xf3] + vcge.u32 q8, q8, q9 +@ CHECK: vcge.f32 q8, q8, q9 @ encoding: [0xe2,0x0e,0x40,0xf3] + vcge.f32 q8, q8, q9 +@ CHECK: vacge.f32 d16, d16, d17 @ encoding: [0xb1,0x0e,0x40,0xf3] + vacge.f32 d16, d16, d17 +@ CHECK: vacge.f32 q8, q8, q9 @ encoding: [0xf2,0x0e,0x40,0xf3] + vacge.f32 q8, q8, q9 + +@ CHECK: vcgt.s8 d16, d16, d17 @ encoding: [0xa1,0x03,0x40,0xf2] + vcgt.s8 d16, d16, d17 +@ CHECK: vcgt.s16 d16, d16, d17 @ encoding: [0xa1,0x03,0x50,0xf2] + vcgt.s16 d16, d16, d17 +@ CHECK: vcgt.s32 d16, d16, d17 @ encoding: [0xa1,0x03,0x60,0xf2] + vcgt.s32 d16, d16, d17 +@ CHECK: vcgt.u8 d16, d16, d17 @ encoding: [0xa1,0x03,0x40,0xf3] + vcgt.u8 d16, d16, d17 +@ CHECK: vcgt.u16 d16, d16, d17 @ encoding: [0xa1,0x03,0x50,0xf3] + vcgt.u16 d16, d16, d17 +@ CHECK: vcgt.u32 d16, d16, d17 @ encoding: [0xa1,0x03,0x60,0xf3] + vcgt.u32 d16, d16, d17 +@ CHECK: vcgt.f32 d16, d16, d17 @ encoding: [0xa1,0x0e,0x60,0xf3] + vcgt.f32 d16, d16, d17 +@ CHECK: vcgt.s8 q8, q8, q9 @ encoding: [0xe2,0x03,0x40,0xf2] + vcgt.s8 q8, q8, q9 +@ CHECK: vcgt.s16 q8, q8, q9 @ encoding: [0xe2,0x03,0x50,0xf2] + vcgt.s16 q8, q8, q9 +@ CHECK: vcgt.s32 q8, q8, q9 @ encoding: [0xe2,0x03,0x60,0xf2] + vcgt.s32 q8, q8, q9 +@ CHECK: vcgt.u8 q8, q8, q9 @ encoding: [0xe2,0x03,0x40,0xf3] + vcgt.u8 q8, q8, q9 +@ CHECK: vcgt.u16 q8, q8, q9 @ encoding: [0xe2,0x03,0x50,0xf3] + vcgt.u16 q8, q8, q9 +@ CHECK: vcgt.u32 q8, q8, q9 @ encoding: [0xe2,0x03,0x60,0xf3] + vcgt.u32 q8, q8, q9 +@ CHECK: vcgt.f32 q8, q8, q9 @ encoding: [0xe2,0x0e,0x60,0xf3] + vcgt.f32 q8, q8, q9 +@ CHECK: vacgt.f32 d16, d16, d17 @ encoding: [0xb1,0x0e,0x60,0xf3] + vacgt.f32 d16, d16, d17 +@ CHECK: vacgt.f32 q8, q8, q9 @ encoding: [0xf2,0x0e,0x60,0xf3] + vacgt.f32 q8, q8, q9 + +@ CHECK: vtst.8 d16, d16, d17 @ encoding: [0xb1,0x08,0x40,0xf2] + vtst.8 d16, d16, d17 +@ CHECK: vtst.16 d16, d16, d17 @ encoding: [0xb1,0x08,0x50,0xf2] + vtst.16 d16, d16, d17 +@ CHECK: vtst.32 d16, d16, d17 @ encoding: [0xb1,0x08,0x60,0xf2] + vtst.32 d16, d16, d17 +@ CHECK: vtst.8 q8, q8, q9 @ encoding: [0xf2,0x08,0x40,0xf2] + vtst.8 q8, q8, q9 +@ CHECK: vtst.16 q8, q8, q9 @ encoding: [0xf2,0x08,0x50,0xf2] + vtst.16 q8, q8, q9 +@ CHECK: vtst.32 q8, q8, q9 @ encoding: [0xf2,0x08,0x60,0xf2] + vtst.32 q8, q8, q9 + +@ CHECK: vceq.i8 d16, d16, #0 @ encoding: [0x20,0x01,0xf1,0xf3] + vceq.i8 d16, d16, #0 +@ CHECK: vcge.s8 d16, d16, #0 @ encoding: [0xa0,0x00,0xf1,0xf3] + vcge.s8 d16, d16, #0 +@ CHECK: vcle.s8 d16, d16, #0 @ encoding: [0xa0,0x01,0xf1,0xf3] + vcle.s8 d16, d16, #0 +@ CHECK: vcgt.s8 d16, d16, #0 @ encoding: [0x20,0x00,0xf1,0xf3] + vcgt.s8 d16, d16, #0 +@ CHECK: vclt.s8 d16, d16, #0 @ encoding: [0x20,0x02,0xf1,0xf3] + vclt.s8 d16, d16, #0 diff --git a/test/MC/ARM/neon-convert-encoding.s b/test/MC/ARM/neon-convert-encoding.s new file mode 100644 index 0000000..1733c52 --- /dev/null +++ b/test/MC/ARM/neon-convert-encoding.s @@ -0,0 +1,38 @@ +@ RUN: llvm-mc -mcpu=cortex-a9 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s + +@ CHECK: vcvt.s32.f32 d16, d16 @ encoding: [0x20,0x07,0xfb,0xf3] + vcvt.s32.f32 d16, d16 +@ CHECK: vcvt.u32.f32 d16, d16 @ encoding: [0xa0,0x07,0xfb,0xf3] + vcvt.u32.f32 d16, d16 +@ CHECK: vcvt.f32.s32 d16, d16 @ encoding: [0x20,0x06,0xfb,0xf3] + vcvt.f32.s32 d16, d16 +@ CHECK: vcvt.f32.u32 d16, d16 @ encoding: [0xa0,0x06,0xfb,0xf3] + vcvt.f32.u32 d16, d16 +@ CHECK: vcvt.s32.f32 q8, q8 @ encoding: [0x60,0x07,0xfb,0xf3] + vcvt.s32.f32 q8, q8 +@ CHECK: vcvt.u32.f32 q8, q8 @ encoding: [0xe0,0x07,0xfb,0xf3] + vcvt.u32.f32 q8, q8 +@ CHECK: vcvt.f32.s32 q8, q8 @ encoding: [0x60,0x06,0xfb,0xf3] + vcvt.f32.s32 q8, q8 +@ CHECK: vcvt.f32.u32 q8, q8 @ encoding: [0xe0,0x06,0xfb,0xf3] + vcvt.f32.u32 q8, q8 +@ CHECK: vcvt.s32.f32 d16, d16, #1 @ encoding: [0x30,0x0f,0xff,0xf2] + vcvt.s32.f32 d16, d16, #1 +@ CHECK: vcvt.u32.f32 d16, d16, #1 @ encoding: [0x30,0x0f,0xff,0xf3] + vcvt.u32.f32 d16, d16, #1 +@ CHECK: vcvt.f32.s32 d16, d16, #1 @ encoding: [0x30,0x0e,0xff,0xf2] + vcvt.f32.s32 d16, d16, #1 +@ CHECK: vcvt.f32.u32 d16, d16, #1 @ encoding: [0x30,0x0e,0xff,0xf3] + vcvt.f32.u32 d16, d16, #1 +@ CHECK: vcvt.s32.f32 q8, q8, #1 @ encoding: [0x70,0x0f,0xff,0xf2] + vcvt.s32.f32 q8, q8, #1 +@ CHECK: vcvt.u32.f32 q8, q8, #1 @ encoding: [0x70,0x0f,0xff,0xf3] + vcvt.u32.f32 q8, q8, #1 +@ CHECK: vcvt.f32.s32 q8, q8, #1 @ encoding: [0x70,0x0e,0xff,0xf2] + vcvt.f32.s32 q8, q8, #1 +@ CHECK: vcvt.f32.u32 q8, q8, #1 @ encoding: [0x70,0x0e,0xff,0xf3] + vcvt.f32.u32 q8, q8, #1 +@ CHECK: vcvt.f32.f16 q8, d16 @ encoding: [0x20,0x07,0xf6,0xf3] + vcvt.f32.f16 q8, d16 +@ CHECK: vcvt.f16.f32 d16, q8 @ encoding: [0x20,0x06,0xf6,0xf3] + vcvt.f16.f32 d16, q8 diff --git a/test/MC/ARM/neon-dup-encoding.s b/test/MC/ARM/neon-dup-encoding.s new file mode 100644 index 0000000..0aebdce --- /dev/null +++ b/test/MC/ARM/neon-dup-encoding.s @@ -0,0 +1,27 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s +@ XFAIL: * + +@ CHECK: vdup.8 d16, r0 @ encoding: [0x90,0x0b,0xc0,0xee] + vdup.8 d16, r0 +@ CHECK: vdup.16 d16, r0 @ encoding: [0xb0,0x0b,0x80,0xee] + vdup.16 d16, r0 +@ CHECK: vdup.32 d16, r0 @ encoding: [0x90,0x0b,0x80,0xee] + vdup.32 d16, r0 +@ CHECK: vdup.8 q8, r0 @ encoding: [0x90,0x0b,0xe0,0xee] + vdup.8 q8, r0 +@ CHECK: vdup.16 q8, r0 @ encoding: [0xb0,0x0b,0xa0,0xee] + vdup.16 q8, r0 +@ CHECK: vdup.32 q8, r0 @ encoding: [0x90,0x0b,0xa0,0xee] + vdup.32 q8, r0 +@ CHECK: vdup.8 d16, d16[1] @ encoding: [0x20,0x0c,0xf3,0xf3] + vdup.8 d16, d16[1] +@ CHECK: vdup.16 d16, d16[1] @ encoding: [0x20,0x0c,0xf6,0xf3] + vdup.16 d16, d16[1] +@ CHECK: vdup.32 d16, d16[1] @ encoding: [0x20,0x0c,0xfc,0xf3] + vdup.32 d16, d16[1] +@ CHECK: vdup.8 q8, d16[1] @ encoding: [0x60,0x0c,0xf3,0xf3] + vdup.8 q8, d16[1] +@ CHECK: vdup.16 q8, d16[1] @ encoding: [0x60,0x0c,0xf6,0xf3] + vdup.16 q8, d16[1] +@ CHECK: vdup.32 q8, d16[1] @ encoding: [0x60,0x0c,0xfc,0xf3] + vdup.32 q8, d16[1] diff --git a/test/MC/ARM/neon-minmax-encoding.s b/test/MC/ARM/neon-minmax-encoding.s new file mode 100644 index 0000000..2d0d8c9 --- /dev/null +++ b/test/MC/ARM/neon-minmax-encoding.s @@ -0,0 +1,58 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s + +@ CHECK: vmin.s8 d16, d16, d17 @ encoding: [0xb1,0x06,0x40,0xf2] + vmin.s8 d16, d16, d17 +@ CHECK: vmin.s16 d16, d16, d17 @ encoding: [0xb1,0x06,0x50,0xf2] + vmin.s16 d16, d16, d17 +@ CHECK: vmin.s32 d16, d16, d17 @ encoding: [0xb1,0x06,0x60,0xf2] + vmin.s32 d16, d16, d17 +@ CHECK: vmin.u8 d16, d16, d17 @ encoding: [0xb1,0x06,0x40,0xf3] + vmin.u8 d16, d16, d17 +@ CHECK: vmin.u16 d16, d16, d17 @ encoding: [0xb1,0x06,0x50,0xf3] + vmin.u16 d16, d16, d17 +@ CHECK: vmin.u32 d16, d16, d17 @ encoding: [0xb1,0x06,0x60,0xf3] + vmin.u32 d16, d16, d17 +@ CHECK: vmin.f32 d16, d16, d17 @ encoding: [0xa1,0x0f,0x60,0xf2] + vmin.f32 d16, d16, d17 +@ CHECK: vmin.s8 q8, q8, q9 @ encoding: [0xf2,0x06,0x40,0xf2] + vmin.s8 q8, q8, q9 +@ CHECK: vmin.s16 q8, q8, q9 @ encoding: [0xf2,0x06,0x50,0xf2] + vmin.s16 q8, q8, q9 +@ CHECK: vmin.s32 q8, q8, q9 @ encoding: [0xf2,0x06,0x60,0xf2] + vmin.s32 q8, q8, q9 +@ CHECK: vmin.u8 q8, q8, q9 @ encoding: [0xf2,0x06,0x40,0xf3] + vmin.u8 q8, q8, q9 +@ CHECK: vmin.u16 q8, q8, q9 @ encoding: [0xf2,0x06,0x50,0xf3] + vmin.u16 q8, q8, q9 +@ CHECK: vmin.u32 q8, q8, q9 @ encoding: [0xf2,0x06,0x60,0xf3] + vmin.u32 q8, q8, q9 +@ CHECK: vmin.f32 q8, q8, q9 @ encoding: [0xe2,0x0f,0x60,0xf2] + vmin.f32 q8, q8, q9 +@ CHECK: vmax.s8 d16, d16, d17 @ encoding: [0xa1,0x06,0x40,0xf2] + vmax.s8 d16, d16, d17 +@ CHECK: vmax.s16 d16, d16, d17 @ encoding: [0xa1,0x06,0x50,0xf2] + vmax.s16 d16, d16, d17 +@ CHECK: vmax.s32 d16, d16, d17 @ encoding: [0xa1,0x06,0x60,0xf2] + vmax.s32 d16, d16, d17 +@ CHECK: vmax.u8 d16, d16, d17 @ encoding: [0xa1,0x06,0x40,0xf3] + vmax.u8 d16, d16, d17 +@ CHECK: vmax.u16 d16, d16, d17 @ encoding: [0xa1,0x06,0x50,0xf3] + vmax.u16 d16, d16, d17 +@ CHECK: vmax.u32 d16, d16, d17 @ encoding: [0xa1,0x06,0x60,0xf3] + vmax.u32 d16, d16, d17 +@ CHECK: vmax.f32 d16, d16, d17 @ encoding: [0xa1,0x0f,0x40,0xf2] + vmax.f32 d16, d16, d17 +@ CHECK: vmax.s8 q8, q8, q9 @ encoding: [0xe2,0x06,0x40,0xf2] + vmax.s8 q8, q8, q9 +@ CHECK: vmax.s16 q8, q8, q9 @ encoding: [0xe2,0x06,0x50,0xf2] + vmax.s16 q8, q8, q9 +@ CHECK: vmax.s32 q8, q8, q9 @ encoding: [0xe2,0x06,0x60,0xf2] + vmax.s32 q8, q8, q9 +@ CHECK: vmax.u8 q8, q8, q9 @ encoding: [0xe2,0x06,0x40,0xf3] + vmax.u8 q8, q8, q9 +@ CHECK: vmax.u16 q8, q8, q9 @ encoding: [0xe2,0x06,0x50,0xf3] + vmax.u16 q8, q8, q9 +@ CHECK: vmax.u32 q8, q8, q9 @ encoding: [0xe2,0x06,0x60,0xf3] + vmax.u32 q8, q8, q9 +@ CHECK: vmax.f32 q8, q8, q9 @ encoding: [0xe2,0x0f,0x40,0xf2] + vmax.f32 q8, q8, q9 diff --git a/test/MC/ARM/neon-mov-encoding.s b/test/MC/ARM/neon-mov-encoding.s new file mode 100644 index 0000000..ca678d0 --- /dev/null +++ b/test/MC/ARM/neon-mov-encoding.s @@ -0,0 +1,117 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s +@ XFAIL: * + +@ CHECK: vmov.i8 d16, #0x8 @ encoding: [0x18,0x0e,0xc0,0xf2] + vmov.i8 d16, #0x8 +@ CHECK: vmov.i16 d16, #0x10 @ encoding: [0x10,0x08,0xc1,0xf2] + vmov.i16 d16, #0x10 +@ CHECK: vmov.i16 d16, #0x1000 @ encoding: [0x10,0x0a,0xc1,0xf2] + vmov.i16 d16, #0x1000 +@ CHECK: vmov.i32 d16, #0x20 @ encoding: [0x10,0x00,0xc2,0xf2] + vmov.i32 d16, #0x20 +@ CHECK: vmov.i32 d16, #0x2000 @ encoding: [0x10,0x02,0xc2,0xf2] + vmov.i32 d16, #0x2000 +@ CHECK: vmov.i32 d16, #0x200000 @ encoding: [0x10,0x04,0xc2,0xf2] + vmov.i32 d16, #0x200000 +@ CHECK: vmov.i32 d16, #0x20000000 @ encoding: [0x10,0x06,0xc2,0xf2] + vmov.i32 d16, #0x20000000 +@ CHECK: vmov.i32 d16, #0x20FF @ encoding: [0x10,0x0c,0xc2,0xf2] + vmov.i32 d16, #0x20FF +@ CHECK: vmov.i32 d16, #0x20FFFF @ encoding: [0x10,0x0d,0xc2,0xf2] + vmov.i32 d16, #0x20FFFF +@ CHECK: vmov.i64 d16, #0xFF0000FF0000FFFF @ encoding: [0x33,0x0e,0xc1,0xf3] + vmov.i64 d16, #0xFF0000FF0000FFFF +@ CHECK: vmov.i8 q8, #0x8 @ encoding: [0x58,0x0e,0xc0,0xf2] + vmov.i8 q8, #0x8 +@ CHECK: vmov.i16 q8, #0x10 @ encoding: [0x50,0x08,0xc1,0xf2] + vmov.i16 q8, #0x10 +@ CHECK: vmov.i16 q8, #0x1000 @ encoding: [0x50,0x0a,0xc1,0xf2] + vmov.i16 q8, #0x1000 +@ CHECK: vmov.i32 q8, #0x20 @ encoding: [0x50,0x00,0xc2,0xf2] + vmov.i32 q8, #0x20 +@ CHECK: vmov.i32 q8, #0x2000 @ encoding: [0x50,0x02,0xc2,0xf2] + vmov.i32 q8, #0x2000 +@ CHECK: vmov.i32 q8, #0x200000 @ encoding: [0x50,0x04,0xc2,0xf2] + vmov.i32 q8, #0x200000 +@ CHECK: vmov.i32 q8, #0x20000000 @ encoding: [0x50,0x06,0xc2,0xf2] + vmov.i32 q8, #0x20000000 +@ CHECK: vmov.i32 q8, #0x20FF @ encoding: [0x50,0x0c,0xc2,0xf2] + vmov.i32 q8, #0x20FF +@ CHECK: vmov.i32 q8, #0x20FFFF @ encoding: [0x50,0x0d,0xc2,0xf2] + vmov.i32 q8, #0x20FFFF +@ CHECK: vmov.i64 q8, #0xFF0000FF0000FFFF @ encoding: [0x73,0x0e,0xc1,0xf3] + vmov.i64 q8, #0xFF0000FF0000FFFF +@ CHECK: vmvn.i16 d16, #0x10 @ encoding: [0x30,0x08,0xc1,0xf2] + vmvn.i16 d16, #0x10 +@ CHECK: vmvn.i16 d16, #0x1000 @ encoding: [0x30,0x0a,0xc1,0xf2] + vmvn.i16 d16, #0x1000 +@ CHECK: vmvn.i32 d16, #0x20 @ encoding: [0x30,0x00,0xc2,0xf2] + vmvn.i32 d16, #0x20 +@ CHECK: vmvn.i32 d16, #0x2000 @ encoding: [0x30,0x02,0xc2,0xf2] + vmvn.i32 d16, #0x2000 +@ CHECK: vmvn.i32 d16, #0x200000 @ encoding: [0x30,0x04,0xc2,0xf2] + vmvn.i32 d16, #0x200000 +@ CHECK: vmvn.i32 d16, #0x20000000 @ encoding: [0x30,0x06,0xc2,0xf2] + vmvn.i32 d16, #0x20000000 +@ CHECK: vmvn.i32 d16, #0x20FF @ encoding: [0x30,0x0c,0xc2,0xf2] + vmvn.i32 d16, #0x20FF +@ CHECK: vmvn.i32 d16, #0x20FFFF @ encoding: [0x30,0x0d,0xc2,0xf2] + vmvn.i32 d16, #0x20FFFF +@ CHECK: vmovl.s8 q8, d16 @ encoding: [0x30,0x0a,0xc8,0xf2] + vmovl.s8 q8, d16 +@ CHECK: vmovl.s16 q8, d16 @ encoding: [0x30,0x0a,0xd0,0xf2] + vmovl.s16 q8, d16 +@ CHECK: vmovl.s32 q8, d16 @ encoding: [0x30,0x0a,0xe0,0xf2] + vmovl.s32 q8, d16 +@ CHECK: vmovl.u8 q8, d16 @ encoding: [0x30,0x0a,0xc8,0xf3] + vmovl.u8 q8, d16 +@ CHECK: vmovl.u16 q8, d16 @ encoding: [0x30,0x0a,0xd0,0xf3] + vmovl.u16 q8, d16 +@ CHECK: vmovl.u32 q8, d16 @ encoding: [0x30,0x0a,0xe0,0xf3] + vmovl.u32 q8, d16 +@ CHECK: vmovn.i16 d16, q8 @ encoding: [0x20,0x02,0xf2,0xf3] + vmovn.i16 d16, q8 +@ CHECK: vmovn.i32 d16, q8 @ encoding: [0x20,0x02,0xf6,0xf3] + vmovn.i32 d16, q8 +@ CHECK: vmovn.i64 d16, q8 @ encoding: [0x20,0x02,0xfa,0xf3] + vmovn.i64 d16, q8 +@ CHECK: vqmovn.s16 d16, q8 @ encoding: [0xa0,0x02,0xf2,0xf3] + vqmovn.s16 d16, q8 +@ CHECK: vqmovn.s32 d16, q8 @ encoding: [0xa0,0x02,0xf6,0xf3] + vqmovn.s32 d16, q8 +@ CHECK: vqmovn.s64 d16, q8 @ encoding: [0xa0,0x02,0xfa,0xf3] + vqmovn.s64 d16, q8 +@ CHECK: vqmovn.u16 d16, q8 @ encoding: [0xe0,0x02,0xf2,0xf3] + vqmovn.u16 d16, q8 +@ CHECK: vqmovn.u32 d16, q8 @ encoding: [0xe0,0x02,0xf6,0xf3] + vqmovn.u32 d16, q8 +@ CHECK: vqmovn.u64 d16, q8 @ encoding: [0xe0,0x02,0xfa,0xf3] + vqmovn.u64 d16, q8 +@ CHECK: vqmovun.s16 d16, q8 @ encoding: [0x60,0x02,0xf2,0xf3] + vqmovun.s16 d16, q8 +@ CHECK: vqmovun.s32 d16, q8 @ encoding: [0x60,0x02,0xf6,0xf3] + vqmovun.s32 d16, q8 +@ CHECK: vqmovun.s64 d16, q8 @ encoding: [0x60,0x02,0xfa,0xf3] + vqmovun.s64 d16, q8 +@ CHECK: vmov.s8 r0, d16[1] @ encoding: [0xb0,0x0b,0x50,0xee] + vmov.s8 r0, d16[1] +@ CHECK: vmov.s16 r0, d16[1] @ encoding: [0xf0,0x0b,0x10,0xee] + vmov.s16 r0, d16[1] +@ CHECK: vmov.u8 r0, d16[1] @ encoding: [0xb0,0x0b,0xd0,0xee] + vmov.u8 r0, d16[1] +@ CHECK: vmov.u16 r0, d16[1] @ encoding: [0xf0,0x0b,0x90,0xee] + vmov.u16 r0, d16[1] +@ CHECK: vmov.32 r0, d16[1] @ encoding: [0x90,0x0b,0x30,0xee] + vmov.32 r0, d16[1] +@ CHECK: vmov.8 d16[1], r1 @ encoding: [0xb0,0x1b,0x40,0xee] + vmov.8 d16[1], r1 +@ CHECK: vmov.16 d16[1], r1 @ encoding: [0xf0,0x1b,0x00,0xee] + vmov.16 d16[1], r1 +@ CHECK: vmov.32 d16[1], r1 @ encoding: [0x90,0x1b,0x20,0xee] + vmov.32 d16[1], r1 +@ CHECK: vmov.8 d18[1], r1 @ encoding: [0xb0,0x1b,0x42,0xee] + vmov.8 d18[1], r1 +@ CHECK: vmov.16 d18[1], r1 @ encoding: [0xf0,0x1b,0x02,0xee] + vmov.16 d18[1], r1 +@ CHECK: vmov.32 d18[1], r1 @ encoding: [0x90,0x1b,0x22,0xee] + vmov.32 d18[1], r1 diff --git a/test/MC/ARM/neon-mul-accum-encoding.s b/test/MC/ARM/neon-mul-accum-encoding.s new file mode 100644 index 0000000..e269dea --- /dev/null +++ b/test/MC/ARM/neon-mul-accum-encoding.s @@ -0,0 +1,67 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s +@ XFAIL: * + +@ CHECK: vmla.i8 d16, d18, d17 @ encoding: [0xa1,0x09,0x42,0xf2] + vmla.i8 d16, d18, d17 +@ CHECK: vmla.i16 d16, d18, d17 @ encoding: [0xa1,0x09,0x52,0xf2] + vmla.i16 d16, d18, d17 +@ CHECK: vmla.i16 d16, d18, d17 @ encoding: [0xa1,0x09,0x52,0xf2] + vmla.i32 d16, d18, d17 +@ CHECK: vmla.f32 d16, d18, d17 @ encoding: [0xb1,0x0d,0x42,0xf2] + vmla.f32 d16, d18, d17 +@ CHECK: vmla.i8 q9, q8, q10 @ encoding: [0xe4,0x29,0x40,0xf2] + vmla.i8 q9, q8, q10 +@ CHECK: vmla.i16 q9, q8, q10 @ encoding: [0xe4,0x29,0x50,0xf2] + vmla.i16 q9, q8, q10 +@ CHECK: vmla.i32 q9, q8, q10 @ encoding: [0xe4,0x29,0x60,0xf2] + vmla.i32 q9, q8, q10 +@ CHECK: vmla.f32 q9, q8, q10 @ encoding: [0xf4,0x2d,0x40,0xf2] + vmla.f32 q9, q8, q10 +@ CHECK: vmlal.s8 q8, d19, d18 @ encoding: [0xa2,0x08,0xc3,0xf2] + vmlal.s8 q8, d19, d18 +@ CHECK: vmlal.s16 q8, d19, d18 @ encoding: [0xa2,0x08,0xd3,0xf2] + vmlal.s16 q8, d19, d18 +@ CHECK: vmlal.s32 q8, d19, d18 @ encoding: [0xa2,0x08,0xe3,0xf2] + vmlal.s32 q8, d19, d18 +@ CHECK: vmlal.u8 q8, d19, d18 @ encoding: [0xa2,0x08,0xc3,0xf3] + vmlal.u8 q8, d19, d18 +@ CHECK: vmlal.u16 q8, d19, d18 @ encoding: [0xa2,0x08,0xd3,0xf3] + vmlal.u16 q8, d19, d18 +@ CHECK: vmlal.u32 q8, d19, d18 @ encoding: [0xa2,0x08,0xe3,0xf3] + vmlal.u32 q8, d19, d18 +@ CHECK: vqdmlal.s16 q8, d19, d18 @ encoding: [0xa2,0x09,0xd3,0xf2] + vqdmlal.s16 q8, d19, d18 +@ CHECK: vqdmlal.s32 q8, d19, d18 @ encoding: [0xa2,0x09,0xe3,0xf2] + vqdmlal.s32 q8, d19, d18 +@ CHECK: vmls.i8 d16, d18, d17 @ encoding: [0xa1,0x09,0x42,0xf3] + vmls.i8 d16, d18, d17 +@ CHECK: vmls.i16 d16, d18, d17 @ encoding: [0xa1,0x09,0x52,0xf3] + vmls.i16 d16, d18, d17 +@ CHECK: vmls.i32 d16, d18, d17 @ encoding: [0xa1,0x09,0x62,0xf3] + vmls.i32 d16, d18, d17 +@ CHECK: vmls.f32 d16, d18, d17 @ encoding: [0xb1,0x0d,0x62,0xf2] + vmls.f32 d16, d18, d17 +@ CHECK: vmls.i8 q9, q8, q10 @ encoding: [0xe4,0x29,0x40,0xf3] + vmls.i8 q9, q8, q10 +@ CHECK: vmls.i16 q9, q8, q10 @ encoding: [0xe4,0x29,0x50,0xf3] + vmls.i16 q9, q8, q10 +@ CHECK: vmls.i32 q9, q8, q10 @ encoding: [0xe4,0x29,0x60,0xf3] + vmls.i32 q9, q8, q10 +@ CHECK: vmls.f32 q9, q8, q10 @ encoding: [0xf4,0x2d,0x60,0xf2] + vmls.f32 q9, q8, q10 +@ CHECK: vmlsl.s8 q8, d19, d18 @ encoding: [0xa2,0x0a,0xc3,0xf2] + vmlsl.s8 q8, d19, d18 +@ CHECK: vmlsl.s16 q8, d19, d18 @ encoding: [0xa2,0x0a,0xd3,0xf2] + vmlsl.s16 q8, d19, d18 +@ CHECK: vmlsl.s32 q8, d19, d18 @ encoding: [0xa2,0x0a,0xe3,0xf2] + vmlsl.s32 q8, d19, d18 +@ CHECK: vmlsl.u8 q8, d19, d18 @ encoding: [0xa2,0x0a,0xc3,0xf3] + vmlsl.u8 q8, d19, d18 +@ CHECK: vmlsl.u16 q8, d19, d18 @ encoding: [0xa2,0x0a,0xd3,0xf3] + vmlsl.u16 q8, d19, d18 +@ CHECK: vmlsl.u32 q8, d19, d18 @ encoding: [0xa2,0x0a,0xe3,0xf3] + vmlsl.u32 q8, d19, d18 +@ CHECK: vqdmlsl.s16 q8, d19, d18 @ encoding: [0xa2,0x0b,0xd3,0xf2] + vqdmlsl.s16 q8, d19, d18 +@ CHECK: vqdmlsl.s32 q8, d19, d18 @ encoding: [0xa2,0x0b,0xe3,0xf2] + vqdmlsl.s32 q8, d19, d18 diff --git a/test/MC/ARM/neon-mul-encoding.s b/test/MC/ARM/neon-mul-encoding.s new file mode 100644 index 0000000..4ff192f --- /dev/null +++ b/test/MC/ARM/neon-mul-encoding.s @@ -0,0 +1,56 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s + +@ CHECK: vmul.i8 d16, d16, d17 @ encoding: [0xb1,0x09,0x40,0xf2] + vmul.i8 d16, d16, d17 +@ CHECK: vmul.i16 d16, d16, d17 @ encoding: [0xb1,0x09,0x50,0xf2] + vmul.i16 d16, d16, d17 +@ CHECK: vmul.i32 d16, d16, d17 @ encoding: [0xb1,0x09,0x60,0xf2] + vmul.i32 d16, d16, d17 +@ CHECK: vmul.f32 d16, d16, d17 @ encoding: [0xb1,0x0d,0x40,0xf3] + vmul.f32 d16, d16, d17 +@ CHECK: vmul.i8 q8, q8, q9 @ encoding: [0xf2,0x09,0x40,0xf2] + vmul.i8 q8, q8, q9 +@ CHECK: vmul.i16 q8, q8, q9 @ encoding: [0xf2,0x09,0x50,0xf2] + vmul.i16 q8, q8, q9 +@ CHECK: vmul.i32 q8, q8, q9 @ encoding: [0xf2,0x09,0x60,0xf2] + vmul.i32 q8, q8, q9 +@ CHECK: vmul.f32 q8, q8, q9 @ encoding: [0xf2,0x0d,0x40,0xf3] + vmul.f32 q8, q8, q9 +@ CHECK: vmul.p8 d16, d16, d17 @ encoding: [0xb1,0x09,0x40,0xf3] + vmul.p8 d16, d16, d17 +@ CHECK: vmul.p8 q8, q8, q9 @ encoding: [0xf2,0x09,0x40,0xf3] + vmul.p8 q8, q8, q9 +@ CHECK: vqdmulh.s16 d16, d16, d17 @ encoding: [0xa1,0x0b,0x50,0xf2] + vqdmulh.s16 d16, d16, d17 +@ CHECK: vqdmulh.s32 d16, d16, d17 @ encoding: [0xa1,0x0b,0x60,0xf2] + vqdmulh.s32 d16, d16, d17 +@ CHECK: vqdmulh.s16 q8, q8, q9 @ encoding: [0xe2,0x0b,0x50,0xf2] + vqdmulh.s16 q8, q8, q9 +@ CHECK: vqdmulh.s32 q8, q8, q9 @ encoding: [0xe2,0x0b,0x60,0xf2] + vqdmulh.s32 q8, q8, q9 +@ CHECK: vqrdmulh.s16 d16, d16, d17 @ encoding: [0xa1,0x0b,0x50,0xf3] + vqrdmulh.s16 d16, d16, d17 +@ CHECK: vqrdmulh.s32 d16, d16, d17 @ encoding: [0xa1,0x0b,0x60,0xf3] + vqrdmulh.s32 d16, d16, d17 +@ CHECK: vqrdmulh.s16 q8, q8, q9 @ encoding: [0xe2,0x0b,0x50,0xf3] + vqrdmulh.s16 q8, q8, q9 +@ CHECK: vqrdmulh.s32 q8, q8, q9 @ encoding: [0xe2,0x0b,0x60,0xf3] + vqrdmulh.s32 q8, q8, q9 +@ CHECK: vmull.s8 q8, d16, d17 @ encoding: [0xa1,0x0c,0xc0,0xf2] + vmull.s8 q8, d16, d17 +@ CHECK: vmull.s16 q8, d16, d17 @ encoding: [0xa1,0x0c,0xd0,0xf2] + vmull.s16 q8, d16, d17 +@ CHECK: vmull.s32 q8, d16, d17 @ encoding: [0xa1,0x0c,0xe0,0xf2] + vmull.s32 q8, d16, d17 +@ CHECK: vmull.u8 q8, d16, d17 @ encoding: [0xa1,0x0c,0xc0,0xf3] + vmull.u8 q8, d16, d17 +@ CHECK: vmull.u16 q8, d16, d17 @ encoding: [0xa1,0x0c,0xd0,0xf3] + vmull.u16 q8, d16, d17 +@ CHECK: vmull.u32 q8, d16, d17 @ encoding: [0xa1,0x0c,0xe0,0xf3] + vmull.u32 q8, d16, d17 +@ CHECK: vmull.p8 q8, d16, d17 @ encoding: [0xa1,0x0e,0xc0,0xf2] + vmull.p8 q8, d16, d17 +@ CHECK: vqdmull.s16 q8, d16, d17 @ encoding: [0xa1,0x0d,0xd0,0xf2] + vqdmull.s16 q8, d16, d17 +@ CHECK: vqdmull.s32 q8, d16, d17 @ encoding: [0xa1,0x0d,0xe0,0xf2] + vqdmull.s32 q8, d16, d17 diff --git a/test/MC/ARM/neon-neg-encoding.s b/test/MC/ARM/neon-neg-encoding.s new file mode 100644 index 0000000..014bdb0 --- /dev/null +++ b/test/MC/ARM/neon-neg-encoding.s @@ -0,0 +1,30 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s + +@ CHECK: vneg.s8 d16, d16 @ encoding: [0xa0,0x03,0xf1,0xf3] + vneg.s8 d16, d16 +@ CHECK: vneg.s16 d16, d16 @ encoding: [0xa0,0x03,0xf5,0xf3] + vneg.s16 d16, d16 +@ CHECK: vneg.s32 d16, d16 @ encoding: [0xa0,0x03,0xf9,0xf3] + vneg.s32 d16, d16 +@ CHECK: vneg.f32 d16, d16 @ encoding: [0xa0,0x07,0xf9,0xf3] + vneg.f32 d16, d16 +@ CHECK: vneg.s8 q8, q8 @ encoding: [0xe0,0x03,0xf1,0xf3] + vneg.s8 q8, q8 +@ CHECK: vneg.s16 q8, q8 @ encoding: [0xe0,0x03,0xf5,0xf3] + vneg.s16 q8, q8 +@ CHECK: vneg.s32 q8, q8 @ encoding: [0xe0,0x03,0xf9,0xf3] + vneg.s32 q8, q8 +@ CHECK: vneg.f32 q8, q8 @ encoding: [0xe0,0x07,0xf9,0xf3] + vneg.f32 q8, q8 +@ CHECK: vqneg.s8 d16, d16 @ encoding: [0xa0,0x07,0xf0,0xf3] + vqneg.s8 d16, d16 +@ CHECK: vqneg.s16 d16, d16 @ encoding: [0xa0,0x07,0xf4,0xf3] + vqneg.s16 d16, d16 +@ CHECK: vqneg.s32 d16, d16 @ encoding: [0xa0,0x07,0xf8,0xf3] + vqneg.s32 d16, d16 +@ CHECK: vqneg.s8 q8, q8 @ encoding: [0xe0,0x07,0xf0,0xf3] + vqneg.s8 q8, q8 +@ CHECK: vqneg.s16 q8, q8 @ encoding: [0xe0,0x07,0xf4,0xf3] + vqneg.s16 q8, q8 +@ CHECK: vqneg.s32 q8, q8 @ encoding: [0xe0,0x07,0xf8,0xf3] + vqneg.s32 q8, q8 diff --git a/test/MC/ARM/neon-pairwise-encoding.s b/test/MC/ARM/neon-pairwise-encoding.s new file mode 100644 index 0000000..65c47bd --- /dev/null +++ b/test/MC/ARM/neon-pairwise-encoding.s @@ -0,0 +1,86 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s + +@ CHECK: vpadd.i8 d16, d17, d16 @ encoding: [0xb0,0x0b,0x41,0xf2] + vpadd.i8 d16, d17, d16 +@ CHECK: vpadd.i16 d16, d17, d16 @ encoding: [0xb0,0x0b,0x51,0xf2] + vpadd.i16 d16, d17, d16 +@ CHECK: vpadd.i32 d16, d17, d16 @ encoding: [0xb0,0x0b,0x61,0xf2] + vpadd.i32 d16, d17, d16 +@ CHECK: vpadd.f32 d16, d16, d17 @ encoding: [0xa1,0x0d,0x40,0xf3] + vpadd.f32 d16, d16, d17 +@ CHECK: vpaddl.s8 d16, d16 @ encoding: [0x20,0x02,0xf0,0xf3] + vpaddl.s8 d16, d16 +@ CHECK: vpaddl.s16 d16, d16 @ encoding: [0x20,0x02,0xf4,0xf3] + vpaddl.s16 d16, d16 +@ CHECK: vpaddl.s32 d16, d16 @ encoding: [0x20,0x02,0xf8,0xf3] + vpaddl.s32 d16, d16 +@ CHECK: vpaddl.u8 d16, d16 @ encoding: [0xa0,0x02,0xf0,0xf3] + vpaddl.u8 d16, d16 +@ CHECK: vpaddl.u16 d16, d16 @ encoding: [0xa0,0x02,0xf4,0xf3] + vpaddl.u16 d16, d16 +@ CHECK: vpaddl.u32 d16, d16 @ encoding: [0xa0,0x02,0xf8,0xf3] + vpaddl.u32 d16, d16 +@ CHECK: vpaddl.s8 q8, q8 @ encoding: [0x60,0x02,0xf0,0xf3] + vpaddl.s8 q8, q8 +@ CHECK: vpaddl.s16 q8, q8 @ encoding: [0x60,0x02,0xf4,0xf3] + vpaddl.s16 q8, q8 +@ CHECK: vpaddl.s32 q8, q8 @ encoding: [0x60,0x02,0xf8,0xf3] + vpaddl.s32 q8, q8 +@ CHECK: vpaddl.u8 q8, q8 @ encoding: [0xe0,0x02,0xf0,0xf3] + vpaddl.u8 q8, q8 +@ CHECK: vpaddl.u16 q8, q8 @ encoding: [0xe0,0x02,0xf4,0xf3] + vpaddl.u16 q8, q8 +@ CHECK: vpaddl.u32 q8, q8 @ encoding: [0xe0,0x02,0xf8,0xf3] + vpaddl.u32 q8, q8 +@ CHECK: vpadal.s8 d16, d17 @ encoding: [0x21,0x06,0xf0,0xf3] + vpadal.s8 d16, d17 +@ CHECK: vpadal.s16 d16, d17 @ encoding: [0x21,0x06,0xf4,0xf3] + vpadal.s16 d16, d17 +@ CHECK: vpadal.s32 d16, d17 @ encoding: [0x21,0x06,0xf8,0xf3] + vpadal.s32 d16, d17 +@ CHECK: vpadal.u8 d16, d17 @ encoding: [0xa1,0x06,0xf0,0xf3] + vpadal.u8 d16, d17 +@ CHECK: vpadal.u16 d16, d17 @ encoding: [0xa1,0x06,0xf4,0xf3] + vpadal.u16 d16, d17 +@ CHECK: vpadal.u32 d16, d17 @ encoding: [0xa1,0x06,0xf8,0xf3] + vpadal.u32 d16, d17 +@ CHECK: vpadal.s8 q9, q8 @ encoding: [0x60,0x26,0xf0,0xf3] + vpadal.s8 q9, q8 +@ CHECK: vpadal.s16 q9, q8 @ encoding: [0x60,0x26,0xf4,0xf3] + vpadal.s16 q9, q8 +@ CHECK: vpadal.s32 q9, q8 @ encoding: [0x60,0x26,0xf8,0xf3] + vpadal.s32 q9, q8 +@ CHECK: vpadal.u8 q9, q8 @ encoding: [0xe0,0x26,0xf0,0xf3] + vpadal.u8 q9, q8 +@ CHECK: vpadal.u16 q9, q8 @ encoding: [0xe0,0x26,0xf4,0xf3] + vpadal.u16 q9, q8 +@ CHECK: vpadal.u32 q9, q8 @ encoding: [0xe0,0x26,0xf8,0xf3] + vpadal.u32 q9, q8 +@ CHECK: vpmin.s8 d16, d16, d17 @ encoding: [0xb1,0x0a,0x40,0xf2] + vpmin.s8 d16, d16, d17 +@ CHECK: vpmin.s16 d16, d16, d17 @ encoding: [0xb1,0x0a,0x50,0xf2] + vpmin.s16 d16, d16, d17 +@ CHECK: vpmin.s32 d16, d16, d17 @ encoding: [0xb1,0x0a,0x60,0xf2] + vpmin.s32 d16, d16, d17 +@ CHECK: vpmin.u8 d16, d16, d17 @ encoding: [0xb1,0x0a,0x40,0xf3] + vpmin.u8 d16, d16, d17 +@ CHECK: vpmin.u16 d16, d16, d17 @ encoding: [0xb1,0x0a,0x50,0xf3] + vpmin.u16 d16, d16, d17 +@ CHECK: vpmin.u32 d16, d16, d17 @ encoding: [0xb1,0x0a,0x60,0xf3] + vpmin.u32 d16, d16, d17 +@ CHECK: vpmin.f32 d16, d16, d17 @ encoding: [0xa1,0x0f,0x60,0xf3] + vpmin.f32 d16, d16, d17 +@ CHECK: vpmax.s8 d16, d16, d17 @ encoding: [0xa1,0x0a,0x40,0xf2] + vpmax.s8 d16, d16, d17 +@ CHECK: vpmax.s16 d16, d16, d17 @ encoding: [0xa1,0x0a,0x50,0xf2] + vpmax.s16 d16, d16, d17 +@ CHECK: vpmax.s32 d16, d16, d17 @ encoding: [0xa1,0x0a,0x60,0xf2] + vpmax.s32 d16, d16, d17 +@ CHECK: vpmax.u8 d16, d16, d17 @ encoding: [0xa1,0x0a,0x40,0xf3] + vpmax.u8 d16, d16, d17 +@ CHECK: vpmax.u16 d16, d16, d17 @ encoding: [0xa1,0x0a,0x50,0xf3] + vpmax.u16 d16, d16, d17 +@ CHECK: vpmax.u32 d16, d16, d17 @ encoding: [0xa1,0x0a,0x60,0xf3] + vpmax.u32 d16, d16, d17 +@ CHECK: vpmax.f32 d16, d16, d17 @ encoding: [0xa1,0x0f,0x40,0xf3] + vpmax.f32 d16, d16, d17 diff --git a/test/MC/ARM/neon-reciprocal-encoding.s b/test/MC/ARM/neon-reciprocal-encoding.s new file mode 100644 index 0000000..e12a473 --- /dev/null +++ b/test/MC/ARM/neon-reciprocal-encoding.s @@ -0,0 +1,26 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s + +@ CHECK: vrecpe.u32 d16, d16 @ encoding: [0x20,0x04,0xfb,0xf3] + vrecpe.u32 d16, d16 +@ CHECK: vrecpe.u32 q8, q8 @ encoding: [0x60,0x04,0xfb,0xf3] + vrecpe.u32 q8, q8 +@ CHECK: vrecpe.f32 d16, d16 @ encoding: [0x20,0x05,0xfb,0xf3] + vrecpe.f32 d16, d16 +@ CHECK: vrecpe.f32 q8, q8 @ encoding: [0x60,0x05,0xfb,0xf3] + vrecpe.f32 q8, q8 +@ CHECK: vrecps.f32 d16, d16, d17 @ encoding: [0xb1,0x0f,0x40,0xf2] + vrecps.f32 d16, d16, d17 +@ CHECK: vrecps.f32 q8, q8, q9 @ encoding: [0xf2,0x0f,0x40,0xf2] + vrecps.f32 q8, q8, q9 +@ CHECK: vrsqrte.u32 d16, d16 @ encoding: [0xa0,0x04,0xfb,0xf3] + vrsqrte.u32 d16, d16 +@ CHECK: vrsqrte.u32 q8, q8 @ encoding: [0xe0,0x04,0xfb,0xf3] + vrsqrte.u32 q8, q8 +@ CHECK: vrsqrte.f32 d16, d16 @ encoding: [0xa0,0x05,0xfb,0xf3] + vrsqrte.f32 d16, d16 +@ CHECK: vrsqrte.f32 q8, q8 @ encoding: [0xe0,0x05,0xfb,0xf3] + vrsqrte.f32 q8, q8 +@ CHECK: vrsqrts.f32 d16, d16, d17 @ encoding: [0xb1,0x0f,0x60,0xf2] + vrsqrts.f32 d16, d16, d17 +@ CHECK: vrsqrts.f32 q8, q8, q9 @ encoding: [0xf2,0x0f,0x60,0xf2] + vrsqrts.f32 q8, q8, q9 diff --git a/test/MC/ARM/neon-reverse-encoding.s b/test/MC/ARM/neon-reverse-encoding.s new file mode 100644 index 0000000..e33b9f3 --- /dev/null +++ b/test/MC/ARM/neon-reverse-encoding.s @@ -0,0 +1,26 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s + +@ CHECK: vrev64.8 d16, d16 @ encoding: [0x20,0x00,0xf0,0xf3] + vrev64.8 d16, d16 +@ CHECK: vrev64.16 d16, d16 @ encoding: [0x20,0x00,0xf4,0xf3] + vrev64.16 d16, d16 +@ CHECK: vrev64.32 d16, d16 @ encoding: [0x20,0x00,0xf8,0xf3] + vrev64.32 d16, d16 +@ CHECK: vrev64.8 q8, q8 @ encoding: [0x60,0x00,0xf0,0xf3] + vrev64.8 q8, q8 +@ CHECK: vrev64.16 q8, q8 @ encoding: [0x60,0x00,0xf4,0xf3] + vrev64.16 q8, q8 +@ CHECK: vrev64.32 q8, q8 @ encoding: [0x60,0x00,0xf8,0xf3] + vrev64.32 q8, q8 +@ CHECK: vrev32.8 d16, d16 @ encoding: [0xa0,0x00,0xf0,0xf3] + vrev32.8 d16, d16 +@ CHECK: vrev32.16 d16, d16 @ encoding: [0xa0,0x00,0xf4,0xf3] + vrev32.16 d16, d16 +@ CHECK: vrev32.8 q8, q8 @ encoding: [0xe0,0x00,0xf0,0xf3] + vrev32.8 q8, q8 +@ CHECK: vrev32.16 q8, q8 @ encoding: [0xe0,0x00,0xf4,0xf3] + vrev32.16 q8, q8 +@ CHECK: vrev16.8 d16, d16 @ encoding: [0x20,0x01,0xf0,0xf3] + vrev16.8 d16, d16 +@ CHECK: vrev16.8 q8, q8 @ encoding: [0x60,0x01,0xf0,0xf3] + vrev16.8 q8, q8 diff --git a/test/MC/ARM/neon-satshift-encoding.s b/test/MC/ARM/neon-satshift-encoding.s new file mode 100644 index 0000000..506f48a --- /dev/null +++ b/test/MC/ARM/neon-satshift-encoding.s @@ -0,0 +1,150 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s + +@ CHECK: vqshl.s8 d16, d16, d17 @ encoding: [0xb0,0x04,0x41,0xf2] + vqshl.s8 d16, d16, d17 +@ CHECK: vqshl.s16 d16, d16, d17 @ encoding: [0xb0,0x04,0x51,0xf2] + vqshl.s16 d16, d16, d17 +@ CHECK: vqshl.s32 d16, d16, d17 @ encoding: [0xb0,0x04,0x61,0xf2] + vqshl.s32 d16, d16, d17 +@ CHECK: vqshl.s64 d16, d16, d17 @ encoding: [0xb0,0x04,0x71,0xf2] + vqshl.s64 d16, d16, d17 +@ CHECK: vqshl.u8 d16, d16, d17 @ encoding: [0xb0,0x04,0x41,0xf3] + vqshl.u8 d16, d16, d17 +@ CHECK: vqshl.u16 d16, d16, d17 @ encoding: [0xb0,0x04,0x51,0xf3] + vqshl.u16 d16, d16, d17 +@ CHECK: vqshl.u32 d16, d16, d17 @ encoding: [0xb0,0x04,0x61,0xf3] + vqshl.u32 d16, d16, d17 +@ CHECK: vqshl.u64 d16, d16, d17 @ encoding: [0xb0,0x04,0x71,0xf3] + vqshl.u64 d16, d16, d17 +@ CHECK: vqshl.s8 q8, q8, q9 @ encoding: [0xf0,0x04,0x42,0xf2] + vqshl.s8 q8, q8, q9 +@ CHECK: vqshl.s16 q8, q8, q9 @ encoding: [0xf0,0x04,0x52,0xf2] + vqshl.s16 q8, q8, q9 +@ CHECK: vqshl.s32 q8, q8, q9 @ encoding: [0xf0,0x04,0x62,0xf2] + vqshl.s32 q8, q8, q9 +@ CHECK: vqshl.s64 q8, q8, q9 @ encoding: [0xf0,0x04,0x72,0xf2] + vqshl.s64 q8, q8, q9 +@ CHECK: vqshl.u8 q8, q8, q9 @ encoding: [0xf0,0x04,0x42,0xf3] + vqshl.u8 q8, q8, q9 +@ CHECK: vqshl.u16 q8, q8, q9 @ encoding: [0xf0,0x04,0x52,0xf3] + vqshl.u16 q8, q8, q9 +@ CHECK: vqshl.u32 q8, q8, q9 @ encoding: [0xf0,0x04,0x62,0xf3] + vqshl.u32 q8, q8, q9 +@ CHECK: vqshl.u64 q8, q8, q9 @ encoding: [0xf0,0x04,0x72,0xf3] + vqshl.u64 q8, q8, q9 +@ CHECK: vqshl.s8 d16, d16, #7 @ encoding: [0x30,0x07,0xcf,0xf2] + vqshl.s8 d16, d16, #7 +@ CHECK: vqshl.s16 d16, d16, #15 @ encoding: [0x30,0x07,0xdf,0xf2] + vqshl.s16 d16, d16, #15 +@ CHECK: vqshl.s32 d16, d16, #31 @ encoding: [0x30,0x07,0xff,0xf2] + vqshl.s32 d16, d16, #31 +@ CHECK: vqshl.s64 d16, d16, #63 @ encoding: [0xb0,0x07,0xff,0xf2] + vqshl.s64 d16, d16, #63 +@ CHECK: vqshl.u8 d16, d16, #7 @ encoding: [0x30,0x07,0xcf,0xf3] + vqshl.u8 d16, d16, #7 +@ CHECK: vqshl.u16 d16, d16, #15 @ encoding: [0x30,0x07,0xdf,0xf3] + vqshl.u16 d16, d16, #15 +@ CHECK: vqshl.u32 d16, d16, #31 @ encoding: [0x30,0x07,0xff,0xf3] + vqshl.u32 d16, d16, #31 +@ CHECK: vqshl.u64 d16, d16, #63 @ encoding: [0xb0,0x07,0xff,0xf3] + vqshl.u64 d16, d16, #63 +@ CHECK: vqshlu.s8 d16, d16, #7 @ encoding: [0x30,0x06,0xcf,0xf3] + vqshlu.s8 d16, d16, #7 +@ CHECK: vqshlu.s16 d16, d16, #15 @ encoding: [0x30,0x06,0xdf,0xf3] + vqshlu.s16 d16, d16, #15 +@ CHECK: vqshlu.s32 d16, d16, #31 @ encoding: [0x30,0x06,0xff,0xf3] + vqshlu.s32 d16, d16, #31 +@ CHECK: vqshlu.s64 d16, d16, #63 @ encoding: [0xb0,0x06,0xff,0xf3] + vqshlu.s64 d16, d16, #63 +@ CHECK: vqshl.s8 q8, q8, #7 @ encoding: [0x70,0x07,0xcf,0xf2] + vqshl.s8 q8, q8, #7 +@ CHECK: vqshl.s16 q8, q8, #15 @ encoding: [0x70,0x07,0xdf,0xf2] + vqshl.s16 q8, q8, #15 +@ CHECK: vqshl.s32 q8, q8, #31 @ encoding: [0x70,0x07,0xff,0xf2] + vqshl.s32 q8, q8, #31 +@ CHECK: vqshl.s64 q8, q8, #63 @ encoding: [0xf0,0x07,0xff,0xf2] + vqshl.s64 q8, q8, #63 +@ CHECK: vqshl.u8 q8, q8, #7 @ encoding: [0x70,0x07,0xcf,0xf3] + vqshl.u8 q8, q8, #7 +@ CHECK: vqshl.u16 q8, q8, #15 @ encoding: [0x70,0x07,0xdf,0xf3] + vqshl.u16 q8, q8, #15 +@ CHECK: vqshl.u32 q8, q8, #31 @ encoding: [0x70,0x07,0xff,0xf3] + vqshl.u32 q8, q8, #31 +@ CHECK: vqshl.u64 q8, q8, #63 @ encoding: [0xf0,0x07,0xff,0xf3] + vqshl.u64 q8, q8, #63 +@ CHECK: vqshlu.s8 q8, q8, #7 @ encoding: [0x70,0x06,0xcf,0xf3] + vqshlu.s8 q8, q8, #7 +@ CHECK: vqshlu.s16 q8, q8, #15 @ encoding: [0x70,0x06,0xdf,0xf3] + vqshlu.s16 q8, q8, #15 +@ CHECK: vqshlu.s32 q8, q8, #31 @ encoding: [0x70,0x06,0xff,0xf3] + vqshlu.s32 q8, q8, #31 +@ CHECK: vqshlu.s64 q8, q8, #63 @ encoding: [0xf0,0x06,0xff,0xf3] + vqshlu.s64 q8, q8, #63 +@ CHECK: vqrshl.s8 d16, d16, d17 @ encoding: [0xb0,0x05,0x41,0xf2] + vqrshl.s8 d16, d16, d17 +@ CHECK: vqrshl.s16 d16, d16, d17 @ encoding: [0xb0,0x05,0x51,0xf2] + vqrshl.s16 d16, d16, d17 +@ CHECK: vqrshl.s32 d16, d16, d17 @ encoding: [0xb0,0x05,0x61,0xf2] + vqrshl.s32 d16, d16, d17 +@ CHECK: vqrshl.s64 d16, d16, d17 @ encoding: [0xb0,0x05,0x71,0xf2] + vqrshl.s64 d16, d16, d17 +@ CHECK: vqrshl.u8 d16, d16, d17 @ encoding: [0xb0,0x05,0x41,0xf3] + vqrshl.u8 d16, d16, d17 +@ CHECK: vqrshl.u16 d16, d16, d17 @ encoding: [0xb0,0x05,0x51,0xf3] + vqrshl.u16 d16, d16, d17 +@ CHECK: vqrshl.u32 d16, d16, d17 @ encoding: [0xb0,0x05,0x61,0xf3] + vqrshl.u32 d16, d16, d17 +@ CHECK: vqrshl.u64 d16, d16, d17 @ encoding: [0xb0,0x05,0x71,0xf3] + vqrshl.u64 d16, d16, d17 +@ CHECK: vqrshl.s8 q8, q8, q9 @ encoding: [0xf0,0x05,0x42,0xf2] + vqrshl.s8 q8, q8, q9 +@ CHECK: vqrshl.s16 q8, q8, q9 @ encoding: [0xf0,0x05,0x52,0xf2] + vqrshl.s16 q8, q8, q9 +@ CHECK: vqrshl.s32 q8, q8, q9 @ encoding: [0xf0,0x05,0x62,0xf2] + vqrshl.s32 q8, q8, q9 +@ CHECK: vqrshl.s64 q8, q8, q9 @ encoding: [0xf0,0x05,0x72,0xf2] + vqrshl.s64 q8, q8, q9 +@ CHECK: vqrshl.u8 q8, q8, q9 @ encoding: [0xf0,0x05,0x42,0xf3] + vqrshl.u8 q8, q8, q9 +@ CHECK: vqrshl.u16 q8, q8, q9 @ encoding: [0xf0,0x05,0x52,0xf3] + vqrshl.u16 q8, q8, q9 +@ CHECK: vqrshl.u32 q8, q8, q9 @ encoding: [0xf0,0x05,0x62,0xf3] + vqrshl.u32 q8, q8, q9 +@ CHECK: vqrshl.u64 q8, q8, q9 @ encoding: [0xf0,0x05,0x72,0xf3] + vqrshl.u64 q8, q8, q9 +@ CHECK: vqshrn.s16 d16, q8, #8 @ encoding: [0x30,0x09,0xc8,0xf2] + vqshrn.s16 d16, q8, #8 +@ CHECK: vqshrn.s32 d16, q8, #16 @ encoding: [0x30,0x09,0xd0,0xf2] + vqshrn.s32 d16, q8, #16 +@ CHECK: vqshrn.s64 d16, q8, #32 @ encoding: [0x30,0x09,0xe0,0xf2] + vqshrn.s64 d16, q8, #32 +@ CHECK: vqshrn.u16 d16, q8, #8 @ encoding: [0x30,0x09,0xc8,0xf3] + vqshrn.u16 d16, q8, #8 +@ CHECK: vqshrn.u32 d16, q8, #16 @ encoding: [0x30,0x09,0xd0,0xf3] + vqshrn.u32 d16, q8, #16 +@ CHECK: vqshrn.u64 d16, q8, #32 @ encoding: [0x30,0x09,0xe0,0xf3] + vqshrn.u64 d16, q8, #32 +@ CHECK: vqshrun.s16 d16, q8, #8 @ encoding: [0x30,0x08,0xc8,0xf3] + vqshrun.s16 d16, q8, #8 +@ CHECK: vqshrun.s32 d16, q8, #16 @ encoding: [0x30,0x08,0xd0,0xf3] + vqshrun.s32 d16, q8, #16 +@ CHECK: vqshrun.s64 d16, q8, #32 @ encoding: [0x30,0x08,0xe0,0xf3] + vqshrun.s64 d16, q8, #32 +@ CHECK: vqrshrn.s16 d16, q8, #8 @ encoding: [0x70,0x09,0xc8,0xf2] + vqrshrn.s16 d16, q8, #8 +@ CHECK: vqrshrn.s32 d16, q8, #16 @ encoding: [0x70,0x09,0xd0,0xf2] + vqrshrn.s32 d16, q8, #16 +@ CHECK: vqrshrn.s64 d16, q8, #32 @ encoding: [0x70,0x09,0xe0,0xf2] + vqrshrn.s64 d16, q8, #32 +@ CHECK: vqrshrn.u16 d16, q8, #8 @ encoding: [0x70,0x09,0xc8,0xf3] + vqrshrn.u16 d16, q8, #8 +@ CHECK: vqrshrn.u32 d16, q8, #16 @ encoding: [0x70,0x09,0xd0,0xf3] + vqrshrn.u32 d16, q8, #16 +@ CHECK: vqrshrn.u64 d16, q8, #32 @ encoding: [0x70,0x09,0xe0,0xf3] + vqrshrn.u64 d16, q8, #32 +@ CHECK: vqrshrun.s16 d16, q8, #8 @ encoding: [0x70,0x08,0xc8,0xf3] + vqrshrun.s16 d16, q8, #8 +@ CHECK: vqrshrun.s32 d16, q8, #16 @ encoding: [0x70,0x08,0xd0,0xf3] + vqrshrun.s32 d16, q8, #16 +@ CHECK: vqrshrun.s64 d16, q8, #32 @ encoding: [0x70,0x08,0xe0,0xf3] + vqrshrun.s64 d16, q8, #32 diff --git a/test/MC/ARM/neon-shift-encoding.s b/test/MC/ARM/neon-shift-encoding.s new file mode 100644 index 0000000..4b4fa08 --- /dev/null +++ b/test/MC/ARM/neon-shift-encoding.s @@ -0,0 +1,160 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s + +@ CHECK: vshl.u8 d16, d17, d16 @ encoding: [0xa1,0x04,0x40,0xf3] + vshl.u8 d16, d17, d16 +@ CHECK: vshl.u16 d16, d17, d16 @ encoding: [0xa1,0x04,0x50,0xf3] + vshl.u16 d16, d17, d16 +@ CHECK: vshl.u32 d16, d17, d16 @ encoding: [0xa1,0x04,0x60,0xf3] + vshl.u32 d16, d17, d16 +@ CHECK: vshl.u64 d16, d17, d16 @ encoding: [0xa1,0x04,0x70,0xf3] + vshl.u64 d16, d17, d16 +@ CHECK: vshl.i8 d16, d16, #7 @ encoding: [0x30,0x05,0xcf,0xf2] + vshl.i8 d16, d16, #7 +@ CHECK: vshl.i16 d16, d16, #15 @ encoding: [0x30,0x05,0xdf,0xf2] + vshl.i16 d16, d16, #15 +@ CHECK: vshl.i32 d16, d16, #31 @ encoding: [0x30,0x05,0xff,0xf2] + vshl.i32 d16, d16, #31 +@ CHECK: vshl.i64 d16, d16, #63 @ encoding: [0xb0,0x05,0xff,0xf2] + vshl.i64 d16, d16, #63 +@ CHECK: vshl.u8 q8, q9, q8 @ encoding: [0xe2,0x04,0x40,0xf3] + vshl.u8 q8, q9, q8 +@ CHECK: vshl.u16 q8, q9, q8 @ encoding: [0xe2,0x04,0x50,0xf3] + vshl.u16 q8, q9, q8 +@ CHECK: vshl.u32 q8, q9, q8 @ encoding: [0xe2,0x04,0x60,0xf3] + vshl.u32 q8, q9, q8 +@ CHECK: vshl.u64 q8, q9, q8 @ encoding: [0xe2,0x04,0x70,0xf3] + vshl.u64 q8, q9, q8 +@ CHECK: vshl.i8 q8, q8, #7 @ encoding: [0x70,0x05,0xcf,0xf2] + vshl.i8 q8, q8, #7 +@ CHECK: vshl.i16 q8, q8, #15 @ encoding: [0x70,0x05,0xdf,0xf2] + vshl.i16 q8, q8, #15 +@ CHECK: vshl.i32 q8, q8, #31 @ encoding: [0x70,0x05,0xff,0xf2] + vshl.i32 q8, q8, #31 +@ CHECK: vshl.i64 q8, q8, #63 @ encoding: [0xf0,0x05,0xff,0xf2] + vshl.i64 q8, q8, #63 +@ CHECK: vshr.u8 d16, d16, #8 @ encoding: [0x30,0x00,0xc8,0xf3] + vshr.u8 d16, d16, #8 +@ CHECK: vshr.u16 d16, d16, #16 @ encoding: [0x30,0x00,0xd0,0xf3] + vshr.u16 d16, d16, #16 +@ CHECK: vshr.u32 d16, d16, #32 @ encoding: [0x30,0x00,0xe0,0xf3] + vshr.u32 d16, d16, #32 +@ CHECK: vshr.u64 d16, d16, #64 @ encoding: [0xb0,0x00,0xc0,0xf3] + vshr.u64 d16, d16, #64 +@ CHECK: vshr.u8 q8, q8, #8 @ encoding: [0x70,0x00,0xc8,0xf3] + vshr.u8 q8, q8, #8 +@ CHECK: vshr.u16 q8, q8, #16 @ encoding: [0x70,0x00,0xd0,0xf3] + vshr.u16 q8, q8, #16 +@ CHECK: vshr.u32 q8, q8, #32 @ encoding: [0x70,0x00,0xe0,0xf3] + vshr.u32 q8, q8, #32 +@ CHECK: vshr.u64 q8, q8, #64 @ encoding: [0xf0,0x00,0xc0,0xf3] + vshr.u64 q8, q8, #64 +@ CHECK: vshr.s8 d16, d16, #8 @ encoding: [0x30,0x00,0xc8,0xf2] + vshr.s8 d16, d16, #8 +@ CHECK: vshr.s16 d16, d16, #16 @ encoding: [0x30,0x00,0xd0,0xf2] + vshr.s16 d16, d16, #16 +@ CHECK: vshr.s32 d16, d16, #32 @ encoding: [0x30,0x00,0xe0,0xf2] + vshr.s32 d16, d16, #32 +@ CHECK: vshr.s64 d16, d16, #64 @ encoding: [0xb0,0x00,0xc0,0xf2] + vshr.s64 d16, d16, #64 +@ CHECK: vshr.s8 q8, q8, #8 @ encoding: [0x70,0x00,0xc8,0xf2] + vshr.s8 q8, q8, #8 +@ CHECK: vshr.s16 q8, q8, #16 @ encoding: [0x70,0x00,0xd0,0xf2] + vshr.s16 q8, q8, #16 +@ CHECK: vshr.s32 q8, q8, #32 @ encoding: [0x70,0x00,0xe0,0xf2 + vshr.s32 q8, q8, #32 +@ CHECK: vshr.s64 q8, q8, #64 @ encoding: [0xf0,0x00,0xc0,0xf2] + vshr.s64 q8, q8, #64 +@ CHECK: vshll.s8 q8, d16, #7 @ encoding: [0x30,0x0a,0xcf,0xf2] + vshll.s8 q8, d16, #7 +@ CHECK: vshll.s16 q8, d16, #15 @ encoding: [0x30,0x0a,0xdf,0xf2] + vshll.s16 q8, d16, #15 +@ CHECK: vshll.s32 q8, d16, #31 @ encoding: [0x30,0x0a,0xff,0xf2] + vshll.s32 q8, d16, #31 +@ CHECK: vshll.u8 q8, d16, #7 @ encoding: [0x30,0x0a,0xcf,0xf3] + vshll.u8 q8, d16, #7 +@ CHECK: vshll.u16 q8, d16, #15 @ encoding: [0x30,0x0a,0xdf,0xf3] + vshll.u16 q8, d16, #15 +@ CHECK: vshll.u32 q8, d16, #31 @ encoding: [0x30,0x0a,0xff,0xf3] + vshll.u32 q8, d16, #31 +@ CHECK: vshll.i8 q8, d16, #8 @ encoding: [0x20,0x03,0xf2,0xf3] + vshll.i8 q8, d16, #8 +@ CHECK: vshll.i16 q8, d16, #16 @ encoding: [0x20,0x03,0xf6,0xf3] + vshll.i16 q8, d16, #16 +@ CHECK: vshll.i32 q8, d16, #32 @ encoding: [0x20,0x03,0xfa,0xf3] + vshll.i32 q8, d16, #32 +@ CHECK: vshrn.i16 d16, q8, #8 @ encoding: [0x30,0x08,0xc8,0xf2] + vshrn.i16 d16, q8, #8 +@ CHECK: vshrn.i32 d16, q8, #16 @ encoding: [0x30,0x08,0xd0,0xf2] + vshrn.i32 d16, q8, #16 +@ CHECK: vshrn.i64 d16, q8, #32 @ encoding: [0x30,0x08,0xe0,0xf2] + vshrn.i64 d16, q8, #32 +@ CHECK: vrshl.s8 d16, d17, d16 @ encoding: [0xa1,0x05,0x40,0xf2] + vrshl.s8 d16, d17, d16 +@ CHECK: vrshl.s16 d16, d17, d16 @ encoding: [0xa1,0x05,0x50,0xf2] + vrshl.s16 d16, d17, d16 +@ CHECK: vrshl.s32 d16, d17, d16 @ encoding: [0xa1,0x05,0x60,0xf2] + vrshl.s32 d16, d17, d16 +@ CHECK: vrshl.s64 d16, d17, d16 @ encoding: [0xa1,0x05,0x70,0 + vrshl.s64 d16, d17, d16 +@ CHECK: vrshl.u8 d16, d17, d16 @ encoding: [0xa1,0x05,0x40,0xf3] + vrshl.u8 d16, d17, d16 +@ CHECK: vrshl.u16 d16, d17, d16 @ encoding: [0xa1,0x05,0x50,0xf3] + vrshl.u16 d16, d17, d16 +@ CHECK: vrshl.u32 d16, d17, d16 @ encoding: [0xa1,0x05,0x60,0xf3] + vrshl.u32 d16, d17, d16 +@ CHECK: vrshl.u64 d16, d17, d16 @ encoding: [0xa1,0x05,0x70,0xf3] + vrshl.u64 d16, d17, d16 +@ CHECK: vrshl.s8 q8, q9, q8 @ encoding: [0xe2,0x05,0x40,0xf2] + vrshl.s8 q8, q9, q8 +@ CHECK: vrshl.s16 q8, q9, q8 @ encoding: [0xe2,0x05,0x50,0xf2] + vrshl.s16 q8, q9, q8 +@ CHECK: vrshl.s32 q8, q9, q8 @ encoding: [0xe2,0x05,0x60,0xf2] + vrshl.s32 q8, q9, q8 +@ CHECK: vrshl.s64 q8, q9, q8 @ encoding: [0xe2,0x05,0x70,0xf2] + vrshl.s64 q8, q9, q8 +@ CHECK: vrshl.u8 q8, q9, q8 @ encoding: [0xe2,0x05,0x40,0xf3] + vrshl.u8 q8, q9, q8 +@ CHECK: vrshl.u16 q8, q9, q8 @ encoding: [0xe2,0x05,0x50,0xf3] + vrshl.u16 q8, q9, q8 +@ CHECK: vrshl.u32 q8, q9, q8 @ encoding: [0xe2,0x05,0x60,0xf3] + vrshl.u32 q8, q9, q8 +@ CHECK: vrshl.u64 q8, q9, q8 @ encoding: [0xe2,0x05,0x70,0xf3] + vrshl.u64 q8, q9, q8 +@ CHECK: vrshr.s8 d16, d16, #8 @ encoding: [0x30,0x02,0xc8,0xf2] + vrshr.s8 d16, d16, #8 +@ CHECK: vrshr.s16 d16, d16, #16 @ encoding: [0x30,0x02,0xd0,0xf2] + vrshr.s16 d16, d16, #16 +@ CHECK: vrshr.s32 d16, d16, #32 @ encoding: [0x30,0x02,0xe0,0xf2] + vrshr.s32 d16, d16, #32 +@ CHECK: vrshr.s64 d16, d16, #64 @ encoding: [0xb0,0x02,0xc0,0xf2] + vrshr.s64 d16, d16, #64 +@ CHECK: vrshr.u8 d16, d16, #8 @ encoding: [0x30,0x02,0xc8,0xf3] + vrshr.u8 d16, d16, #8 +@ CHECK: vrshr.u16 d16, d16, #16 @ encoding: [0x30,0x02,0xd0,0xf3] + vrshr.u16 d16, d16, #16 +@ CHECK: vrshr.u32 d16, d16, #32 @ encoding: [0x30,0x02,0xe0,0xf3] + vrshr.u32 d16, d16, #32 +@ CHECK: vrshr.u64 d16, d16, #64 @ encoding: [0xb0,0x02,0xc0,0xf3] + vrshr.u64 d16, d16, #64 +@ CHECK: vrshr.s8 q8, q8, #8 @ encoding: [0x70,0x02,0xc8,0xf2] + vrshr.s8 q8, q8, #8 +@ CHECK: vrshr.s16 q8, q8, #16 @ encoding: [0x70,0x02,0xd0,0xf2] + vrshr.s16 q8, q8, #16 +@ CHECK: vrshr.s32 q8, q8, #32 @ encoding: [0x70,0x02,0xe0,0xf2] + vrshr.s32 q8, q8, #32 +@ CHECK: vrshr.s64 q8, q8, #64 @ encoding: [0xf0,0x02,0xc0,0xf2] + vrshr.s64 q8, q8, #64 +@ CHECK: vrshr.u8 q8, q8, #8 @ encoding: [0x70,0x02,0xc8,0xf3] + vrshr.u8 q8, q8, #8 +@ CHECK: vrshr.u16 q8, q8, #16 @ encoding: [0x70,0x02,0xd0,0xf3] + vrshr.u16 q8, q8, #16 +@ CHECK: vrshr.u32 q8, q8, #32 @ encoding: [0x70,0x02,0xe0,0xf3] + vrshr.u32 q8, q8, #32 +@ CHECK: vrshr.u64 q8, q8, #64 @ encoding: [0xf0,0x02,0xc0,0xf3] + vrshr.u64 q8, q8, #64 +@ CHECK: vrshrn.i16 d16, q8, #8 @ encoding: [0x70,0x08,0xc8,0xf2] + vrshrn.i16 d16, q8, #8 +@ CHECK: vrshrn.i32 d16, q8, #16 @ encoding: [0x70,0x08,0xd0,0xf2] + vrshrn.i32 d16, q8, #16 +@ CHECK: vrshrn.i64 d16, q8, #32 @ encoding: [0x70,0x08,0xe0,0xf2] + vrshrn.i64 d16, q8, #32 diff --git a/test/MC/ARM/neon-shiftaccum-encoding.s b/test/MC/ARM/neon-shiftaccum-encoding.s new file mode 100644 index 0000000..0dc630d --- /dev/null +++ b/test/MC/ARM/neon-shiftaccum-encoding.s @@ -0,0 +1,98 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s + +@ CHECK: vsra.s8 d17, d16, #8 @ encoding: [0x30,0x11,0xc8,0xf2] + vsra.s8 d17, d16, #8 +@ CHECK: vsra.s16 d17, d16, #16 @ encoding: [0x30,0x11,0xd0,0xf2] + vsra.s16 d17, d16, #16 +@ CHECK: vsra.s32 d17, d16, #32 @ encoding: [0x30,0x11,0xe0,0xf2] + vsra.s32 d17, d16, #32 +@ CHECK: vsra.s64 d17, d16, #64 @ encoding: [0xb0,0x11,0xc0,0xf2] + vsra.s64 d17, d16, #64 +@ CHECK: vsra.s8 q8, q9, #8 @ encoding: [0x72,0x01,0xc8,0xf2] + vsra.s8 q8, q9, #8 +@ CHECK: vsra.s16 q8, q9, #16 @ encoding: [0x72,0x01,0xd0,0xf2] + vsra.s16 q8, q9, #16 +@ CHECK: vsra.s32 q8, q9, #32 @ encoding: [0x72,0x01,0xe0,0xf2] + vsra.s32 q8, q9, #32 +@ CHECK: vsra.s64 q8, q9, #64 @ encoding: [0xf2,0x01,0xc0,0xf2] + vsra.s64 q8, q9, #64 +@ CHECK: vsra.u8 d17, d16, #8 @ encoding: [0x30,0x11,0xc8,0xf3] + vsra.u8 d17, d16, #8 +@ CHECK: vsra.u16 d17, d16, #16 @ encoding: [0x30,0x11,0xd0,0xf3] + vsra.u16 d17, d16, #16 +@ CHECK: vsra.u32 d17, d16, #32 @ encoding: [0x30,0x11,0xe0,0xf3] + vsra.u32 d17, d16, #32 +@ CHECK: vsra.u64 d17, d16, #64 @ encoding: [0xb0,0x11,0xc0,0xf3] + vsra.u64 d17, d16, #64 +@ CHECK: vsra.u8 q8, q9, #8 @ encoding: [0x72,0x01,0xc8,0xf3] + vsra.u8 q8, q9, #8 +@ CHECK: vsra.u16 q8, q9, #16 @ encoding: [0x72,0x01,0xd0,0xf3] + vsra.u16 q8, q9, #16 +@ CHECK: vsra.u32 q8, q9, #32 @ encoding: [0x72,0x01,0xe0,0xf3] + vsra.u32 q8, q9, #32 +@ CHECK: vsra.u64 q8, q9, #64 @ encoding: [0xf2,0x01,0xc0,0xf3] + vsra.u64 q8, q9, #64 +@ CHECK: vrsra.s8 d17, d16, #8 @ encoding: [0x30,0x13,0xc8,0xf2] + vrsra.s8 d17, d16, #8 +@ CHECK: vrsra.s16 d17, d16, #16 @ encoding: [0x30,0x13,0xd0,0xf2] + vrsra.s16 d17, d16, #16 +@ CHECK: vrsra.s32 d17, d16, #32 @ encoding: [0x30,0x13,0xe0,0xf2] + vrsra.s32 d17, d16, #32 +@ CHECK: vrsra.s64 d17, d16, #64 @ encoding: [0xb0,0x13,0xc0,0xf2] + vrsra.s64 d17, d16, #64 +@ CHECK: vrsra.u8 d17, d16, #8 @ encoding: [0x30,0x13,0xc8,0xf3] + vrsra.u8 d17, d16, #8 +@ CHECK: vrsra.u16 d17, d16, #16 @ encoding: [0x30,0x13,0xd0,0xf3] + vrsra.u16 d17, d16, #16 +@ CHECK: vrsra.u32 d17, d16, #32 @ encoding: [0x30,0x13,0xe0,0xf3] + vrsra.u32 d17, d16, #32 +@ CHECK: vrsra.u64 d17, d16, #64 @ encoding: [0xb0,0x13,0xc0,0xf3] + vrsra.u64 d17, d16, #64 +@ CHECK: vrsra.s8 q8, q9, #8 @ encoding: [0x72,0x03,0xc8,0xf2] + vrsra.s8 q8, q9, #8 +@ CHECK: vrsra.s16 q8, q9, #16 @ encoding: [0x72,0x03,0xd0,0xf2] + vrsra.s16 q8, q9, #16 +@ CHECK: vrsra.s32 q8, q9, #32 @ encoding: [0x72,0x03,0xe0,0xf2] + vrsra.s32 q8, q9, #32 +@ CHECK: vrsra.s64 q8, q9, #64 @ encoding: [0xf2,0x03,0xc0,0xf2] + vrsra.s64 q8, q9, #64 +@ CHECK: vrsra.u8 q8, q9, #8 @ encoding: [0x72,0x03,0xc8,0xf3] + vrsra.u8 q8, q9, #8 +@ CHECK: vrsra.u16 q8, q9, #16 @ encoding: [0x72,0x03,0xd0,0xf3] + vrsra.u16 q8, q9, #16 +@ CHECK: vrsra.u32 q8, q9, #32 @ encoding: [0x72,0x03,0xe0,0xf3] + vrsra.u32 q8, q9, #32 +@ CHECK: vrsra.u64 q8, q9, #64 @ encoding: [0xf2,0x03,0xc0,0xf3] + vrsra.u64 q8, q9, #64 +@ CHECK: vsli.8 d17, d16, #7 @ encoding: [0x30,0x15,0xcf,0xf3] + vsli.8 d17, d16, #7 +@ CHECK: vsli.16 d17, d16, #15 @ encoding: [0x30,0x15,0xdf,0xf3] + vsli.16 d17, d16, #15 +@ CHECK: vsli.32 d17, d16, #31 @ encoding: [0x30,0x15,0xff,0xf3] + vsli.32 d17, d16, #31 +@ CHECK: vsli.64 d17, d16, #63 @ encoding: [0xb0,0x15,0xff,0xf3] + vsli.64 d17, d16, #63 +@ CHECK: vsli.8 q9, q8, #7 @ encoding: [0x70,0x25,0xcf,0xf3] + vsli.8 q9, q8, #7 +@ CHECK: vsli.16 q9, q8, #15 @ encoding: [0x70,0x25,0xdf,0xf3] + vsli.16 q9, q8, #15 +@ CHECK: vsli.32 q9, q8, #31 @ encoding: [0x70,0x25,0xff,0xf3] + vsli.32 q9, q8, #31 +@ CHECK: vsli.64 q9, q8, #63 @ encoding: [0xf0,0x25,0xff,0xf3] + vsli.64 q9, q8, #63 +@ CHECK: vsri.8 d17, d16, #8 @ encoding: [0x30,0x14,0xc8,0xf3] + vsri.8 d17, d16, #8 +@ CHECK: vsri.16 d17, d16, #16 @ encoding: [0x30,0x14,0xd0,0xf3] + vsri.16 d17, d16, #16 +@ CHECK: vsri.32 d17, d16, #32 @ encoding: [0x30,0x14,0xe0,0xf3] + vsri.32 d17, d16, #32 +@ CHECK: vsri.64 d17, d16, #64 @ encoding: [0xb0,0x14,0xc0,0xf3] + vsri.64 d17, d16, #64 +@ CHECK: vsri.8 q9, q8, #8 @ encoding: [0x70,0x24,0xc8,0xf3] + vsri.8 q9, q8, #8 +@ CHECK: vsri.16 q9, q8, #16 @ encoding: [0x70,0x24,0xd0,0xf3] + vsri.16 q9, q8, #16 +@ CHECK: vsri.32 q9, q8, #32 @ encoding: [0x70,0x24,0xe0,0xf3] + vsri.32 q9, q8, #32 +@ CHECK: vsri.64 q9, q8, #64 @ encoding: [0xf0,0x24,0xc0,0xf3] + vsri.64 q9, q8, #64 diff --git a/test/MC/ARM/neon-shuffle-encoding.s b/test/MC/ARM/neon-shuffle-encoding.s new file mode 100644 index 0000000..ce7eb66 --- /dev/null +++ b/test/MC/ARM/neon-shuffle-encoding.s @@ -0,0 +1,46 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s + +@ CHECK: vext.8 d16, d17, d16, #3 @ encoding: [0xa0,0x03,0xf1,0xf2] + vext.8 d16, d17, d16, #3 +@ CHECK: vext.8 d16, d17, d16, #5 @ encoding: [0xa0,0x05,0xf1,0xf2] + vext.8 d16, d17, d16, #5 +@ CHECK: vext.8 q8, q9, q8, #3 @ encoding: [0xe0,0x03,0xf2,0xf2] + vext.8 q8, q9, q8, #3 +@ CHECK: vext.8 q8, q9, q8, #7 @ encoding: [0xe0,0x07,0xf2,0xf2] + vext.8 q8, q9, q8, #7 +@ CHECK: vext.16 d16, d17, d16, #3 @ encoding: [0xa0,0x06,0xf1,0xf2] + vext.16 d16, d17, d16, #3 +@ CHECK: vext.32 q8, q9, q8, #3 @ encoding: [0xe0,0x0c,0xf2,0xf2] + vext.32 q8, q9, q8, #3 +@ CHECK: vtrn.8 d17, d16 @ encoding: [0xa0,0x10,0xf2,0xf3] + vtrn.8 d17, d16 +@ CHECK: vtrn.16 d17, d16 @ encoding: [0xa0,0x10,0xf6,0xf3] + vtrn.16 d17, d16 +@ CHECK: vtrn.32 d17, d16 @ encoding: [0xa0,0x10,0xfa,0xf3] + vtrn.32 d17, d16 +@ CHECK: vtrn.8 q9, q8 @ encoding: [0xe0,0x20,0xf2,0xf3] + vtrn.8 q9, q8 +@ CHECK: vtrn.16 q9, q8 @ encoding: [0xe0,0x20,0xf6,0xf3] + vtrn.16 q9, q8 +@ CHECK: vtrn.32 q9, q8 @ encoding: [0xe0,0x20,0xfa,0xf3] + vtrn.32 q9, q8 +@ CHECK: vuzp.8 d17, d16 @ encoding: [0x20,0x11,0xf2,0xf3] + vuzp.8 d17, d16 +@ CHECK: vuzp.16 d17, d16 @ encoding: [0x20,0x11,0xf6,0xf3] + vuzp.16 d17, d16 +@ CHECK: vuzp.8 q9, q8 @ encoding: [0x60,0x21,0xf2,0xf3] + vuzp.8 q9, q8 +@ CHECK: vuzp.16 q9, q8 @ encoding: [0x60,0x21,0xf6,0xf3] + vuzp.16 q9, q8 +@ CHECK: vuzp.32 q9, q8 @ encoding: [0x60,0x21,0xfa,0xf3] + vuzp.32 q9, q8 +@ CHECK: vzip.8 d17, d16 @ encoding: [0xa0,0x11,0xf2,0xf3] + vzip.8 d17, d16 +@ CHECK: vzip.16 d17, d16 @ encoding: [0xa0,0x11,0xf6,0xf3] + vzip.16 d17, d16 +@ CHECK: vzip.8 q9, q8 @ encoding: [0xe0,0x21,0xf2,0xf3] + vzip.8 q9, q8 +@ CHECK: vzip.16 q9, q8 @ encoding: [0xe0,0x21,0xf6,0xf3] + vzip.16 q9, q8 +@ CHECK: vzip.32 q9, q8 @ encoding: [0xe0,0x21,0xfa,0xf3] + vzip.32 q9, q8 diff --git a/test/MC/ARM/neon-sub-encoding.s b/test/MC/ARM/neon-sub-encoding.s new file mode 100644 index 0000000..241a01f --- /dev/null +++ b/test/MC/ARM/neon-sub-encoding.s @@ -0,0 +1,108 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s + +@ CHECK: vsub.i8 d16, d17, d16 @ encoding: [0xa0,0x08,0x41,0xf3] + vsub.i8 d16, d17, d16 +@ CHECK: vsub.i16 d16, d17, d16 @ encoding: [0xa0,0x08,0x51,0xf3] + vsub.i16 d16, d17, d16 +@ CHECK: vsub.i32 d16, d17, d16 @ encoding: [0xa0,0x08,0x61,0xf3] + vsub.i32 d16, d17, d16 +@ CHECK: vsub.i64 d16, d17, d16 @ encoding: [0xa0,0x08,0x71,0xf3] + vsub.i64 d16, d17, d16 +@ CHECK: vsub.f32 d16, d16, d17 @ encoding: [0xa1,0x0d,0x60,0xf2] + vsub.f32 d16, d16, d17 +@ CHECK: vsub.i8 q8, q8, q9 @ encoding: [0xe2,0x08,0x40,0xf3] + vsub.i8 q8, q8, q9 +@ CHECK: vsub.i16 q8, q8, q9 @ encoding: [0xe2,0x08,0x50,0xf3] + vsub.i16 q8, q8, q9 +@ CHECK: vsub.i32 q8, q8, q9 @ encoding: [0xe2,0x08,0x60,0xf3] + vsub.i32 q8, q8, q9 +@ CHECK: vsub.i64 q8, q8, q9 @ encoding: [0xe2,0x08,0x70,0xf3] + vsub.i64 q8, q8, q9 +@ CHECK: vsub.f32 q8, q8, q9 @ encoding: [0xe2,0x0d,0x60,0xf2] + vsub.f32 q8, q8, q9 +@ CHECK: vsubl.s8 q8, d17, d16 @ encoding: [0xa0,0x02,0xc1,0xf2] + vsubl.s8 q8, d17, d16 +@ CHECK: vsubl.s16 q8, d17, d16 @ encoding: [0xa0,0x02,0xd1,0xf2] + vsubl.s16 q8, d17, d16 +@ CHECK: vsubl.s32 q8, d17, d16 @ encoding: [0xa0,0x02,0xe1,0xf2] + vsubl.s32 q8, d17, d16 +@ CHECK: vsubl.u8 q8, d17, d16 @ encoding: [0xa0,0x02,0xc1,0xf3] + vsubl.u8 q8, d17, d16 +@ CHECK: vsubl.u16 q8, d17, d16 @ encoding: [0xa0,0x02,0xd1,0xf3] + vsubl.u16 q8, d17, d16 +@ CHECK: vsubl.u32 q8, d17, d16 @ encoding: [0xa0,0x02,0xe1,0xf3] + vsubl.u32 q8, d17, d16 +@ CHECK: vsubw.s8 q8, q8, d18 @ encoding: [0xa2,0x03,0xc0,0xf2] + vsubw.s8 q8, q8, d18 +@ CHECK: vsubw.s16 q8, q8, d18 @ encoding: [0xa2,0x03,0xd0,0xf2] + vsubw.s16 q8, q8, d18 +@ CHECK: vsubw.s32 q8, q8, d18 @ encoding: [0xa2,0x03,0xe0,0xf2] + vsubw.s32 q8, q8, d18 +@ CHECK: vsubw.u8 q8, q8, d18 @ encoding: [0xa2,0x03,0xc0,0xf3] + vsubw.u8 q8, q8, d18 +@ CHECK: vsubw.u16 q8, q8, d18 @ encoding: [0xa2,0x03,0xd0,0xf3] + vsubw.u16 q8, q8, d18 +@ CHECK: vsubw.u32 q8, q8, d18 @ encoding: [0xa2,0x03,0xe0,0xf3] + vsubw.u32 q8, q8, d18 +@ CHECK: vhsub.s8 d16, d16, d17 @ encoding: [0xa1,0x02,0x40,0xf2] + vhsub.s8 d16, d16, d17 +@ CHECK: vhsub.s16 d16, d16, d17 @ encoding: [0xa1,0x02,0x50,0xf2] + vhsub.s16 d16, d16, d17 +@ CHECK: vhsub.s32 d16, d16, d17 @ encoding: [0xa1,0x02,0x60,0xf2] + vhsub.s32 d16, d16, d17 +@ CHECK: vhsub.u8 d16, d16, d17 @ encoding: [0xa1,0x02,0x40,0xf3] + vhsub.u8 d16, d16, d17 +@ CHECK: vhsub.u16 d16, d16, d17 @ encoding: [0xa1,0x02,0x50,0xf3] + vhsub.u16 d16, d16, d17 +@ CHECK: vhsub.u32 d16, d16, d17 @ encoding: [0xa1,0x02,0x60,0xf3] + vhsub.u32 d16, d16, d17 +@ CHECK: vhsub.s8 q8, q8, q9 @ encoding: [0xe2,0x02,0x40,0xf2] + vhsub.s8 q8, q8, q9 +@ CHECK: vhsub.s16 q8, q8, q9 @ encoding: [0xe2,0x02,0x50,0xf2] + vhsub.s16 q8, q8, q9 +@ CHECK: vhsub.s32 q8, q8, q9 @ encoding: [0xe2,0x02,0x60,0xf2] + vhsub.s32 q8, q8, q9 +@ CHECK: vqsub.s8 d16, d16, d17 @ encoding: [0xb1,0x02,0x40,0xf2] + vqsub.s8 d16, d16, d17 +@ CHECK: vqsub.s16 d16, d16, d17 @ encoding: [0xb1,0x02,0x50,0xf2] + vqsub.s16 d16, d16, d17 +@ CHECK: vqsub.s32 d16, d16, d17 @ encoding: [0xb1,0x02,0x60,0xf2] + vqsub.s32 d16, d16, d17 +@ CHECK: vqsub.s64 d16, d16, d17 @ encoding: [0xb1,0x02,0x70,0xf2] + vqsub.s64 d16, d16, d17 +@ CHECK: vqsub.u8 d16, d16, d17 @ encoding: [0xb1,0x02,0x40,0xf3] + vqsub.u8 d16, d16, d17 +@ CHECK: vqsub.u16 d16, d16, d17 @ encoding: [0xb1,0x02,0x50,0xf3] + vqsub.u16 d16, d16, d17 +@ CHECK: vqsub.u32 d16, d16, d17 @ encoding: [0xb1,0x02,0x60,0xf3] + vqsub.u32 d16, d16, d17 +@ CHECK: vqsub.u64 d16, d16, d17 @ encoding: [0xb1,0x02,0x70,0xf3] + vqsub.u64 d16, d16, d17 +@ CHECK: vqsub.s8 q8, q8, q9 @ encoding: [0xf2,0x02,0x40,0xf2] + vqsub.s8 q8, q8, q9 +@ CHECK: vqsub.s16 q8, q8, q9 @ encoding: [0xf2,0x02,0x50,0xf2] + vqsub.s16 q8, q8, q9 +@ CHECK: vqsub.s32 q8, q8, q9 @ encoding: [0xf2,0x02,0x60,0xf2] + vqsub.s32 q8, q8, q9 +@ CHECK: vqsub.s64 q8, q8, q9 @ encoding: [0xf2,0x02,0x70,0xf2] + vqsub.s64 q8, q8, q9 +@ CHECK: vqsub.u8 q8, q8, q9 @ encoding: [0xf2,0x02,0x40,0xf3] + vqsub.u8 q8, q8, q9 +@ CHECK: vqsub.u16 q8, q8, q9 @ encoding: [0xf2,0x02,0x50,0xf3] + vqsub.u16 q8, q8, q9 +@ CHECK: vqsub.u32 q8, q8, q9 @ encoding: [0xf2,0x02,0x60,0xf3] + vqsub.u32 q8, q8, q9 +@ CHECK: vqsub.u64 q8, q8, q9 @ encoding: [0xf2,0x02,0x70,0xf3] + vqsub.u64 q8, q8, q9 +@ CHECK: vsubhn.i16 d16, q8, q9 @ encoding: [0xa2,0x06,0xc0,0xf2] + vsubhn.i16 d16, q8, q9 +@ CHECK: vsubhn.i32 d16, q8, q9 @ encoding: [0xa2,0x06,0xd0,0xf2] + vsubhn.i32 d16, q8, q9 +@ CHECK: vsubhn.i64 d16, q8, q9 @ encoding: [0xa2,0x06,0xe0,0xf2] + vsubhn.i64 d16, q8, q9 +@ CHECK: vrsubhn.i16 d16, q8, q9 @ encoding: [0xa2,0x06,0xc0,0xf3] + vrsubhn.i16 d16, q8, q9 +@ CHECK: vrsubhn.i32 d16, q8, q9 @ encoding: [0xa2,0x06,0xd0,0xf3] + vrsubhn.i32 d16, q8, q9 +@ CHECK: vrsubhn.i64 d16, q8, q9 @ encoding: [0xa2,0x06,0xe0,0xf3] + vrsubhn.i64 d16, q8, q9 diff --git a/test/MC/ARM/neon-table-encoding.s b/test/MC/ARM/neon-table-encoding.s new file mode 100644 index 0000000..7bf47c7 --- /dev/null +++ b/test/MC/ARM/neon-table-encoding.s @@ -0,0 +1,19 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s +@ XFAIL: * + +@ CHECK: vtbl.8 d16, {d17}, d16 @ encoding: [0xa0,0x08,0xf1,0xf3] + vtbl.8 d16, {d17}, d16 +@ CHECK: vtbl.8 d16, {d16, d17}, d18 @ encoding: [0xa2,0x09,0xf0,0xf3] + vtbl.8 d16, {d16, d17}, d18 +@ CHECK: vtbl.8 d16, {d16, d17, d18}, d20 @ encoding: [0xa4,0x0a,0xf0,0xf3] + vtbl.8 d16, {d16, d17, d18}, d20 +@ CHECK: vtbl.8 d16, {d16, d17, d18, d19}, d20 @ encoding: [0xa4,0x0b,0xf0,0xf3] + vtbl.8 d16, {d16, d17, d18, d19}, d20 +@ CHECK: vtbx.8 d18, {d16}, d17 @ encoding: [0xe1,0x28,0xf0,0xf3] + vtbx.8 d18, {d16}, d17 +@ CHECK: vtbx.8 d19, {d16, d17}, d18 @ encoding: [0xe2,0x39,0xf0,0xf3] + vtbx.8 d19, {d16, d17}, d18 +@ CHECK: vtbx.8 d20, {d16, d17, d18}, d21 @ encoding: [0xe5,0x4a,0xf0,0xf3] + vtbx.8 d20, {d16, d17, d18}, d21 +@ CHECK: vtbx.8 d20, {d16, d17, d18, d19}, d21 @ encoding: [0xe5,0x4b,0xf0,0xf3] + vtbx.8 d20, {d16, d17, d18, d19}, d21 diff --git a/test/MC/ARM/neon-vld-encoding.s b/test/MC/ARM/neon-vld-encoding.s new file mode 100644 index 0000000..be55f47 --- /dev/null +++ b/test/MC/ARM/neon-vld-encoding.s @@ -0,0 +1,110 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple armv7-apple-darwin -show-encoding < %s | FileCheck %s +@ XFAIL: * + +@ CHECK: vld1.8 {d16}, [r0, :64] @ encoding: [0x1f,0x07,0x60,0xf4] + vld1.8 {d16}, [r0, :64] +@ CHECK: vld1.16 {d16}, [r0] @ encoding: [0x4f,0x07,0x60,0xf4] + vld1.16 {d16}, [r0] +@ CHECK: vld1.32 {d16}, [r0] @ encoding: [0x8f,0x07,0x60,0xf4] + vld1.32 {d16}, [r0] +@ CHECK: vld1.64 {d16}, [r0] @ encoding: [0xcf,0x07,0x60,0xf4] + vld1.64 {d16}, [r0] +@ CHECK: vld1.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x0a,0x60,0xf4] + vld1.8 {d16, d17}, [r0, :64] +@ CHECK: vld1.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x0a,0x60,0xf4] + vld1.16 {d16, d17}, [r0, :128] +@ CHECK: vld1.32 {d16, d17}, [r0] @ encoding: [0x8f,0x0a,0x60,0xf4] + vld1.32 {d16, d17}, [r0] +@ CHECK: vld1.64 {d16, d17}, [r0] @ encoding: [0xcf,0x0a,0x60,0xf4] + vld1.64 {d16, d17}, [r0] + +@ CHECK: vld2.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x08,0x60,0xf4] + vld2.8 {d16, d17}, [r0, :64] +@ CHECK: vld2.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x08,0x60,0xf4] + vld2.16 {d16, d17}, [r0, :128] +@ CHECK: vld2.32 {d16, d17}, [r0] @ encoding: [0x8f,0x08,0x60,0xf4] + vld2.32 {d16, d17}, [r0] +@ CHECK: vld2.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x03,0x60,0xf4] + vld2.8 {d16, d17, d18, d19}, [r0, :64] +@ CHECK: vld2.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x03,0x60,0xf4] + vld2.16 {d16, d17, d18, d19}, [r0, :128] +@ CHECK: vld2.32 {d16, d17, d18, d19}, [r0, :256] @ encoding: [0xbf,0x03,0x60,0xf4] + vld2.32 {d16, d17, d18, d19}, [r0, :256] + +@ CHECK: vld3.8 {d16, d17, d18}, [r0, :64] @ encoding: [0x1f,0x04,0x60,0xf4] + vld3.8 {d16, d17, d18}, [r0, :64] +@ CHECK: vld3.16 {d16, d17, d18}, [r0] @ encoding: [0x4f,0x04,0x60,0xf4] + vld3.16 {d16, d17, d18}, [r0] +@ CHECK: vld3.32 {d16, d17, d18}, [r0] @ encoding: [0x8f,0x04,0x60,0xf4] + vld3.32 {d16, d17, d18}, [r0] +@ CHECK: vld3.8 {d16, d18, d20}, [r0, :64]! @ encoding: [0x1d,0x05,0x60,0xf4] + vld3.8 {d16, d18, d20}, [r0, :64]! +@ CHECK: vld3.8 {d17, d19, d21}, [r0, :64]! @ encoding: [0x1d,0x15,0x60,0xf4] + vld3.8 {d17, d19, d21}, [r0, :64]! +@ CHECK: vld3.16 {d16, d18, d20}, [r0]! @ encoding: [0x4d,0x05,0x60,0xf4] + vld3.16 {d16, d18, d20}, [r0]! +@ CHECK: vld3.16 {d17, d19, d21}, [r0]! @ encoding: [0x4d,0x15,0x60,0xf4] + vld3.16 {d17, d19, d21}, [r0]! +@ CHECK: vld3.32 {d16, d18, d20}, [r0]! @ encoding: [0x8d,0x05,0x60,0xf4] + vld3.32 {d16, d18, d20}, [r0]! +@ CHECK: vld3.32 {d17, d19, d21}, [r0]! @ encoding: [0x8d,0x15,0x60,0xf4] + vld3.32 {d17, d19, d21}, [r0]! + +@ CHECK: vld4.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x00,0x60,0xf4] + vld4.8 {d16, d17, d18, d19}, [r0, :64] +@ CHECK: vld4.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x00,0x60,0xf4] + vld4.16 {d16, d17, d18, d19}, [r0, :128] +@ CHECK: vld4.32 {d16, d17, d18, d19}, [r0, :256] @ encoding: [0xbf,0x00,0x60,0xf4] + vld4.32 {d16, d17, d18, d19}, [r0, :256] +@ CHECK: vld4.8 {d16, d18, d20, d22}, [r0, :256]! @ encoding: [0x3d,0x01,0x60,0xf4] + vld4.8 {d16, d18, d20, d22}, [r0, :256]! +@ CHECK: vld4.8 {d17, d19, d21, d23}, [r0, :256]! @ encoding: [0x3d,0x11,0x60,0xf4] + vld4.8 {d17, d19, d21, d23}, [r0, :256]! +@ CHECK: vld4.16 {d16, d18, d20, d22}, [r0]! @ encoding: [0x4d,0x01,0x60,0xf4] + vld4.16 {d16, d18, d20, d22}, [r0]! +@ CHECK: vld4.16 {d17, d19, d21, d23}, [r0]! @ encoding: [0x4d,0x11,0x60,0xf4] + vld4.16 {d17, d19, d21, d23}, [r0]! +@ CHECK: vld4.32 {d16, d18, d20, d22}, [r0]! @ encoding: [0x8d,0x01,0x60,0xf4] + vld4.32 {d16, d18, d20, d22}, [r0]! +@ CHECK: vld4.32 {d17, d19, d21, d23}, [r0]! @ encoding: [0x8d,0x11,0x60,0xf4] + vld4.32 {d17, d19, d21, d23}, [r0]! + +@ CHECK: vld1.8 {d16[3]}, [r0] @ encoding: [0x6f,0x00,0xe0,0xf4] + vld1.8 {d16[3]}, [r0] +@ CHECK: vld1.16 {d16[2]}, [r0, :16] @ encoding: [0x9f,0x04,0xe0,0xf4] + vld1.16 {d16[2]}, [r0, :16] +@ CHECK: vld1.32 {d16[1]}, [r0, :32] @ encoding: [0xbf,0x08,0xe0,0xf4] + vld1.32 {d16[1]}, [r0, :32] + +@ CHECK: vld2.8 {d16[1], d17[1]}, [r0, :16] @ encoding: [0x3f,0x01,0xe0,0xf4] + vld2.8 {d16[1], d17[1]}, [r0, :16] +@ CHECK: vld2.16 {d16[1], d17[1]}, [r0, :32] @ encoding: [0x5f,0x05,0xe0,0xf4] + vld2.16 {d16[1], d17[1]}, [r0, :32] +@ CHECK: vld2.32 {d16[1], d17[1]}, [r0] @ encoding: [0x8f,0x09,0xe0,0xf4] + vld2.32 {d16[1], d17[1]}, [r0] +@ CHECK: vld2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xe0,0xf4] + vld2.16 {d17[1], d19[1]}, [r0] +@ CHECK: vld2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xe0,0xf4] + vld2.32 {d17[0], d19[0]}, [r0, :64] + +@ CHECK: vld3.8 {d16[1], d17[1], d18[1]}, [r0] @ encoding: [0x2f,0x02,0xe0,0xf4] + vld3.8 {d16[1], d17[1], d18[1]}, [r0] +@ CHECK: vld3.16 {d16[1], d17[1], d18[1]}, [r0] @ encoding: [0x4f,0x06,0xe0,0xf4] + vld3.16 {d16[1], d17[1], d18[1]}, [r0] +@ CHECK: vld3.32 {d16[1], d17[1], d18[1]}, [r0] @ encoding: [0x8f,0x0a,0xe0,0xf4] + vld3.32 {d16[1], d17[1], d18[1]}, [r0] +@ CHECK: vld3.16 {d16[1], d18[1], d20[1]}, [r0] @ encoding: [0x6f,0x06,0xe0,0xf4] + vld3.16 {d16[1], d18[1], d20[1]}, [r0] +@ CHECK: vld3.32 {d17[1], d19[1], d21[1]}, [r0] @ encoding: [0xcf,0x1a,0xe0,0xf4] + vld3.32 {d17[1], d19[1], d21[1]}, [r0] + +@ CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] @ encoding: [0x3f,0x03,0xe0,0xf4] + vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] +@ CHECK: vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] @ encoding: [0x4f,0x07,0xe0,0xf4] + vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] +@ CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128] @ encoding: [0xaf,0x0b,0xe0,0xf4] + vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128] +@ CHECK: vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r0, :64] @ encoding: [0x7f,0x07,0xe0,0xf4] + vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r0, :64] +@ CHECK: vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] @ encoding: [0x4f,0x1b,0xe0,0xf4] + vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] diff --git a/test/MC/ARM/neon-vst-encoding.s b/test/MC/ARM/neon-vst-encoding.s new file mode 100644 index 0000000..c595aa2 --- /dev/null +++ b/test/MC/ARM/neon-vst-encoding.s @@ -0,0 +1,101 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple armv7-apple-darwin -show-encoding < %s | FileCheck %s +@ XFAIL: * + +@ CHECK: vst1.8 {d16}, [r0, :64] @ encoding: [0x1f,0x07,0x40,0xf4] + vst1.8 {d16}, [r0, :64] +@ CHECK: vst1.16 {d16}, [r0] @ encoding: [0x4f,0x07,0x40,0xf4] + vst1.16 {d16}, [r0] +@ CHECK: vst1.32 {d16}, [r0] @ encoding: [0x8f,0x07,0x40,0xf4] + vst1.32 {d16}, [r0] +@ CHECK: vst1.64 {d16}, [r0] @ encoding: [0xcf,0x07,0x40,0xf4] + vst1.64 {d16}, [r0] +@ CHECK: vst1.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x0a,0x40,0xf4] + vst1.8 {d16, d17}, [r0, :64] +@ CHECK: vst1.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x0a,0x40,0xf4] + vst1.16 {d16, d17}, [r0, :128] +@ CHECK: vst1.32 {d16, d17}, [r0] @ encoding: [0x8f,0x0a,0x40,0xf4] + vst1.32 {d16, d17}, [r0] +@ CHECK: vst1.64 {d16, d17}, [r0] @ encoding: [0xcf,0x0a,0x40,0xf4] + vst1.64 {d16, d17}, [r0] + +@ CHECK: vst2.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x08,0x40,0xf4] + vst2.8 {d16, d17}, [r0, :64] +@ CHECK: vst2.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x08,0x40,0xf4] + vst2.16 {d16, d17}, [r0, :128] +@ CHECK: vst2.32 {d16, d17}, [r0] @ encoding: [0x8f,0x08,0x40,0xf4] + vst2.32 {d16, d17}, [r0] +@ CHECK: vst2.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x03,0x40,0xf4] + vst2.8 {d16, d17, d18, d19}, [r0, :64] +@ CHECK: vst2.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x03,0x40,0xf4] + vst2.16 {d16, d17, d18, d19}, [r0, :128] +@ CHECK: vst2.32 {d16, d17, d18, d19}, [r0, :256] @ encoding: [0xbf,0x03,0x40,0xf4] + vst2.32 {d16, d17, d18, d19}, [r0, :256] + +@ CHECK: vst3.8 {d16, d17, d18}, [r0, :64] @ encoding: [0x1f,0x04,0x40,0xf4] + vst3.8 {d16, d17, d18}, [r0, :64] +@ CHECK: vst3.16 {d16, d17, d18}, [r0] @ encoding: [0x4f,0x04,0x40,0xf4] + vst3.16 {d16, d17, d18}, [r0] +@ CHECK: vst3.32 {d16, d17, d18}, [r0] @ encoding: [0x8f,0x04,0x40,0xf4] + vst3.32 {d16, d17, d18}, [r0] +@ CHECK: vst3.8 {d16, d18, d20}, [r0, :64]! @ encoding: [0x1d,0x05,0x40,0xf4] + vst3.8 {d16, d18, d20}, [r0, :64]! +@ CHECK: vst3.8 {d17, d19, d21}, [r0, :64]! @ encoding: [0x1d,0x15,0x40,0xf4] + vst3.8 {d17, d19, d21}, [r0, :64]! +@ CHECK: vst3.16 {d16, d18, d20}, [r0]! @ encoding: [0x4d,0x05,0x40,0xf4] + vst3.16 {d16, d18, d20}, [r0]! +@ CHECK: vst3.16 {d17, d19, d21}, [r0]! @ encoding: [0x4d,0x15,0x40,0xf4] + vst3.16 {d17, d19, d21}, [r0]! +@ CHECK: vst3.32 {d16, d18, d20}, [r0]! @ encoding: [0x8d,0x05,0x40,0xf4] + vst3.32 {d16, d18, d20}, [r0]! +@ CHECK: vst3.32 {d17, d19, d21}, [r0]! @ encoding: [0x8d,0x15,0x40,0xf4] + vst3.32 {d17, d19, d21}, [r0]! + +@ CHECK: vst4.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x00,0x40,0xf4] + vst4.8 {d16, d17, d18, d19}, [r0, :64] +@ CHECK: vst4.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x00,0x40,0xf4] + vst4.16 {d16, d17, d18, d19}, [r0, :128] +@ CHECK: vst4.8 {d16, d18, d20, d22}, [r0, :256]! @ encoding: [0x3d,0x01,0x40,0xf4] + vst4.8 {d16, d18, d20, d22}, [r0, :256]! +@ CHECK: vst4.8 {d17, d19, d21, d23}, [r0, :256]! @ encoding: [0x3d,0x11,0x40,0xf4] + vst4.8 {d17, d19, d21, d23}, [r0, :256]! +@ CHECK: vst4.16 {d16, d18, d20, d22}, [r0]! @ encoding: [0x4d,0x01,0x40,0xf4] + vst4.16 {d16, d18, d20, d22}, [r0]! +@ CHECK: vst4.16 {d17, d19, d21, d23}, [r0]! @ encoding: [0x4d,0x11,0x40,0xf4] + vst4.16 {d17, d19, d21, d23}, [r0]! +@ CHECK: vst4.32 {d16, d18, d20, d22}, [r0]! @ encoding: [0x8d,0x01,0x40,0xf4] + vst4.32 {d16, d18, d20, d22}, [r0]! +@ CHECK: vst4.32 {d17, d19, d21, d23}, [r0]! @ encoding: [0x8d,0x11,0x40,0xf4] + vst4.32 {d17, d19, d21, d23}, [r0]! + +@ CHECK: vst2.8 {d16[1], d17[1]}, [r0, :16] @ encoding: [0x3f,0x01,0xc0,0xf4] + vst2.8 {d16[1], d17[1]}, [r0, :16] +@ CHECK: vst2.16 {d16[1], d17[1]}, [r0, :32] @ encoding: [0x5f,0x05,0xc0,0xf4] + vst2.16 {d16[1], d17[1]}, [r0, :32] +@ CHECK: vst2.32 {d16[1], d17[1]}, [r0] @ encoding: [0x8f,0x09,0xc0,0xf4] + vst2.32 {d16[1], d17[1]}, [r0] +@ CHECK: vst2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xc0,0xf4] + vst2.16 {d17[1], d19[1]}, [r0] +@ CHECK: vst2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xc0,0xf4] + vst2.32 {d17[0], d19[0]}, [r0, :64] + +@ CHECK: vst3.8 {d16[1], d17[1], d18[1]}, [r0] @ encoding: [0x2f,0x02,0xc0,0xf4] + vst3.8 {d16[1], d17[1], d18[1]}, [r0] +@ CHECK: vst3.16 {d16[1], d17[1], d18[1]}, [r0] @ encoding: [0x4f,0x06,0xc0,0xf4] + vst3.16 {d16[1], d17[1], d18[1]}, [r0] +@ CHECK: vst3.32 {d16[1], d17[1], d18[1]}, [r0] @ encoding: [0x8f,0x0a,0xc0,0xf4] + vst3.32 {d16[1], d17[1], d18[1]}, [r0] +@ CHECK: vst3.16 {d17[2], d19[2], d21[2]}, [r0] @ encoding: [0xaf,0x16,0xc0,0xf4] + vst3.16 {d17[2], d19[2], d21[2]}, [r0] +@ CHECK: vst3.32 {d16[0], d18[0], d20[0]}, [r0] @ encoding: [0x4f,0x0a,0xc0,0xf4] + vst3.32 {d16[0], d18[0], d20[0]}, [r0] + +@ CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] @ encoding: [0x3f,0x03,0xc0,0xf4] + vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] +@ CHECK: vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] @ encoding: [0x4f,0x07,0xc0,0xf4] + vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] +@ CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128] @ encoding: [0xaf,0x0b,0xc0,0xf4] + vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128] +@ CHECK: vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0, :64] @ encoding: [0xff,0x17,0xc0,0xf4] + vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0, :64] +@ CHECK: vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] @ encoding: [0x4f,0x1b,0xc0,0xf4] + vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] diff --git a/test/MC/ARM/neont2-abs-encoding.s b/test/MC/ARM/neont2-abs-encoding.s new file mode 100644 index 0000000..5c8bc33 --- /dev/null +++ b/test/MC/ARM/neont2-abs-encoding.s @@ -0,0 +1,33 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s + +.code 16 + +@ CHECK: vabs.s8 d16, d16 @ encoding: [0xf1,0xff,0x20,0x03] + vabs.s8 d16, d16 +@ CHECK: vabs.s16 d16, d16 @ encoding: [0xf5,0xff,0x20,0x03] + vabs.s16 d16, d16 +@ CHECK: vabs.s32 d16, d16 @ encoding: [0xf9,0xff,0x20,0x03] + vabs.s32 d16, d16 +@ CHECK: vabs.f32 d16, d16 @ encoding: [0xf9,0xff,0x20,0x07] + vabs.f32 d16, d16 +@ CHECK: vabs.s8 q8, q8 @ encoding: [0xf1,0xff,0x60,0x03] + vabs.s8 q8, q8 +@ CHECK: vabs.s16 q8, q8 @ encoding: [0xf5,0xff,0x60,0x03] + vabs.s16 q8, q8 +@ CHECK: vabs.s32 q8, q8 @ encoding: [0xf9,0xff,0x60,0x03] + vabs.s32 q8, q8 +@ CHECK: vabs.f32 q8, q8 @ encoding: [0xf9,0xff,0x60,0x07] + vabs.f32 q8, q8 + +@ CHECK: vqabs.s8 d16, d16 @ encoding: [0xf0,0xff,0x20,0x07] + vqabs.s8 d16, d16 +@ CHECK: vqabs.s16 d16, d16 @ encoding: [0xf4,0xff,0x20,0x07] + vqabs.s16 d16, d16 +@ CHECK: vqabs.s32 d16, d16 @ encoding: [0xf8,0xff,0x20,0x07] + vqabs.s32 d16, d16 +@ CHECK: vqabs.s8 q8, q8 @ encoding: [0xf0,0xff,0x60,0x07] + vqabs.s8 q8, q8 +@ CHECK: vqabs.s16 q8, q8 @ encoding: [0xf4,0xff,0x60,0x07] + vqabs.s16 q8, q8 +@ CHECK: vqabs.s32 q8, q8 @ encoding: [0xf8,0xff,0x60,0x07] + vqabs.s32 q8, q8 diff --git a/test/MC/ARM/neont2-absdiff-encoding.s b/test/MC/ARM/neont2-absdiff-encoding.s new file mode 100644 index 0000000..2096357 --- /dev/null +++ b/test/MC/ARM/neont2-absdiff-encoding.s @@ -0,0 +1,86 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s +@ XFAIL: * +@ NOTE: This currently fails because the ASM parser doesn't parse vabal. + +.code 16 + +@ CHECK: vabd.s8 d16, d16, d17 @ encoding: [0xa1,0x07,0x40,0xef] + vabd.s8 d16, d16, d17 +@ CHECK: vabd.s16 d16, d16, d17 @ encoding: [0xa1,0x07,0x50,0xef] + vabd.s16 d16, d16, d17 +@ CHECK: vabd.s32 d16, d16, d17 @ encoding: [0xa1,0x07,0x60,0xef] + vabd.s32 d16, d16, d17 +@ CHECK: vabd.u8 d16, d16, d17 @ encoding: [0xa1,0x07,0x40,0xff] + vabd.u8 d16, d16, d17 +@ CHECK: vabd.u16 d16, d16, d17 @ encoding: [0xa1,0x07,0x50,0xff] + vabd.u16 d16, d16, d17 + @ CHECK: vabd.u32 d16, d16, d17 @ encoding: [0xa1,0x07,0x60,0xff] + vabd.u32 d16, d16, d17 +@ CHECK: vabd.f32 d16, d16, d17 @ encoding: [0xa1,0x0d,0x60,0xff] + vabd.f32 d16, d16, d17 +@ CHECK: vabd.s8 q8, q8, q9 @ encoding: [0xe2,0x07,0x40,0xef] + vabd.s8 q8, q8, q9 +@ CHECK: vabd.s16 q8, q8, q9 @ encoding: [0xe2,0x07,0x50,0xef] + vabd.s16 q8, q8, q9 +@ CHECK: vabd.s32 q8, q8, q9 @ encoding: [0xe2,0x07,0x60,0xef] + vabd.s32 q8, q8, q9 +@ CHECK: vabd.u8 q8, q8, q9 @ encoding: [0xe2,0x07,0x40,0xff] + vabd.u8 q8, q8, q9 +@ CHECK: vabd.u16 q8, q8, q9 @ encoding: [0xe2,0x07,0x50,0xff] + vabd.u16 q8, q8, q9 +@ CHECK: vabd.u32 q8, q8, q9 @ encoding: [0xe2,0x07,0x60,0xff] + vabd.u32 q8, q8, q9 +@ CHECK: vabd.f32 q8, q8, q9 @ encoding: [0xe2,0x0d,0x60,0xff] + vabd.f32 q8, q8, q9 + +@ CHECK: vabdl.s8 q8, d16, d17 @ encoding: [0xa1,0x07,0xc0,0xef] + vabdl.s8 q8, d16, d17 +@ CHECK: vabdl.s16 q8, d16, d17 @ encoding: [0xa1,0x07,0xd0,0xef] + vabdl.s16 q8, d16, d17 +@ CHECK: vabdl.s32 q8, d16, d17 @ encoding: [0xa1,0x07,0xe0,0xef] + vabdl.s32 q8, d16, d17 +@ CHECK: vabdl.u8 q8, d16, d17 @ encoding: [0xa1,0x07,0xc0,0xff] + vabdl.u8 q8, d16, d17 +@ CHECK: vabdl.u16 q8, d16, d17 @ encoding: [0xa1,0x07,0xd0,0xff] + vabdl.u16 q8, d16, d17 +@ CHECK: vabdl.u32 q8, d16, d17 @ encoding: [0xa1,0x07,0xe0,0xff] + vabdl.u32 q8, d16, d17 + +@ CHECK: vaba.s8 d16, d18, d17 @ encoding: [0xb1,0x07,0x42,0xef] + vaba.s8 d16, d18, d17 +@ CHECK: vaba.s16 d16, d18, d17 @ encoding: [0xb1,0x07,0x52,0xef] + vaba.s16 d16, d18, d17 +@ CHECK: vaba.s32 d16, d18, d17 @ encoding: [0xb1,0x07,0x62,0xef] + vaba.s32 d16, d18, d17 +@ CHECK: vaba.u8 d16, d18, d17 @ encoding: [0xb1,0x07,0x42,0xff] + vaba.u8 d16, d18, d17 +@ CHECK: vaba.u16 d16, d18, d17 @ encoding: [0xb1,0x07,0x52,0xff] + vaba.u16 d16, d18, d17 +@ CHECK: vaba.u32 d16, d18, d17 @ encoding: [0xb1,0x07,0x62,0xff] + vaba.u32 d16, d18, d17 +@ CHECK: vaba.s8 q9, q8, q10 @ encoding: [0xf4,0x27,0x40,0xef] + vaba.s8 q9, q8, q10 +@ CHECK: vaba.s16 q9, q8, q10 @ encoding: [0xf4,0x27,0x50,0xef] + vaba.s16 q9, q8, q10 +@ CHECK: vaba.s32 q9, q8, q10 @ encoding: [0xf4,0x27,0x60,0xef] + vaba.s32 q9, q8, q10 +@ CHECK: vaba.u8 q9, q8, q10 @ encoding: [0xf4,0x27,0x40,0xff] + vaba.u8 q9, q8, q10 +@ CHECK: vaba.u16 q9, q8, q10 @ encoding: [0xf4,0x27,0x50,0xff] + vaba.u16 q9, q8, q10 +@ CHECK: vaba.u32 q9, q8, q10 @ encoding: [0xf4,0x27,0x60,0xff] + vaba.u32 q9, q8, q10 + +@ CHECK: vabal.s8 q8, d19, d18 @ encoding: [0xa2,0x05,0xc3,0xef] + vabal.s8 q8, d19, d18 +@ CHECK: vabal.s16 q8, d19, d18 @ encoding: [0xa2,0x05,0xd3,0xef] + vabal.s16 q8, d19, d18 +@ CHECK: vabal.s32 q8, d19, d18 @ encoding: [0xa2,0x05,0xe3,0xef] + vabal.s32 q8, d19, d18 +@ CHECK: vabal.u8 q8, d19, d18 @ encoding: [0xa2,0x05,0xc3,0xff] + vabal.u8 q8, d19, d18 +@ CHECK: vabal.u16 q8, d19, d18 @ encoding: [0xa2,0x05,0xd3,0xff] + vabal.u16 q8, d19, d18 +@ CHECK: vabal.u32 q8, d19, d18 @ encoding: [0xa2,0x05,0xe3,0xff] + vabal.u32 q8, d19, d18 + diff --git a/test/MC/ARM/neont2-add-encoding.s b/test/MC/ARM/neont2-add-encoding.s new file mode 100644 index 0000000..c384d76 --- /dev/null +++ b/test/MC/ARM/neont2-add-encoding.s @@ -0,0 +1,138 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s + +.code 16 + +@ CHECK: vadd.i8 d16, d17, d16 @ encoding: [0x41,0xef,0xa0,0x08] + vadd.i8 d16, d17, d16 +@ CHECK: vadd.i16 d16, d17, d16 @ encoding: [0x51,0xef,0xa0,0x08] + vadd.i16 d16, d17, d16 +@ CHECK: vadd.i64 d16, d17, d16 @ encoding: [0x71,0xef,0xa0,0x08] + vadd.i64 d16, d17, d16 +@ CHECK: vadd.i32 d16, d17, d16 @ encoding: [0x61,0xef,0xa0,0x08] + vadd.i32 d16, d17, d16 +@ CHECK: vadd.f32 d16, d16, d17 @ encoding: [0x40,0xef,0xa1,0x0d] + vadd.f32 d16, d16, d17 +@ CHECK: vadd.f32 q8, q8, q9 @ encoding: [0x40,0xef,0xe2,0x0d] + vadd.f32 q8, q8, q9 + +@ CHECK: vaddl.s8 q8, d17, d16 @ encoding: [0xc1,0xef,0xa0,0x00] + vaddl.s8 q8, d17, d16 +@ CHECK: vaddl.s16 q8, d17, d16 @ encoding: [0xd1,0xef,0xa0,0x00] + vaddl.s16 q8, d17, d16 +@ CHECK: vaddl.s32 q8, d17, d16 @ encoding: [0xe1,0xef,0xa0,0x00] + vaddl.s32 q8, d17, d16 +@ CHECK: vaddl.u8 q8, d17, d16 @ encoding: [0xc1,0xff,0xa0,0x00] + vaddl.u8 q8, d17, d16 +@ CHECK: vaddl.u16 q8, d17, d16 @ encoding: [0xd1,0xff,0xa0,0x00] + vaddl.u16 q8, d17, d16 +@ CHECK: vaddl.u32 q8, d17, d16 @ encoding: [0xe1,0xff,0xa0,0x00] + vaddl.u32 q8, d17, d16 + +@ CHECK: vaddw.s8 q8, q8, d18 @ encoding: [0xc0,0xef,0xa2,0x01] + vaddw.s8 q8, q8, d18 +@ CHECK: vaddw.s16 q8, q8, d18 @ encoding: [0xd0,0xef,0xa2,0x01] + vaddw.s16 q8, q8, d18 +@ CHECK: vaddw.s32 q8, q8, d18 @ encoding: [0xe0,0xef,0xa2,0x01] + vaddw.s32 q8, q8, d18 +@ CHECK: vaddw.u8 q8, q8, d18 @ encoding: [0xc0,0xff,0xa2,0x01] + vaddw.u8 q8, q8, d18 +@ CHECK: vaddw.u16 q8, q8, d18 @ encoding: [0xd0,0xff,0xa2,0x01] + vaddw.u16 q8, q8, d18 +@ CHECK: vaddw.u32 q8, q8, d18 @ encoding: [0xe0,0xff,0xa2,0x01] + vaddw.u32 q8, q8, d18 + +@ CHECK: vhadd.s8 d16, d16, d17 @ encoding: [0x40,0xef,0xa1,0x00] + vhadd.s8 d16, d16, d17 +@ CHECK: vhadd.s16 d16, d16, d17 @ encoding: [0x50,0xef,0xa1,0x00] + vhadd.s16 d16, d16, d17 +@ CHECK: vhadd.s32 d16, d16, d17 @ encoding: [0x60,0xef,0xa1,0x00] + vhadd.s32 d16, d16, d17 +@ CHECK: vhadd.u8 d16, d16, d17 @ encoding: [0x40,0xff,0xa1,0x00] + vhadd.u8 d16, d16, d17 +@ CHECK: vhadd.u16 d16, d16, d17 @ encoding: [0x50,0xff,0xa1,0x00] + vhadd.u16 d16, d16, d17 +@ CHECK: vhadd.u32 d16, d16, d17 @ encoding: [0x60,0xff,0xa1,0x00] + vhadd.u32 d16, d16, d17 +@ CHECK: vhadd.s8 q8, q8, q9 @ encoding: [0x40,0xef,0xe2,0x00] + vhadd.s8 q8, q8, q9 +@ CHECK: vhadd.s16 q8, q8, q9 @ encoding: [0x50,0xef,0xe2,0x00] + vhadd.s16 q8, q8, q9 +@ CHECK: vhadd.s32 q8, q8, q9 @ encoding: [0x60,0xef,0xe2,0x00] + vhadd.s32 q8, q8, q9 + @ CHECK: vhadd.u8 q8, q8, q9 @ encoding: [0x40,0xff,0xe2,0x00] + vhadd.u8 q8, q8, q9 +@ CHECK: vhadd.u16 q8, q8, q9 @ encoding: [0x50,0xff,0xe2,0x00] + vhadd.u16 q8, q8, q9 +@ CHECK: vhadd.u32 q8, q8, q9 @ encoding: [0x60,0xff,0xe2,0x00] + vhadd.u32 q8, q8, q9 + +@ CHECK: vrhadd.s8 d16, d16, d17 @ encoding: [0x40,0xef,0xa1,0x01] + vrhadd.s8 d16, d16, d17 +@ CHECK: vrhadd.s16 d16, d16, d17 @ encoding: [0x50,0xef,0xa1,0x01] + vrhadd.s16 d16, d16, d17 +@ CHECK: vrhadd.s32 d16, d16, d17 @ encoding: [0x60,0xef,0xa1,0x01] + vrhadd.s32 d16, d16, d17 +@ CHECK: vrhadd.u8 d16, d16, d17 @ encoding: [0x40,0xff,0xa1,0x01] + vrhadd.u8 d16, d16, d17 +@ CHECK: vrhadd.u16 d16, d16, d17 @ encoding: [0x50,0xff,0xa1,0x01] + vrhadd.u16 d16, d16, d17 +@ CHECK: vrhadd.u32 d16, d16, d17 @ encoding: [0x60,0xff,0xa1,0x01] + vrhadd.u32 d16, d16, d17 +@ CHECK: vrhadd.s8 q8, q8, q9 @ encoding: [0x40,0xef,0xe2,0x01] + vrhadd.s8 q8, q8, q9 +@ CHECK: vrhadd.s16 q8, q8, q9 @ encoding: [0x50,0xef,0xe2,0x01] + vrhadd.s16 q8, q8, q9 +@ CHECK: vrhadd.s32 q8, q8, q9 @ encoding: [0x60,0xef,0xe2,0x01] + vrhadd.s32 q8, q8, q9 +@ CHECK: vrhadd.u8 q8, q8, q9 @ encoding: [0x40,0xff,0xe2,0x01] + vrhadd.u8 q8, q8, q9 +@ CHECK: vrhadd.u16 q8, q8, q9 @ encoding: [0x50,0xff,0xe2,0x01] + vrhadd.u16 q8, q8, q9 +@ CHECK: vrhadd.u32 q8, q8, q9 @ encoding: [0x60,0xff,0xe2,0x01] + vrhadd.u32 q8, q8, q9 + +@ CHECK: vqadd.s8 d16, d16, d17 @ encoding: [0x40,0xef,0xb1,0x00] + vqadd.s8 d16, d16, d17 +@ CHECK: vqadd.s16 d16, d16, d17 @ encoding: [0x50,0xef,0xb1,0x00] + vqadd.s16 d16, d16, d17 +@ CHECK: vqadd.s32 d16, d16, d17 @ encoding: [0x60,0xef,0xb1,0x00] + vqadd.s32 d16, d16, d17 +@ CHECK: vqadd.s64 d16, d16, d17 @ encoding: [0x70,0xef,0xb1,0x00] + vqadd.s64 d16, d16, d17 +@ CHECK: vqadd.u8 d16, d16, d17 @ encoding: [0x40,0xff,0xb1,0x00] + vqadd.u8 d16, d16, d17 +@ CHECK: vqadd.u16 d16, d16, d17 @ encoding: [0x50,0xff,0xb1,0x00] + vqadd.u16 d16, d16, d17 +@ CHECK: vqadd.u32 d16, d16, d17 @ encoding: [0x60,0xff,0xb1,0x00] + vqadd.u32 d16, d16, d17 +@ CHECK: vqadd.u64 d16, d16, d17 @ encoding: [0x70,0xff,0xb1,0x00] + vqadd.u64 d16, d16, d17 +@ CHECK: vqadd.s8 q8, q8, q9 @ encoding: [0x40,0xef,0xf2,0x00] + vqadd.s8 q8, q8, q9 +@ CHECK: vqadd.s16 q8, q8, q9 @ encoding: [0x50,0xef,0xf2,0x00] + vqadd.s16 q8, q8, q9 +@ CHECK: vqadd.s32 q8, q8, q9 @ encoding: [0x60,0xef,0xf2,0x00] + vqadd.s32 q8, q8, q9 +@ CHECK: vqadd.s64 q8, q8, q9 @ encoding: [0x70,0xef,0xf2,0x00] + vqadd.s64 q8, q8, q9 +@ CHECK: vqadd.u8 q8, q8, q9 @ encoding: [0x40,0xff,0xf2,0x00] + vqadd.u8 q8, q8, q9 +@ CHECK: vqadd.u16 q8, q8, q9 @ encoding: [0x50,0xff,0xf2,0x00] + vqadd.u16 q8, q8, q9 +@ CHECK: vqadd.u32 q8, q8, q9 @ encoding: [0x60,0xff,0xf2,0x00] + vqadd.u32 q8, q8, q9 +@ CHECK: vqadd.u64 q8, q8, q9 @ encoding: [0x70,0xff,0xf2,0x00] + vqadd.u64 q8, q8, q9 + +@ CHECK: vaddhn.i16 d16, q8, q9 @ encoding: [0xc0,0xef,0xa2,0x04] + vaddhn.i16 d16, q8, q9 +@ CHECK: vaddhn.i32 d16, q8, q9 @ encoding: [0xd0,0xef,0xa2,0x04] + vaddhn.i32 d16, q8, q9 +@ CHECK: vaddhn.i64 d16, q8, q9 @ encoding: [0xe0,0xef,0xa2,0x04] + vaddhn.i64 d16, q8, q9 +@ CHECK: vraddhn.i16 d16, q8, q9 @ encoding: [0xc0,0xff,0xa2,0x04] + vraddhn.i16 d16, q8, q9 +@ CHECK: vraddhn.i32 d16, q8, q9 @ encoding: [0xd0,0xff,0xa2,0x04] + vraddhn.i32 d16, q8, q9 +@ CHECK: vraddhn.i64 d16, q8, q9 @ encoding: [0xe0,0xff,0xa2,0x04] + vraddhn.i64 d16, q8, q9 diff --git a/test/MC/ARM/neont2-bitcount-encoding.s b/test/MC/ARM/neont2-bitcount-encoding.s new file mode 100644 index 0000000..4280cbd --- /dev/null +++ b/test/MC/ARM/neont2-bitcount-encoding.s @@ -0,0 +1,34 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s +@ XFAIL: * + +.code 16 + +@ CHECK: vcnt.8 d16, d16 @ encoding: [0x20,0x05,0xf0,0xff] + vcnt.8 d16, d16 +@ CHECK: vcnt.8 q8, q8 @ encoding: [0x60,0x05,0xf0,0xff] + vcnt.8 q8, q8 +@ CHECK: vclz.i8 d16, d16 @ encoding: [0xa0,0x04,0xf0,0xff] + vclz.i8 d16, d16 +@ CHECK: vclz.i16 d16, d16 @ encoding: [0xa0,0x04,0xf4,0xff] + vclz.i16 d16, d16 +@ CHECK: vclz.i32 d16, d16 @ encoding: [0xa0,0x04,0xf8,0xff] + vclz.i32 d16, d16 +@ CHECK: vclz.i8 q8, q8 @ encoding: [0xe0,0x04,0xf0,0xff] + vclz.i8 q8, q8 +@ CHECK: vclz.i16 q8, q8 @ encoding: [0xe0,0x04,0xf4,0xff] + vclz.i16 q8, q8 +@ CHECK: vclz.i32 q8, q8 @ encoding: [0xe0,0x04,0xf8,0xff] + vclz.i32 q8, q8 +@ CHECK: vcls.s8 d16, d16 @ encoding: [0x20,0x04,0xf0,0xff] + vcls.s8 d16, d16 +@ CHECK: vcls.s16 d16, d16 @ encoding: [0x20,0x04,0xf4,0xff] + vcls.s16 d16, d16 +@ CHECK: vcls.s32 d16, d16 @ encoding: [0x20,0x04,0xf8,0xff] + vcls.s32 d16, d16 +@ CHECK: vcls.s8 q8, q8 @ encoding: [0x60,0x04,0xf0,0xff] + vcls.s8 q8, q8 +@ CHECK: vcls.s16 q8, q8 @ encoding: [0x60,0x04,0xf4,0xff] + vcls.s16 q8, q8 +@ CHECK: vcls.s32 q8, q8 @ encoding: [0x60,0x04,0xf8,0xff] + vcls.s32 q8, q8 + diff --git a/test/MC/ARM/neont2-bitwise-encoding.s b/test/MC/ARM/neont2-bitwise-encoding.s new file mode 100644 index 0000000..3acd7a8 --- /dev/null +++ b/test/MC/ARM/neont2-bitwise-encoding.s @@ -0,0 +1,49 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s +@ XFAIL: * + +.code 16 + +@ CHECK: vand d16, d17, d16 @ encoding: [0xb0,0x01,0x41,0xef] + vand d16, d17, d16 +@ CHECK: vand q8, q8, q9 @ encoding: [0xf2,0x01,0x40,0xef] + vand q8, q8, q9 + +@ CHECK: veor d16, d17, d16 @ encoding: [0xb0,0x01,0x41,0xff] + veor d16, d17, d16 +@ CHECK: veor q8, q8, q9 @ encoding: [0xf2,0x01,0x40,0xff] + veor q8, q8, q9 + +@ CHECK: vorr d16, d17, d16 @ encoding: [0xb0,0x01,0x61,0xef] + vorr d16, d17, d16 +@ CHECK: vorr q8, q8, q9 @ encoding: [0xf2,0x01,0x60,0xef] + vorr q8, q8, q9 +@ CHECK: vorr.i32 d16, #0x1000000 @ encoding: [0x11,0x07,0xc0,0xef] + vorr.i32 d16, #0x1000000 +@ CHECK: vorr.i32 q8, #0x1000000 @ encoding: [0x51,0x07,0xc0,0xef] + vorr.i32 q8, #0x1000000 +@ CHECK: vorr.i32 q8, #0x0 @ encoding: [0x50,0x01,0xc0,0xef] + vorr.i32 q8, #0x0 + +@ CHECK: vbic d16, d17, d16 @ encoding: [0xb0,0x01,0x51,0xef] + vbic d16, d17, d16 +@ CHECK: vbic q8, q8, q9 @ encoding: [0xf2,0x01,0x50,0xef] + vbic q8, q8, q9 +@ CHECK: vbic.i32 d16, #0xFF000000 @ encoding: [0x3f,0x07,0xc7,0xff] + vbic.i32 d16, #0xFF000000 +@ CHECK: vbic.i32 q8, #0xFF000000 @ encoding: [0x7f,0x07,0xc7,0xff] + vbic.i32 q8, #0xFF000000 + +@ CHECK: vorn d16, d17, d16 @ encoding: [0xb0,0x01,0x71,0xef] + vorn d16, d17, d16 +@ CHECK: vorn q8, q8, q9 @ encoding: [0xf2,0x01,0x70,0xef] + vorn q8, q8, q9 + +@ CHECK: vmvn d16, d16 @ encoding: [0xa0,0x05,0xf0,0xff] + vmvn d16, d16 +@ CHECK: vmvn q8, q8 @ encoding: [0xe0,0x05,0xf0,0xff] + vmvn q8, q8 + +@ CHECK: vbsl d18, d17, d16 @ encoding: [0xb0,0x21,0x51,0xff] + vbsl d18, d17, d16 +@ CHECK: vbsl q8, q10, q9 @ encoding: [0xf2,0x01,0x54,0xff] + vbsl q8, q10, q9 diff --git a/test/MC/ARM/neont2-cmp-encoding.s b/test/MC/ARM/neont2-cmp-encoding.s new file mode 100644 index 0000000..1dbd42a --- /dev/null +++ b/test/MC/ARM/neont2-cmp-encoding.s @@ -0,0 +1,36 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s + +.code 16 + +@ CHECK: vcvt.s32.f32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x07] + vcvt.s32.f32 d16, d16 +@ CHECK: vcvt.u32.f32 d16, d16 @ encoding: [0xfb,0xff,0xa0,0x07] + vcvt.u32.f32 d16, d16 +@ CHECK: vcvt.f32.s32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x06] + vcvt.f32.s32 d16, d16 +@ CHECK: vcvt.f32.u32 d16, d16 @ encoding: [0xfb,0xff,0xa0,0x06] + vcvt.f32.u32 d16, d16 +@ CHECK: vcvt.s32.f32 q8, q8 @ encoding: [0xfb,0xff,0x60,0x07] + vcvt.s32.f32 q8, q8 +@ CHECK: vcvt.u32.f32 q8, q8 @ encoding: [0xfb,0xff,0xe0,0x07] + vcvt.u32.f32 q8, q8 +@ CHECK: vcvt.f32.s32 q8, q8 @ encoding: [0xfb,0xff,0x60,0x06] + vcvt.f32.s32 q8, q8 +@ CHECK: vcvt.f32.u32 q8, q8 @ encoding: [0xfb,0xff,0xe0,0x06] + vcvt.f32.u32 q8, q8 +@ CHECK: vcvt.s32.f32 d16, d16, #1 @ encoding: [0xff,0xef,0x30,0x0f] + vcvt.s32.f32 d16, d16, #1 +@ CHECK: vcvt.u32.f32 d16, d16, #1 @ encoding: [0xff,0xff,0x30,0x0f] + vcvt.u32.f32 d16, d16, #1 +@ CHECK: vcvt.f32.s32 d16, d16, #1 @ encoding: [0xff,0xef,0x30,0x0e] + vcvt.f32.s32 d16, d16, #1 +@ CHECK: vcvt.f32.u32 d16, d16, #1 @ encoding: [0xff,0xff,0x30,0x0e] + vcvt.f32.u32 d16, d16, #1 +@ CHECK: vcvt.s32.f32 q8, q8, #1 @ encoding: [0xff,0xef,0x70,0x0f] + vcvt.s32.f32 q8, q8, #1 +@ CHECK: vcvt.u32.f32 q8, q8, #1 @ encoding: [0xff,0xff,0x70,0x0f] + vcvt.u32.f32 q8, q8, #1 +@ CHECK: vcvt.f32.s32 q8, q8, #1 @ encoding: [0xff,0xef,0x70,0x0e] + vcvt.f32.s32 q8, q8, #1 +@ CHECK: vcvt.f32.u32 q8, q8, #1 @ encoding: [0xff,0xff,0x70,0x0e] + vcvt.f32.u32 q8, q8, #1 diff --git a/test/MC/ARM/neont2-convert-encoding.s b/test/MC/ARM/neont2-convert-encoding.s new file mode 100644 index 0000000..1df3b43 --- /dev/null +++ b/test/MC/ARM/neont2-convert-encoding.s @@ -0,0 +1,40 @@ +@ RUN: llvm-mc -mcpu=cortex-a9 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s + +.code 16 + +@ CHECK: vcvt.s32.f32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x07] + vcvt.s32.f32 d16, d16 +@ CHECK: vcvt.u32.f32 d16, d16 @ encoding: [0xfb,0xff,0xa0,0x07] + vcvt.u32.f32 d16, d16 +@ CHECK: vcvt.f32.s32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x06] + vcvt.f32.s32 d16, d16 +@ CHECK: vcvt.f32.u32 d16, d16 @ encoding: [0xfb,0xff,0xa0,0x06] + vcvt.f32.u32 d16, d16 +@ CHECK: vcvt.s32.f32 q8, q8 @ encoding: [0xfb,0xff,0x60,0x07] + vcvt.s32.f32 q8, q8 +@ CHECK: vcvt.u32.f32 q8, q8 @ encoding: [0xfb,0xff,0xe0,0x07] + vcvt.u32.f32 q8, q8 +@ CHECK: vcvt.f32.s32 q8, q8 @ encoding: [0xfb,0xff,0x60,0x06] + vcvt.f32.s32 q8, q8 +@ CHECK: vcvt.f32.u32 q8, q8 @ encoding: [0xfb,0xff,0xe0,0x06] + vcvt.f32.u32 q8, q8 +@ CHECK: vcvt.s32.f32 d16, d16, #1 @ encoding: [0xff,0xef,0x30,0x0f] + vcvt.s32.f32 d16, d16, #1 +@ CHECK: vcvt.u32.f32 d16, d16, #1 @ encoding: [0xff,0xff,0x30,0x0f] + vcvt.u32.f32 d16, d16, #1 +@ CHECK: vcvt.f32.s32 d16, d16, #1 @ encoding: [0xff,0xef,0x30,0x0e] + vcvt.f32.s32 d16, d16, #1 +@ CHECK: vcvt.f32.u32 d16, d16, #1 @ encoding: [0xff,0xff,0x30,0x0e] + vcvt.f32.u32 d16, d16, #1 +@ CHECK: vcvt.s32.f32 q8, q8, #1 @ encoding: [0xff,0xef,0x70,0x0f] + vcvt.s32.f32 q8, q8, #1 +@ CHECK: vcvt.u32.f32 q8, q8, #1 @ encoding: [0xff,0xff,0x70,0x0f] + vcvt.u32.f32 q8, q8, #1 +@ CHECK: vcvt.f32.s32 q8, q8, #1 @ encoding: [0xff,0xef,0x70,0x0e] + vcvt.f32.s32 q8, q8, #1 +@ CHECK: vcvt.f32.u32 q8, q8, #1 @ encoding: [0xff,0xff,0x70,0x0e] + vcvt.f32.u32 q8, q8, #1 +@ CHECK: vcvt.f32.f16 q8, d16 @ encoding: [0xf6,0xff,0x20,0x07] + vcvt.f32.f16 q8, d16 +@ CHECK: vcvt.f16.f32 d16, q8 @ encoding: [0xf6,0xff,0x20,0x06] + vcvt.f16.f32 d16, q8 diff --git a/test/MC/ARM/neont2-dup-encoding.s b/test/MC/ARM/neont2-dup-encoding.s new file mode 100644 index 0000000..da6e78f --- /dev/null +++ b/test/MC/ARM/neont2-dup-encoding.s @@ -0,0 +1,29 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s +@ XFAIL: * + +.code 16 + +@ CHECK: vdup.8 d16, r0 @ encoding: [0x90,0x0b,0xc0,0xee] + vdup.8 d16, r0 +@ CHECK: vdup.16 d16, r0 @ encoding: [0xb0,0x0b,0x80,0xee] + vdup.16 d16, r0 +@ CHECK: vdup.32 d16, r0 @ encoding: [0x90,0x0b,0x80,0xee] + vdup.32 d16, r0 +@ CHECK: vdup.8 q8, r0 @ encoding: [0x90,0x0b,0xe0,0xee] + vdup.8 q8, r0 +@ CHECK: vdup.16 q8, r0 @ encoding: [0xb0,0x0b,0xa0,0xee] + vdup.16 q8, r0 +@ CHECK: vdup.32 q8, r0 @ encoding: [0x90,0x0b,0xa0,0xee] + vdup.32 q8, r0 +@ CHECK: vdup.8 d16, d16[1] @ encoding: [0x20,0x0c,0xf3,0xff] + vdup.8 d16, d16[1] +@ CHECK: vdup.16 d16, d16[1] @ encoding: [0x20,0x0c,0xf6,0xff] + vdup.16 d16, d16[1] +@ CHECK: vdup.32 d16, d16[1] @ encoding: [0x20,0x0c,0xfc,0xff] + vdup.32 d16, d16[1] +@ CHECK: vdup.8 q8, d16[1] @ encoding: [0x60,0x0c,0xf3,0xff] + vdup.8 q8, d16[1] +@ CHECK: vdup.16 q8, d16[1] @ encoding: [0x60,0x0c,0xf6,0xff] + vdup.16 q8, d16[1] +@ CHECK: vdup.32 q8, d16[1] @ encoding: [0x60,0x0c,0xfc,0xff] + vdup.32 q8, d16[1] diff --git a/test/MC/ARM/neont2-minmax-encoding.s b/test/MC/ARM/neont2-minmax-encoding.s new file mode 100644 index 0000000..7e86d45 --- /dev/null +++ b/test/MC/ARM/neont2-minmax-encoding.s @@ -0,0 +1,60 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s + +.code 16 + +@ CHECK: vmin.s8 d16, d16, d17 @ encoding: [0x40,0xef,0xb1,0x06] + vmin.s8 d16, d16, d17 +@ CHECK: vmin.s16 d16, d16, d17 @ encoding: [0x50,0xef,0xb1,0x06] + vmin.s16 d16, d16, d17 +@ CHECK: vmin.s32 d16, d16, d17 @ encoding: [0x60,0xef,0xb1,0x06] + vmin.s32 d16, d16, d17 +@ CHECK: vmin.u8 d16, d16, d17 @ encoding: [0x40,0xff,0xb1,0x06] + vmin.u8 d16, d16, d17 +@ CHECK: vmin.u16 d16, d16, d17 @ encoding: [0x50,0xff,0xb1,0x06] + vmin.u16 d16, d16, d17 +@ CHECK: vmin.u32 d16, d16, d17 @ encoding: [0x60,0xff,0xb1,0x06] + vmin.u32 d16, d16, d17 +@ CHECK: vmin.f32 d16, d16, d17 @ encoding: [0x60,0xef,0xa1,0x0f] + vmin.f32 d16, d16, d17 +@ CHECK: vmin.s8 q8, q8, q9 @ encoding: [0x40,0xef,0xf2,0x06] + vmin.s8 q8, q8, q9 +@ CHECK: vmin.s16 q8, q8, q9 @ encoding: [0x50,0xef,0xf2,0x06] + vmin.s16 q8, q8, q9 +@ CHECK: vmin.s32 q8, q8, q9 @ encoding: [0x60,0xef,0xf2,0x06] + vmin.s32 q8, q8, q9 +@ CHECK: vmin.u8 q8, q8, q9 @ encoding: [0x40,0xff,0xf2,0x06] + vmin.u8 q8, q8, q9 +@ CHECK: vmin.u16 q8, q8, q9 @ encoding: [0x50,0xff,0xf2,0x06] + vmin.u16 q8, q8, q9 +@ CHECK: vmin.u32 q8, q8, q9 @ encoding: [0x60,0xff,0xf2,0x06] + vmin.u32 q8, q8, q9 +@ CHECK: vmin.f32 q8, q8, q9 @ encoding: [0x60,0xef,0xe2,0x0f] + vmin.f32 q8, q8, q9 +@ CHECK: vmax.s8 d16, d16, d17 @ encoding: [0x40,0xef,0xa1,0x06] + vmax.s8 d16, d16, d17 +@ CHECK: vmax.s16 d16, d16, d17 @ encoding: [0x50,0xef,0xa1,0x06] + vmax.s16 d16, d16, d17 +@ CHECK: vmax.s32 d16, d16, d17 @ encoding: [0x60,0xef,0xa1,0x06] + vmax.s32 d16, d16, d17 +@ CHECK: vmax.u8 d16, d16, d17 @ encoding: [0x40,0xff,0xa1,0x06] + vmax.u8 d16, d16, d17 +@ CHECK: vmax.u16 d16, d16, d17 @ encoding: [0x50,0xff,0xa1,0x06] + vmax.u16 d16, d16, d17 +@ CHECK: vmax.u32 d16, d16, d17 @ encoding: [0x60,0xff,0xa1,0x06] + vmax.u32 d16, d16, d17 +@ CHECK: vmax.f32 d16, d16, d17 @ encoding: [0x40,0xef,0xa1,0x0f] + vmax.f32 d16, d16, d17 +@ CHECK: vmax.s8 q8, q8, q9 @ encoding: [0x40,0xef,0xe2,0x06] + vmax.s8 q8, q8, q9 +@ CHECK: vmax.s16 q8, q8, q9 @ encoding: [0x50,0xef,0xe2,0x06] + vmax.s16 q8, q8, q9 +@ CHECK: vmax.s32 q8, q8, q9 @ encoding: [0x60,0xef,0xe2,0x06] + vmax.s32 q8, q8, q9 +@ CHECK: vmax.u8 q8, q8, q9 @ encoding: [0x40,0xff,0xe2,0x06] + vmax.u8 q8, q8, q9 +@ CHECK: vmax.u16 q8, q8, q9 @ encoding: [0x50,0xff,0xe2,0x06] + vmax.u16 q8, q8, q9 +@ CHECK: vmax.u32 q8, q8, q9 @ encoding: [0x60,0xff,0xe2,0x06] + vmax.u32 q8, q8, q9 +@ CHECK: vmax.f32 q8, q8, q9 @ encoding: [0x40,0xef,0xe2,0x0f] + vmax.f32 q8, q8, q9 diff --git a/test/MC/ARM/neont2-mov-encoding.s b/test/MC/ARM/neont2-mov-encoding.s new file mode 100644 index 0000000..ababbb7 --- /dev/null +++ b/test/MC/ARM/neont2-mov-encoding.s @@ -0,0 +1,119 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s +@ XFAIL: * + +.code 16 + +@ CHECK: vmov.i8 d16, #0x8 @ encoding: [0x18,0x0e,0xc0,0xef] + vmov.i8 d16, #0x8 +@ CHECK: vmov.i16 d16, #0x10 @ encoding: [0x10,0x08,0xc1,0xef] + vmov.i16 d16, #0x10 +@ CHECK: vmov.i16 d16, #0x1000 @ encoding: [0x10,0x0a,0xc1,0xef] + vmov.i16 d16, #0x1000 +@ CHECK: vmov.i32 d16, #0x20 @ encoding: [0x10,0x00,0xc2,0xef] + vmov.i32 d16, #0x20 +@ CHECK: vmov.i32 d16, #0x2000 @ encoding: [0x10,0x02,0xc2,0xef] + vmov.i32 d16, #0x2000 +@ CHECK: vmov.i32 d16, #0x200000 @ encoding: [0x10,0x04,0xc2,0xef] + vmov.i32 d16, #0x200000 +@ CHECK: vmov.i32 d16, #0x20000000 @ encoding: [0x10,0x06,0xc2,0xef] + vmov.i32 d16, #0x20000000 +@ CHECK: vmov.i32 d16, #0x20FF @ encoding: [0x10,0x0c,0xc2,0xef] + vmov.i32 d16, #0x20FF +@ CHECK: vmov.i32 d16, #0x20FFFF @ encoding: [0x10,0x0d,0xc2,0xef] + vmov.i32 d16, #0x20FFFF +@ CHECK: vmov.i64 d16, #0xFF0000FF0000FFFF @ encoding: [0x33,0x0e,0xc1,0xff] + vmov.i64 d16, #0xFF0000FF0000FFFF +@ CHECK: vmov.i8 q8, #0x8 @ encoding: [0x58,0x0e,0xc0,0xef] + vmov.i8 q8, #0x8 +@ CHECK: vmov.i16 q8, #0x10 @ encoding: [0x50,0x08,0xc1,0xef] + vmov.i16 q8, #0x10 +@ CHECK: vmov.i16 q8, #0x1000 @ encoding: [0x50,0x0a,0xc1,0xef] + vmov.i16 q8, #0x1000 +@ CHECK: vmov.i32 q8, #0x20 @ encoding: [0x50,0x00,0xc2,0xef] + vmov.i32 q8, #0x20 +@ CHECK: vmov.i32 q8, #0x2000 @ encoding: [0x50,0x02,0xc2,0xef] + vmov.i32 q8, #0x2000 +@ CHECK: vmov.i32 q8, #0x200000 @ encoding: [0x50,0x04,0xc2,0xef] + vmov.i32 q8, #0x200000 +@ CHECK: vmov.i32 q8, #0x20000000 @ encoding: [0x50,0x06,0xc2,0xef] + vmov.i32 q8, #0x20000000 +@ CHECK: vmov.i32 q8, #0x20FF @ encoding: [0x50,0x0c,0xc2,0xef] + vmov.i32 q8, #0x20FF +@ CHECK: vmov.i32 q8, #0x20FFFF @ encoding: [0x50,0x0d,0xc2,0xef] + vmov.i32 q8, #0x20FFFF +@ CHECK: vmov.i64 q8, #0xFF0000FF0000FFFF @ encoding: [0x73,0x0e,0xc1,0xff] + vmov.i64 q8, #0xFF0000FF0000FFFF +@ CHECK: vmvn.i16 d16, #0x10 @ encoding: [0x30,0x08,0xc1,0xef] + vmvn.i16 d16, #0x10 +@ CHECK: vmvn.i16 d16, #0x1000 @ encoding: [0x30,0x0a,0xc1,0xef] + vmvn.i16 d16, #0x1000 +@ CHECK: vmvn.i32 d16, #0x20 @ encoding: [0x30,0x00,0xc2,0xef] + vmvn.i32 d16, #0x20 +@ CHECK: vmvn.i32 d16, #0x2000 @ encoding: [0x30,0x02,0xc2,0xef] + vmvn.i32 d16, #0x2000 +@ CHECK: vmvn.i32 d16, #0x200000 @ encoding: [0x30,0x04,0xc2,0xef] + vmvn.i32 d16, #0x200000 +@ CHECK: vmvn.i32 d16, #0x20000000 @ encoding: [0x30,0x06,0xc2,0xef] + vmvn.i32 d16, #0x20000000 +@ CHECK: vmvn.i32 d16, #0x20FF @ encoding: [0x30,0x0c,0xc2,0xef] + vmvn.i32 d16, #0x20FF +@ CHECK: vmvn.i32 d16, #0x20FFFF @ encoding: [0x30,0x0d,0xc2,0xef] + vmvn.i32 d16, #0x20FFFF +@ CHECK: vmovl.s8 q8, d16 @ encoding: [0x30,0x0a,0xc8,0xef] + vmovl.s8 q8, d16 +@ CHECK: vmovl.s16 q8, d16 @ encoding: [0x30,0x0a,0xd0,0xef] + vmovl.s16 q8, d16 +@ CHECK: vmovl.s32 q8, d16 @ encoding: [0x30,0x0a,0xe0,0xef] + vmovl.s32 q8, d16 +@ CHECK: vmovl.u8 q8, d16 @ encoding: [0x30,0x0a,0xc8,0xff] + vmovl.u8 q8, d16 +@ CHECK: vmovl.u16 q8, d16 @ encoding: [0x30,0x0a,0xd0,0xff] + vmovl.u16 q8, d16 +@ CHECK: vmovl.u32 q8, d16 @ encoding: [0x30,0x0a,0xe0,0xff] + vmovl.u32 q8, d16 +@ CHECK: vmovn.i16 d16, q8 @ encoding: [0x20,0x02,0xf2,0xff] + vmovn.i16 d16, q8 +@ CHECK: vmovn.i32 d16, q8 @ encoding: [0x20,0x02,0xf6,0xff] + vmovn.i32 d16, q8 +@ CHECK: vmovn.i64 d16, q8 @ encoding: [0x20,0x02,0xfa,0xff] + vmovn.i64 d16, q8 +@ CHECK: vqmovn.s16 d16, q8 @ encoding: [0xa0,0x02,0xf2,0xff] + vqmovn.s16 d16, q8 +@ CHECK: vqmovn.s32 d16, q8 @ encoding: [0xa0,0x02,0xf6,0xff] + vqmovn.s32 d16, q8 +@ CHECK: vqmovn.s64 d16, q8 @ encoding: [0xa0,0x02,0xfa,0xff] + vqmovn.s64 d16, q8 +@ CHECK: vqmovn.u16 d16, q8 @ encoding: [0xe0,0x02,0xf2,0xff] + vqmovn.u16 d16, q8 +@ CHECK: vqmovn.u32 d16, q8 @ encoding: [0xe0,0x02,0xf6,0xff] + vqmovn.u32 d16, q8 +@ CHECK: vqmovn.u64 d16, q8 @ encoding: [0xe0,0x02,0xfa,0xff] + vqmovn.u64 d16, q8 +@ CHECK: vqmovun.s16 d16, q8 @ encoding: [0x60,0x02,0xf2,0xff] + vqmovun.s16 d16, q8 +@ CHECK: vqmovun.s32 d16, q8 @ encoding: [0x60,0x02,0xf6,0xff] + vqmovun.s32 d16, q8 +@ CHECK: vqmovun.s64 d16, q8 @ encoding: [0x60,0x02,0xfa,0xff] + vqmovun.s64 d16, q8 +@ CHECK: vmov.s8 r0, d16[1] @ encoding: [0xb0,0x0b,0x50,0xee] + vmov.s8 r0, d16[1] +@ CHECK: vmov.s16 r0, d16[1] @ encoding: [0xf0,0x0b,0x10,0xee] + vmov.s16 r0, d16[1] +@ CHECK: vmov.u8 r0, d16[1] @ encoding: [0xb0,0x0b,0xd0,0xee] + vmov.u8 r0, d16[1] +@ CHECK: vmov.u16 r0, d16[1] @ encoding: [0xf0,0x0b,0x90,0xee] + vmov.u16 r0, d16[1] +@ CHECK: vmov.32 r0, d16[1] @ encoding: [0x90,0x0b,0x30,0xee] + vmov.32 r0, d16[1] +@ CHECK: vmov.8 d16[1], r1 @ encoding: [0xb0,0x1b,0x40,0xee] + vmov.8 d16[1], r1 +@ CHECK: vmov.16 d16[1], r1 @ encoding: [0xf0,0x1b,0x00,0xee] + vmov.16 d16[1], r1 +@ CHECK: vmov.32 d16[1], r1 @ encoding: [0x90,0x1b,0x20,0xee] + vmov.32 d16[1], r1 +@ CHECK: vmov.8 d18[1], r1 @ encoding: [0xb0,0x1b,0x42,0xee] + vmov.8 d18[1], r1 +@ CHECK: vmov.16 d18[1], r1 @ encoding: [0xf0,0x1b,0x02,0xee] + vmov.16 d18[1], r1 +@ CHECK: vmov.32 d18[1], r1 @ encoding: [0x90,0x1b,0x22,0xee] + vmov.32 d18[1], r1 diff --git a/test/MC/ARM/neont2-mul-accum-encoding.s b/test/MC/ARM/neont2-mul-accum-encoding.s new file mode 100644 index 0000000..e21c67d --- /dev/null +++ b/test/MC/ARM/neont2-mul-accum-encoding.s @@ -0,0 +1,69 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s +@ XFAIL: * + +.code 16 + +@ CHECK: vmla.i8 d16, d18, d17 @ encoding: [0xa1,0x09,0x42,0xef] + vmla.i8 d16, d18, d17 +@ CHECK: vmla.i16 d16, d18, d17 @ encoding: [0xa1,0x09,0x52,0xef] + vmla.i16 d16, d18, d17 +@ CHECK: vmla.i16 d16, d18, d17 @ encoding: [0xa1,0x09,0x52,0xef] + vmla.i32 d16, d18, d17 +@ CHECK: vmla.f32 d16, d18, d17 @ encoding: [0xb1,0x0d,0x42,0xef] + vmla.f32 d16, d18, d17 +@ CHECK: vmla.i8 q9, q8, q10 @ encoding: [0xe4,0x29,0x40,0xef] + vmla.i8 q9, q8, q10 +@ CHECK: vmla.i16 q9, q8, q10 @ encoding: [0xe4,0x29,0x50,0xef] + vmla.i16 q9, q8, q10 +@ CHECK: vmla.i32 q9, q8, q10 @ encoding: [0xe4,0x29,0x60,0xef] + vmla.i32 q9, q8, q10 +@ CHECK: vmla.f32 q9, q8, q10 @ encoding: [0xf4,0x2d,0x40,0xef] + vmla.f32 q9, q8, q10 +@ CHECK: vmlal.s8 q8, d19, d18 @ encoding: [0xa2,0x08,0xc3,0xef] + vmlal.s8 q8, d19, d18 +@ CHECK: vmlal.s16 q8, d19, d18 @ encoding: [0xa2,0x08,0xd3,0xef] + vmlal.s16 q8, d19, d18 +@ CHECK: vmlal.s32 q8, d19, d18 @ encoding: [0xa2,0x08,0xe3,0xef] + vmlal.s32 q8, d19, d18 +@ CHECK: vmlal.u8 q8, d19, d18 @ encoding: [0xa2,0x08,0xc3,0xff] + vmlal.u8 q8, d19, d18 +@ CHECK: vmlal.u16 q8, d19, d18 @ encoding: [0xa2,0x08,0xd3,0xff] + vmlal.u16 q8, d19, d18 +@ CHECK: vmlal.u32 q8, d19, d18 @ encoding: [0xa2,0x08,0xe3,0xff] + vmlal.u32 q8, d19, d18 +@ CHECK: vqdmlal.s16 q8, d19, d18 @ encoding: [0xa2,0x09,0xd3,0xef] + vqdmlal.s16 q8, d19, d18 +@ CHECK: vqdmlal.s32 q8, d19, d18 @ encoding: [0xa2,0x09,0xe3,0xef] + vqdmlal.s32 q8, d19, d18 +@ CHECK: vmls.i8 d16, d18, d17 @ encoding: [0xa1,0x09,0x42,0xff] + vmls.i8 d16, d18, d17 +@ CHECK: vmls.i16 d16, d18, d17 @ encoding: [0xa1,0x09,0x52,0xff] + vmls.i16 d16, d18, d17 +@ CHECK: vmls.i32 d16, d18, d17 @ encoding: [0xa1,0x09,0x62,0xff] + vmls.i32 d16, d18, d17 +@ CHECK: vmls.f32 d16, d18, d17 @ encoding: [0xb1,0x0d,0x62,0xef] + vmls.f32 d16, d18, d17 +@ CHECK: vmls.i8 q9, q8, q10 @ encoding: [0xe4,0x29,0x40,0xff] + vmls.i8 q9, q8, q10 +@ CHECK: vmls.i16 q9, q8, q10 @ encoding: [0xe4,0x29,0x50,0xff] + vmls.i16 q9, q8, q10 +@ CHECK: vmls.i32 q9, q8, q10 @ encoding: [0xe4,0x29,0x60,0xff] + vmls.i32 q9, q8, q10 +@ CHECK: vmls.f32 q9, q8, q10 @ encoding: [0xf4,0x2d,0x60,0xef] + vmls.f32 q9, q8, q10 +@ CHECK: vmlsl.s8 q8, d19, d18 @ encoding: [0xa2,0x0a,0xc3,0xef] + vmlsl.s8 q8, d19, d18 +@ CHECK: vmlsl.s16 q8, d19, d18 @ encoding: [0xa2,0x0a,0xd3,0xef] + vmlsl.s16 q8, d19, d18 +@ CHECK: vmlsl.s32 q8, d19, d18 @ encoding: [0xa2,0x0a,0xe3,0xef] + vmlsl.s32 q8, d19, d18 +@ CHECK: vmlsl.u8 q8, d19, d18 @ encoding: [0xa2,0x0a,0xc3,0xff] + vmlsl.u8 q8, d19, d18 +@ CHECK: vmlsl.u16 q8, d19, d18 @ encoding: [0xa2,0x0a,0xd3,0xff] + vmlsl.u16 q8, d19, d18 +@ CHECK: vmlsl.u32 q8, d19, d18 @ encoding: [0xa2,0x0a,0xe3,0xff] + vmlsl.u32 q8, d19, d18 +@ CHECK: vqdmlsl.s16 q8, d19, d18 @ encoding: [0xa2,0x0b,0xd3,0xef] + vqdmlsl.s16 q8, d19, d18 +@ CHECK: vqdmlsl.s32 q8, d19, d18 @ encoding: [0xa2,0x0b,0xe3,0xef] + vqdmlsl.s32 q8, d19, d18 diff --git a/test/MC/ARM/neont2-mul-encoding.s b/test/MC/ARM/neont2-mul-encoding.s new file mode 100644 index 0000000..93ecabb --- /dev/null +++ b/test/MC/ARM/neont2-mul-encoding.s @@ -0,0 +1,58 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s + +.code 16 + +@ CHECK: vmul.i8 d16, d16, d17 @ encoding: [0x40,0xef,0xb1,0x09] + vmul.i8 d16, d16, d17 +@ CHECK: vmul.i16 d16, d16, d17 @ encoding: [0x50,0xef,0xb1,0x09] + vmul.i16 d16, d16, d17 +@ CHECK: vmul.i32 d16, d16, d17 @ encoding: [0x60,0xef,0xb1,0x09] + vmul.i32 d16, d16, d17 +@ CHECK: vmul.f32 d16, d16, d17 @ encoding: [0x40,0xff,0xb1,0x0d] + vmul.f32 d16, d16, d17 +@ CHECK: vmul.i8 q8, q8, q9 @ encoding: [0x40,0xef,0xf2,0x09] + vmul.i8 q8, q8, q9 +@ CHECK: vmul.i16 q8, q8, q9 @ encoding: [0x50,0xef,0xf2,0x09] + vmul.i16 q8, q8, q9 +@ CHECK: vmul.i32 q8, q8, q9 @ encoding: [0x60,0xef,0xf2,0x09] + vmul.i32 q8, q8, q9 +@ CHECK: vmul.f32 q8, q8, q9 @ encoding: [0x40,0xff,0xf2,0x0d] + vmul.f32 q8, q8, q9 +@ CHECK: vmul.p8 d16, d16, d17 @ encoding: [0x40,0xff,0xb1,0x09] + vmul.p8 d16, d16, d17 +@ CHECK: vmul.p8 q8, q8, q9 @ encoding: [0x40,0xff,0xf2,0x09] + vmul.p8 q8, q8, q9 +@ CHECK: vqdmulh.s16 d16, d16, d17 @ encoding: [0x50,0xef,0xa1,0x0b] + vqdmulh.s16 d16, d16, d17 +@ CHECK: vqdmulh.s32 d16, d16, d17 @ encoding: [0x60,0xef,0xa1,0x0b] + vqdmulh.s32 d16, d16, d17 +@ CHECK: vqdmulh.s16 q8, q8, q9 @ encoding: [0x50,0xef,0xe2,0x0b] + vqdmulh.s16 q8, q8, q9 +@ CHECK: vqdmulh.s32 q8, q8, q9 @ encoding: [0x60,0xef,0xe2,0x0b] + vqdmulh.s32 q8, q8, q9 +@ CHECK: vqrdmulh.s16 d16, d16, d17 @ encoding: [0x50,0xff,0xa1,0x0b] + vqrdmulh.s16 d16, d16, d17 +@ CHECK: vqrdmulh.s32 d16, d16, d17 @ encoding: [0x60,0xff,0xa1,0x0b] + vqrdmulh.s32 d16, d16, d17 +@ CHECK: vqrdmulh.s16 q8, q8, q9 @ encoding: [0x50,0xff,0xe2,0x0b] + vqrdmulh.s16 q8, q8, q9 +@ CHECK: vqrdmulh.s32 q8, q8, q9 @ encoding: [0x60,0xff,0xe2,0x0b] + vqrdmulh.s32 q8, q8, q9 +@ CHECK: vmull.s8 q8, d16, d17 @ encoding: [0xc0,0xef,0xa1,0x0c] + vmull.s8 q8, d16, d17 +@ CHECK: vmull.s16 q8, d16, d17 @ encoding: [0xd0,0xef,0xa1,0x0c] + vmull.s16 q8, d16, d17 +@ CHECK: vmull.s32 q8, d16, d17 @ encoding: [0xe0,0xef,0xa1,0x0c] + vmull.s32 q8, d16, d17 +@ CHECK: vmull.u8 q8, d16, d17 @ encoding: [0xc0,0xff,0xa1,0x0c] + vmull.u8 q8, d16, d17 +@ CHECK: vmull.u16 q8, d16, d17 @ encoding: [0xd0,0xff,0xa1,0x0c] + vmull.u16 q8, d16, d17 +@ CHECK: vmull.u32 q8, d16, d17 @ encoding: [0xe0,0xff,0xa1,0x0c] + vmull.u32 q8, d16, d17 +@ CHECK: vmull.p8 q8, d16, d17 @ encoding: [0xc0,0xef,0xa1,0x0e] + vmull.p8 q8, d16, d17 +@ CHECK: vqdmull.s16 q8, d16, d17 @ encoding: [0xd0,0xef,0xa1,0x0d] + vqdmull.s16 q8, d16, d17 +@ CHECK: vqdmull.s32 q8, d16, d17 @ encoding: [0xe0,0xef,0xa1,0x0d] + vqdmull.s32 q8, d16, d17 diff --git a/test/MC/ARM/neont2-neg-encoding.s b/test/MC/ARM/neont2-neg-encoding.s new file mode 100644 index 0000000..21dab65 --- /dev/null +++ b/test/MC/ARM/neont2-neg-encoding.s @@ -0,0 +1,32 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s + +.code 16 + +@ CHECK: vneg.s8 d16, d16 @ encoding: [0xf1,0xff,0xa0,0x03] + vneg.s8 d16, d16 +@ CHECK: vneg.s16 d16, d16 @ encoding: [0xf5,0xff,0xa0,0x03] + vneg.s16 d16, d16 +@ CHECK: vneg.s32 d16, d16 @ encoding: [0xf9,0xff,0xa0,0x03] + vneg.s32 d16, d16 +@ CHECK: vneg.f32 d16, d16 @ encoding: [0xf9,0xff,0xa0,0x07] + vneg.f32 d16, d16 +@ CHECK: vneg.s8 q8, q8 @ encoding: [0xf1,0xff,0xe0,0x03] + vneg.s8 q8, q8 +@ CHECK: vneg.s16 q8, q8 @ encoding: [0xf5,0xff,0xe0,0x03] + vneg.s16 q8, q8 +@ CHECK: vneg.s32 q8, q8 @ encoding: [0xf9,0xff,0xe0,0x03] + vneg.s32 q8, q8 +@ CHECK: vneg.f32 q8, q8 @ encoding: [0xf9,0xff,0xe0,0x07] + vneg.f32 q8, q8 +@ CHECK: vqneg.s8 d16, d16 @ encoding: [0xf0,0xff,0xa0,0x07] + vqneg.s8 d16, d16 +@ CHECK: vqneg.s16 d16, d16 @ encoding: [0xf4,0xff,0xa0,0x07] + vqneg.s16 d16, d16 +@ CHECK: vqneg.s32 d16, d16 @ encoding: [0xf8,0xff,0xa0,0x07] + vqneg.s32 d16, d16 +@ CHECK: vqneg.s8 q8, q8 @ encoding: [0xf0,0xff,0xe0,0x07] + vqneg.s8 q8, q8 +@ CHECK: vqneg.s16 q8, q8 @ encoding: [0xf4,0xff,0xe0,0x07] + vqneg.s16 q8, q8 +@ CHECK: vqneg.s32 q8, q8 @ encoding: [0xf8,0xff,0xe0,0x07] + vqneg.s32 q8, q8 diff --git a/test/MC/ARM/neont2-pairwise-encoding.s b/test/MC/ARM/neont2-pairwise-encoding.s new file mode 100644 index 0000000..ef90922 --- /dev/null +++ b/test/MC/ARM/neont2-pairwise-encoding.s @@ -0,0 +1,89 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s +@ XFAIL: * + +.code 16 + +@ CHECK: vpadd.i8 d16, d17, d16 @ encoding: [0xb0,0x0b,0x41,0xef] + vpadd.i8 d16, d17, d16 +@ CHECK: vpadd.i16 d16, d17, d16 @ encoding: [0xb0,0x0b,0x51,0xef] + vpadd.i16 d16, d17, d16 +@ CHECK: vpadd.i32 d16, d17, d16 @ encoding: [0xb0,0x0b,0x61,0xef] + vpadd.i32 d16, d17, d16 +@ CHECK: vpadd.f32 d16, d16, d17 @ encoding: [0xa1,0x0d,0x40,0xff] + vpadd.f32 d16, d16, d17 +@ CHECK: vpaddl.s8 d16, d16 @ encoding: [0x20,0x02,0xf0,0xff] + vpaddl.s8 d16, d16 +@ CHECK: vpaddl.s16 d16, d16 @ encoding: [0x20,0x02,0xf4,0xff] + vpaddl.s16 d16, d16 +@ CHECK: vpaddl.s32 d16, d16 @ encoding: [0x20,0x02,0xf8,0xff] + vpaddl.s32 d16, d16 +@ CHECK: vpaddl.u8 d16, d16 @ encoding: [0xa0,0x02,0xf0,0xff] + vpaddl.u8 d16, d16 +@ CHECK: vpaddl.u16 d16, d16 @ encoding: [0xa0,0x02,0xf4,0xff] + vpaddl.u16 d16, d16 +@ CHECK: vpaddl.u32 d16, d16 @ encoding: [0xa0,0x02,0xf8,0xff] + vpaddl.u32 d16, d16 +@ CHECK: vpaddl.s8 q8, q8 @ encoding: [0x60,0x02,0xf0,0xff] + vpaddl.s8 q8, q8 +@ CHECK: vpaddl.s16 q8, q8 @ encoding: [0x60,0x02,0xf4,0xff] + vpaddl.s16 q8, q8 +@ CHECK: vpaddl.s32 q8, q8 @ encoding: [0x60,0x02,0xf8,0xff] + vpaddl.s32 q8, q8 +@ CHECK: vpaddl.u8 q8, q8 @ encoding: [0xe0,0x02,0xf0,0xff] + vpaddl.u8 q8, q8 +@ CHECK: vpaddl.u16 q8, q8 @ encoding: [0xe0,0x02,0xf4,0xff] + vpaddl.u16 q8, q8 +@ CHECK: vpaddl.u32 q8, q8 @ encoding: [0xe0,0x02,0xf8,0xff] + vpaddl.u32 q8, q8 +@ CHECK: vpadal.s8 d16, d17 @ encoding: [0x21,0x06,0xf0,0xff] + vpadal.s8 d16, d17 +@ CHECK: vpadal.s16 d16, d17 @ encoding: [0x21,0x06,0xf4,0xff] + vpadal.s16 d16, d17 +@ CHECK: vpadal.s32 d16, d17 @ encoding: [0x21,0x06,0xf8,0xff] + vpadal.s32 d16, d17 +@ CHECK: vpadal.u8 d16, d17 @ encoding: [0xa1,0x06,0xf0,0xff] + vpadal.u8 d16, d17 +@ CHECK: vpadal.u16 d16, d17 @ encoding: [0xa1,0x06,0xf4,0xff] + vpadal.u16 d16, d17 +@ CHECK: vpadal.u32 d16, d17 @ encoding: [0xa1,0x06,0xf8,0xff] + vpadal.u32 d16, d17 +@ CHECK: vpadal.s8 q9, q8 @ encoding: [0x60,0x26,0xf0,0xff] + vpadal.s8 q9, q8 +@ CHECK: vpadal.s16 q9, q8 @ encoding: [0x60,0x26,0xf4,0xff] + vpadal.s16 q9, q8 +@ CHECK: vpadal.s32 q9, q8 @ encoding: [0x60,0x26,0xf8,0xff] + vpadal.s32 q9, q8 +@ CHECK: vpadal.u8 q9, q8 @ encoding: [0xe0,0x26,0xf0,0xff] + vpadal.u8 q9, q8 +@ CHECK: vpadal.u16 q9, q8 @ encoding: [0xe0,0x26,0xf4,0xff] + vpadal.u16 q9, q8 +@ CHECK: vpadal.u32 q9, q8 @ encoding: [0xe0,0x26,0xf8,0xff] + vpadal.u32 q9, q8 +@ CHECK: vpmin.s8 d16, d16, d17 @ encoding: [0xb1,0x0a,0x40,0xef] + vpmin.s8 d16, d16, d17 +@ CHECK: vpmin.s16 d16, d16, d17 @ encoding: [0xb1,0x0a,0x50,0xef] + vpmin.s16 d16, d16, d17 +@ CHECK: vpmin.s32 d16, d16, d17 @ encoding: [0xb1,0x0a,0x60,0xef] + vpmin.s32 d16, d16, d17 +@ CHECK: vpmin.u8 d16, d16, d17 @ encoding: [0xb1,0x0a,0x40,0xff] + vpmin.u8 d16, d16, d17 +@ CHECK: vpmin.u16 d16, d16, d17 @ encoding: [0xb1,0x0a,0x50,0xff] + vpmin.u16 d16, d16, d17 +@ CHECK: vpmin.u32 d16, d16, d17 @ encoding: [0xb1,0x0a,0x60,0xff] + vpmin.u32 d16, d16, d17 +@ CHECK: vpmin.f32 d16, d16, d17 @ encoding: [0xa1,0x0f,0x60,0xff] + vpmin.f32 d16, d16, d17 +@ CHECK: vpmax.s8 d16, d16, d17 @ encoding: [0xa1,0x0a,0x40,0xef] + vpmax.s8 d16, d16, d17 +@ CHECK: vpmax.s16 d16, d16, d17 @ encoding: [0xa1,0x0a,0x50,0xef] + vpmax.s16 d16, d16, d17 +@ CHECK: vpmax.s32 d16, d16, d17 @ encoding: [0xa1,0x0a,0x60,0xef] + vpmax.s32 d16, d16, d17 +@ CHECK: vpmax.u8 d16, d16, d17 @ encoding: [0xa1,0x0a,0x40,0xff] + vpmax.u8 d16, d16, d17 +@ CHECK: vpmax.u16 d16, d16, d17 @ encoding: [0xa1,0x0a,0x50,0xff] + vpmax.u16 d16, d16, d17 +@ CHECK: vpmax.u32 d16, d16, d17 @ encoding: [0xa1,0x0a,0x60,0xff] + vpmax.u32 d16, d16, d17 +@ CHECK: vpmax.f32 d16, d16, d17 @ encoding: [0xa1,0x0f,0x40,0xff] + vpmax.f32 d16, d16, d17 diff --git a/test/MC/ARM/neont2-reciprocal-encoding.s b/test/MC/ARM/neont2-reciprocal-encoding.s new file mode 100644 index 0000000..8ea77d7 --- /dev/null +++ b/test/MC/ARM/neont2-reciprocal-encoding.s @@ -0,0 +1,28 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s + +.code 16 + +@ CHECK: vrecpe.u32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x04] + vrecpe.u32 d16, d16 +@ CHECK: vrecpe.u32 q8, q8 @ encoding: [0xfb,0xff,0x60,0x04] + vrecpe.u32 q8, q8 +@ CHECK: vrecpe.f32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x05] + vrecpe.f32 d16, d16 +@ CHECK: vrecpe.f32 q8, q8 @ encoding: [0xfb,0xff,0x60,0x05] + vrecpe.f32 q8, q8 +@ CHECK: vrecps.f32 d16, d16, d17 @ encoding: [0x40,0xef,0xb1,0x0f] + vrecps.f32 d16, d16, d17 +@ CHECK: vrecps.f32 q8, q8, q9 @ encoding: [0x40,0xef,0xf2,0x0f] + vrecps.f32 q8, q8, q9 +@ CHECK: vrsqrte.u32 d16, d16 @ encoding: [0xfb,0xff,0xa0,0x04] + vrsqrte.u32 d16, d16 +@ CHECK: vrsqrte.u32 q8, q8 @ encoding: [0xfb,0xff,0xe0,0x04] + vrsqrte.u32 q8, q8 +@ CHECK: vrsqrte.f32 d16, d16 @ encoding: [0xfb,0xff,0xa0,0x05] + vrsqrte.f32 d16, d16 +@ CHECK: vrsqrte.f32 q8, q8 @ encoding: [0xfb,0xff,0xe0,0x05] + vrsqrte.f32 q8, q8 +@ CHECK: vrsqrts.f32 d16, d16, d17 @ encoding: [0x60,0xef,0xb1,0x0f] + vrsqrts.f32 d16, d16, d17 +@ CHECK: vrsqrts.f32 q8, q8, q9 @ encoding: [0x60,0xef,0xf2,0x0f] + vrsqrts.f32 q8, q8, q9 diff --git a/test/MC/ARM/neont2-reverse-encoding.s b/test/MC/ARM/neont2-reverse-encoding.s new file mode 100644 index 0000000..f37d72d --- /dev/null +++ b/test/MC/ARM/neont2-reverse-encoding.s @@ -0,0 +1,26 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s + +@ CHECK: vrev64.8 d16, d16 @ encoding: [0xf0,0xff,0x20,0x00] + vrev64.8 d16, d16 +@ CHECK: vrev64.16 d16, d16 @ encoding: [0xf4,0xff,0x20,0x00] + vrev64.16 d16, d16 +@ CHECK: vrev64.32 d16, d16 @ encoding: [0xf8,0xff,0x20,0x00] + vrev64.32 d16, d16 +@ CHECK: vrev64.8 q8, q8 @ encoding: [0xf0,0xff,0x60,0x00] + vrev64.8 q8, q8 +@ CHECK: vrev64.16 q8, q8 @ encoding: [0xf4,0xff,0x60,0x00] + vrev64.16 q8, q8 +@ CHECK: vrev64.32 q8, q8 @ encoding: [0xf8,0xff,0x60,0x00] + vrev64.32 q8, q8 +@ CHECK: vrev32.8 d16, d16 @ encoding: [0xf0,0xff,0xa0,0x00] + vrev32.8 d16, d16 +@ CHECK: vrev32.16 d16, d16 @ encoding: [0xf4,0xff,0xa0,0x00] + vrev32.16 d16, d16 +@ CHECK: vrev32.8 q8, q8 @ encoding: [0xf0,0xff,0xe0,0x00] + vrev32.8 q8, q8 +@ CHECK: vrev32.16 q8, q8 @ encoding: [0xf4,0xff,0xe0,0x00] + vrev32.16 q8, q8 +@ CHECK: vrev16.8 d16, d16 @ encoding: [0xf0,0xff,0x20,0x01] + vrev16.8 d16, d16 +@ CHECK: vrev16.8 q8, q8 @ encoding: [0xf0,0xff,0x60,0x01] + vrev16.8 q8, q8 diff --git a/test/MC/ARM/neont2-satshift-encoding.s b/test/MC/ARM/neont2-satshift-encoding.s new file mode 100644 index 0000000..34e50f1 --- /dev/null +++ b/test/MC/ARM/neont2-satshift-encoding.s @@ -0,0 +1,152 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s + +.code 16 + +@ CHECK: vqshl.s8 d16, d16, d17 @ encoding: [0x41,0xef,0xb0,0x04] + vqshl.s8 d16, d16, d17 +@ CHECK: vqshl.s16 d16, d16, d17 @ encoding: [0x51,0xef,0xb0,0x04] + vqshl.s16 d16, d16, d17 +@ CHECK: vqshl.s32 d16, d16, d17 @ encoding: [0x61,0xef,0xb0,0x04] + vqshl.s32 d16, d16, d17 +@ CHECK: vqshl.s64 d16, d16, d17 @ encoding: [0x71,0xef,0xb0,0x04] + vqshl.s64 d16, d16, d17 +@ CHECK: vqshl.u8 d16, d16, d17 @ encoding: [0x41,0xff,0xb0,0x04] + vqshl.u8 d16, d16, d17 +@ CHECK: vqshl.u16 d16, d16, d17 @ encoding: [0x51,0xff,0xb0,0x04] + vqshl.u16 d16, d16, d17 +@ CHECK: vqshl.u32 d16, d16, d17 @ encoding: [0x61,0xff,0xb0,0x04] + vqshl.u32 d16, d16, d17 +@ CHECK: vqshl.u64 d16, d16, d17 @ encoding: [0x71,0xff,0xb0,0x04] + vqshl.u64 d16, d16, d17 +@ CHECK: vqshl.s8 q8, q8, q9 @ encoding: [0x42,0xef,0xf0,0x04] + vqshl.s8 q8, q8, q9 +@ CHECK: vqshl.s16 q8, q8, q9 @ encoding: [0x52,0xef,0xf0,0x04] + vqshl.s16 q8, q8, q9 +@ CHECK: vqshl.s32 q8, q8, q9 @ encoding: [0x62,0xef,0xf0,0x04] + vqshl.s32 q8, q8, q9 +@ CHECK: vqshl.s64 q8, q8, q9 @ encoding: [0x72,0xef,0xf0,0x04] + vqshl.s64 q8, q8, q9 +@ CHECK: vqshl.u8 q8, q8, q9 @ encoding: [0x42,0xff,0xf0,0x04] + vqshl.u8 q8, q8, q9 +@ CHECK: vqshl.u16 q8, q8, q9 @ encoding: [0x52,0xff,0xf0,0x04] + vqshl.u16 q8, q8, q9 +@ CHECK: vqshl.u32 q8, q8, q9 @ encoding: [0x62,0xff,0xf0,0x04] + vqshl.u32 q8, q8, q9 +@ CHECK: vqshl.u64 q8, q8, q9 @ encoding: [0x72,0xff,0xf0,0x04] + vqshl.u64 q8, q8, q9 +@ CHECK: vqshl.s8 d16, d16, #7 @ encoding: [0xcf,0xef,0x30,0x07] + vqshl.s8 d16, d16, #7 +@ CHECK: vqshl.s16 d16, d16, #15 @ encoding: [0xdf,0xef,0x30,0x07] + vqshl.s16 d16, d16, #15 +@ CHECK: vqshl.s32 d16, d16, #31 @ encoding: [0xff,0xef,0x30,0x07] + vqshl.s32 d16, d16, #31 +@ CHECK: vqshl.s64 d16, d16, #63 @ encoding: [0xff,0xef,0xb0,0x07] + vqshl.s64 d16, d16, #63 +@ CHECK: vqshl.u8 d16, d16, #7 @ encoding: [0xcf,0xff,0x30,0x07] + vqshl.u8 d16, d16, #7 +@ CHECK: vqshl.u16 d16, d16, #15 @ encoding: [0xdf,0xff,0x30,0x07] + vqshl.u16 d16, d16, #15 +@ CHECK: vqshl.u32 d16, d16, #31 @ encoding: [0xff,0xff,0x30,0x07] + vqshl.u32 d16, d16, #31 +@ CHECK: vqshl.u64 d16, d16, #63 @ encoding: [0xff,0xff,0xb0,0x07] + vqshl.u64 d16, d16, #63 +@ CHECK: vqshlu.s8 d16, d16, #7 @ encoding: [0xcf,0xff,0x30,0x06] + vqshlu.s8 d16, d16, #7 +@ CHECK: vqshlu.s16 d16, d16, #15 @ encoding: [0xdf,0xff,0x30,0x06] + vqshlu.s16 d16, d16, #15 +@ CHECK: vqshlu.s32 d16, d16, #31 @ encoding: [0xff,0xff,0x30,0x06] + vqshlu.s32 d16, d16, #31 +@ CHECK: vqshlu.s64 d16, d16, #63 @ encoding: [0xff,0xff,0xb0,0x06] + vqshlu.s64 d16, d16, #63 +@ CHECK: vqshl.s8 q8, q8, #7 @ encoding: [0xcf,0xef,0x70,0x07] + vqshl.s8 q8, q8, #7 +@ CHECK: vqshl.s16 q8, q8, #15 @ encoding: [0xdf,0xef,0x70,0x07] + vqshl.s16 q8, q8, #15 +@ CHECK: vqshl.s32 q8, q8, #31 @ encoding: [0xff,0xef,0x70,0x07] + vqshl.s32 q8, q8, #31 +@ CHECK: vqshl.s64 q8, q8, #63 @ encoding: [0xff,0xef,0xf0,0x07] + vqshl.s64 q8, q8, #63 +@ CHECK: vqshl.u8 q8, q8, #7 @ encoding: [0xcf,0xff,0x70,0x07] + vqshl.u8 q8, q8, #7 +@ CHECK: vqshl.u16 q8, q8, #15 @ encoding: [0xdf,0xff,0x70,0x07] + vqshl.u16 q8, q8, #15 +@ CHECK: vqshl.u32 q8, q8, #31 @ encoding: [0xff,0xff,0x70,0x07] + vqshl.u32 q8, q8, #31 +@ CHECK: vqshl.u64 q8, q8, #63 @ encoding: [0xff,0xff,0xf0,0x07] + vqshl.u64 q8, q8, #63 +@ CHECK: vqshlu.s8 q8, q8, #7 @ encoding: [0xcf,0xff,0x70,0x06] + vqshlu.s8 q8, q8, #7 +@ CHECK: vqshlu.s16 q8, q8, #15 @ encoding: [0xdf,0xff,0x70,0x06] + vqshlu.s16 q8, q8, #15 +@ CHECK: vqshlu.s32 q8, q8, #31 @ encoding: [0xff,0xff,0x70,0x06] + vqshlu.s32 q8, q8, #31 +@ CHECK: vqshlu.s64 q8, q8, #63 @ encoding: [0xff,0xff,0xf0,0x06] + vqshlu.s64 q8, q8, #63 +@ CHECK: vqrshl.s8 d16, d16, d17 @ encoding: [0x41,0xef,0xb0,0x05] + vqrshl.s8 d16, d16, d17 +@ CHECK: vqrshl.s16 d16, d16, d17 @ encoding: [0x51,0xef,0xb0,0x05] + vqrshl.s16 d16, d16, d17 +@ CHECK: vqrshl.s32 d16, d16, d17 @ encoding: [0x61,0xef,0xb0,0x05] + vqrshl.s32 d16, d16, d17 +@ CHECK: vqrshl.s64 d16, d16, d17 @ encoding: [0x71,0xef,0xb0,0x05] + vqrshl.s64 d16, d16, d17 +@ CHECK: vqrshl.u8 d16, d16, d17 @ encoding: [0x41,0xff,0xb0,0x05] + vqrshl.u8 d16, d16, d17 +@ CHECK: vqrshl.u16 d16, d16, d17 @ encoding: [0x51,0xff,0xb0,0x05] + vqrshl.u16 d16, d16, d17 +@ CHECK: vqrshl.u32 d16, d16, d17 @ encoding: [0x61,0xff,0xb0,0x05] + vqrshl.u32 d16, d16, d17 +@ CHECK: vqrshl.u64 d16, d16, d17 @ encoding: [0x71,0xff,0xb0,0x05] + vqrshl.u64 d16, d16, d17 +@ CHECK: vqrshl.s8 q8, q8, q9 @ encoding: [0x42,0xef,0xf0,0x05] + vqrshl.s8 q8, q8, q9 +@ CHECK: vqrshl.s16 q8, q8, q9 @ encoding: [0x52,0xef,0xf0,0x05] + vqrshl.s16 q8, q8, q9 +@ CHECK: vqrshl.s32 q8, q8, q9 @ encoding: [0x62,0xef,0xf0,0x05] + vqrshl.s32 q8, q8, q9 +@ CHECK: vqrshl.s64 q8, q8, q9 @ encoding: [0x72,0xef,0xf0,0x05] + vqrshl.s64 q8, q8, q9 +@ CHECK: vqrshl.u8 q8, q8, q9 @ encoding: [0x42,0xff,0xf0,0x05] + vqrshl.u8 q8, q8, q9 +@ CHECK: vqrshl.u16 q8, q8, q9 @ encoding: [0x52,0xff,0xf0,0x05] + vqrshl.u16 q8, q8, q9 +@ CHECK: vqrshl.u32 q8, q8, q9 @ encoding: [0x62,0xff,0xf0,0x05] + vqrshl.u32 q8, q8, q9 +@ CHECK: vqrshl.u64 q8, q8, q9 @ encoding: [0x72,0xff,0xf0,0x05] + vqrshl.u64 q8, q8, q9 +@ CHECK: vqshrn.s16 d16, q8, #8 @ encoding: [0xc8,0xef,0x30,0x09] + vqshrn.s16 d16, q8, #8 +@ CHECK: vqshrn.s32 d16, q8, #16 @ encoding: [0xd0,0xef,0x30,0x09] + vqshrn.s32 d16, q8, #16 +@ CHECK: vqshrn.s64 d16, q8, #32 @ encoding: [0xe0,0xef,0x30,0x09] + vqshrn.s64 d16, q8, #32 +@ CHECK: vqshrn.u16 d16, q8, #8 @ encoding: [0xc8,0xff,0x30,0x09] + vqshrn.u16 d16, q8, #8 +@ CHECK: vqshrn.u32 d16, q8, #16 @ encoding: [0xd0,0xff,0x30,0x09] + vqshrn.u32 d16, q8, #16 +@ CHECK: vqshrn.u64 d16, q8, #32 @ encoding: [0xe0,0xff,0x30,0x09] + vqshrn.u64 d16, q8, #32 +@ CHECK: vqshrun.s16 d16, q8, #8 @ encoding: [0xc8,0xff,0x30,0x08] + vqshrun.s16 d16, q8, #8 +@ CHECK: vqshrun.s32 d16, q8, #16 @ encoding: [0xd0,0xff,0x30,0x08] + vqshrun.s32 d16, q8, #16 +@ CHECK: vqshrun.s64 d16, q8, #32 @ encoding: [0xe0,0xff,0x30,0x08] + vqshrun.s64 d16, q8, #32 +@ CHECK: vqrshrn.s16 d16, q8, #8 @ encoding: [0xc8,0xef,0x70,0x09] + vqrshrn.s16 d16, q8, #8 +@ CHECK: vqrshrn.s32 d16, q8, #16 @ encoding: [0xd0,0xef,0x70,0x09] + vqrshrn.s32 d16, q8, #16 +@ CHECK: vqrshrn.s64 d16, q8, #32 @ encoding: [0xe0,0xef,0x70,0x09] + vqrshrn.s64 d16, q8, #32 +@ CHECK: vqrshrn.u16 d16, q8, #8 @ encoding: [0xc8,0xff,0x70,0x09] + vqrshrn.u16 d16, q8, #8 +@ CHECK: vqrshrn.u32 d16, q8, #16 @ encoding: [0xd0,0xff,0x70,0x09] + vqrshrn.u32 d16, q8, #16 +@ CHECK: vqrshrn.u64 d16, q8, #32 @ encoding: [0xe0,0xff,0x70,0x09] + vqrshrn.u64 d16, q8, #32 +@ CHECK: vqrshrun.s16 d16, q8, #8 @ encoding: [0xc8,0xff,0x70,0x08] + vqrshrun.s16 d16, q8, #8 +@ CHECK: vqrshrun.s32 d16, q8, #16 @ encoding: [0xd0,0xff,0x70,0x08] + vqrshrun.s32 d16, q8, #16 +@ CHECK: vqrshrun.s64 d16, q8, #32 @ encoding: [0xe0,0xff,0x70,0x08] + vqrshrun.s64 d16, q8, #32 diff --git a/test/MC/ARM/neont2-shift-encoding.s b/test/MC/ARM/neont2-shift-encoding.s new file mode 100644 index 0000000..d098f54 --- /dev/null +++ b/test/MC/ARM/neont2-shift-encoding.s @@ -0,0 +1,162 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s + +.code 16 + +@ CHECK: vshl.u8 d16, d17, d16 @ encoding: [0x40,0xff,0xa1,0x04] + vshl.u8 d16, d17, d16 +@ CHECK: vshl.u16 d16, d17, d16 @ encoding: [0x50,0xff,0xa1,0x04] + vshl.u16 d16, d17, d16 +@ CHECK: vshl.u32 d16, d17, d16 @ encoding: [0x60,0xff,0xa1,0x04] + vshl.u32 d16, d17, d16 +@ CHECK: vshl.u64 d16, d17, d16 @ encoding: [0x70,0xff,0xa1,0x04] + vshl.u64 d16, d17, d16 +@ CHECK: vshl.i8 d16, d16, #7 @ encoding: [0xcf,0xef,0x30,0x05] + vshl.i8 d16, d16, #7 +@ CHECK: vshl.i16 d16, d16, #15 @ encoding: [0xdf,0xef,0x30,0x05] + vshl.i16 d16, d16, #15 +@ CHECK: vshl.i32 d16, d16, #31 @ encoding: [0xff,0xef,0x30,0x05] + vshl.i32 d16, d16, #31 +@ CHECK: vshl.i64 d16, d16, #63 @ encoding: [0xff,0xef,0xb0,0x05] + vshl.i64 d16, d16, #63 +@ CHECK: vshl.u8 q8, q9, q8 @ encoding: [0x40,0xff,0xe2,0x04] + vshl.u8 q8, q9, q8 +@ CHECK: vshl.u16 q8, q9, q8 @ encoding: [0x50,0xff,0xe2,0x04] + vshl.u16 q8, q9, q8 +@ CHECK: vshl.u32 q8, q9, q8 @ encoding: [0x60,0xff,0xe2,0x04] + vshl.u32 q8, q9, q8 +@ CHECK: vshl.u64 q8, q9, q8 @ encoding: [0x70,0xff,0xe2,0x04] + vshl.u64 q8, q9, q8 +@ CHECK: vshl.i8 q8, q8, #7 @ encoding: [0xcf,0xef,0x70,0x05] + vshl.i8 q8, q8, #7 +@ CHECK: vshl.i16 q8, q8, #15 @ encoding: [0xdf,0xef,0x70,0x05] + vshl.i16 q8, q8, #15 +@ CHECK: vshl.i32 q8, q8, #31 @ encoding: [0xff,0xef,0x70,0x05] + vshl.i32 q8, q8, #31 +@ CHECK: vshl.i64 q8, q8, #63 @ encoding: [0xff,0xef,0xf0,0x05] + vshl.i64 q8, q8, #63 +@ CHECK: vshr.u8 d16, d16, #8 @ encoding: [0xc8,0xff,0x30,0x00] + vshr.u8 d16, d16, #8 +@ CHECK: vshr.u16 d16, d16, #16 @ encoding: [0xd0,0xff,0x30,0x00] + vshr.u16 d16, d16, #16 +@ CHECK: vshr.u32 d16, d16, #32 @ encoding: [0xe0,0xff,0x30,0x00] + vshr.u32 d16, d16, #32 +@ CHECK: vshr.u64 d16, d16, #64 @ encoding: [0xc0,0xff,0xb0,0x00] + vshr.u64 d16, d16, #64 +@ CHECK: vshr.u8 q8, q8, #8 @ encoding: [0xc8,0xff,0x70,0x00] + vshr.u8 q8, q8, #8 +@ CHECK: vshr.u16 q8, q8, #16 @ encoding: [0xd0,0xff,0x70,0x00] + vshr.u16 q8, q8, #16 +@ CHECK: vshr.u32 q8, q8, #32 @ encoding: [0xe0,0xff,0x70,0x00] + vshr.u32 q8, q8, #32 +@ CHECK: vshr.u64 q8, q8, #64 @ encoding: [0xc0,0xff,0xf0,0x00] + vshr.u64 q8, q8, #64 +@ CHECK: vshr.s8 d16, d16, #8 @ encoding: [0xc8,0xef,0x30,0x00] + vshr.s8 d16, d16, #8 +@ CHECK: vshr.s16 d16, d16, #16 @ encoding: [0xd0,0xef,0x30,0x00] + vshr.s16 d16, d16, #16 +@ CHECK: vshr.s32 d16, d16, #32 @ encoding: [0xe0,0xef,0x30,0x00] + vshr.s32 d16, d16, #32 +@ CHECK: vshr.s64 d16, d16, #64 @ encoding: [0xc0,0xef,0xb0,0x00] + vshr.s64 d16, d16, #64 +@ CHECK: vshr.s8 q8, q8, #8 @ encoding: [0xc8,0xef,0x70,0x00] + vshr.s8 q8, q8, #8 +@ CHECK: vshr.s16 q8, q8, #16 @ encoding: [0xd0,0xef,0x70,0x00] + vshr.s16 q8, q8, #16 +@ CHECK: vshr.s32 q8, q8, #32 @ encoding: [0xe0,0xef,0x70,0x00] + vshr.s32 q8, q8, #32 +@ CHECK: vshr.s64 q8, q8, #64 @ encoding: [0xc0,0xef,0xf0,0x00] + vshr.s64 q8, q8, #64 +@ CHECK: vshll.s8 q8, d16, #7 @ encoding: [0xcf,0xef,0x30,0x0a] + vshll.s8 q8, d16, #7 +@ CHECK: vshll.s16 q8, d16, #15 @ encoding: [0xdf,0xef,0x30,0x0a] + vshll.s16 q8, d16, #15 +@ CHECK: vshll.s32 q8, d16, #31 @ encoding: [0xff,0xef,0x30,0x0a] + vshll.s32 q8, d16, #31 +@ CHECK: vshll.u8 q8, d16, #7 @ encoding: [0xcf,0xff,0x30,0x0a] + vshll.u8 q8, d16, #7 +@ CHECK: vshll.u16 q8, d16, #15 @ encoding: [0xdf,0xff,0x30,0x0a] + vshll.u16 q8, d16, #15 +@ CHECK: vshll.u32 q8, d16, #31 @ encoding: [0xff,0xff,0x30,0x0a] + vshll.u32 q8, d16, #31 +@ CHECK: vshll.i8 q8, d16, #8 @ encoding: [0xf2,0xff,0x20,0x03] + vshll.i8 q8, d16, #8 +@ CHECK: vshll.i16 q8, d16, #16 @ encoding: [0xf6,0xff,0x20,0x03] + vshll.i16 q8, d16, #16 +@ CHECK: vshll.i32 q8, d16, #32 @ encoding: [0xfa,0xff,0x20,0x03] + vshll.i32 q8, d16, #32 +@ CHECK: vshrn.i16 d16, q8, #8 @ encoding: [0xc8,0xef,0x30,0x08] + vshrn.i16 d16, q8, #8 +@ CHECK: vshrn.i32 d16, q8, #16 @ encoding: [0xd0,0xef,0x30,0x08] + vshrn.i32 d16, q8, #16 +@ CHECK: vshrn.i64 d16, q8, #32 @ encoding: [0xe0,0xef,0x30,0x08] + vshrn.i64 d16, q8, #32 +@ CHECK: vrshl.s8 d16, d17, d16 @ encoding: [0x40,0xef,0xa1,0x05] + vrshl.s8 d16, d17, d16 +@ CHECK: vrshl.s16 d16, d17, d16 @ encoding: [0x50,0xef,0xa1,0x05] + vrshl.s16 d16, d17, d16 +@ CHECK: vrshl.s32 d16, d17, d16 @ encoding: [0x60,0xef,0xa1,0x05] + vrshl.s32 d16, d17, d16 +@ CHECK: vrshl.s64 d16, d17, d16 @ encoding: [0x70,0xef,0xa1,0x05] + vrshl.s64 d16, d17, d16 +@ CHECK: vrshl.u8 d16, d17, d16 @ encoding: [0x40,0xff,0xa1,0x05] + vrshl.u8 d16, d17, d16 +@ CHECK: vrshl.u16 d16, d17, d16 @ encoding: [0x50,0xff,0xa1,0x05] + vrshl.u16 d16, d17, d16 +@ CHECK: vrshl.u32 d16, d17, d16 @ encoding: [0x60,0xff,0xa1,0x05] + vrshl.u32 d16, d17, d16 +@ CHECK: vrshl.u64 d16, d17, d16 @ encoding: [0x70,0xff,0xa1,0x05] + vrshl.u64 d16, d17, d16 +@ CHECK: vrshl.s8 q8, q9, q8 @ encoding: [0x40,0xef,0xe2,0x05] + vrshl.s8 q8, q9, q8 +@ CHECK: vrshl.s16 q8, q9, q8 @ encoding: [0x50,0xef,0xe2,0x05] + vrshl.s16 q8, q9, q8 +@ CHECK: vrshl.s32 q8, q9, q8 @ encoding: [0x60,0xef,0xe2,0x05] + vrshl.s32 q8, q9, q8 +@ CHECK: vrshl.s64 q8, q9, q8 @ encoding: [0x70,0xef,0xe2,0x05] + vrshl.s64 q8, q9, q8 +@ CHECK: vrshl.u8 q8, q9, q8 @ encoding: [0x40,0xff,0xe2,0x05] + vrshl.u8 q8, q9, q8 +@ CHECK: vrshl.u16 q8, q9, q8 @ encoding: [0x50,0xff,0xe2,0x05] + vrshl.u16 q8, q9, q8 +@ CHECK: vrshl.u32 q8, q9, q8 @ encoding: [0x60,0xff,0xe2,0x05] + vrshl.u32 q8, q9, q8 +@ CHECK: vrshl.u64 q8, q9, q8 @ encoding: [0x70,0xff,0xe2,0x05] + vrshl.u64 q8, q9, q8 +@ CHECK: vrshr.s8 d16, d16, #8 @ encoding: [0xc8,0xef,0x30,0x02] + vrshr.s8 d16, d16, #8 +@ CHECK: vrshr.s16 d16, d16, #16 @ encoding: [0xd0,0xef,0x30,0x02] + vrshr.s16 d16, d16, #16 +@ CHECK: vrshr.s32 d16, d16, #32 @ encoding: [0xe0,0xef,0x30,0x02] + vrshr.s32 d16, d16, #32 +@ CHECK: vrshr.s64 d16, d16, #64 @ encoding: [0xc0,0xef,0xb0,0x02] + vrshr.s64 d16, d16, #64 +@ CHECK: vrshr.u8 d16, d16, #8 @ encoding: [0xc8,0xff,0x30,0x02] + vrshr.u8 d16, d16, #8 +@ CHECK: vrshr.u16 d16, d16, #16 @ encoding: [0xd0,0xff,0x30,0x02] + vrshr.u16 d16, d16, #16 +@ CHECK: vrshr.u32 d16, d16, #32 @ encoding: [0xe0,0xff,0x30,0x02] + vrshr.u32 d16, d16, #32 +@ CHECK: vrshr.u64 d16, d16, #64 @ encoding: [0xc0,0xff,0xb0,0x02] + vrshr.u64 d16, d16, #64 +@ CHECK: vrshr.s8 q8, q8, #8 @ encoding: [0xc8,0xef,0x70,0x02] + vrshr.s8 q8, q8, #8 +@ CHECK: vrshr.s16 q8, q8, #16 @ encoding: [0xd0,0xef,0x70,0x02] + vrshr.s16 q8, q8, #16 +@ CHECK: vrshr.s32 q8, q8, #32 @ encoding: [0xe0,0xef,0x70,0x02] + vrshr.s32 q8, q8, #32 +@ CHECK: vrshr.s64 q8, q8, #64 @ encoding: [0xc0,0xef,0xf0,0x02] + vrshr.s64 q8, q8, #64 +@ CHECK: vrshr.u8 q8, q8, #8 @ encoding: [0xc8,0xff,0x70,0x02] + vrshr.u8 q8, q8, #8 +@ CHECK: vrshr.u16 q8, q8, #16 @ encoding: [0xd0,0xff,0x70,0x02] + vrshr.u16 q8, q8, #16 +@ CHECK: vrshr.u32 q8, q8, #32 @ encoding: [0xe0,0xff,0x70,0x02] + vrshr.u32 q8, q8, #32 +@ CHECK: vrshr.u64 q8, q8, #64 @ encoding: [0xc0,0xff,0xf0,0x02] + vrshr.u64 q8, q8, #64 +@ CHECK: vrshrn.i16 d16, q8, #8 @ encoding: [0xc8,0xef,0x70,0x08] + vrshrn.i16 d16, q8, #8 +@ CHECK: vrshrn.i32 d16, q8, #16 @ encoding: [0xd0,0xef,0x70,0x08] + vrshrn.i32 d16, q8, #16 +@ CHECK: vrshrn.i64 d16, q8, #32 @ encoding: [0xe0,0xef,0x70,0x08] + vrshrn.i64 d16, q8, #32 diff --git a/test/MC/ARM/neont2-shiftaccum-encoding.s b/test/MC/ARM/neont2-shiftaccum-encoding.s new file mode 100644 index 0000000..a3a18fc --- /dev/null +++ b/test/MC/ARM/neont2-shiftaccum-encoding.s @@ -0,0 +1,100 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s + +.code 16 + +@ CHECK: vsra.s8 d17, d16, #8 @ encoding: [0xc8,0xef,0x30,0x11] + vsra.s8 d17, d16, #8 +@ CHECK: vsra.s16 d17, d16, #16 @ encoding: [0xd0,0xef,0x30,0x11] + vsra.s16 d17, d16, #16 +@ CHECK: vsra.s32 d17, d16, #32 @ encoding: [0xe0,0xef,0x30,0x11] + vsra.s32 d17, d16, #32 +@ CHECK: vsra.s64 d17, d16, #64 @ encoding: [0xc0,0xef,0xb0,0x11] + vsra.s64 d17, d16, #64 +@ CHECK: vsra.s8 q8, q9, #8 @ encoding: [0xc8,0xef,0x72,0x01] + vsra.s8 q8, q9, #8 +@ CHECK: vsra.s16 q8, q9, #16 @ encoding: [0xd0,0xef,0x72,0x01] + vsra.s16 q8, q9, #16 +@ CHECK: vsra.s32 q8, q9, #32 @ encoding: [0xe0,0xef,0x72,0x01] + vsra.s32 q8, q9, #32 +@ CHECK: vsra.s64 q8, q9, #64 @ encoding: [0xc0,0xef,0xf2,0x01] + vsra.s64 q8, q9, #64 +@ CHECK: vsra.u8 d17, d16, #8 @ encoding: [0xc8,0xff,0x30,0x11] + vsra.u8 d17, d16, #8 +@ CHECK: vsra.u16 d17, d16, #16 @ encoding: [0xd0,0xff,0x30,0x11] + vsra.u16 d17, d16, #16 +@ CHECK: vsra.u32 d17, d16, #32 @ encoding: [0xe0,0xff,0x30,0x11] + vsra.u32 d17, d16, #32 +@ CHECK: vsra.u64 d17, d16, #64 @ encoding: [0xc0,0xff,0xb0,0x11] + vsra.u64 d17, d16, #64 +@ CHECK: vsra.u8 q8, q9, #8 @ encoding: [0xc8,0xff,0x72,0x01] + vsra.u8 q8, q9, #8 +@ CHECK: vsra.u16 q8, q9, #16 @ encoding: [0xd0,0xff,0x72,0x01] + vsra.u16 q8, q9, #16 +@ CHECK: vsra.u32 q8, q9, #32 @ encoding: [0xe0,0xff,0x72,0x01] + vsra.u32 q8, q9, #32 +@ CHECK: vsra.u64 q8, q9, #64 @ encoding: [0xc0,0xff,0xf2,0x01] + vsra.u64 q8, q9, #64 +@ CHECK: vrsra.s8 d17, d16, #8 @ encoding: [0xc8,0xef,0x30,0x13] + vrsra.s8 d17, d16, #8 +@ CHECK: vrsra.s16 d17, d16, #16 @ encoding: [0xd0,0xef,0x30,0x13] + vrsra.s16 d17, d16, #16 +@ CHECK: vrsra.s32 d17, d16, #32 @ encoding: [0xe0,0xef,0x30,0x13] + vrsra.s32 d17, d16, #32 +@ CHECK: vrsra.s64 d17, d16, #64 @ encoding: [0xc0,0xef,0xb0,0x13] + vrsra.s64 d17, d16, #64 +@ CHECK: vrsra.u8 d17, d16, #8 @ encoding: [0xc8,0xff,0x30,0x13] + vrsra.u8 d17, d16, #8 +@ CHECK: vrsra.u16 d17, d16, #16 @ encoding: [0xd0,0xff,0x30,0x13] + vrsra.u16 d17, d16, #16 +@ CHECK: vrsra.u32 d17, d16, #32 @ encoding: [0xe0,0xff,0x30,0x13] + vrsra.u32 d17, d16, #32 +@ CHECK: vrsra.u64 d17, d16, #64 @ encoding: [0xc0,0xff,0xb0,0x13] + vrsra.u64 d17, d16, #64 +@ CHECK: vrsra.s8 q8, q9, #8 @ encoding: [0xc8,0xef,0x72,0x03] + vrsra.s8 q8, q9, #8 +@ CHECK: vrsra.s16 q8, q9, #16 @ encoding: [0xd0,0xef,0x72,0x03] + vrsra.s16 q8, q9, #16 +@ CHECK: vrsra.s32 q8, q9, #32 @ encoding: [0xe0,0xef,0x72,0x03] + vrsra.s32 q8, q9, #32 +@ CHECK: vrsra.s64 q8, q9, #64 @ encoding: [0xc0,0xef,0xf2,0x03] + vrsra.s64 q8, q9, #64 +@ CHECK: vrsra.u8 q8, q9, #8 @ encoding: [0xc8,0xff,0x72,0x03] + vrsra.u8 q8, q9, #8 +@ CHECK: vrsra.u16 q8, q9, #16 @ encoding: [0xd0,0xff,0x72,0x03] + vrsra.u16 q8, q9, #16 +@ CHECK: vrsra.u32 q8, q9, #32 @ encoding: [0xe0,0xff,0x72,0x03] + vrsra.u32 q8, q9, #32 +@ CHECK: vrsra.u64 q8, q9, #64 @ encoding: [0xc0,0xff,0xf2,0x03] + vrsra.u64 q8, q9, #64 +@ CHECK: vsli.8 d17, d16, #7 @ encoding: [0xcf,0xff,0x30,0x15] + vsli.8 d17, d16, #7 +@ CHECK: vsli.16 d17, d16, #15 @ encoding: [0xdf,0xff,0x30,0x15] + vsli.16 d17, d16, #15 +@ CHECK: vsli.32 d17, d16, #31 @ encoding: [0xff,0xff,0x30,0x15] + vsli.32 d17, d16, #31 +@ CHECK: vsli.64 d17, d16, #63 @ encoding: [0xff,0xff,0xb0,0x15] + vsli.64 d17, d16, #63 +@ CHECK: vsli.8 q9, q8, #7 @ encoding: [0xcf,0xff,0x70,0x25] + vsli.8 q9, q8, #7 +@ CHECK: vsli.16 q9, q8, #15 @ encoding: [0xdf,0xff,0x70,0x25] + vsli.16 q9, q8, #15 +@ CHECK: vsli.32 q9, q8, #31 @ encoding: [0xff,0xff,0x70,0x25] + vsli.32 q9, q8, #31 +@ CHECK: vsli.64 q9, q8, #63 @ encoding: [0xff,0xff,0xf0,0x25] + vsli.64 q9, q8, #63 +@ CHECK: vsri.8 d17, d16, #8 @ encoding: [0xc8,0xff,0x30,0x14] + vsri.8 d17, d16, #8 +@ CHECK: vsri.16 d17, d16, #16 @ encoding: [0xd0,0xff,0x30,0x14] + vsri.16 d17, d16, #16 +@ CHECK: vsri.32 d17, d16, #32 @ encoding: [0xe0,0xff,0x30,0x14] + vsri.32 d17, d16, #32 +@ CHECK: vsri.64 d17, d16, #64 @ encoding: [0xc0,0xff,0xb0,0x14] + vsri.64 d17, d16, #64 +@ CHECK: vsri.8 q9, q8, #8 @ encoding: [0xc8,0xff,0x70,0x24] + vsri.8 q9, q8, #8 +@ CHECK: vsri.16 q9, q8, #16 @ encoding: [0xd0,0xff,0x70,0x24] + vsri.16 q9, q8, #16 +@ CHECK: vsri.32 q9, q8, #32 @ encoding: [0xe0,0xff,0x70,0x24] + vsri.32 q9, q8, #32 +@ CHECK: vsri.64 q9, q8, #64 @ encoding: [0xc0,0xff,0xf0,0x24] + vsri.64 q9, q8, #64 diff --git a/test/MC/ARM/neont2-shuffle-encoding.s b/test/MC/ARM/neont2-shuffle-encoding.s new file mode 100644 index 0000000..f471a2b --- /dev/null +++ b/test/MC/ARM/neont2-shuffle-encoding.s @@ -0,0 +1,48 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s + +.code 16 + +@ CHECK: vext.8 d16, d17, d16, #3 @ encoding: [0xf1,0xef,0xa0,0x03] + vext.8 d16, d17, d16, #3 +@ CHECK: vext.8 d16, d17, d16, #5 @ encoding: [0xf1,0xef,0xa0,0x05] + vext.8 d16, d17, d16, #5 +@ CHECK: vext.8 q8, q9, q8, #3 @ encoding: [0xf2,0xef,0xe0,0x03] + vext.8 q8, q9, q8, #3 +@ CHECK: vext.8 q8, q9, q8, #7 @ encoding: [0xf2,0xef,0xe0,0x07] + vext.8 q8, q9, q8, #7 +@ CHECK: vext.16 d16, d17, d16, #3 @ encoding: [0xf1,0xef,0xa0,0x06] + vext.16 d16, d17, d16, #3 +@ CHECK: vext.32 q8, q9, q8, #3 @ encoding: [0xf2,0xef,0xe0,0x0c] + vext.32 q8, q9, q8, #3 +@ CHECK: vtrn.8 d17, d16 @ encoding: [0xf2,0xff,0xa0,0x10] + vtrn.8 d17, d16 +@ CHECK: vtrn.16 d17, d16 @ encoding: [0xf6,0xff,0xa0,0x10] + vtrn.16 d17, d16 +@ CHECK: vtrn.32 d17, d16 @ encoding: [0xfa,0xff,0xa0,0x10] + vtrn.32 d17, d16 +@ CHECK: vtrn.8 q9, q8 @ encoding: [0xf2,0xff,0xe0,0x20] + vtrn.8 q9, q8 +@ CHECK: vtrn.16 q9, q8 @ encoding: [0xf6,0xff,0xe0,0x20] + vtrn.16 q9, q8 +@ CHECK: vtrn.32 q9, q8 @ encoding: [0xfa,0xff,0xe0,0x20] + vtrn.32 q9, q8 +@ CHECK: vuzp.8 d17, d16 @ encoding: [0xf2,0xff,0x20,0x11] + vuzp.8 d17, d16 +@ CHECK: vuzp.16 d17, d16 @ encoding: [0xf6,0xff,0x20,0x11] + vuzp.16 d17, d16 +@ CHECK: vuzp.8 q9, q8 @ encoding: [0xf2,0xff,0x60,0x21] + vuzp.8 q9, q8 +@ CHECK: vuzp.16 q9, q8 @ encoding: [0xf6,0xff,0x60,0x21] + vuzp.16 q9, q8 +@ CHECK: vuzp.32 q9, q8 @ encoding: [0xfa,0xff,0x60,0x21] + vuzp.32 q9, q8 +@ CHECK: vzip.8 d17, d16 @ encoding: [0xf2,0xff,0xa0,0x11] + vzip.8 d17, d16 +@ CHECK: vzip.16 d17, d16 @ encoding: [0xf6,0xff,0xa0,0x11] + vzip.16 d17, d16 +@ CHECK: vzip.8 q9, q8 @ encoding: [0xf2,0xff,0xe0,0x21] + vzip.8 q9, q8 +@ CHECK: vzip.16 q9, q8 @ encoding: [0xf6,0xff,0xe0,0x21] + vzip.16 q9, q8 +@ CHECK: vzip.32 q9, q8 @ encoding: [0xfa,0xff,0xe0,0x21] + vzip.32 q9, q8 diff --git a/test/MC/ARM/neont2-sub-encoding.s b/test/MC/ARM/neont2-sub-encoding.s new file mode 100644 index 0000000..fa9d145 --- /dev/null +++ b/test/MC/ARM/neont2-sub-encoding.s @@ -0,0 +1,46 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s + +@ CHECK: vext.8 d16, d17, d16, #3 @ encoding: [0xf1,0xef,0xa0,0x03] + vext.8 d16, d17, d16, #3 +@ CHECK: vext.8 d16, d17, d16, #5 @ encoding: [0xf1,0xef,0xa0,0x05] + vext.8 d16, d17, d16, #5 +@ CHECK: vext.8 q8, q9, q8, #3 @ encoding: [0xf2,0xef,0xe0,0x03] + vext.8 q8, q9, q8, #3 +@ CHECK: vext.8 q8, q9, q8, #7 @ encoding: [0xf2,0xef,0xe0,0x07] + vext.8 q8, q9, q8, #7 +@ CHECK: vext.16 d16, d17, d16, #3 @ encoding: [0xf1,0xef,0xa0,0x06] + vext.16 d16, d17, d16, #3 +@ CHECK: vext.32 q8, q9, q8, #3 @ encoding: [0xf2,0xef,0xe0,0x0c] + vext.32 q8, q9, q8, #3 +@ CHECK: vtrn.8 d17, d16 @ encoding: [0xf2,0xff,0xa0,0x10] + vtrn.8 d17, d16 +@ CHECK: vtrn.16 d17, d16 @ encoding: [0xf6,0xff,0xa0,0x10] + vtrn.16 d17, d16 +@ CHECK: vtrn.32 d17, d16 @ encoding: [0xfa,0xff,0xa0,0x10] + vtrn.32 d17, d16 +@ CHECK: vtrn.8 q9, q8 @ encoding: [0xf2,0xff,0xe0,0x20] + vtrn.8 q9, q8 +@ CHECK: vtrn.16 q9, q8 @ encoding: [0xf6,0xff,0xe0,0x20] + vtrn.16 q9, q8 +@ CHECK: vtrn.32 q9, q8 @ encoding: [0xfa,0xff,0xe0,0x20] + vtrn.32 q9, q8 +@ CHECK: vuzp.8 d17, d16 @ encoding: [0xf2,0xff,0x20,0x11] + vuzp.8 d17, d16 +@ CHECK: vuzp.16 d17, d16 @ encoding: [0xf6,0xff,0x20,0x11] + vuzp.16 d17, d16 +@ CHECK: vuzp.8 q9, q8 @ encoding: [0xf2,0xff,0x60,0x21] + vuzp.8 q9, q8 +@ CHECK: vuzp.16 q9, q8 @ encoding: [0xf6,0xff,0x60,0x21] + vuzp.16 q9, q8 +@ CHECK: vuzp.32 q9, q8 @ encoding: [0xfa,0xff,0x60,0x21] + vuzp.32 q9, q8 +@ CHECK: vzip.8 d17, d16 @ encoding: [0xf2,0xff,0xa0,0x11] + vzip.8 d17, d16 +@ CHECK: vzip.16 d17, d16 @ encoding: [0xf6,0xff,0xa0,0x11] + vzip.16 d17, d16 +@ CHECK: vzip.8 q9, q8 @ encoding: [0xf2,0xff,0xe0,0x21] + vzip.8 q9, q8 +@ CHECK: vzip.16 q9, q8 @ encoding: [0xf6,0xff,0xe0,0x21] + vzip.16 q9, q8 +@ CHECK: vzip.32 q9, q8 @ encoding: [0xfa,0xff,0xe0,0x21] + vzip.32 q9, q8 diff --git a/test/MC/ARM/neont2-table-encoding.s b/test/MC/ARM/neont2-table-encoding.s new file mode 100644 index 0000000..46fb934 --- /dev/null +++ b/test/MC/ARM/neont2-table-encoding.s @@ -0,0 +1,21 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s +@ XFAIL: * + +.code 16 + +@ CHECK: vtbl.8 d16, {d17}, d16 @ encoding: [0xa0,0x08,0xf1,0xff] + vtbl.8 d16, {d17}, d16 +@ CHECK: vtbl.8 d16, {d16, d17}, d18 @ encoding: [0xa2,0x09,0xf0,0xff] + vtbl.8 d16, {d16, d17}, d18 +@ CHECK: vtbl.8 d16, {d16, d17, d18}, d20 @ encoding: [0xa4,0x0a,0xf0,0xff] + vtbl.8 d16, {d16, d17, d18}, d20 +@ CHECK: vtbl.8 d16, {d16, d17, d18, d19}, d20 @ encoding: [0xa4,0x0b,0xf0,0xff] + vtbl.8 d16, {d16, d17, d18, d19}, d20 +@ CHECK: vtbx.8 d18, {d16}, d17 @ encoding: [0xe1,0x28,0xf0,0xff] + vtbx.8 d18, {d16}, d17 +@ CHECK: vtbx.8 d19, {d16, d17}, d18 @ encoding: [0xe2,0x39,0xf0,0xff] + vtbx.8 d19, {d16, d17}, d18 +@ CHECK: vtbx.8 d20, {d16, d17, d18}, d21 @ encoding: [0xe5,0x4a,0xf0,0xff] + vtbx.8 d20, {d16, d17, d18}, d21 +@ CHECK: vtbx.8 d20, {d16, d17, d18, d19}, d21 @ encoding: [0xe5,0x4b,0xf0,0xff] + vtbx.8 d20, {d16, d17, d18, d19}, d21 diff --git a/test/MC/ARM/neont2-vld-encoding.s b/test/MC/ARM/neont2-vld-encoding.s new file mode 100644 index 0000000..031205a --- /dev/null +++ b/test/MC/ARM/neont2-vld-encoding.s @@ -0,0 +1,112 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s +@ XFAIL: * + +.code 16 + +@ CHECK: vld1.8 {d16}, [r0, :64] @ encoding: [0x1f,0x07,0x60,0xf9] + vld1.8 {d16}, [r0, :64] +@ CHECK: vld1.16 {d16}, [r0] @ encoding: [0x4f,0x07,0x60,0xf9] + vld1.16 {d16}, [r0] +@ CHECK: vld1.32 {d16}, [r0] @ encoding: [0x8f,0x07,0x60,0xf9] + vld1.32 {d16}, [r0] +@ CHECK: vld1.64 {d16}, [r0] @ encoding: [0xcf,0x07,0x60,0xf9] + vld1.64 {d16}, [r0] +@ CHECK: vld1.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x0a,0x60,0xf9] + vld1.8 {d16, d17}, [r0, :64] +@ CHECK: vld1.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x0a,0x60,0xf9] + vld1.16 {d16, d17}, [r0, :128] +@ CHECK: vld1.32 {d16, d17}, [r0] @ encoding: [0x8f,0x0a,0x60,0xf9] + vld1.32 {d16, d17}, [r0] +@ CHECK: vld1.64 {d16, d17}, [r0] @ encoding: [0xcf,0x0a,0x60,0xf9] + vld1.64 {d16, d17}, [r0] + +@ CHECK: vld2.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x08,0x60,0xf9] + vld2.8 {d16, d17}, [r0, :64] +@ CHECK: vld2.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x08,0x60,0xf9] + vld2.16 {d16, d17}, [r0, :128] +@ CHECK: vld2.32 {d16, d17}, [r0] @ encoding: [0x8f,0x08,0x60,0xf9] + vld2.32 {d16, d17}, [r0] +@ CHECK: vld2.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x03,0x60,0xf9] + vld2.8 {d16, d17, d18, d19}, [r0, :64] +@ CHECK: vld2.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x03,0x60,0xf9] + vld2.16 {d16, d17, d18, d19}, [r0, :128] +@ CHECK: vld2.32 {d16, d17, d18, d19}, [r0, :256] @ encoding: [0xbf,0x03,0x60,0xf9] + vld2.32 {d16, d17, d18, d19}, [r0, :256] + +@ CHECK: vld3.8 {d16, d17, d18}, [r0, :64] @ encoding: [0x1f,0x04,0x60,0xf9] + vld3.8 {d16, d17, d18}, [r0, :64] +@ CHECK: vld3.16 {d16, d17, d18}, [r0] @ encoding: [0x4f,0x04,0x60,0xf9] + vld3.16 {d16, d17, d18}, [r0] +@ CHECK: vld3.32 {d16, d17, d18}, [r0] @ encoding: [0x8f,0x04,0x60,0xf9] + vld3.32 {d16, d17, d18}, [r0] +@ CHECK: vld3.8 {d16, d18, d20}, [r0, :64]! @ encoding: [0x1d,0x05,0x60,0xf9] + vld3.8 {d16, d18, d20}, [r0, :64]! +@ CHECK: vld3.8 {d17, d19, d21}, [r0, :64]! @ encoding: [0x1d,0x15,0x60,0xf9] + vld3.8 {d17, d19, d21}, [r0, :64]! +@ CHECK: vld3.16 {d16, d18, d20}, [r0]! @ encoding: [0x4d,0x05,0x60,0xf9] + vld3.16 {d16, d18, d20}, [r0]! +@ CHECK: vld3.16 {d17, d19, d21}, [r0]! @ encoding: [0x4d,0x15,0x60,0xf9] + vld3.16 {d17, d19, d21}, [r0]! +@ CHECK: vld3.32 {d16, d18, d20}, [r0]! @ encoding: [0x8d,0x05,0x60,0xf9] + vld3.32 {d16, d18, d20}, [r0]! +@ CHECK: vld3.32 {d17, d19, d21}, [r0]! @ encoding: [0x8d,0x15,0x60,0xf9] + vld3.32 {d17, d19, d21}, [r0]! + +@ CHECK: vld4.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x00,0x60,0xf9] + vld4.8 {d16, d17, d18, d19}, [r0, :64] +@ CHECK: vld4.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x00,0x60,0xf9] + vld4.16 {d16, d17, d18, d19}, [r0, :128] +@ CHECK: vld4.32 {d16, d17, d18, d19}, [r0, :256] @ encoding: [0xbf,0x00,0x60,0xf9] + vld4.32 {d16, d17, d18, d19}, [r0, :256] +@ CHECK: vld4.8 {d16, d18, d20, d22}, [r0, :256]! @ encoding: [0x3d,0x01,0x60,0xf9] + vld4.8 {d16, d18, d20, d22}, [r0, :256]! +@ CHECK: vld4.8 {d17, d19, d21, d23}, [r0, :256]! @ encoding: [0x3d,0x11,0x60,0xf9] + vld4.8 {d17, d19, d21, d23}, [r0, :256]! +@ CHECK: vld4.16 {d16, d18, d20, d22}, [r0]! @ encoding: [0x4d,0x01,0x60,0xf9] + vld4.16 {d16, d18, d20, d22}, [r0]! +@ CHECK: vld4.16 {d17, d19, d21, d23}, [r0]! @ encoding: [0x4d,0x11,0x60,0xf9] + vld4.16 {d17, d19, d21, d23}, [r0]! +@ CHECK: vld4.32 {d16, d18, d20, d22}, [r0]! @ encoding: [0x8d,0x01,0x60,0xf9] + vld4.32 {d16, d18, d20, d22}, [r0]! +@ CHECK: vld4.32 {d17, d19, d21, d23}, [r0]! @ encoding: [0x8d,0x11,0x60,0xf9] + vld4.32 {d17, d19, d21, d23}, [r0]! + +@ CHECK: vld1.8 {d16[3]}, [r0] @ encoding: [0x6f,0x00,0xe0,0xf9] + vld1.8 {d16[3]}, [r0] +@ CHECK: vld1.16 {d16[2]}, [r0, :16] @ encoding: [0x9f,0x04,0xe0,0xf9] + vld1.16 {d16[2]}, [r0, :16] +@ CHECK: vld1.32 {d16[1]}, [r0, :32] @ encoding: [0xbf,0x08,0xe0,0xf9] + vld1.32 {d16[1]}, [r0, :32] + +@ CHECK: vld2.8 {d16[1], d17[1]}, [r0, :16] @ encoding: [0x3f,0x01,0xe0,0xf9] + vld2.8 {d16[1], d17[1]}, [r0, :16] +@ CHECK: vld2.16 {d16[1], d17[1]}, [r0, :32] @ encoding: [0x5f,0x05,0xe0,0xf9] + vld2.16 {d16[1], d17[1]}, [r0, :32] +@ CHECK: vld2.32 {d16[1], d17[1]}, [r0] @ encoding: [0x8f,0x09,0xe0,0xf9] + vld2.32 {d16[1], d17[1]}, [r0] +@ CHECK: vld2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xe0,0xf9] + vld2.16 {d17[1], d19[1]}, [r0] +@ CHECK: vld2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xe0,0xf9] + vld2.32 {d17[0], d19[0]}, [r0, :64] + +@ CHECK: vld3.8 {d16[1], d17[1], d18[1]}, [r0] @ encoding: [0x2f,0x02,0xe0,0xf9] + vld3.8 {d16[1], d17[1], d18[1]}, [r0] +@ CHECK: vld3.16 {d16[1], d17[1], d18[1]}, [r0] @ encoding: [0x4f,0x06,0xe0,0xf9] + vld3.16 {d16[1], d17[1], d18[1]}, [r0] +@ CHECK: vld3.32 {d16[1], d17[1], d18[1]}, [r0] @ encoding: [0x8f,0x0a,0xe0,0xf9] + vld3.32 {d16[1], d17[1], d18[1]}, [r0] +@ CHECK: vld3.16 {d16[1], d18[1], d20[1]}, [r0] @ encoding: [0x6f,0x06,0xe0,0xf9] + vld3.16 {d16[1], d18[1], d20[1]}, [r0] +@ CHECK: vld3.32 {d17[1], d19[1], d21[1]}, [r0] @ encoding: [0xcf,0x1a,0xe0,0xf9] + vld3.32 {d17[1], d19[1], d21[1]}, [r0] + +@ CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] @ encoding: [0x3f,0x03,0xe0,0xf9] + vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] +@ CHECK: vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] @ encoding: [0x4f,0x07,0xe0,0xf9] + vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] +@ CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128] @ encoding: [0xaf,0x0b,0xe0,0xf9] + vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128] +@ CHECK: vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r0, :64] @ encoding: [0x7f,0x07,0xe0,0xf9] + vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r0, :64] +@ CHECK: vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] @ encoding: [0x4f,0x1b,0xe0,0xf9] + vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] diff --git a/test/MC/ARM/neont2-vst-encoding.s b/test/MC/ARM/neont2-vst-encoding.s new file mode 100644 index 0000000..1722f12 --- /dev/null +++ b/test/MC/ARM/neont2-vst-encoding.s @@ -0,0 +1,103 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s +@ XFAIL: * + +.code 16 + +@ CHECK: vst1.8 {d16}, [r0, :64] @ encoding: [0x1f,0x07,0x40,0xf9] + vst1.8 {d16}, [r0, :64] +@ CHECK: vst1.16 {d16}, [r0] @ encoding: [0x4f,0x07,0x40,0xf9] + vst1.16 {d16}, [r0] +@ CHECK: vst1.32 {d16}, [r0] @ encoding: [0x8f,0x07,0x40,0xf9] + vst1.32 {d16}, [r0] +@ CHECK: vst1.64 {d16}, [r0] @ encoding: [0xcf,0x07,0x40,0xf9] + vst1.64 {d16}, [r0] +@ CHECK: vst1.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x0a,0x40,0xf9] + vst1.8 {d16, d17}, [r0, :64] +@ CHECK: vst1.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x0a,0x40,0xf9] + vst1.16 {d16, d17}, [r0, :128] +@ CHECK: vst1.32 {d16, d17}, [r0] @ encoding: [0x8f,0x0a,0x40,0xf9] + vst1.32 {d16, d17}, [r0] +@ CHECK: vst1.64 {d16, d17}, [r0] @ encoding: [0xcf,0x0a,0x40,0xf9] + vst1.64 {d16, d17}, [r0] + +@ CHECK: vst2.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x08,0x40,0xf9] + vst2.8 {d16, d17}, [r0, :64] +@ CHECK: vst2.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x08,0x40,0xf9] + vst2.16 {d16, d17}, [r0, :128] +@ CHECK: vst2.32 {d16, d17}, [r0] @ encoding: [0x8f,0x08,0x40,0xf9] + vst2.32 {d16, d17}, [r0] +@ CHECK: vst2.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x03,0x40,0xf9] + vst2.8 {d16, d17, d18, d19}, [r0, :64] +@ CHECK: vst2.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x03,0x40,0xf9] + vst2.16 {d16, d17, d18, d19}, [r0, :128] +@ CHECK: vst2.32 {d16, d17, d18, d19}, [r0, :256] @ encoding: [0xbf,0x03,0x40,0xf9] + vst2.32 {d16, d17, d18, d19}, [r0, :256] + +@ CHECK: vst3.8 {d16, d17, d18}, [r0, :64] @ encoding: [0x1f,0x04,0x40,0xf9] + vst3.8 {d16, d17, d18}, [r0, :64] +@ CHECK: vst3.16 {d16, d17, d18}, [r0] @ encoding: [0x4f,0x04,0x40,0xf9] + vst3.16 {d16, d17, d18}, [r0] +@ CHECK: vst3.32 {d16, d17, d18}, [r0] @ encoding: [0x8f,0x04,0x40,0xf9] + vst3.32 {d16, d17, d18}, [r0] +@ CHECK: vst3.8 {d16, d18, d20}, [r0, :64]! @ encoding: [0x1d,0x05,0x40,0xf9] + vst3.8 {d16, d18, d20}, [r0, :64]! +@ CHECK: vst3.8 {d17, d19, d21}, [r0, :64]! @ encoding: [0x1d,0x15,0x40,0xf9] + vst3.8 {d17, d19, d21}, [r0, :64]! +@ CHECK: vst3.16 {d16, d18, d20}, [r0]! @ encoding: [0x4d,0x05,0x40,0xf9] + vst3.16 {d16, d18, d20}, [r0]! +@ CHECK: vst3.16 {d17, d19, d21}, [r0]! @ encoding: [0x4d,0x15,0x40,0xf9] + vst3.16 {d17, d19, d21}, [r0]! +@ CHECK: vst3.32 {d16, d18, d20}, [r0]! @ encoding: [0x8d,0x05,0x40,0xf9] + vst3.32 {d16, d18, d20}, [r0]! +@ CHECK: vst3.32 {d17, d19, d21}, [r0]! @ encoding: [0x8d,0x15,0x40,0xf9] + vst3.32 {d17, d19, d21}, [r0]! + +@ CHECK: vst4.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x00,0x40,0xf9] + vst4.8 {d16, d17, d18, d19}, [r0, :64] +@ CHECK: vst4.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x00,0x40,0xf9] + vst4.16 {d16, d17, d18, d19}, [r0, :128] +@ CHECK: vst4.8 {d16, d18, d20, d22}, [r0, :256]! @ encoding: [0x3d,0x01,0x40,0xf9] + vst4.8 {d16, d18, d20, d22}, [r0, :256]! +@ CHECK: vst4.8 {d17, d19, d21, d23}, [r0, :256]! @ encoding: [0x3d,0x11,0x40,0xf9] + vst4.8 {d17, d19, d21, d23}, [r0, :256]! +@ CHECK: vst4.16 {d16, d18, d20, d22}, [r0]! @ encoding: [0x4d,0x01,0x40,0xf9] + vst4.16 {d16, d18, d20, d22}, [r0]! +@ CHECK: vst4.16 {d17, d19, d21, d23}, [r0]! @ encoding: [0x4d,0x11,0x40,0xf9] + vst4.16 {d17, d19, d21, d23}, [r0]! +@ CHECK: vst4.32 {d16, d18, d20, d22}, [r0]! @ encoding: [0x8d,0x01,0x40,0xf9] + vst4.32 {d16, d18, d20, d22}, [r0]! +@ CHECK: vst4.32 {d17, d19, d21, d23}, [r0]! @ encoding: [0x8d,0x11,0x40,0xf9] + vst4.32 {d17, d19, d21, d23}, [r0]! + +@ CHECK: vst2.8 {d16[1], d17[1]}, [r0, :16] @ encoding: [0x3f,0x01,0xc0,0xf9] + vst2.8 {d16[1], d17[1]}, [r0, :16] +@ CHECK: vst2.16 {d16[1], d17[1]}, [r0, :32] @ encoding: [0x5f,0x05,0xc0,0xf9] + vst2.16 {d16[1], d17[1]}, [r0, :32] +@ CHECK: vst2.32 {d16[1], d17[1]}, [r0] @ encoding: [0x8f,0x09,0xc0,0xf9] + vst2.32 {d16[1], d17[1]}, [r0] +@ CHECK: vst2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xc0,0xf9] + vst2.16 {d17[1], d19[1]}, [r0] +@ CHECK: vst2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xc0,0xf9] + vst2.32 {d17[0], d19[0]}, [r0, :64] + +@ CHECK: vst3.8 {d16[1], d17[1], d18[1]}, [r0] @ encoding: [0x2f,0x02,0xc0,0xf9] + vst3.8 {d16[1], d17[1], d18[1]}, [r0] +@ CHECK: vst3.16 {d16[1], d17[1], d18[1]}, [r0] @ encoding: [0x4f,0x06,0xc0,0xf9] + vst3.16 {d16[1], d17[1], d18[1]}, [r0] +@ CHECK: vst3.32 {d16[1], d17[1], d18[1]}, [r0] @ encoding: [0x8f,0x0a,0xc0,0xf9] + vst3.32 {d16[1], d17[1], d18[1]}, [r0] +@ CHECK: vst3.16 {d17[2], d19[2], d21[2]}, [r0] @ encoding: [0xaf,0x16,0xc0,0xf9] + vst3.16 {d17[2], d19[2], d21[2]}, [r0] +@ CHECK: vst3.32 {d16[0], d18[0], d20[0]}, [r0] @ encoding: [0x4f,0x0a,0xc0,0xf9] + vst3.32 {d16[0], d18[0], d20[0]}, [r0] + +@ CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] @ encoding: [0x3f,0x03,0xc0,0xf9] + vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] +@ CHECK: vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] @ encoding: [0x4f,0x07,0xc0,0xf9] + vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] +@ CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128] @ encoding: [0xaf,0x0b,0xc0,0xf9] + vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128] +@ CHECK: vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0, :64] @ encoding: [0xff,0x17,0xc0,0xf9] + vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0, :64] +@ CHECK: vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] @ encoding: [0x4f,0x1b,0xc0,0xf9] + vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] diff --git a/test/MC/ARM/prefetch.ll b/test/MC/ARM/prefetch.ll new file mode 100644 index 0000000..674b8f3 --- /dev/null +++ b/test/MC/ARM/prefetch.ll @@ -0,0 +1,58 @@ +; RUN: llc < %s -mtriple=armv7-apple-darwin -mattr=+v7a,+mp -show-mc-encoding | FileCheck %s -check-prefix=ARM +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+v7a -show-mc-encoding | FileCheck %s -check-prefix=T2 +; rdar://8924681 + +define void @t1(i8* %ptr) nounwind { +entry: +; ARM: t1: +; ARM: pldw [r0] @ encoding: [0x00,0xf0,0x90,0xf5] +; ARM: pld [r0] @ encoding: [0x00,0xf0,0xd0,0xf5] + +; T2: t1: +; T2: pld [r0] @ encoding: [0x90,0xf8,0x00,0xf0] + tail call void @llvm.prefetch( i8* %ptr, i32 1, i32 3 ) + tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3 ) + ret void +} + +define void @t2(i8* %ptr) nounwind { +entry: +; ARM: t2: +; ARM: pld [r0, #1023] @ encoding: [0xff,0xf3,0xd0,0xf5] + +; T2: t2: +; T2: pld [r0, #1023] @ encoding: [0x90,0xf8,0xff,0xf3] + %tmp = getelementptr i8* %ptr, i32 1023 + tail call void @llvm.prefetch( i8* %tmp, i32 0, i32 3 ) + ret void +} + +define void @t3(i32 %base, i32 %offset) nounwind { +entry: +; ARM: t3: +; ARM: pld [r0, r1, lsr #2] @ encoding: [0x21,0xf1,0xd0,0xf7] + +; T2: t3: +; T2: pld [r0, r1] @ encoding: [0x10,0xf8,0x01,0xf0] + %tmp1 = lshr i32 %offset, 2 + %tmp2 = add i32 %base, %tmp1 + %tmp3 = inttoptr i32 %tmp2 to i8* + tail call void @llvm.prefetch( i8* %tmp3, i32 0, i32 3 ) + ret void +} + +define void @t4(i32 %base, i32 %offset) nounwind { +entry: +; ARM: t4: +; ARM: pld [r0, r1, lsl #2] @ encoding: [0x01,0xf1,0xd0,0xf7] + +; T2: t4: +; T2: pld [r0, r1, lsl #2] @ encoding: [0x10,0xf8,0x21,0xf0] + %tmp1 = shl i32 %offset, 2 + %tmp2 = add i32 %base, %tmp1 + %tmp3 = inttoptr i32 %tmp2 to i8* + tail call void @llvm.prefetch( i8* %tmp3, i32 0, i32 3 ) + ret void +} + +declare void @llvm.prefetch(i8*, i32, i32) nounwind diff --git a/test/MC/ARM/reg-list.s b/test/MC/ARM/reg-list.s new file mode 100644 index 0000000..4dd392e --- /dev/null +++ b/test/MC/ARM/reg-list.s @@ -0,0 +1,8 @@ +@ RUN: llvm-mc -triple thumb-apple-darwin10 -show-encoding < %s 2> %t | FileCheck %s +@ RUN: FileCheck --check-prefix=CHECK-WARNINGS < %t %s + + push {r7, lr} +@ CHECK-WARNINGS: register not in ascending order in register list + + push {lr, r7} +@ CHECK: push {lr, r7} diff --git a/test/MC/ARM/simple-encoding.ll b/test/MC/ARM/simple-encoding.ll new file mode 100644 index 0000000..0877e8e --- /dev/null +++ b/test/MC/ARM/simple-encoding.ll @@ -0,0 +1,237 @@ +;RUN: llc -mtriple=armv7-apple-darwin -show-mc-encoding < %s | FileCheck %s + + +;FIXME: Once the ARM integrated assembler is up and going, these sorts of tests +; should run on .s source files rather than using llc to generate the +; assembly. There's also a large number of instruction encodings the +; compiler never generates, so we need the integrated assembler to be +; able to test those at all. + +declare void @llvm.trap() nounwind +declare i32 @llvm.ctlz.i32(i32) + +define i32 @foo(i32 %a, i32 %b) { +; CHECK: foo +; CHECK: trap @ encoding: [0xfe,0xde,0xff,0xe7] +; CHECK: bx lr @ encoding: [0x1e,0xff,0x2f,0xe1] + + tail call void @llvm.trap() + ret i32 undef +} + +define i32 @f2(i32 %a, i32 %b) { +; CHECK: f2 +; CHECK: add r0, r1, r0 @ encoding: [0x00,0x00,0x81,0xe0] +; CHECK: bx lr @ encoding: [0x1e,0xff,0x2f,0xe1] + %add = add nsw i32 %b, %a + ret i32 %add +} + + +define i32 @f3(i32 %a, i32 %b) { +; CHECK: f3 +; CHECK: add r0, r0, r1, lsl #3 @ encoding: [0x81,0x01,0x80,0xe0] +; CHECK: bx lr @ encoding: [0x1e,0xff,0x2f,0xe1] + %mul = shl i32 %b, 3 + %add = add nsw i32 %mul, %a + ret i32 %add +} + +define i32 @f4(i32 %a, i32 %b) { +; CHECK: f4 +; CHECK: add r0, r0, #254, 28 @ encoding: [0xfe,0x0e,0x80,0xe2] +; CHECK: @ 4064 +; CHECK: bx lr @ encoding: [0x1e,0xff,0x2f,0xe1] + %add = add nsw i32 %a, 4064 + ret i32 %add +} + +define i32 @f5(i32 %a, i32 %b, i32 %c) { +; CHECK: f5 +; CHECK: cmp r0, r1 @ encoding: [0x01,0x00,0x50,0xe1] +; CHECK: mov r0, r2 @ encoding: [0x02,0x00,0xa0,0xe1] +; CHECK: movgt r0, r1 @ encoding: [0x01,0x00,0xa0,0xc1] + %cmp = icmp sgt i32 %a, %b + %retval.0 = select i1 %cmp, i32 %b, i32 %c + ret i32 %retval.0 +} + +define i64 @f6(i64 %a, i64 %b, i64 %c) { +; CHECK: f6 +; CHECK: adds r0, r2, r0 @ encoding: [0x00,0x00,0x92,0xe0] +; CHECK: adc r1, r3, r1 @ encoding: [0x01,0x10,0xa3,0xe0] + %add = add nsw i64 %b, %a + ret i64 %add +} + +define i32 @f7(i32 %a, i32 %b) { +; CHECK: f7 +; CHECK: uxtab r0, r0, r1 @ encoding: [0x71,0x00,0xe0,0xe6] + %and = and i32 %b, 255 + %add = add i32 %and, %a + ret i32 %add +} + +define i32 @f8(i32 %a) { +; CHECK: f8 +; CHECK: movt r0, #42405 @ encoding: [0xa5,0x05,0x4a,0xe3] + %and = and i32 %a, 65535 + %or = or i32 %and, -1515913216 + ret i32 %or +} + +define i32 @f9() { +; CHECK: f9 +; CHECK: movw r0, #42405 @ encoding: [0xa5,0x05,0x0a,0xe3] + ret i32 42405 +} + +define i64 @f10(i64 %a) { +; CHECK: f10 +; CHECK: asrs r1, r1, #1 @ encoding: [0xc1,0x10,0xb0,0xe1] +; CHECK: rrx r0, r0 @ encoding: [0x60,0x00,0xa0,0xe1] + %shr = ashr i64 %a, 1 + ret i64 %shr +} + +define i32 @f11([1 x i32] %A.coerce0, [1 x i32] %B.coerce0) { +; CHECK: f11 +; CHECK: ubfx r1, r1, #8, #5 @ encoding: [0x51,0x14,0xe4,0xe7] +; CHECK: sbfx r0, r0, #13, #7 @ encoding: [0xd0,0x06,0xa6,0xe7] + %tmp1 = extractvalue [1 x i32] %A.coerce0, 0 + %tmp2 = extractvalue [1 x i32] %B.coerce0, 0 + %tmp3 = shl i32 %tmp1, 12 + %bf.val.sext = ashr i32 %tmp3, 25 + %tmp4 = lshr i32 %tmp2, 8 + %bf.clear2 = and i32 %tmp4, 31 + %mul = mul nsw i32 %bf.val.sext, %bf.clear2 + ret i32 %mul +} + +define i32 @f12(i32 %a) { +; CHECK: f12: +; CHECK: bfc r0, #4, #20 @ encoding: [0x1f,0x02,0xd7,0xe7] + %tmp = and i32 %a, 4278190095 + ret i32 %tmp +} + +define i64 @f13() { +; CHECK: f13: +; CHECK: mvn r0, #0 @ encoding: [0x00,0x00,0xe0,0xe3] +; CHECK: mvn r1, #2, 2 @ encoding: [0x02,0x11,0xe0,0xe3] + ret i64 9223372036854775807 +} + +define i32 @f14(i32 %x, i32 %y) { +; CHECK: f14: +; CHECK: smmul r0, r1, r0 @ encoding: [0x11,0xf0,0x50,0xe7] + %tmp = sext i32 %x to i64 + %tmp1 = sext i32 %y to i64 + %tmp2 = mul i64 %tmp1, %tmp + %tmp3 = lshr i64 %tmp2, 32 + %tmp3.upgrd.1 = trunc i64 %tmp3 to i32 + ret i32 %tmp3.upgrd.1 +} + +define i32 @f15(i32 %x, i32 %y) { +; CHECK: f15: +; CHECK: umull r1, r0, r1, r0 @ encoding: [0x91,0x10,0x80,0xe0] + %tmp = zext i32 %x to i64 + %tmp1 = zext i32 %y to i64 + %tmp2 = mul i64 %tmp1, %tmp + %tmp3 = lshr i64 %tmp2, 32 + %tmp3.upgrd.2 = trunc i64 %tmp3 to i32 + ret i32 %tmp3.upgrd.2 +} + +define i32 @f16(i16 %x, i32 %y) { +; CHECK: f16: +; CHECK: smulbt r0, r0, r1 @ encoding: [0xc0,0x01,0x60,0xe1] + %tmp1 = add i16 %x, 2 + %tmp2 = sext i16 %tmp1 to i32 + %tmp3 = ashr i32 %y, 16 + %tmp4 = mul i32 %tmp2, %tmp3 + ret i32 %tmp4 +} + +define i32 @f17(i32 %x, i32 %y) { +; CHECK: f17: +; CHECK: smultt r0, r1, r0 @ encoding: [0xe1,0x00,0x60,0xe1] + %tmp1 = ashr i32 %x, 16 + %tmp3 = ashr i32 %y, 16 + %tmp4 = mul i32 %tmp3, %tmp1 + ret i32 %tmp4 +} + +define i32 @f18(i32 %a, i16 %x, i32 %y) { +; CHECK: f18: +; CHECK: smlabt r0, r1, r2, r0 @ encoding: [0xc1,0x02,0x00,0xe1] + %tmp = sext i16 %x to i32 + %tmp2 = ashr i32 %y, 16 + %tmp3 = mul i32 %tmp2, %tmp + %tmp5 = add i32 %tmp3, %a + ret i32 %tmp5 +} + +define i32 @f19(i32 %x) { +; CHECK: f19 +; CHECK: clz r0, r0 @ encoding: [0x10,0x0f,0x6f,0xe1] + %tmp.1 = call i32 @llvm.ctlz.i32( i32 %x ) + ret i32 %tmp.1 +} + +define i32 @f20(i32 %X) { +; CHECK: f20 +; CHECK: rev16 r0, r0 @ encoding: [0xb0,0x0f,0xbf,0xe6] + %tmp1 = lshr i32 %X, 8 + %X15 = bitcast i32 %X to i32 + %tmp4 = shl i32 %X15, 8 + %tmp2 = and i32 %tmp1, 16711680 + %tmp5 = and i32 %tmp4, -16777216 + %tmp9 = and i32 %tmp1, 255 + %tmp13 = and i32 %tmp4, 65280 + %tmp6 = or i32 %tmp5, %tmp2 + %tmp10 = or i32 %tmp6, %tmp13 + %tmp14 = or i32 %tmp10, %tmp9 + ret i32 %tmp14 +} + +define i32 @f21(i32 %X) { +; CHECK: f21 +; CHECK: revsh r0, r0 @ encoding: [0xb0,0x0f,0xff,0xe6] + %tmp1 = lshr i32 %X, 8 + %tmp1.upgrd.1 = trunc i32 %tmp1 to i16 + %tmp3 = trunc i32 %X to i16 + %tmp2 = and i16 %tmp1.upgrd.1, 255 + %tmp4 = shl i16 %tmp3, 8 + %tmp5 = or i16 %tmp2, %tmp4 + %tmp5.upgrd.2 = sext i16 %tmp5 to i32 + ret i32 %tmp5.upgrd.2 +} + +define i32 @f22(i32 %X, i32 %Y) { +; CHECK: f22 +; CHECK: pkhtb r0, r0, r1, asr #22 @ encoding: [0x51,0x0b,0x80,0xe6] + %tmp1 = and i32 %X, -65536 + %tmp2 = lshr i32 %Y, 22 + %tmp3 = or i32 %tmp2, %tmp1 + ret i32 %tmp3 +} + +define i32 @f23(i32 %X, i32 %Y) { +; CHECK: f23 +; CHECK: pkhbt r0, r0, r1, lsl #18 @ encoding: [0x11,0x09,0x80,0xe6] + %tmp1 = and i32 %X, 65535 + %tmp2 = shl i32 %Y, 18 + %tmp3 = or i32 %tmp1, %tmp2 + ret i32 %tmp3 +} + +define void @f24(i32 %a) { +; CHECK: f24 +; CHECK: cmp r0, #1, 16 @ encoding: [0x01,0x08,0x50,0xe3] + %b = icmp ugt i32 %a, 65536 + br i1 %b, label %r, label %r +r: + ret void +} diff --git a/test/MC/ARM/simple-fp-encoding.s b/test/MC/ARM/simple-fp-encoding.s new file mode 100644 index 0000000..8917380 --- /dev/null +++ b/test/MC/ARM/simple-fp-encoding.s @@ -0,0 +1,236 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple armv7-apple-darwin -show-encoding < %s | FileCheck %s + +@ CHECK: vadd.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x71,0xee] + vadd.f64 d16, d17, d16 + +@ CHECK: vadd.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x30,0xee] + vadd.f32 s0, s1, s0 + +@ CHECK: vsub.f64 d16, d17, d16 @ encoding: [0xe0,0x0b,0x71,0xee] + vsub.f64 d16, d17, d16 + +@ CHECK: vsub.f32 s0, s1, s0 @ encoding: [0xc0,0x0a,0x30,0xee] + vsub.f32 s0, s1, s0 + +@ CHECK: vdiv.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0xc1,0xee] + vdiv.f64 d16, d17, d16 + +@ CHECK: vdiv.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x80,0xee] + vdiv.f32 s0, s1, s0 + +@ CHECK: vmul.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x61,0xee] + vmul.f64 d16, d17, d16 + +@ CHECK: vmul.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x20,0xee] + vmul.f32 s0, s1, s0 + +@ CHECK: vnmul.f64 d16, d17, d16 @ encoding: [0xe0,0x0b,0x61,0xee] + vnmul.f64 d16, d17, d16 + +@ CHECK: vnmul.f32 s0, s1, s0 @ encoding: [0xc0,0x0a,0x20,0xee] + vnmul.f32 s0, s1, s0 + +@ CHECK: vcmpe.f64 d17, d16 @ encoding: [0xe0,0x1b,0xf4,0xee] + vcmpe.f64 d17, d16 + +@ CHECK: vcmpe.f32 s1, s0 @ encoding: [0xc0,0x0a,0xf4,0xee] + vcmpe.f32 s1, s0 + +@ FIXME: vcmpe.f64 d16, #0 @ encoding: [0xc0,0x0b,0xf5,0xee] +@ vcmpe.f64 d16, #0 + +@ FIXME: vcmpe.f32 s0, #0 @ encoding: [0xc0,0x0a,0xb5,0xee] +@ vcmpe.f32 s0, #0 + +@ CHECK: vabs.f64 d16, d16 @ encoding: [0xe0,0x0b,0xf0,0xee] + vabs.f64 d16, d16 + +@ CHECK: vabs.f32 s0, s0 @ encoding: [0xc0,0x0a,0xb0,0xee] + vabs.f32 s0, s0 + +@ CHECK: vcvt.f32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xb7,0xee] + vcvt.f32.f64 s0, d16 + +@ CHECK: vcvt.f64.f32 d16, s0 @ encoding: [0xc0,0x0a,0xf7,0xee] + vcvt.f64.f32 d16, s0 + +@ CHECK: vneg.f64 d16, d16 @ encoding: [0x60,0x0b,0xf1,0xee] + vneg.f64 d16, d16 + +@ CHECK: vneg.f32 s0, s0 @ encoding: [0x40,0x0a,0xb1,0xee] + vneg.f32 s0, s0 + +@ CHECK: vsqrt.f64 d16, d16 @ encoding: [0xe0,0x0b,0xf1,0xee] + vsqrt.f64 d16, d16 + +@ CHECK: vsqrt.f32 s0, s0 @ encoding: [0xc0,0x0a,0xb1,0xee] + vsqrt.f32 s0, s0 + +@ CHECK: vcvt.f64.s32 d16, s0 @ encoding: [0xc0,0x0b,0xf8,0xee] + vcvt.f64.s32 d16, s0 + +@ CHECK: vcvt.f32.s32 s0, s0 @ encoding: [0xc0,0x0a,0xb8,0xee] + vcvt.f32.s32 s0, s0 + +@ CHECK: vcvt.f64.u32 d16, s0 @ encoding: [0x40,0x0b,0xf8,0xee] + vcvt.f64.u32 d16, s0 + +@ CHECK: vcvt.f32.u32 s0, s0 @ encoding: [0x40,0x0a,0xb8,0xee] + vcvt.f32.u32 s0, s0 + +@ CHECK: vcvt.s32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xbd,0xee] + vcvt.s32.f64 s0, d16 + +@ CHECK: vcvt.s32.f32 s0, s0 @ encoding: [0xc0,0x0a,0xbd,0xee] + vcvt.s32.f32 s0, s0 + +@ CHECK: vcvt.u32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xbc,0xee] + vcvt.u32.f64 s0, d16 + +@ CHECK: vcvt.u32.f32 s0, s0 @ encoding: [0xc0,0x0a,0xbc,0xee] + vcvt.u32.f32 s0, s0 + +@ CHECK: vmla.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0x42,0xee] + vmla.f64 d16, d18, d17 + +@ CHECK: vmla.f32 s1, s2, s0 @ encoding: [0x00,0x0a,0x41,0xee] + vmla.f32 s1, s2, s0 + +@ CHECK: vmls.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0x42,0xee] + vmls.f64 d16, d18, d17 + +@ CHECK: vmls.f32 s1, s2, s0 @ encoding: [0x40,0x0a,0x41,0xee] + vmls.f32 s1, s2, s0 + +@ CHECK: vnmla.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0x52,0xee] + vnmla.f64 d16, d18, d17 + +@ CHECK: vnmla.f32 s1, s2, s0 @ encoding: [0x40,0x0a,0x51,0xee] + vnmla.f32 s1, s2, s0 + +@ CHECK: vnmls.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0x52,0xee] + vnmls.f64 d16, d18, d17 + +@ CHECK: vnmls.f32 s1, s2, s0 @ encoding: [0x00,0x0a,0x51,0xee] + vnmls.f32 s1, s2, s0 + +@ FIXME: vmrs apsr_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee] +@ vmrs apsr_nzcv, fpscr + +@ CHECK: vnegne.f64 d16, d16 @ encoding: [0x60,0x0b,0xf1,0x1e] + vnegne.f64 d16, d16 + +@ CHECK: vmovne s0, r0 @ encoding: [0x10,0x0a,0x00,0x1e] +@ CHECK: vmoveq s0, r1 @ encoding: [0x10,0x1a,0x00,0x0e] + vmovne s0, r0 + vmoveq s0, r1 + +@ CHECK: vmrs r0, fpscr @ encoding: [0x10,0x0a,0xf1,0xee] + vmrs r0, fpscr +@ CHECK: vmrs r0, fpexc @ encoding: [0x10,0x0a,0xf8,0xee] + vmrs r0, fpexc +@ CHECK: vmrs r0, fpsid @ encoding: [0x10,0x0a,0xf0,0xee] + vmrs r0, fpsid + +@ CHECK: vmsr fpscr, r0 @ encoding: [0x10,0x0a,0xe1,0xee] + vmsr fpscr, r0 +@ CHECK: vmsr fpexc, r0 @ encoding: [0x10,0x0a,0xe8,0xee] + vmsr fpexc, r0 +@ CHECK: vmsr fpsid, r0 @ encoding: [0x10,0x0a,0xe0,0xee] + vmsr fpsid, r0 + +@ FIXME: vmov.f64 d16, #3.000000e+00 @ encoding: [0x08,0x0b,0xf0,0xee] +@ vmov.f64 d16, #3.000000e+00 + +@ FIXME: vmov.f32 s0, #3.000000e+00 @ encoding: [0x08,0x0a,0xb0,0xee] +@ vmov.f32 s0, #3.000000e+00 + +@ CHECK: vmov s0, r0 @ encoding: [0x10,0x0a,0x00,0xee] +@ CHECK: vmov s1, r1 @ encoding: [0x90,0x1a,0x00,0xee] +@ CHECK: vmov s2, r2 @ encoding: [0x10,0x2a,0x01,0xee] +@ CHECK: vmov s3, r3 @ encoding: [0x90,0x3a,0x01,0xee] + vmov s0, r0 + vmov s1, r1 + vmov s2, r2 + vmov s3, r3 + +@ CHECK: vmov r0, s0 @ encoding: [0x10,0x0a,0x10,0xee] +@ CHECK: vmov r1, s1 @ encoding: [0x90,0x1a,0x10,0xee] +@ CHECK: vmov r2, s2 @ encoding: [0x10,0x2a,0x11,0xee] +@ CHECK: vmov r3, s3 @ encoding: [0x90,0x3a,0x11,0xee] + vmov r0, s0 + vmov r1, s1 + vmov r2, s2 + vmov r3, s3 + +@ CHECK: vmov r0, r1, d16 @ encoding: [0x30,0x0b,0x51,0xec] + vmov r0, r1, d16 + +@ CHECK: vldr.64 d17, [r0] @ encoding: [0x00,0x1b,0xd0,0xed] + vldr.64 d17, [r0] + +@ CHECK: vldr.64 d1, [r2, #32] @ encoding: [0x08,0x1b,0x92,0xed] +@ CHECK: vldr.64 d1, [r2, #-32] @ encoding: [0x08,0x1b,0x12,0xed] + vldr.64 d1, [r2, #32] + vldr.64 d1, [r2, #-32] + +@ CHECK: vldr.64 d2, [r3] @ encoding: [0x00,0x2b,0x93,0xed] + vldr.64 d2, [r3] + +@ CHECK: vldr.64 d3, [pc] @ encoding: [0x00,0x3b,0x9f,0xed] +@ CHECK: vldr.64 d3, [pc] @ encoding: [0x00,0x3b,0x9f,0xed] +@ CHECK: vldr.64 d3, [pc] @ encoding: [0x00,0x3b,0x9f,0xed] + vldr.64 d3, [pc] + vldr.64 d3, [pc,#0] + vldr.64 d3, [pc,#-0] + +@ CHECK: vldr.32 s13, [r0] @ encoding: [0x00,0x6a,0xd0,0xed] + vldr.32 s13, [r0] + +@ CHECK: vldr.32 s1, [r2, #32] @ encoding: [0x08,0x0a,0xd2,0xed] +@ CHECK: vldr.32 s1, [r2, #-32] @ encoding: [0x08,0x0a,0x52,0xed] + vldr.32 s1, [r2, #32] + vldr.32 s1, [r2, #-32] + +@ CHECK: vldr.32 s2, [r3] @ encoding: [0x00,0x1a,0x93,0xed] + vldr.32 s2, [r3] + +@ CHECK: vldr.32 s5, [pc] @ encoding: [0x00,0x2a,0xdf,0xed] +@ CHECK: vldr.32 s5, [pc] @ encoding: [0x00,0x2a,0xdf,0xed] +@ CHECK: vldr.32 s5, [pc] @ encoding: [0x00,0x2a,0xdf,0xed] + vldr.32 s5, [pc] + vldr.32 s5, [pc,#0] + vldr.32 s5, [pc,#-0] + +@ CHECK: vstr.64 d4, [r1] @ encoding: [0x00,0x4b,0x81,0xed] +@ CHECK: vstr.64 d4, [r1, #24] @ encoding: [0x06,0x4b,0x81,0xed] +@ CHECK: vstr.64 d4, [r1, #-24] @ encoding: [0x06,0x4b,0x01,0xed] + vstr.64 d4, [r1] + vstr.64 d4, [r1, #24] + vstr.64 d4, [r1, #-24] + +@ CHECK: vstr.32 s4, [r1] @ encoding: [0x00,0x2a,0x81,0xed] +@ CHECK: vstr.32 s4, [r1, #24] @ encoding: [0x06,0x2a,0x81,0xed] +@ CHECK: vstr.32 s4, [r1, #-24] @ encoding: [0x06,0x2a,0x01,0xed] + vstr.32 s4, [r1] + vstr.32 s4, [r1, #24] + vstr.32 s4, [r1, #-24] + +@ CHECK: vldmia r1, {d2, d3, d4, d5, d6, d7} @ encoding: [0x0c,0x2b,0x91,0xec] +@ CHECK: vldmia r1, {s2, s3, s4, s5, s6, s7} @ encoding: [0x06,0x1a,0x91,0xec] + vldmia r1, {d2,d3-d6,d7} + vldmia r1, {s2,s3-s6,s7} + +@ CHECK: vstmia r1, {d2, d3, d4, d5, d6, d7} @ encoding: [0x0c,0x2b,0x81,0xec] +@ CHECK: vstmia r1, {s2, s3, s4, s5, s6, s7} @ encoding: [0x06,0x1a,0x81,0xec] + vstmia r1, {d2,d3-d6,d7} + vstmia r1, {s2,s3-s6,s7} + +@ CHECK: vcvtr.s32.f64 s0, d0 @ encoding: [0x40,0x0b,0xbd,0xee] +@ CHECK: vcvtr.s32.f32 s0, s1 @ encoding: [0x60,0x0a,0xbd,0xee] +@ CHECK: vcvtr.u32.f64 s0, d0 @ encoding: [0x40,0x0b,0xbc,0xee] +@ CHECK: vcvtr.u32.f32 s0, s1 @ encoding: [0x60,0x0a,0xbc,0xee] + vcvtr.s32.f64 s0, d0 + vcvtr.s32.f32 s0, s1 + vcvtr.u32.f64 s0, d0 + vcvtr.u32.f32 s0, s1 diff --git a/test/MC/ARM/thumb.s b/test/MC/ARM/thumb.s new file mode 100644 index 0000000..342a390 --- /dev/null +++ b/test/MC/ARM/thumb.s @@ -0,0 +1,70 @@ +@ RUN: llvm-mc -triple thumbv6-apple-darwin -show-encoding < %s | FileCheck %s + .code 16 + +@ CHECK: cmp r1, r2 @ encoding: [0x91,0x42] + cmp r1, r2 + +@ CHECK: pop {r1, r2, r4} @ encoding: [0x16,0xbc] + pop {r1, r2, r4} + +@ CHECK: trap @ encoding: [0xfe,0xde] + trap + +@ CHECK: blx r9 @ encoding: [0xc8,0x47] + blx r9 + +@ CHECK: rev r2, r3 @ encoding: [0x1a,0xba] +@ CHECK: rev16 r3, r4 @ encoding: [0x63,0xba] +@ CHECK: revsh r5, r6 @ encoding: [0xf5,0xba] + rev r2, r3 + rev16 r3, r4 + revsh r5, r6 + +@ CHECK: sxtb r2, r3 @ encoding: [0x5a,0xb2] +@ CHECK: sxth r2, r3 @ encoding: [0x1a,0xb2] + sxtb r2, r3 + sxth r2, r3 + +@ CHECK: tst r4, r5 @ encoding: [0x2c,0x42] + tst r4, r5 + +@ CHECK: uxtb r3, r6 @ encoding: [0xf3,0xb2] +@ CHECK: uxth r3, r6 @ encoding: [0xb3,0xb2] + uxtb r3, r6 + uxth r3, r6 + +@ CHECK: ldr r3, [r1, r2] @ encoding: [0x8b,0x58] + ldr r3, [r1, r2] + +@ CHECK: bkpt #2 @ encoding: [0x02,0xbe] + bkpt #2 + +@ CHECK: mcr p7, #1, r5, c1, c1, #4 @ encoding: [0x21,0xee,0x91,0x57] + mcr p7, #1, r5, c1, c1, #4 + +@ CHECK: mrc p14, #0, r1, c1, c2, #4 @ encoding: [0x11,0xee,0x92,0x1e] + mrc p14, #0, r1, c1, c2, #4 + +@ CHECK: mcrr p7, #1, r5, r4, c1 @ encoding: [0x44,0xec,0x11,0x57] + mcrr p7, #1, r5, r4, c1 + +@ CHECK: mrrc p7, #1, r5, r4, c1 @ encoding: [0x54,0xec,0x11,0x57] + mrrc p7, #1, r5, r4, c1 + +@ CHECK: cdp p7, #1, c1, c1, c1, #4 @ encoding: [0x11,0xee,0x81,0x17] + cdp p7, #1, c1, c1, c1, #4 + +@ CHECK: nop @ encoding: [0x00,0xbf] + nop + +@ CHECK: yield @ encoding: [0x10,0xbf] + yield + +@ CHECK: wfe @ encoding: [0x20,0xbf] + wfe + +@ CHECK: wfi @ encoding: [0x30,0xbf] + wfi + +@ CHECK: cpsie aif @ encoding: [0x67,0xb6] + cpsie aif diff --git a/test/MC/ARM/thumb2.s b/test/MC/ARM/thumb2.s new file mode 100644 index 0000000..cd09311 --- /dev/null +++ b/test/MC/ARM/thumb2.s @@ -0,0 +1,286 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s +@ XFAIL: * +.code 16 + +@ CHECK: adc r1, r1, #171 @ encoding: [0xab,0x01,0x41,0xf1] + adc r1, r1, #171 +@ CHECK: adc r1, r1, #1179666 @ encoding: [0x12,0x11,0x41,0xf1] + adc r1, r1, #1179666 +@ CHECK: adc r1, r1, #872428544 @ encoding: [0x34,0x21,0x41,0xf1] + adc r1, r1, #872428544 +@ CHECK: adc r1, r1, #1448498774 @ encoding: [0x56,0x31,0x41,0xf1] + adc r1, r1, #1448498774 +@ CHECK: adc r1, r1, #66846720 @ encoding: [0x7f,0x71,0x41,0xf1] + adc r1, r1, #66846720 + +@ CHECK: mvn r0, #187 @ encoding: [0xbb,0x00,0x6f,0xf0] + mvn r0, #187 +@ CHECK: mvn r0, #11141290 @ encoding: [0xaa,0x10,0x6f,0xf0] + mvn r0, #11141290 +@ CHECK: mvn r0, #-872363008 @ encoding: [0xcc,0x20,0x6f,0xf0] + mvn r0, #-872363008 +@ CHECK: mvn r0, #1114112 @ encoding: [0x88,0x10,0x6f,0xf4] + mvn r0, #1114112 + +@ CHECK: cmp.w r0, #11141290 @ encoding: [0xaa,0x1f,0xb0,0xf1] + cmp.w r0, #11141290 +@ CHECK: cmp.w r0, #-872363008 @ encoding: [0xcc,0x2f,0xb0,0xf1] + cmp.w r0, #-872363008 +@ CHECK: cmp.w r0, #-572662307 @ encoding: [0xdd,0x3f,0xb0,0xf1] + cmp.w r0, #-572662307 +@ CHECK: cmp.w r0, #1114112 @ encoding: [0x88,0x1f,0xb0,0xf5] + cmp.w r0, #1114112 +@ CHECK: cmp.w r0, r1, lsl #5 @ encoding: [0x41,0x1f,0xb0,0xeb] + cmp.w r0, r1, lsl #5 + +@ CHECK: sxtab r0, r1, r0 @ encoding: [0x80,0xf0,0x41,0xfa] + sxtab r0, r1, r0 @ encoding: [0x80,0xf0,0x41,0xfa] + +@ CHECK: movw r0, #65535 @ encoding: [0xff,0x70,0x4f,0xf6] + movw r0, #65535 +@ CHECK: movw r1, #43777 @ encoding: [0x01,0x31,0x4a,0xf6] + movw r1, #43777 +@ CHECK: movt r1, #427 @ encoding: [0xab,0x11,0xc0,0xf2] + movt r1, #427 +@ CHECK: movw r1, #43792 @ encoding: [0x10,0x31,0x4a,0xf6] + movw r1, #43792 +@ CHECK: movt r1, #4267 @ encoding: [0xab,0x01,0xc0,0xf2] + movt r1, #4267 +@ CHECK: mov.w r0, #66846720 @ encoding: [0x7f,0x70,0x4f,0xf0] + mov.w r0, #66846720 + +@ CHECK: rrx r0, r0 @ encoding: [0x30,0x00,0x4f,0xea] + rrx r0, r0 + +@ CHECK: bfc r0, #4, #20 @ encoding: [0x17,0x10,0x6f,0xf3] + bfc r0, #4, #20 +@ CHECK: bfc r0, #0, #23 @ encoding: [0x16,0x00,0x6f,0xf3] + bfc r0, #0, #23 +@ CHECK: bfc r0, #12, #20 @ encoding: [0x1f,0x30,0x6f,0xf3] + bfc r0, #12, #20 + +@ CHECK: sbfx r0, r0, #7, #11 @ encoding: [0xca,0x10,0x40,0xf3] + sbfx r0, r0, #7, #11 +@ CHECK: ubfx r0, r0, #7, #11 @ encoding: [0xca,0x10,0xc0,0xf3] + ubfx r0, r0, #7, #11 + +@ CHECK: mla r0, r0, r1, r2 @ encoding: [0x01,0x20,0x00,0xfb] + mla r0, r0, r1, r2 +@ CHECK: mls r0, r0, r1, r2 @ encoding: [0x11,0x20,0x00,0xfb] + mls r0, r0, r1, r2 + +@ CHECK: smlabt r0, r1, r2, r0 @ encoding: [0x12,0x00,0x11,0xfb] + smlabt r0, r1, r2, r0 + +@ CHECK: clz r0, r0 @ encoding: [0x80,0xf0,0xb0,0xfa] + clz r0, r0 + +@ CHECK: pkhbt r0, r0, r1, lsl #16 @ encoding: [0x01,0x40,0xc0,0xea] + pkhbt r0, r0, r1, lsl #16 +@ CHECK: pkhbt r0, r0, r1, lsl #12 @ encoding: [0x01,0x30,0xc0,0xea] + pkhbt r0, r0, r1, lsl #16 +@ CHECK: pkhbt r0, r0, r1, lsl #18 @ encoding: [0x81,0x40,0xc0,0xea] + pkhbt r0, r0, r1, lsl #18 +@ CHECK: pkhbt r0, r0, r1 @ encoding: [0x01,0x00,0xc0,0xea] + pkhbt r0, r0, r1 +@ CHECK: pkhtb r0, r0, r1, asr #16 @ encoding: [0x21,0x40,0xc0,0xea] + pkhtb r0, r0, r1, asr #16 +@ CHECK: pkhtb r0, r0, r1, asr #12 @ encoding: [0x21,0x30,0xc0,0xea] + pkhtb r0, r0, r1, asr #12 +@ CHECK: pkhtb r0, r0, r1, asr #18 @ encoding: [0xa1,0x40,0xc0,0xea] + pkhtb r0, r0, r1, asr #18 +@ CHECK: pkhtb r0, r0, r1, asr #22 @ encoding: [0xa1,0x50,0xc0,0xea] + pkhtb r0, r0, r1, asr #22 + +@ CHECK: str.w r0, [r1, #4092] @ encoding: [0xfc,0x0f,0xc1,0xf8] + str.w r0, [r1, #4092] +@ CHECK: str r0, [r1, #-128] @ encoding: [0x80,0x0c,0x41,0xf8] + str r0, [r1, #-128] +@ CHECK: str.w r0, [r1, r2, lsl #2] @ encoding: [0x22,0x00,0x41,0xf8 + str.w r0, [r1, r2, lsl #2] + +@ CHECK: ldr.w r0, [r0, #4092] @ encoding: [0xfc,0x0f,0xd0,0xf8] + ldr.w r0, [r0, #4092] +@ CHECK: ldr r0, [r0, #-128] @ encoding: [0x80,0x0c,0x50,0xf8] + ldr r0, [r0, #-128] +@ CHECK: ldr.w r0, [r0, r1, lsl #2] @ encoding: [0x21,0x00,0x50,0xf8] + ldr.w r0, [r0, r1, lsl #2] + +@ CHECK: str r1, [r0, #16]! @ encoding: [0x10,0x1f,0x40,0xf8] + str r1, [r0, #16]! +@ CHECK: strh r1, [r0, #8]! @ encoding: [0x08,0x1f,0x20,0xf8] + strh r1, [r0, #8]! +@ CHECK: strh r2, [r0], #-4 @ encoding: [0x04,0x29,0x20,0xf8] + strh r2, [r0], #-4 +@ CHECK: str r2, [r0], #-4 @ encoding: [0x04,0x29,0x40,0xf8] + str r2, [r0], #-4 + +@ CHECK: ldr r2, [r0, #16]! @ encoding: [0x10,0x2f,0x50,0xf8] + ldr r2, [r0, #16]! +@ CHECK: ldr r2, [r0, #-64]! @ encoding: [0x40,0x2d,0x50,0xf8] + ldr r2, [r0, #-64]! +@ CHECK: ldrsb r2, [r0, #4]! @ encoding: [0x04,0x2f,0x10,0xf9] + ldrsb r2, [r0, #4]! + +@ CHECK: strb.w r0, [r1, #4092] @ encoding: [0xfc,0x0f,0x81,0xf8] + strb.w r0, [r1, #4092] +@ CHECK: strb r0, [r1, #-128] @ encoding: [0x80,0x0c,0x01,0xf8] + strb r0, [r1, #-128] +@ CHECK: strb.w r0, [r1, r2, lsl #2] @ encoding: [0x22,0x00,0x01,0xf8] + strb.w r0, [r1, r2, lsl #2] +@ CHECK: strh.w r0, [r1, #4092] @ encoding: [0xfc,0x0f,0xa1,0xf8] + strh.w r0, [r1, #4092] +@ CHECK: strh r0, [r1, #-128] @ encoding: [0x80,0x0c,0x21,0xf8] + strh r0, [r1, #-128] +@ CHECK: strh r0, [r1, #-128] @ encoding: [0x80,0x0c,0x21,0xf8] + strh r0, [r1, #-128] +@ CHECK: strh.w r0, [r1, r2, lsl #2] @ encoding: [0x22,0x00,0x21,0xf8] + strh.w r0, [r1, r2, lsl #2] + +@ CHECK: ldrb r0, [r0, #-1] @ encoding: [0x01,0x0c,0x10,0xf8] + ldrb r0, [r0, #-1] +@ CHECK: ldrb r0, [r0, #-128] @ encoding: [0x80,0x0c,0x10,0xf8] + ldrb r0, [r0, #-128] +@ CHECK: ldrb.w r0, [r0, r1, lsl #2] @ encoding: [0x21,0x00,0x10,0xf8] + ldrb.w r0, [r0, r1, lsl #2] +@ CHECK: ldrh.w r0, [r0, #2046] @ encoding: [0xfe,0x07,0xb0,0xf8] + ldrh.w r0, [r0, #2046] +@ CHECK: ldrh r0, [r0, #-128] @ encoding: [0x80,0x0c,0x30,0xf8] + ldrh r0, [r0, #-128] +@ CHECK: ldrh.w r0, [r0, r1, lsl #2] @ encoding: [0x21,0x00,0x30,0xf8] + ldrh.w r0, [r0, r1, lsl #2] +@ CHECK: ldrsb.w r0, [r0] @ encoding: [0x00,0x00,0x90,0xf9] + ldrsb.w r0, [r0] +@ CHECK: ldrsh.w r0, [r0] @ encoding: [0x00,0x00,0xb0,0xf9] + ldrsh.w r0, [r0] +@ CHECK: bfi r0, r0, #5, #7 @ encoding: [0x60,0xf3,0x4b,0x10] + bfi r0, r0, #5, #7 +@ CHECK: isb @ encoding: [0xbf,0xf3,0x6f,0x8f] + isb +@ CHECK: mrs r0, cpsr @ encoding: [0xef,0xf3,0x00,0x80] + mrs r0, cpsr +@ CHECK: vmrs r0, fpscr @ encoding: [0xf1,0xee,0x10,0x0a] + vmrs r0, fpscr +@ CHECK: vmrs r0, fpexc @ encoding: [0xf8,0xee,0x10,0x0a] + vmrs r0, fpexc +@ CHECK: vmrs r0, fpsid @ encoding: [0xf0,0xee,0x10,0x0a] + vmrs r0, fpsid + +@ CHECK: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a] + vmsr fpscr, r0 +@ CHECK: vmsr fpexc, r0 @ encoding: [0xe8,0xee,0x10,0x0a] + vmsr fpexc, r0 +@ CHECK: vmsr fpsid, r0 @ encoding: [0xe0,0xee,0x10,0x0a] + vmsr fpsid, r0 + +@ CHECK: mcr2 p7, #1, r5, c1, c1, #4 @ encoding: [0x21,0xfe,0x91,0x57] + mcr2 p7, #1, r5, c1, c1, #4 + +@ CHECK: mrc2 p14, #0, r1, c1, c2, #4 @ encoding: [0x11,0xfe,0x92,0x1e] + mrc2 p14, #0, r1, c1, c2, #4 + +@ CHECK: mcrr2 p7, #1, r5, r4, c1 @ encoding: [0x44,0xfc,0x11,0x57] + mcrr2 p7, #1, r5, r4, c1 + +@ CHECK: mrrc2 p7, #1, r5, r4, c1 @ encoding: [0x54,0xfc,0x11,0x57] + mrrc2 p7, #1, r5, r4, c1 + +@ CHECK: cdp2 p7, #1, c1, c1, c1, #4 @ encoding: [0x11,0xfe,0x81,0x17] + cdp2 p7, #1, c1, c1, c1, #4 + +@ CHECK: clrex @ encoding: [0xbf,0xf3,0x2f,0x8f] + clrex + +@ CHECK: clz r9, r0 @ encoding: [0xb0,0xfa,0x80,0xf9] + clz r9, r0 + +@ CHECK: qadd r1, r2, r3 @ encoding: [0x83,0xfa,0x82,0xf1] + qadd r1, r2, r3 + +@ CHECK: qsub r1, r2, r3 @ encoding: [0x83,0xfa,0xa2,0xf1] + qsub r1, r2, r3 + +@ CHECK: qdadd r1, r2, r3 @ encoding: [0x83,0xfa,0x92,0xf1] + qdadd r1, r2, r3 + +@ CHECK: qdsub r1, r2, r3 @ encoding: [0x83,0xfa,0xb2,0xf1] + qdsub r1, r2, r3 + +@ CHECK: nop.w @ encoding: [0xaf,0xf3,0x00,0x80] + nop.w + +@ CHECK: yield.w @ encoding: [0xaf,0xf3,0x01,0x80] + yield.w + +@ CHECK: wfe.w @ encoding: [0xaf,0xf3,0x02,0x80] + wfe.w + +@ CHECK: wfi.w @ encoding: [0xaf,0xf3,0x03,0x80] + wfi.w + +@ CHECK: dmb sy @ encoding: [0xbf,0xf3,0x5f,0x8f] + dmb sy +@ CHECK: dmb st @ encoding: [0xbf,0xf3,0x5e,0x8f] + dmb st +@ CHECK: dmb ish @ encoding: [0xbf,0xf3,0x5b,0x8f] + dmb ish +@ CHECK: dmb ishst @ encoding: [0xbf,0xf3,0x5a,0x8f] + dmb ishst +@ CHECK: dmb nsh @ encoding: [0xbf,0xf3,0x57,0x8f] + dmb nsh +@ CHECK: dmb nshst @ encoding: [0xbf,0xf3,0x56,0x8f] + dmb nshst +@ CHECK: dmb osh @ encoding: [0xbf,0xf3,0x53,0x8f] + dmb osh +@ CHECK: dmb oshst @ encoding: [0xbf,0xf3,0x52,0x8f] + dmb oshst + +@ CHECK: dsb sy @ encoding: [0xbf,0xf3,0x4f,0x8f] + dsb sy +@ CHECK: dsb st @ encoding: [0xbf,0xf3,0x4e,0x8f] + dsb st +@ CHECK: dsb ish @ encoding: [0xbf,0xf3,0x4b,0x8f] + dsb ish +@ CHECK: dsb ishst @ encoding: [0xbf,0xf3,0x4a,0x8f] + dsb ishst +@ CHECK: dsb nsh @ encoding: [0xbf,0xf3,0x47,0x8f] + dsb nsh +@ CHECK: dsb nshst @ encoding: [0xbf,0xf3,0x46,0x8f] + dsb nshst +@ CHECK: dsb osh @ encoding: [0xbf,0xf3,0x43,0x8f] + dsb osh +@ CHECK: dsb oshst @ encoding: [0xbf,0xf3,0x42,0x8f] + dsb oshst + +@ CHECK: cpsie.w aif @ encoding: [0xaf,0xf3,0xe0,0x84] + cpsie.w aif +@ CHECK: cps #15 @ encoding: [0xaf,0xf3,0x0f,0x81] + cps #15 +@ CHECK: cpsie.w if, #10 @ encoding: [0xaf,0xf3,0x6a,0x85] + cpsie.w if, #10 + +@ CHECK: msr cpsr_fc, r0 @ encoding: [0x80,0xf3,0x00,0x89] + msr apsr, r0 +@ CHECK: msr cpsr_s, r0 @ encoding: [0x80,0xf3,0x00,0x84] + msr apsr_g, r0 +@ CHECK: msr cpsr_f, r0 @ encoding: [0x80,0xf3,0x00,0x88] + msr apsr_nzcvq, r0 +@ CHECK: msr cpsr_fs, r0 @ encoding: [0x80,0xf3,0x00,0x8c] + msr apsr_nzcvqg, r0 +@ CHECK: msr cpsr_fc, r0 @ encoding: [0x80,0xf3,0x00,0x89] + msr cpsr_fc, r0 +@ CHECK: msr cpsr_c, r0 @ encoding: [0x80,0xf3,0x00,0x81] + msr cpsr_c, r0 +@ CHECK: msr cpsr_x, r0 @ encoding: [0x80,0xf3,0x00,0x82] + msr cpsr_x, r0 +@ CHECK: msr cpsr_fc, r0 @ encoding: [0x80,0xf3,0x00,0x89] + msr cpsr_fc, r0 +@ CHECK: msr cpsr_fsx, r0 @ encoding: [0x80,0xf3,0x00,0x8e] + msr cpsr_fsx, r0 +@ CHECK: msr spsr_fc, r0 @ encoding: [0x90,0xf3,0x00,0x89] + msr spsr_fc, r0 +@ CHECK: msr spsr_fsxc, r0 @ encoding: [0x90,0xf3,0x00,0x8f] + msr spsr_fsxc, r0 +@ CHECK: msr cpsr_fsxc, r0 @ encoding: [0x80,0xf3,0x00,0x8f] + msr cpsr_fsxc, r0 + diff --git a/test/MC/ARM/thumb2_instructions.s b/test/MC/ARM/thumb2_instructions.s new file mode 100644 index 0000000..71cd4ae --- /dev/null +++ b/test/MC/ARM/thumb2_instructions.s @@ -0,0 +1,12 @@ +@ RUN: llvm-mc -triple thumbv7-unknown-unknown -show-encoding %s > %t +@ RUN: FileCheck < %t %s + + .syntax unified + .text + +@ FIXME: This is not the correct instruction representation, but at least we are +@ parsing the ldr to something. +@ +@ CHECK: ldr r0, [r7, #258] + ldr r0, [r7, #-8] + |
