diff options
Diffstat (limited to 'test/MC/ARM/simple-fp-encoding.s')
-rw-r--r-- | test/MC/ARM/simple-fp-encoding.s | 124 |
1 files changed, 71 insertions, 53 deletions
diff --git a/test/MC/ARM/simple-fp-encoding.s b/test/MC/ARM/simple-fp-encoding.s index b592f1e..2a22620 100644 --- a/test/MC/ARM/simple-fp-encoding.s +++ b/test/MC/ARM/simple-fp-encoding.s @@ -1,124 +1,121 @@ @ RUN: llvm-mc -mcpu=cortex-a8 -triple armv7-apple-darwin -show-encoding < %s | FileCheck %s + vadd.f64 d16, d17, d16 + vadd.f32 s0, s1, s0 @ CHECK: vadd.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x71,0xee] - vadd.f64 d16, d17, d16 - @ CHECK: vadd.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x30,0xee] - vadd.f32 s0, s1, s0 + vsub.f64 d16, d17, d16 + vsub.f32 s0, s1, s0 @ CHECK: vsub.f64 d16, d17, d16 @ encoding: [0xe0,0x0b,0x71,0xee] - vsub.f64 d16, d17, d16 - @ CHECK: vsub.f32 s0, s1, s0 @ encoding: [0xc0,0x0a,0x30,0xee] - vsub.f32 s0, s1, s0 -@ CHECK: vdiv.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0xc1,0xee] - vdiv.f64 d16, d17, d16 + vdiv.f64 d16, d17, d16 + vdiv.f32 s0, s1, s0 + vdiv.f32 s5, s7 + vdiv.f64 d5, d7 -@ CHECK: vdiv.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x80,0xee] - vdiv.f32 s0, s1, s0 +@ CHECK: vdiv.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0xc1,0xee] +@ CHECK: vdiv.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x80,0xee] +@ CHECK: vdiv.f32 s5, s5, s7 @ encoding: [0xa3,0x2a,0xc2,0xee] +@ CHECK: vdiv.f64 d5, d5, d7 @ encoding: [0x07,0x5b,0x85,0xee] -@ CHECK: vmul.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x61,0xee] - vmul.f64 d16, d17, d16 -@ CHECK: vmul.f64 d20, d20, d17 @ encoding: [0xa1,0x4b,0x64,0xee] + vmul.f64 d16, d17, d16 vmul.f64 d20, d17 + vmul.f32 s0, s1, s0 + vmul.f32 s11, s21 -@ CHECK: vmul.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x20,0xee] - vmul.f32 s0, s1, s0 -@ CHECK: vmul.f32 s11, s11, s21 @ encoding: [0xaa,0x5a,0x65,0xee] - vmul.f32 s11, s21 +@ CHECK: vmul.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x61,0xee] +@ CHECK: vmul.f64 d20, d20, d17 @ encoding: [0xa1,0x4b,0x64,0xee] +@ CHECK: vmul.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x20,0xee] +@ CHECK: vmul.f32 s11, s11, s21 @ encoding: [0xaa,0x5a,0x65,0xee] -@ CHECK: vnmul.f64 d16, d17, d16 @ encoding: [0xe0,0x0b,0x61,0xee] vnmul.f64 d16, d17, d16 + vnmul.f32 s0, s1, s0 +@ CHECK: vnmul.f64 d16, d17, d16 @ encoding: [0xe0,0x0b,0x61,0xee] @ CHECK: vnmul.f32 s0, s1, s0 @ encoding: [0xc0,0x0a,0x20,0xee] - vnmul.f32 s0, s1, s0 -@ CHECK: vcmpe.f64 d17, d16 @ encoding: [0xe0,0x1b,0xf4,0xee] vcmpe.f64 d17, d16 + vcmpe.f32 s1, s0 +@ CHECK: vcmpe.f64 d17, d16 @ encoding: [0xe0,0x1b,0xf4,0xee] @ CHECK: vcmpe.f32 s1, s0 @ encoding: [0xc0,0x0a,0xf4,0xee] - vcmpe.f32 s1, s0 -@ CHECK: vcmpe.f64 d16, #0 @ encoding: [0xc0,0x0b,0xf5,0xee] vcmpe.f64 d16, #0 + vcmpe.f32 s0, #0 +@ CHECK: vcmpe.f64 d16, #0 @ encoding: [0xc0,0x0b,0xf5,0xee] @ CHECK: vcmpe.f32 s0, #0 @ encoding: [0xc0,0x0a,0xb5,0xee] - vcmpe.f32 s0, #0 -@ CHECK: vabs.f64 d16, d16 @ encoding: [0xe0,0x0b,0xf0,0xee] vabs.f64 d16, d16 + vabs.f32 s0, s0 +@ CHECK: vabs.f64 d16, d16 @ encoding: [0xe0,0x0b,0xf0,0xee] @ CHECK: vabs.f32 s0, s0 @ encoding: [0xc0,0x0a,0xb0,0xee] - vabs.f32 s0, s0 -@ CHECK: vcvt.f32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xb7,0xee] vcvt.f32.f64 s0, d16 + vcvt.f64.f32 d16, s0 +@ CHECK: vcvt.f32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xb7,0xee] @ CHECK: vcvt.f64.f32 d16, s0 @ encoding: [0xc0,0x0a,0xf7,0xee] - vcvt.f64.f32 d16, s0 -@ CHECK: vneg.f64 d16, d16 @ encoding: [0x60,0x0b,0xf1,0xee] vneg.f64 d16, d16 + vneg.f32 s0, s0 +@ CHECK: vneg.f64 d16, d16 @ encoding: [0x60,0x0b,0xf1,0xee] @ CHECK: vneg.f32 s0, s0 @ encoding: [0x40,0x0a,0xb1,0xee] - vneg.f32 s0, s0 -@ CHECK: vsqrt.f64 d16, d16 @ encoding: [0xe0,0x0b,0xf1,0xee] vsqrt.f64 d16, d16 + vsqrt.f32 s0, s0 +@ CHECK: vsqrt.f64 d16, d16 @ encoding: [0xe0,0x0b,0xf1,0xee] @ CHECK: vsqrt.f32 s0, s0 @ encoding: [0xc0,0x0a,0xb1,0xee] - vsqrt.f32 s0, s0 -@ CHECK: vcvt.f64.s32 d16, s0 @ encoding: [0xc0,0x0b,0xf8,0xee] vcvt.f64.s32 d16, s0 - -@ CHECK: vcvt.f32.s32 s0, s0 @ encoding: [0xc0,0x0a,0xb8,0xee] vcvt.f32.s32 s0, s0 - -@ CHECK: vcvt.f64.u32 d16, s0 @ encoding: [0x40,0x0b,0xf8,0xee] vcvt.f64.u32 d16, s0 - -@ CHECK: vcvt.f32.u32 s0, s0 @ encoding: [0x40,0x0a,0xb8,0xee] vcvt.f32.u32 s0, s0 - -@ CHECK: vcvt.s32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xbd,0xee] vcvt.s32.f64 s0, d16 - -@ CHECK: vcvt.s32.f32 s0, s0 @ encoding: [0xc0,0x0a,0xbd,0xee] vcvt.s32.f32 s0, s0 - -@ CHECK: vcvt.u32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xbc,0xee] vcvt.u32.f64 s0, d16 + vcvt.u32.f32 s0, s0 +@ CHECK: vcvt.f64.s32 d16, s0 @ encoding: [0xc0,0x0b,0xf8,0xee] +@ CHECK: vcvt.f32.s32 s0, s0 @ encoding: [0xc0,0x0a,0xb8,0xee] +@ CHECK: vcvt.f64.u32 d16, s0 @ encoding: [0x40,0x0b,0xf8,0xee] +@ CHECK: vcvt.f32.u32 s0, s0 @ encoding: [0x40,0x0a,0xb8,0xee] +@ CHECK: vcvt.s32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xbd,0xee] +@ CHECK: vcvt.s32.f32 s0, s0 @ encoding: [0xc0,0x0a,0xbd,0xee] +@ CHECK: vcvt.u32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xbc,0xee] @ CHECK: vcvt.u32.f32 s0, s0 @ encoding: [0xc0,0x0a,0xbc,0xee] - vcvt.u32.f32 s0, s0 -@ CHECK: vmla.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0x42,0xee] + vmla.f64 d16, d18, d17 + vmla.f32 s1, s2, s0 +@ CHECK: vmla.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0x42,0xee] @ CHECK: vmla.f32 s1, s2, s0 @ encoding: [0x00,0x0a,0x41,0xee] - vmla.f32 s1, s2, s0 -@ CHECK: vmls.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0x42,0xee] vmls.f64 d16, d18, d17 + vmls.f32 s1, s2, s0 +@ CHECK: vmls.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0x42,0xee] @ CHECK: vmls.f32 s1, s2, s0 @ encoding: [0x40,0x0a,0x41,0xee] - vmls.f32 s1, s2, s0 -@ CHECK: vnmla.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0x52,0xee] vnmla.f64 d16, d18, d17 + vnmla.f32 s1, s2, s0 +@ CHECK: vnmla.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0x52,0xee] @ CHECK: vnmla.f32 s1, s2, s0 @ encoding: [0x40,0x0a,0x51,0xee] - vnmla.f32 s1, s2, s0 -@ CHECK: vnmls.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0x52,0xee] vnmls.f64 d16, d18, d17 + vnmls.f32 s1, s2, s0 +@ CHECK: vnmls.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0x52,0xee] @ CHECK: vnmls.f32 s1, s2, s0 @ encoding: [0x00,0x0a,0x51,0xee] - vnmls.f32 s1, s2, s0 vmrs APSR_nzcv, fpscr vmrs apsr_nzcv, fpscr @@ -199,6 +196,27 @@ @ CHECK: vmov r0, r1, d16 @ encoding: [0x30,0x0b,0x51,0xec] vmov r0, r1, d16 +@ Between two single precision registers and two core registers + vmov s3, s4, r1, r2 + vmov s2, s3, r1, r2 + vmov r1, r2, s3, s4 + vmov r1, r2, s2, s3 +@ CHECK: vmov s3, s4, r1, r2 @ encoding: [0x31,0x1a,0x42,0xec] +@ CHECK: vmov s2, s3, r1, r2 @ encoding: [0x11,0x1a,0x42,0xec] +@ CHECK: vmov r1, r2, s3, s4 @ encoding: [0x31,0x1a,0x52,0xec] +@ CHECK: vmov r1, r2, s2, s3 @ encoding: [0x11,0x1a,0x52,0xec] + +@ Between one double precision register and two core registers + vmov d15, r1, r2 + vmov d16, r1, r2 + vmov r1, r2, d15 + vmov r1, r2, d16 +@ CHECK: vmov d15, r1, r2 @ encoding: [0x1f,0x1b,0x42,0xec] +@ CHECK: vmov d16, r1, r2 @ encoding: [0x30,0x1b,0x42,0xec] +@ CHECK: vmov r1, r2, d15 @ encoding: [0x1f,0x1b,0x52,0xec] +@ CHECK: vmov r1, r2, d16 @ encoding: [0x30,0x1b,0x52,0xec] + + @ CHECK: vldr d17, [r0] @ encoding: [0x00,0x1b,0xd0,0xed] @ CHECK: vldr s0, [lr] @ encoding: [0x00,0x0a,0x9e,0xed] @ CHECK: vldr d0, [lr] @ encoding: [0x00,0x0b,0x9e,0xed] |