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-rw-r--r--test/CodeGen/ARM/armv4.ll13
-rw-r--r--test/CodeGen/ARM/indirectbr.ll4
-rw-r--r--test/CodeGen/MBlaze/cc.ll28
-rw-r--r--test/CodeGen/MSP430/AddrMode-bis-rx.ll4
-rw-r--r--test/CodeGen/MSP430/AddrMode-bis-xr.ll4
-rw-r--r--test/CodeGen/MSP430/AddrMode-mov-rx.ll4
-rw-r--r--test/CodeGen/MSP430/AddrMode-mov-xr.ll4
-rw-r--r--test/CodeGen/PowerPC/2010-03-09-indirect-call.ll19
-rw-r--r--test/CodeGen/PowerPC/indirectbr.ll12
-rw-r--r--test/CodeGen/Thumb/2009-08-20-ISelBug.ll2
-rw-r--r--test/CodeGen/Thumb2/2010-03-08-addi12-ccout.ll266
-rw-r--r--test/CodeGen/Thumb2/machine-licm.ll6
-rw-r--r--test/CodeGen/X86/2007-10-16-IllegalAsm.ll272
-rw-r--r--test/CodeGen/X86/2009-08-06-inlineasm.ll10
-rw-r--r--test/CodeGen/X86/aliases.ll4
-rw-r--r--test/CodeGen/X86/machine-cse.ll39
-rw-r--r--test/CodeGen/X86/pre-split6.ll2
-rw-r--r--test/CodeGen/X86/sibcall.ll (renamed from test/CodeGen/X86/tailcall2.ll)0
-rw-r--r--test/CodeGen/X86/stack-color-with-reg.ll3
-rw-r--r--test/CodeGen/XCore/addsub64.ll38
-rw-r--r--test/CodeGen/XCore/ladd_lsub_combine.ll67
-rw-r--r--test/CodeGen/XCore/mul64.ll39
22 files changed, 522 insertions, 318 deletions
diff --git a/test/CodeGen/ARM/armv4.ll b/test/CodeGen/ARM/armv4.ll
new file mode 100644
index 0000000..49b129da
--- /dev/null
+++ b/test/CodeGen/ARM/armv4.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -mtriple=arm-unknown-eabi | FileCheck %s -check-prefix=THUMB
+; RUN: llc < %s -mtriple=arm-unknown-eabi -mcpu=strongarm | FileCheck %s -check-prefix=ARM
+; RUN: llc < %s -mtriple=arm-unknown-eabi -mcpu=cortex-a8 | FileCheck %s -check-prefix=THUMB
+; RUN: llc < %s -mtriple=arm-unknown-eabi -mattr=+v6 | FileCheck %s -check-prefix=THUMB
+; RUN: llc < %s -mtriple=armv4-unknown-eabi | FileCheck %s -check-prefix=ARM
+; RUN: llc < %s -mtriple=armv4t-unknown-eabi | FileCheck %s -check-prefix=THUMB
+
+define arm_aapcscc i32 @test(i32 %a) nounwind readnone {
+entry:
+; ARM: mov pc
+; THUMB: bx
+ ret i32 %a
+}
diff --git a/test/CodeGen/ARM/indirectbr.ll b/test/CodeGen/ARM/indirectbr.ll
index 5135d03..f050337 100644
--- a/test/CodeGen/ARM/indirectbr.ll
+++ b/test/CodeGen/ARM/indirectbr.ll
@@ -15,14 +15,14 @@ entry:
; indirect branch gets duplicated here
; ARM: bx
; THUMB: mov pc, r1
-; THUMB2: mov pc, r1
+; THUMB2: mov pc, r2
br i1 %1, label %bb3, label %bb2
bb2: ; preds = %entry, %bb3
%gotovar.4.0 = phi i8* [ %gotovar.4.0.pre, %bb3 ], [ %0, %entry ] ; <i8*> [#uses=1]
; ARM: bx
; THUMB: mov pc, r1
-; THUMB2: mov pc, r1
+; THUMB2: mov pc, r2
indirectbr i8* %gotovar.4.0, [label %L5, label %L4, label %L3, label %L2, label %L1]
bb3: ; preds = %entry
diff --git a/test/CodeGen/MBlaze/cc.ll b/test/CodeGen/MBlaze/cc.ll
index de55728..aaa918f 100644
--- a/test/CodeGen/MBlaze/cc.ll
+++ b/test/CodeGen/MBlaze/cc.ll
@@ -101,7 +101,7 @@ define i32 @params7_32bitret(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f,
i32 %g) {
; CHECK: params7_32bitret:
ret i32 %g
- ; CHECK: {{lwi? r3, r1, 8}}
+ ; CHECK: {{lwi? r3, r1, 32}}
; CHECK-NOT: {{.* r4, .*, .*}}
; CHECK: rtsd
}
@@ -110,7 +110,7 @@ define i32 @params8_32bitret(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f,
i32 %g, i32 %h) {
; CHECK: params8_32bitret:
ret i32 %h
- ; CHECK: {{lwi? r3, r1, 12}}
+ ; CHECK: {{lwi? r3, r1, 36}}
; CHECK-NOT: {{.* r4, .*, .*}}
; CHECK: rtsd
}
@@ -119,7 +119,7 @@ define i32 @params9_32bitret(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f,
i32 %g, i32 %h, i32 %i) {
; CHECK: params9_32bitret:
ret i32 %i
- ; CHECK: {{lwi? r3, r1, 16}}
+ ; CHECK: {{lwi? r3, r1, 40}}
; CHECK-NOT: {{.* r4, .*, .*}}
; CHECK: rtsd
}
@@ -128,7 +128,7 @@ define i32 @params10_32bitret(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f,
i32 %g, i32 %h, i32 %i, i32 %j) {
; CHECK: params10_32bitret:
ret i32 %j
- ; CHECK: {{lwi? r3, r1, 20}}
+ ; CHECK: {{lwi? r3, r1, 44}}
; CHECK-NOT: {{.* r4, .*, .*}}
; CHECK: rtsd
}
@@ -243,7 +243,7 @@ define void @testing() {
%tmp.11 = call i32 @params7_32bitret(i32 1, i32 2, i32 3, i32 4, i32 5,
i32 6, i32 7)
- ; CHECK: {{swi? .*, r1, 4}}
+ ; CHECK: {{swi? .*, r1, 28}}
; CHECK: {{.* r5, .*, .*}}
; CHECK: {{.* r6, .*, .*}}
; CHECK: {{.* r7, .*, .*}}
@@ -259,8 +259,8 @@ define void @testing() {
%tmp.12 = call i32 @params8_32bitret(i32 1, i32 2, i32 3, i32 4, i32 5,
i32 6, i32 7, i32 8)
- ; CHECK: {{swi? .*, r1, 4}}
- ; CHECK: {{swi? .*, r1, 8}}
+ ; CHECK: {{swi? .*, r1, 28}}
+ ; CHECK: {{swi? .*, r1, 32}}
; CHECK: {{.* r5, .*, .*}}
; CHECK: {{.* r6, .*, .*}}
; CHECK: {{.* r7, .*, .*}}
@@ -276,9 +276,9 @@ define void @testing() {
%tmp.13 = call i32 @params9_32bitret(i32 1, i32 2, i32 3, i32 4, i32 5,
i32 6, i32 7, i32 8, i32 9)
- ; CHECK: {{swi? .*, r1, 4}}
- ; CHECK: {{swi? .*, r1, 8}}
- ; CHECK: {{swi? .*, r1, 12}}
+ ; CHECK: {{swi? .*, r1, 28}}
+ ; CHECK: {{swi? .*, r1, 32}}
+ ; CHECK: {{swi? .*, r1, 36}}
; CHECK: {{.* r5, .*, .*}}
; CHECK: {{.* r6, .*, .*}}
; CHECK: {{.* r7, .*, .*}}
@@ -294,10 +294,10 @@ define void @testing() {
%tmp.14 = call i32 @params10_32bitret(i32 1, i32 2, i32 3, i32 4, i32 5,
i32 6, i32 7, i32 8, i32 9, i32 10)
- ; CHECK: {{swi? .*, r1, 4}}
- ; CHECK: {{swi? .*, r1, 8}}
- ; CHECK: {{swi? .*, r1, 12}}
- ; CHECK: {{swi? .*, r1, 16}}
+ ; CHECK: {{swi? .*, r1, 28}}
+ ; CHECK: {{swi? .*, r1, 32}}
+ ; CHECK: {{swi? .*, r1, 36}}
+ ; CHECK: {{swi? .*, r1, 40}}
; CHECK: {{.* r5, .*, .*}}
; CHECK: {{.* r6, .*, .*}}
; CHECK: {{.* r7, .*, .*}}
diff --git a/test/CodeGen/MSP430/AddrMode-bis-rx.ll b/test/CodeGen/MSP430/AddrMode-bis-rx.ll
index 115464d..4f9a724 100644
--- a/test/CodeGen/MSP430/AddrMode-bis-rx.ll
+++ b/test/CodeGen/MSP430/AddrMode-bis-rx.ll
@@ -29,7 +29,7 @@ define i8 @am3(i8 %x, i16 %n) nounwind {
ret i8 %3
}
; CHECK: am3:
-; CHECK: bis.b &bar(r14), r15
+; CHECK: bis.b bar(r14), r15
define i16 @am4(i16 %x) nounwind {
%1 = volatile load i16* inttoptr(i16 32 to i16*)
@@ -70,5 +70,5 @@ define i8 @am7(i8 %x, i16 %n) nounwind {
ret i8 %4
}
; CHECK: am7:
-; CHECK: bis.b &duh+2(r14), r15
+; CHECK: bis.b duh+2(r14), r15
diff --git a/test/CodeGen/MSP430/AddrMode-bis-xr.ll b/test/CodeGen/MSP430/AddrMode-bis-xr.ll
index 3baf332..17ebd87 100644
--- a/test/CodeGen/MSP430/AddrMode-bis-xr.ll
+++ b/test/CodeGen/MSP430/AddrMode-bis-xr.ll
@@ -32,7 +32,7 @@ define void @am3(i16 %i, i8 %x) nounwind {
ret void
}
; CHECK: am3:
-; CHECK: bis.b r14, &bar(r15)
+; CHECK: bis.b r14, bar(r15)
define void @am4(i16 %x) nounwind {
%1 = volatile load i16* inttoptr(i16 32 to i16*)
@@ -77,5 +77,5 @@ define void @am7(i16 %n, i8 %x) nounwind {
ret void
}
; CHECK: am7:
-; CHECK: bis.b r14, &duh+2(r15)
+; CHECK: bis.b r14, duh+2(r15)
diff --git a/test/CodeGen/MSP430/AddrMode-mov-rx.ll b/test/CodeGen/MSP430/AddrMode-mov-rx.ll
index 9144f9a..6676b88 100644
--- a/test/CodeGen/MSP430/AddrMode-mov-rx.ll
+++ b/test/CodeGen/MSP430/AddrMode-mov-rx.ll
@@ -26,7 +26,7 @@ define i8 @am3(i16 %n) nounwind {
ret i8 %2
}
; CHECK: am3:
-; CHECK: mov.b &bar(r15), r15
+; CHECK: mov.b bar(r15), r15
define i16 @am4() nounwind {
%1 = volatile load i16* inttoptr(i16 32 to i16*)
@@ -63,5 +63,5 @@ define i8 @am7(i16 %n) nounwind {
ret i8 %3
}
; CHECK: am7:
-; CHECK: mov.b &duh+2(r15), r15
+; CHECK: mov.b duh+2(r15), r15
diff --git a/test/CodeGen/MSP430/AddrMode-mov-xr.ll b/test/CodeGen/MSP430/AddrMode-mov-xr.ll
index 333c800..4b327b0 100644
--- a/test/CodeGen/MSP430/AddrMode-mov-xr.ll
+++ b/test/CodeGen/MSP430/AddrMode-mov-xr.ll
@@ -26,7 +26,7 @@ define void @am3(i16 %i, i8 %a) nounwind {
ret void
}
; CHECK: am3:
-; CHECK: mov.b r14, &bar(r15)
+; CHECK: mov.b r14, bar(r15)
define void @am4(i16 %a) nounwind {
volatile store i16 %a, i16* inttoptr(i16 32 to i16*)
@@ -63,5 +63,5 @@ define void @am7(i16 %n, i8 %a) nounwind {
ret void
}
; CHECK: am7:
-; CHECK: mov.b r14, &duh+2(r15)
+; CHECK: mov.b r14, duh+2(r15)
diff --git a/test/CodeGen/PowerPC/2010-03-09-indirect-call.ll b/test/CodeGen/PowerPC/2010-03-09-indirect-call.ll
new file mode 100644
index 0000000..d094509
--- /dev/null
+++ b/test/CodeGen/PowerPC/2010-03-09-indirect-call.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -march=ppc32 -mcpu=g5 -mtriple=powerpc-apple-darwin10.0 | FileCheck %s
+; ModuleID = 'nn.c'
+target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
+target triple = "powerpc-apple-darwin11.0"
+; Indirect calls must use R12 on Darwin (i.e., R12 must contain the address of
+; the function being called; the mtctr is not required to use it).
+
+@p = external global void (...)* ; <void (...)**> [#uses=1]
+
+define void @foo() nounwind ssp {
+entry:
+; CHECK: mtctr r12
+ %0 = load void (...)** @p, align 4 ; <void (...)*> [#uses=1]
+ call void (...)* %0() nounwind
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
diff --git a/test/CodeGen/PowerPC/indirectbr.ll b/test/CodeGen/PowerPC/indirectbr.ll
index 2094e10..233d923 100644
--- a/test/CodeGen/PowerPC/indirectbr.ll
+++ b/test/CodeGen/PowerPC/indirectbr.ll
@@ -43,13 +43,13 @@ L2: ; preds = %L3, %bb2
L1: ; preds = %L2, %bb2
%res.3 = phi i32 [ %phitmp, %L2 ], [ 2, %bb2 ] ; <i32> [#uses=1]
-; PIC: addis r5, r4, ha16(L_BA4__foo_L5-"L1$pb")
+; PIC: addis r4, r4, ha16(L_BA4__foo_L5-"L1$pb")
; PIC: li r6, lo16(L_BA4__foo_L5-"L1$pb")
-; PIC: add r5, r5, r6
-; PIC: stw r5
-; STATIC: li r4, lo16(L_BA4__foo_L5)
-; STATIC: addis r4, r4, ha16(L_BA4__foo_L5)
-; STATIC: stw r4
+; PIC: add r4, r4, r6
+; PIC: stw r4
+; STATIC: li r5, lo16(L_BA4__foo_L5)
+; STATIC: addis r5, r5, ha16(L_BA4__foo_L5)
+; STATIC: stw r5
store i8* blockaddress(@foo, %L5), i8** @nextaddr, align 4
ret i32 %res.3
}
diff --git a/test/CodeGen/Thumb/2009-08-20-ISelBug.ll b/test/CodeGen/Thumb/2009-08-20-ISelBug.ll
index c31b65b..72c9e62 100644
--- a/test/CodeGen/Thumb/2009-08-20-ISelBug.ll
+++ b/test/CodeGen/Thumb/2009-08-20-ISelBug.ll
@@ -11,7 +11,7 @@
define arm_apcscc i32 @t(%struct.asl_file_t* %s, i64 %off, i64* %out) nounwind optsize {
; CHECK: t:
-; CHECK: adds r3, #8
+; CHECK: adds r0, #8
entry:
%val = alloca i64, align 4 ; <i64*> [#uses=3]
%0 = icmp eq %struct.asl_file_t* %s, null ; <i1> [#uses=1]
diff --git a/test/CodeGen/Thumb2/2010-03-08-addi12-ccout.ll b/test/CodeGen/Thumb2/2010-03-08-addi12-ccout.ll
new file mode 100644
index 0000000..54f4122
--- /dev/null
+++ b/test/CodeGen/Thumb2/2010-03-08-addi12-ccout.ll
@@ -0,0 +1,266 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin
+
+@.str41196 = external constant [2 x i8], align 4 ; <[2 x i8]*> [#uses=1]
+
+declare arm_apcscc void @syStopraw(i32) nounwind
+
+declare arm_apcscc i32 @SyFopen(i8*, i8*) nounwind
+
+declare arm_apcscc i8* @SyFgets(i8*, i32) nounwind
+
+define arm_apcscc void @SyHelp(i8* nocapture %topic, i32 %fin) nounwind {
+entry:
+ %line = alloca [256 x i8], align 4 ; <[256 x i8]*> [#uses=1]
+ %secname = alloca [1024 x i8], align 4 ; <[1024 x i8]*> [#uses=0]
+ %last = alloca [256 x i8], align 4 ; <[256 x i8]*> [#uses=1]
+ %last2 = alloca [256 x i8], align 4 ; <[256 x i8]*> [#uses=1]
+ br i1 undef, label %bb, label %bb2
+
+bb: ; preds = %entry
+ br i1 undef, label %bb2, label %bb3
+
+bb2: ; preds = %bb, %entry
+ br label %bb3
+
+bb3: ; preds = %bb2, %bb
+ %storemerge = phi i32 [ 0, %bb2 ], [ 1, %bb ] ; <i32> [#uses=1]
+ br i1 undef, label %bb19, label %bb20
+
+bb19: ; preds = %bb3
+ br label %bb20
+
+bb20: ; preds = %bb19, %bb3
+ br i1 undef, label %bb25, label %bb26
+
+bb25: ; preds = %bb20
+ br label %bb26
+
+bb26: ; preds = %bb25, %bb20
+ %offset.2 = phi i32 [ -2, %bb25 ], [ 0, %bb20 ] ; <i32> [#uses=1]
+ br i1 undef, label %bb.nph508, label %bb49
+
+bb.nph508: ; preds = %bb26
+ unreachable
+
+bb49: ; preds = %bb26
+ br i1 undef, label %bb51, label %bb50
+
+bb50: ; preds = %bb49
+ br i1 undef, label %bb51, label %bb104
+
+bb51: ; preds = %bb50, %bb49
+ unreachable
+
+bb104: ; preds = %bb50
+ br i1 undef, label %bb106, label %bb105
+
+bb105: ; preds = %bb104
+ br i1 undef, label %bb106, label %bb161
+
+bb106: ; preds = %bb105, %bb104
+ unreachable
+
+bb161: ; preds = %bb105
+ br i1 false, label %bb163, label %bb162
+
+bb162: ; preds = %bb161
+ br i1 undef, label %bb163, label %bb224
+
+bb163: ; preds = %bb162, %bb161
+ unreachable
+
+bb224: ; preds = %bb162
+ %0 = call arm_apcscc i32 @SyFopen(i8* undef, i8* getelementptr inbounds ([2 x i8]* @.str41196, i32 0, i32 0)) nounwind ; <i32> [#uses=2]
+ br i1 false, label %bb297, label %bb300
+
+bb297: ; preds = %bb224
+ unreachable
+
+bb300: ; preds = %bb224
+ %1 = icmp eq i32 %offset.2, -1 ; <i1> [#uses=1]
+ br label %bb440
+
+bb307: ; preds = %isdigit1498.exit67
+ br label %bb308
+
+bb308: ; preds = %bb440, %bb307
+ br i1 undef, label %bb309, label %isdigit1498.exit67
+
+isdigit1498.exit67: ; preds = %bb308
+ br i1 undef, label %bb309, label %bb307
+
+bb309: ; preds = %isdigit1498.exit67, %bb308
+ br i1 undef, label %bb310, label %bb313
+
+bb310: ; preds = %bb309
+ br label %bb313
+
+bb313: ; preds = %bb310, %bb309
+ br i1 false, label %bb318, label %bb317
+
+bb317: ; preds = %bb313
+ %2 = icmp sgt i8 undef, -1 ; <i1> [#uses=1]
+ br i1 %2, label %bb.i.i73, label %bb1.i.i74
+
+bb.i.i73: ; preds = %bb317
+ br i1 false, label %bb318, label %bb329.outer
+
+bb1.i.i74: ; preds = %bb317
+ unreachable
+
+bb318: ; preds = %bb.i.i73, %bb313
+ ret void
+
+bb329.outer: ; preds = %bb.i.i73
+ br i1 undef, label %bb333, label %bb329.us.us
+
+bb329.us.us: ; preds = %bb329.us.us, %bb329.outer
+ br i1 undef, label %bb333, label %bb329.us.us
+
+bb333: ; preds = %bb329.us.us, %bb329.outer
+ %match.0.lcssa = phi i32 [ undef, %bb329.us.us ], [ 2, %bb329.outer ] ; <i32> [#uses=2]
+ br i1 undef, label %bb335, label %bb388
+
+bb335: ; preds = %bb333
+ %3 = and i1 undef, %1 ; <i1> [#uses=1]
+ br i1 %3, label %bb339, label %bb348
+
+bb339: ; preds = %bb335
+ br i1 false, label %bb340, label %bb345
+
+bb340: ; preds = %bb339
+ br i1 undef, label %return, label %bb341
+
+bb341: ; preds = %bb340
+ ret void
+
+bb345: ; preds = %bb345, %bb339
+ %4 = phi i8 [ %5, %bb345 ], [ undef, %bb339 ] ; <i8> [#uses=0]
+ %indvar670 = phi i32 [ %tmp673, %bb345 ], [ 0, %bb339 ] ; <i32> [#uses=1]
+ %tmp673 = add i32 %indvar670, 1 ; <i32> [#uses=2]
+ %scevgep674 = getelementptr [256 x i8]* %last, i32 0, i32 %tmp673 ; <i8*> [#uses=1]
+ %5 = load i8* %scevgep674, align 1 ; <i8> [#uses=1]
+ br i1 undef, label %bb347, label %bb345
+
+bb347: ; preds = %bb345
+ br label %bb348
+
+bb348: ; preds = %bb347, %bb335
+ br i1 false, label %bb352, label %bb356
+
+bb352: ; preds = %bb348
+ unreachable
+
+bb356: ; preds = %bb348
+ br i1 undef, label %bb360, label %bb369
+
+bb360: ; preds = %bb356
+ br i1 false, label %bb361, label %bb366
+
+bb361: ; preds = %bb360
+ br i1 undef, label %return, label %bb362
+
+bb362: ; preds = %bb361
+ ret void
+
+bb366: ; preds = %bb366, %bb360
+ %indvar662 = phi i32 [ %tmp665, %bb366 ], [ 0, %bb360 ] ; <i32> [#uses=1]
+ %tmp665 = add i32 %indvar662, 1 ; <i32> [#uses=2]
+ %scevgep666 = getelementptr [256 x i8]* %last2, i32 0, i32 %tmp665 ; <i8*> [#uses=1]
+ %6 = load i8* %scevgep666, align 1 ; <i8> [#uses=0]
+ br i1 false, label %bb368, label %bb366
+
+bb368: ; preds = %bb366
+ br label %bb369
+
+bb369: ; preds = %bb368, %bb356
+ br i1 undef, label %bb373, label %bb388
+
+bb373: ; preds = %bb383, %bb369
+ %7 = call arm_apcscc i8* @SyFgets(i8* undef, i32 %0) nounwind ; <i8*> [#uses=1]
+ %8 = icmp eq i8* %7, null ; <i1> [#uses=1]
+ br i1 %8, label %bb375, label %bb383
+
+bb375: ; preds = %bb373
+ %9 = icmp eq i32 %storemerge, 0 ; <i1> [#uses=1]
+ br i1 %9, label %return, label %bb376
+
+bb376: ; preds = %bb375
+ ret void
+
+bb383: ; preds = %bb373
+ %10 = load i8* undef, align 1 ; <i8> [#uses=1]
+ %cond1 = icmp eq i8 %10, 46 ; <i1> [#uses=1]
+ br i1 %cond1, label %bb373, label %bb388
+
+bb388: ; preds = %bb383, %bb369, %bb333
+ %match.1140 = phi i32 [ %match.0.lcssa, %bb369 ], [ 0, %bb333 ], [ %match.0.lcssa, %bb383 ] ; <i32> [#uses=1]
+ br label %bb391
+
+bb390: ; preds = %isdigit1498.exit83, %bb392
+ %indvar.next725 = add i32 %indvar724, 1 ; <i32> [#uses=1]
+ br label %bb391
+
+bb391: ; preds = %bb390, %bb388
+ %indvar724 = phi i32 [ %indvar.next725, %bb390 ], [ 0, %bb388 ] ; <i32> [#uses=2]
+ %11 = load i8* undef, align 1 ; <i8> [#uses=0]
+ br i1 false, label %bb395, label %bb392
+
+bb392: ; preds = %bb391
+ br i1 undef, label %bb390, label %isdigit1498.exit83
+
+isdigit1498.exit83: ; preds = %bb392
+ br i1 undef, label %bb390, label %bb395
+
+bb394: ; preds = %isdigit1498.exit87
+ br label %bb395
+
+bb395: ; preds = %bb394, %isdigit1498.exit83, %bb391
+ %storemerge14.sum = add i32 %indvar724, undef ; <i32> [#uses=1]
+ %p.26 = getelementptr [256 x i8]* %line, i32 0, i32 %storemerge14.sum ; <i8*> [#uses=1]
+ br i1 undef, label %bb400, label %isdigit1498.exit87
+
+isdigit1498.exit87: ; preds = %bb395
+ br i1 false, label %bb400, label %bb394
+
+bb400: ; preds = %isdigit1498.exit87, %bb395
+ br i1 undef, label %bb402, label %bb403
+
+bb402: ; preds = %bb400
+ %12 = getelementptr inbounds i8* %p.26, i32 undef ; <i8*> [#uses=1]
+ br label %bb403
+
+bb403: ; preds = %bb402, %bb400
+ %p.29 = phi i8* [ %12, %bb402 ], [ undef, %bb400 ] ; <i8*> [#uses=0]
+ br i1 undef, label %bb405, label %bb404
+
+bb404: ; preds = %bb403
+ br i1 undef, label %bb405, label %bb407
+
+bb405: ; preds = %bb404, %bb403
+ br i1 undef, label %return, label %bb406
+
+bb406: ; preds = %bb405
+ call arm_apcscc void @syStopraw(i32 %fin) nounwind
+ ret void
+
+bb407: ; preds = %bb404
+ %cond = icmp eq i32 %match.1140, 2 ; <i1> [#uses=1]
+ br i1 %cond, label %bb408, label %bb428
+
+bb408: ; preds = %bb407
+ unreachable
+
+bb428: ; preds = %bb407
+ br label %bb440
+
+bb440: ; preds = %bb428, %bb300
+ %13 = call arm_apcscc i8* @SyFgets(i8* undef, i32 %0) nounwind ; <i8*> [#uses=0]
+ br i1 false, label %bb442, label %bb308
+
+bb442: ; preds = %bb440
+ unreachable
+
+return: ; preds = %bb405, %bb375, %bb361, %bb340
+ ret void
+}
diff --git a/test/CodeGen/Thumb2/machine-licm.ll b/test/CodeGen/Thumb2/machine-licm.ll
index 9ab19e9..53ff537 100644
--- a/test/CodeGen/Thumb2/machine-licm.ll
+++ b/test/CodeGen/Thumb2/machine-licm.ll
@@ -18,9 +18,8 @@ entry:
bb.nph: ; preds = %entry
; CHECK: BB#1
; CHECK: ldr.n r2, LCPI1_0
-; CHECK: ldr r3, [r2]
-; CHECK: ldr r3, [r3]
; CHECK: ldr r2, [r2]
+; CHECK: ldr r3, [r2]
; CHECK: LBB1_2
; CHECK: LCPI1_0:
; CHECK-NOT: LCPI1_1:
@@ -29,9 +28,8 @@ bb.nph: ; preds = %entry
; PIC: BB#1
; PIC: ldr.n r2, LCPI1_0
; PIC: add r2, pc
-; PIC: ldr r3, [r2]
-; PIC: ldr r3, [r3]
; PIC: ldr r2, [r2]
+; PIC: ldr r3, [r2]
; PIC: LBB1_2
; PIC: LCPI1_0:
; PIC-NOT: LCPI1_1:
diff --git a/test/CodeGen/X86/2007-10-16-IllegalAsm.ll b/test/CodeGen/X86/2007-10-16-IllegalAsm.ll
deleted file mode 100644
index 6d0cb47..0000000
--- a/test/CodeGen/X86/2007-10-16-IllegalAsm.ll
+++ /dev/null
@@ -1,272 +0,0 @@
-; RUN: llc < %s -mtriple=x86_64-linux-gnu | grep movb | not grep x
-; PR1734
-
- %struct.CUMULATIVE_ARGS = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
- %struct.eh_status = type opaque
- %struct.emit_status = type { i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.sequence_stack*, i32, %struct.location_t, i32, i8*, %struct.rtx_def** }
- %struct.expr_status = type { i32, i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def* }
- %struct.function = type { %struct.eh_status*, %struct.expr_status*, %struct.emit_status*, %struct.varasm_status*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.function*, i32, i32, i32, i32, %struct.rtx_def*, %struct.CUMULATIVE_ARGS, %struct.rtx_def*, %struct.rtx_def*, %struct.initial_value_struct*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, i8, i32, i64, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, %struct.varray_head_tag*, %struct.temp_slot*, i32, %struct.var_refs_queue*, i32, i32, %struct.rtvec_def*, %struct.tree_node*, i32, i32, i32, %struct.machine_function*, i32, i32, i8, i8, %struct.language_function*, %struct.rtx_def*, i32, i32, i32, i32, %struct.location_t, %struct.varray_head_tag*, %struct.tree_node*, %struct.tree_node*, i8, i8, i8 }
- %struct.initial_value_struct = type opaque
- %struct.lang_decl = type opaque
- %struct.lang_type = type opaque
- %struct.language_function = type opaque
- %struct.location_t = type { i8*, i32 }
- %struct.machine_function = type { %struct.stack_local_entry*, i8*, %struct.rtx_def*, i32, i32, i32, i32, i32 }
- %struct.rtunion = type { i8* }
- %struct.rtvec_def = type { i32, [1 x %struct.rtx_def*] }
- %struct.rtx_def = type { i16, i8, i8, %struct.u }
- %struct.sequence_stack = type { %struct.rtx_def*, %struct.rtx_def*, %struct.sequence_stack* }
- %struct.stack_local_entry = type opaque
- %struct.temp_slot = type opaque
- %struct.tree_common = type { %struct.tree_node*, %struct.tree_node*, %union.tree_ann_d*, i8, i8, i8, i8, i8 }
- %struct.tree_decl = type { %struct.tree_common, %struct.location_t, i32, %struct.tree_node*, i8, i8, i8, i8, i8, i8, i8, i8, i32, %struct.tree_decl_u1, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, i32, %struct.tree_decl_u2, %struct.tree_node*, %struct.tree_node*, i64, %struct.lang_decl* }
- %struct.tree_decl_u1 = type { i64 }
- %struct.tree_decl_u2 = type { %struct.function* }
- %struct.tree_node = type { %struct.tree_decl }
- %struct.tree_type = type { %struct.tree_common, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, i32, i16, i8, i8, i32, %struct.tree_node*, %struct.tree_node*, %struct.rtunion, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, i64, %struct.lang_type* }
- %struct.u = type { [1 x %struct.rtunion] }
- %struct.var_refs_queue = type { %struct.rtx_def*, i32, i32, %struct.var_refs_queue* }
- %struct.varasm_status = type opaque
- %struct.varray_data = type { [1 x i64] }
- %struct.varray_head_tag = type { i64, i64, i32, i8*, %struct.varray_data }
- %union.tree_ann_d = type opaque
-@.str = external constant [28 x i8] ; <[28 x i8]*> [#uses=1]
-@tree_code_type = external constant [0 x i32] ; <[0 x i32]*> [#uses=5]
-@global_trees = external global [47 x %struct.tree_node*] ; <[47 x %struct.tree_node*]*> [#uses=1]
-@mode_size = external global [48 x i8] ; <[48 x i8]*> [#uses=1]
-@__FUNCTION__.22683 = external constant [12 x i8] ; <[12 x i8]*> [#uses=1]
-
-define void @layout_type(%struct.tree_node* %type) {
-entry:
- %tmp15 = icmp eq %struct.tree_node* %type, null ; <i1> [#uses=1]
- br i1 %tmp15, label %cond_true, label %cond_false
-
-cond_true: ; preds = %entry
- tail call void @fancy_abort( i8* getelementptr ([28 x i8]* @.str, i32 0, i64 0), i32 1713, i8* getelementptr ([12 x i8]* @__FUNCTION__.22683, i32 0, i32 0) )
- unreachable
-
-cond_false: ; preds = %entry
- %tmp19 = load %struct.tree_node** getelementptr ([47 x %struct.tree_node*]* @global_trees, i32 0, i64 0), align 8 ; <%struct.tree_node*> [#uses=1]
- %tmp21 = icmp eq %struct.tree_node* %tmp19, %type ; <i1> [#uses=1]
- br i1 %tmp21, label %UnifiedReturnBlock, label %cond_next25
-
-cond_next25: ; preds = %cond_false
- %tmp30 = getelementptr %struct.tree_node* %type, i32 0, i32 0, i32 0, i32 3 ; <i8*> [#uses=1]
- %tmp3031 = bitcast i8* %tmp30 to i32* ; <i32*> [#uses=6]
- %tmp32 = load i32* %tmp3031, align 8 ; <i32> [#uses=3]
- %tmp3435 = trunc i32 %tmp32 to i8 ; <i8> [#uses=3]
- %tmp34353637 = zext i8 %tmp3435 to i64 ; <i64> [#uses=1]
- %tmp38 = getelementptr [0 x i32]* @tree_code_type, i32 0, i64 %tmp34353637 ; <i32*> [#uses=1]
- %tmp39 = load i32* %tmp38, align 4 ; <i32> [#uses=1]
- %tmp40 = icmp eq i32 %tmp39, 2 ; <i1> [#uses=4]
- br i1 %tmp40, label %cond_next46, label %cond_true43
-
-cond_true43: ; preds = %cond_next25
- tail call void @tree_class_check_failed( %struct.tree_node* %type, i32 2, i8* getelementptr ([28 x i8]* @.str, i32 0, i64 0), i32 1719, i8* getelementptr ([12 x i8]* @__FUNCTION__.22683, i32 0, i32 0) )
- unreachable
-
-cond_next46: ; preds = %cond_next25
- %tmp4950 = bitcast %struct.tree_node* %type to %struct.tree_type* ; <%struct.tree_type*> [#uses=2]
- %tmp51 = getelementptr %struct.tree_type* %tmp4950, i32 0, i32 2 ; <%struct.tree_node**> [#uses=2]
- %tmp52 = load %struct.tree_node** %tmp51, align 8 ; <%struct.tree_node*> [#uses=1]
- %tmp53 = icmp eq %struct.tree_node* %tmp52, null ; <i1> [#uses=1]
- br i1 %tmp53, label %cond_next57, label %UnifiedReturnBlock
-
-cond_next57: ; preds = %cond_next46
- %tmp65 = and i32 %tmp32, 255 ; <i32> [#uses=1]
- switch i32 %tmp65, label %UnifiedReturnBlock [
- i32 6, label %bb140
- i32 7, label %bb69
- i32 8, label %bb140
- i32 13, label %bb478
- i32 23, label %bb
- ]
-
-bb: ; preds = %cond_next57
- tail call void @fancy_abort( i8* getelementptr ([28 x i8]* @.str, i32 0, i64 0), i32 1727, i8* getelementptr ([12 x i8]* @__FUNCTION__.22683, i32 0, i32 0) )
- unreachable
-
-bb69: ; preds = %cond_next57
- br i1 %tmp40, label %cond_next91, label %cond_true88
-
-cond_true88: ; preds = %bb69
- tail call void @tree_class_check_failed( %struct.tree_node* %type, i32 2, i8* getelementptr ([28 x i8]* @.str, i32 0, i64 0), i32 1730, i8* getelementptr ([12 x i8]* @__FUNCTION__.22683, i32 0, i32 0) )
- unreachable
-
-cond_next91: ; preds = %bb69
- %tmp96 = getelementptr %struct.tree_node* %type, i32 0, i32 0, i32 8 ; <i8*> [#uses=1]
- %tmp9697 = bitcast i8* %tmp96 to i32* ; <i32*> [#uses=2]
- %tmp98 = load i32* %tmp9697, align 8 ; <i32> [#uses=2]
- %tmp100101552 = and i32 %tmp98, 511 ; <i32> [#uses=1]
- %tmp102 = icmp eq i32 %tmp100101552, 0 ; <i1> [#uses=1]
- br i1 %tmp102, label %cond_true105, label %bb140
-
-cond_true105: ; preds = %cond_next91
- br i1 %tmp40, label %cond_next127, label %cond_true124
-
-cond_true124: ; preds = %cond_true105
- tail call void @tree_class_check_failed( %struct.tree_node* %type, i32 2, i8* getelementptr ([28 x i8]* @.str, i32 0, i64 0), i32 1731, i8* getelementptr ([12 x i8]* @__FUNCTION__.22683, i32 0, i32 0) )
- unreachable
-
-cond_next127: ; preds = %cond_true105
- %tmp136 = or i32 %tmp98, 1 ; <i32> [#uses=1]
- %tmp137 = and i32 %tmp136, -511 ; <i32> [#uses=1]
- store i32 %tmp137, i32* %tmp9697, align 8
- br label %bb140
-
-bb140: ; preds = %cond_next127, %cond_next91, %cond_next57, %cond_next57
- switch i8 %tmp3435, label %cond_true202 [
- i8 6, label %cond_next208
- i8 9, label %cond_next208
- i8 7, label %cond_next208
- i8 8, label %cond_next208
- i8 10, label %cond_next208
- ]
-
-cond_true202: ; preds = %bb140
- tail call void (%struct.tree_node*, i8*, i32, i8*, ...)* @tree_check_failed( %struct.tree_node* %type, i8* getelementptr ([28 x i8]* @.str, i32 0, i64 0), i32 1738, i8* getelementptr ([12 x i8]* @__FUNCTION__.22683, i32 0, i32 0), i32 9, i32 6, i32 7, i32 8, i32 10, i32 0 )
- unreachable
-
-cond_next208: ; preds = %bb140, %bb140, %bb140, %bb140, %bb140
- %tmp213 = getelementptr %struct.tree_type* %tmp4950, i32 0, i32 14 ; <%struct.tree_node**> [#uses=1]
- %tmp214 = load %struct.tree_node** %tmp213, align 8 ; <%struct.tree_node*> [#uses=2]
- %tmp217 = getelementptr %struct.tree_node* %tmp214, i32 0, i32 0, i32 0, i32 3 ; <i8*> [#uses=1]
- %tmp217218 = bitcast i8* %tmp217 to i32* ; <i32*> [#uses=1]
- %tmp219 = load i32* %tmp217218, align 8 ; <i32> [#uses=1]
- %tmp221222 = trunc i32 %tmp219 to i8 ; <i8> [#uses=1]
- %tmp223 = icmp eq i8 %tmp221222, 24 ; <i1> [#uses=1]
- br i1 %tmp223, label %cond_true226, label %cond_next340
-
-cond_true226: ; preds = %cond_next208
- switch i8 %tmp3435, label %cond_true288 [
- i8 6, label %cond_next294
- i8 9, label %cond_next294
- i8 7, label %cond_next294
- i8 8, label %cond_next294
- i8 10, label %cond_next294
- ]
-
-cond_true288: ; preds = %cond_true226
- tail call void (%struct.tree_node*, i8*, i32, i8*, ...)* @tree_check_failed( %struct.tree_node* %type, i8* getelementptr ([28 x i8]* @.str, i32 0, i64 0), i32 1739, i8* getelementptr ([12 x i8]* @__FUNCTION__.22683, i32 0, i32 0), i32 9, i32 6, i32 7, i32 8, i32 10, i32 0 )
- unreachable
-
-cond_next294: ; preds = %cond_true226, %cond_true226, %cond_true226, %cond_true226, %cond_true226
- %tmp301 = tail call i32 @tree_int_cst_sgn( %struct.tree_node* %tmp214 ) ; <i32> [#uses=1]
- %tmp302 = icmp sgt i32 %tmp301, -1 ; <i1> [#uses=1]
- br i1 %tmp302, label %cond_true305, label %cond_next340
-
-cond_true305: ; preds = %cond_next294
- %tmp313 = load i32* %tmp3031, align 8 ; <i32> [#uses=2]
- %tmp315316 = trunc i32 %tmp313 to i8 ; <i8> [#uses=1]
- %tmp315316317318 = zext i8 %tmp315316 to i64 ; <i64> [#uses=1]
- %tmp319 = getelementptr [0 x i32]* @tree_code_type, i32 0, i64 %tmp315316317318 ; <i32*> [#uses=1]
- %tmp320 = load i32* %tmp319, align 4 ; <i32> [#uses=1]
- %tmp321 = icmp eq i32 %tmp320, 2 ; <i1> [#uses=1]
- br i1 %tmp321, label %cond_next327, label %cond_true324
-
-cond_true324: ; preds = %cond_true305
- tail call void @tree_class_check_failed( %struct.tree_node* %type, i32 2, i8* getelementptr ([28 x i8]* @.str, i32 0, i64 0), i32 1740, i8* getelementptr ([12 x i8]* @__FUNCTION__.22683, i32 0, i32 0) )
- unreachable
-
-cond_next327: ; preds = %cond_true305
- %tmp338 = or i32 %tmp313, 8192 ; <i32> [#uses=1]
- store i32 %tmp338, i32* %tmp3031, align 8
- br label %cond_next340
-
-cond_next340: ; preds = %cond_next327, %cond_next294, %cond_next208
- %tmp348 = load i32* %tmp3031, align 8 ; <i32> [#uses=1]
- %tmp350351 = trunc i32 %tmp348 to i8 ; <i8> [#uses=1]
- %tmp350351352353 = zext i8 %tmp350351 to i64 ; <i64> [#uses=1]
- %tmp354 = getelementptr [0 x i32]* @tree_code_type, i32 0, i64 %tmp350351352353 ; <i32*> [#uses=1]
- %tmp355 = load i32* %tmp354, align 4 ; <i32> [#uses=1]
- %tmp356 = icmp eq i32 %tmp355, 2 ; <i1> [#uses=1]
- br i1 %tmp356, label %cond_next385, label %cond_true359
-
-cond_true359: ; preds = %cond_next340
- tail call void @tree_class_check_failed( %struct.tree_node* %type, i32 2, i8* getelementptr ([28 x i8]* @.str, i32 0, i64 0), i32 1742, i8* getelementptr ([12 x i8]* @__FUNCTION__.22683, i32 0, i32 0) )
- unreachable
-
-cond_next385: ; preds = %cond_next340
- %tmp390 = getelementptr %struct.tree_node* %type, i32 0, i32 0, i32 8 ; <i8*> [#uses=1]
- %tmp390391 = bitcast i8* %tmp390 to i32* ; <i32*> [#uses=3]
- %tmp392 = load i32* %tmp390391, align 8 ; <i32> [#uses=1]
- %tmp394 = and i32 %tmp392, 511 ; <i32> [#uses=1]
- %tmp397 = tail call i32 @smallest_mode_for_size( i32 %tmp394, i32 2 ) ; <i32> [#uses=1]
- %tmp404 = load i32* %tmp390391, align 8 ; <i32> [#uses=1]
- %tmp397398405 = shl i32 %tmp397, 9 ; <i32> [#uses=1]
- %tmp407 = and i32 %tmp397398405, 65024 ; <i32> [#uses=1]
- %tmp408 = and i32 %tmp404, -65025 ; <i32> [#uses=1]
- %tmp409 = or i32 %tmp408, %tmp407 ; <i32> [#uses=2]
- store i32 %tmp409, i32* %tmp390391, align 8
- %tmp417 = load i32* %tmp3031, align 8 ; <i32> [#uses=1]
- %tmp419420 = trunc i32 %tmp417 to i8 ; <i8> [#uses=1]
- %tmp419420421422 = zext i8 %tmp419420 to i64 ; <i64> [#uses=1]
- %tmp423 = getelementptr [0 x i32]* @tree_code_type, i32 0, i64 %tmp419420421422 ; <i32*> [#uses=1]
- %tmp424 = load i32* %tmp423, align 4 ; <i32> [#uses=1]
- %tmp425 = icmp eq i32 %tmp424, 2 ; <i1> [#uses=1]
- br i1 %tmp425, label %cond_next454, label %cond_true428
-
-cond_true428: ; preds = %cond_next385
- tail call void @tree_class_check_failed( %struct.tree_node* %type, i32 2, i8* getelementptr ([28 x i8]* @.str, i32 0, i64 0), i32 1744, i8* getelementptr ([12 x i8]* @__FUNCTION__.22683, i32 0, i32 0) )
- unreachable
-
-cond_next454: ; preds = %cond_next385
- lshr i32 %tmp409, 9 ; <i32>:0 [#uses=1]
- trunc i32 %0 to i8 ; <i8>:1 [#uses=1]
- %tmp463464 = and i8 %1, 127 ; <i8> [#uses=1]
- %tmp463464465466 = zext i8 %tmp463464 to i64 ; <i64> [#uses=1]
- %tmp467 = getelementptr [48 x i8]* @mode_size, i32 0, i64 %tmp463464465466 ; <i8*> [#uses=1]
- %tmp468 = load i8* %tmp467, align 1 ; <i8> [#uses=1]
- %tmp468469553 = zext i8 %tmp468 to i16 ; <i16> [#uses=1]
- %tmp470471 = shl i16 %tmp468469553, 3 ; <i16> [#uses=1]
- %tmp470471472 = zext i16 %tmp470471 to i64 ; <i64> [#uses=1]
- %tmp473 = tail call %struct.tree_node* @size_int_kind( i64 %tmp470471472, i32 2 ) ; <%struct.tree_node*> [#uses=1]
- store %struct.tree_node* %tmp473, %struct.tree_node** %tmp51, align 8
- ret void
-
-bb478: ; preds = %cond_next57
- br i1 %tmp40, label %cond_next500, label %cond_true497
-
-cond_true497: ; preds = %bb478
- tail call void @tree_class_check_failed( %struct.tree_node* %type, i32 2, i8* getelementptr ([28 x i8]* @.str, i32 0, i64 0), i32 1755, i8* getelementptr ([12 x i8]* @__FUNCTION__.22683, i32 0, i32 0) )
- unreachable
-
-cond_next500: ; preds = %bb478
- %tmp506 = getelementptr %struct.tree_node* %type, i32 0, i32 0, i32 0, i32 1 ; <%struct.tree_node**> [#uses=1]
- %tmp507 = load %struct.tree_node** %tmp506, align 8 ; <%struct.tree_node*> [#uses=2]
- %tmp511 = getelementptr %struct.tree_node* %tmp507, i32 0, i32 0, i32 0, i32 3 ; <i8*> [#uses=1]
- %tmp511512 = bitcast i8* %tmp511 to i32* ; <i32*> [#uses=1]
- %tmp513 = load i32* %tmp511512, align 8 ; <i32> [#uses=2]
- %tmp515516 = trunc i32 %tmp513 to i8 ; <i8> [#uses=1]
- %tmp515516517518 = zext i8 %tmp515516 to i64 ; <i64> [#uses=1]
- %tmp519 = getelementptr [0 x i32]* @tree_code_type, i32 0, i64 %tmp515516517518 ; <i32*> [#uses=1]
- %tmp520 = load i32* %tmp519, align 4 ; <i32> [#uses=1]
- %tmp521 = icmp eq i32 %tmp520, 2 ; <i1> [#uses=1]
- br i1 %tmp521, label %cond_next527, label %cond_true524
-
-cond_true524: ; preds = %cond_next500
- tail call void @tree_class_check_failed( %struct.tree_node* %tmp507, i32 2, i8* getelementptr ([28 x i8]* @.str, i32 0, i64 0), i32 1755, i8* getelementptr ([12 x i8]* @__FUNCTION__.22683, i32 0, i32 0) )
- unreachable
-
-cond_next527: ; preds = %cond_next500
- %tmp545 = and i32 %tmp513, 8192 ; <i32> [#uses=1]
- %tmp547 = and i32 %tmp32, -8193 ; <i32> [#uses=1]
- %tmp548 = or i32 %tmp547, %tmp545 ; <i32> [#uses=1]
- store i32 %tmp548, i32* %tmp3031, align 8
- ret void
-
-UnifiedReturnBlock: ; preds = %cond_next57, %cond_next46, %cond_false
- ret void
-}
-
-declare void @fancy_abort(i8*, i32, i8*)
-
-declare void @tree_class_check_failed(%struct.tree_node*, i32, i8*, i32, i8*)
-
-declare i32 @smallest_mode_for_size(i32, i32)
-
-declare %struct.tree_node* @size_int_kind(i64, i32)
-
-declare void @tree_check_failed(%struct.tree_node*, i8*, i32, i8*, ...)
-
-declare i32 @tree_int_cst_sgn(%struct.tree_node*)
diff --git a/test/CodeGen/X86/2009-08-06-inlineasm.ll b/test/CodeGen/X86/2009-08-06-inlineasm.ll
index cc2f3d8..de32c21 100644
--- a/test/CodeGen/X86/2009-08-06-inlineasm.ll
+++ b/test/CodeGen/X86/2009-08-06-inlineasm.ll
@@ -1,8 +1,10 @@
-; RUN: llc < %s
+; RUN: llc -mtriple=i386-pc-linux-gnu < %s
; PR4668
-; ModuleID = '<stdin>'
-target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
-target triple = "i386-pc-linux-gnu"
+; XFAIL: *
+; FIXME: If the coalescer happens to coalesce %level.1 with the copy to EAX
+; (for ret) then this will fail to compile. The fundamental problem is
+; once the coalescer fixes a virtual register to physical register we can't
+; evict it.
define i32 @x(i32 %qscale) nounwind {
entry:
diff --git a/test/CodeGen/X86/aliases.ll b/test/CodeGen/X86/aliases.ll
index 3020eb3..3ed3bd6 100644
--- a/test/CodeGen/X86/aliases.ll
+++ b/test/CodeGen/X86/aliases.ll
@@ -1,6 +1,6 @@
; RUN: llc < %s -mtriple=i686-pc-linux-gnu -asm-verbose=false -o %t
-; RUN: grep { = } %t | count 7
-; RUN: grep set %t | count 16
+; RUN: grep { = } %t | count 16
+; RUN: grep set %t | count 18
; RUN: grep globl %t | count 6
; RUN: grep weak %t | count 1
; RUN: grep hidden %t | count 1
diff --git a/test/CodeGen/X86/machine-cse.ll b/test/CodeGen/X86/machine-cse.ll
new file mode 100644
index 0000000..a8afdc8
--- /dev/null
+++ b/test/CodeGen/X86/machine-cse.ll
@@ -0,0 +1,39 @@
+; RUN: llc -mtriple=x86_64-apple-darwin < %s | FileCheck %s
+; rdar://7610418
+
+%ptr = type { i8* }
+%struct.s1 = type { %ptr, %ptr }
+%struct.s2 = type { i32, i8*, i8*, [256 x %struct.s1*], [8 x i32], i64, i8*, i32, i64, i64, i32, %struct.s3*, %struct.s3*, [49 x i64] }
+%struct.s3 = type { %struct.s3*, %struct.s3*, i32, i32, i32 }
+
+define fastcc i8* @t(i64 %size) nounwind {
+entry:
+; CHECK: t:
+; CHECK: leaq (%rax,%rax,4)
+ %0 = zext i32 undef to i64
+ %1 = getelementptr inbounds %struct.s2* null, i64 %0
+ br i1 undef, label %bb1, label %bb2
+
+bb1:
+; CHECK: %bb1
+; CHECK-NOT: shlq $9
+; CHECK-NOT: leaq
+; CHECK: call
+ %2 = getelementptr inbounds %struct.s2* null, i64 %0, i32 0
+ call void @bar(i32* %2) nounwind
+ unreachable
+
+bb2:
+; CHECK: %bb2
+; CHECK-NOT: leaq
+; CHECK: callq
+ %3 = call fastcc i8* @foo(%struct.s2* %1) nounwind
+ unreachable
+
+bb3:
+ ret i8* undef
+}
+
+declare void @bar(i32*)
+
+declare fastcc i8* @foo(%struct.s2*) nounwind
diff --git a/test/CodeGen/X86/pre-split6.ll b/test/CodeGen/X86/pre-split6.ll
index d38e630..837e238 100644
--- a/test/CodeGen/X86/pre-split6.ll
+++ b/test/CodeGen/X86/pre-split6.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split | grep {divsd 8} | count 1
+; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse2 -pre-alloc-split | grep {divsd 24} | count 1
@current_surfaces.b = external global i1 ; <i1*> [#uses=1]
diff --git a/test/CodeGen/X86/tailcall2.ll b/test/CodeGen/X86/sibcall.ll
index 90315fd..90315fd 100644
--- a/test/CodeGen/X86/tailcall2.ll
+++ b/test/CodeGen/X86/sibcall.ll
diff --git a/test/CodeGen/X86/stack-color-with-reg.ll b/test/CodeGen/X86/stack-color-with-reg.ll
index 42e7a39..83f56c1 100644
--- a/test/CodeGen/X86/stack-color-with-reg.ll
+++ b/test/CodeGen/X86/stack-color-with-reg.ll
@@ -1,5 +1,6 @@
; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -relocation-model=pic -disable-fp-elim -color-ss-with-regs -stats -info-output-file - > %t
-; RUN: grep stackcoloring %t | grep "stack slot refs replaced with reg refs" | grep 8
+; RUN: grep asm-printer %t | grep 156
+; RUN: grep stackcoloring %t | grep "stack slot refs replaced with reg refs" | grep 4
type { [62 x %struct.Bitvec*] } ; type %0
type { i8* } ; type %1
diff --git a/test/CodeGen/XCore/addsub64.ll b/test/CodeGen/XCore/addsub64.ll
index a1494ad..0432e5e 100644
--- a/test/CodeGen/XCore/addsub64.ll
+++ b/test/CodeGen/XCore/addsub64.ll
@@ -1,12 +1,44 @@
-; RUN: llc < %s -march=xcore -mcpu=xs1b-generic > %t1.s
-; RUN: grep ladd %t1.s | count 2
-; RUN: grep lsub %t1.s | count 2
+; RUN: llc < %s -march=xcore | FileCheck %s
define i64 @add64(i64 %a, i64 %b) {
%result = add i64 %a, %b
ret i64 %result
}
+; CHECK: add64
+; CHECK: ldc r11, 0
+; CHECK-NEXT: ladd r2, r0, r0, r2, r11
+; CHECK-NEXT: ladd r2, r1, r1, r3, r2
+; CHECK-NEXT: retsp 0
define i64 @sub64(i64 %a, i64 %b) {
%result = sub i64 %a, %b
ret i64 %result
}
+; CHECK: sub64
+; CHECK: ldc r11, 0
+; CHECK-NEXT: lsub r2, r0, r0, r2, r11
+; CHECK-NEXT: lsub r2, r1, r1, r3, r2
+; CHECK-NEXT: retsp 0
+
+define i64 @maccu(i64 %a, i32 %b, i32 %c) {
+entry:
+ %0 = zext i32 %b to i64
+ %1 = zext i32 %c to i64
+ %2 = mul i64 %1, %0
+ %3 = add i64 %2, %a
+ ret i64 %3
+}
+; CHECK: maccu:
+; CHECK: maccu r1, r0, r3, r2
+; CHECK-NEXT: retsp 0
+
+define i64 @maccs(i64 %a, i32 %b, i32 %c) {
+entry:
+ %0 = sext i32 %b to i64
+ %1 = sext i32 %c to i64
+ %2 = mul i64 %1, %0
+ %3 = add i64 %2, %a
+ ret i64 %3
+}
+; CHECK: maccs:
+; CHECK: maccs r1, r0, r3, r2
+; CHECK-NEXT: retsp 0
diff --git a/test/CodeGen/XCore/ladd_lsub_combine.ll b/test/CodeGen/XCore/ladd_lsub_combine.ll
new file mode 100644
index 0000000..a693ee2
--- /dev/null
+++ b/test/CodeGen/XCore/ladd_lsub_combine.ll
@@ -0,0 +1,67 @@
+; RUN: llvm-as < %s | llc -march=xcore | FileCheck %s
+
+; Only needs one ladd
+define i64 @f1(i32 %x, i32 %y) nounwind {
+entry:
+ %0 = zext i32 %x to i64 ; <i64> [#uses=1]
+ %1 = zext i32 %y to i64 ; <i64> [#uses=1]
+ %2 = add i64 %1, %0 ; <i64> [#uses=1]
+ ret i64 %2
+}
+; CHECK: f1:
+; CHECK: ldc r2, 0
+; CHECK-NEXT: ladd r1, r0, r1, r0, r2
+; CHECK-NEXT: retsp 0
+
+; Only needs one lsub and one neg
+define i64 @f2(i32 %x, i32 %y) nounwind {
+entry:
+ %0 = zext i32 %x to i64 ; <i64> [#uses=1]
+ %1 = zext i32 %y to i64 ; <i64> [#uses=1]
+ %2 = sub i64 %1, %0 ; <i64> [#uses=1]
+ ret i64 %2
+}
+; CHECK: f2:
+; CHECK: ldc r2, 0
+; CHECK-NEXT: lsub r1, r0, r1, r0, r2
+; CHECK-NEXT: neg r1, r1
+; CHECK-NEXT: retsp 0
+
+; Should compile to one ladd and one add
+define i64 @f3(i64 %x, i32 %y) nounwind {
+entry:
+ %0 = zext i32 %y to i64 ; <i64> [#uses=1]
+ %1 = add i64 %x, %0 ; <i64> [#uses=1]
+ ret i64 %1
+}
+; CHECK: f3:
+; CHECK: ldc r3, 0
+; CHECK-NEXT: ladd r2, r0, r0, r2, r3
+; CHECK-NEXT: add r1, r1, r2
+; CHECK-NEXT: retsp 0
+
+; Should compile to one ladd and one add
+define i64 @f4(i32 %x, i64 %y) nounwind {
+entry:
+ %0 = zext i32 %x to i64 ; <i64> [#uses=1]
+ %1 = add i64 %0, %y ; <i64> [#uses=1]
+ ret i64 %1
+}
+; CHECK: f4:
+; CHECK: ldc r3, 0
+; CHECK-NEXT: ladd r1, r0, r0, r1, r3
+; CHECK-NEXT: add r1, r2, r1
+; CHECK-NEXT: retsp 0
+
+; Should compile to one lsub and one sub
+define i64 @f5(i64 %x, i32 %y) nounwind {
+entry:
+ %0 = zext i32 %y to i64 ; <i64> [#uses=1]
+ %1 = sub i64 %x, %0 ; <i64> [#uses=1]
+ ret i64 %1
+}
+; CHECK: f5:
+; CHECK: ldc r3, 0
+; CHECK-NEXT: lsub r2, r0, r0, r2, r3
+; CHECK-NEXT: sub r1, r1, r2
+; CHECK-NEXT: retsp 0
diff --git a/test/CodeGen/XCore/mul64.ll b/test/CodeGen/XCore/mul64.ll
new file mode 100644
index 0000000..329e214
--- /dev/null
+++ b/test/CodeGen/XCore/mul64.ll
@@ -0,0 +1,39 @@
+; RUN: llc < %s -march=xcore | FileCheck %s
+define i64 @umul_lohi(i32 %a, i32 %b) {
+entry:
+ %0 = zext i32 %a to i64
+ %1 = zext i32 %b to i64
+ %2 = mul i64 %1, %0
+ ret i64 %2
+}
+; CHECK: umul_lohi:
+; CHECK: ldc r2, 0
+; CHECK-NEXT: lmul r1, r0, r1, r0, r2, r2
+; CHECK-NEXT: retsp 0
+
+define i64 @smul_lohi(i32 %a, i32 %b) {
+entry:
+ %0 = sext i32 %a to i64
+ %1 = sext i32 %b to i64
+ %2 = mul i64 %1, %0
+ ret i64 %2
+}
+; CHECK: smul_lohi:
+; CHECK: ldc r2, 0
+; CHECK-NEXT: mov r3, r2
+; CHECK-NEXT: maccs r2, r3, r1, r0
+; CHECK-NEXT: mov r0, r3
+; CHECK-NEXT: mov r1, r2
+; CHECK-NEXT: retsp 0
+
+define i64 @mul64(i64 %a, i64 %b) {
+entry:
+ %0 = mul i64 %a, %b
+ ret i64 %0
+}
+; CHECK: mul64:
+; CHECK: ldc r11, 0
+; CHECK-NEXT: lmul r11, r4, r0, r2, r11, r11
+; CHECK-NEXT: mul r0, r0, r3
+; CHECK-NEXT: lmul r0, r1, r1, r2, r11, r0
+; CHECK-NEXT: mov r0, r4
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