diff options
Diffstat (limited to 'test/CodeGen')
108 files changed, 2151 insertions, 116 deletions
diff --git a/test/CodeGen/2005-07-20-SqrtNoErrno.c b/test/CodeGen/2005-07-20-SqrtNoErrno.c index f40f61d..96761e4 100644 --- a/test/CodeGen/2005-07-20-SqrtNoErrno.c +++ b/test/CodeGen/2005-07-20-SqrtNoErrno.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 %s -emit-llvm -o - | FileCheck %s +// RUN: %clang_cc1 -triple x86_64-apple-darwin %s -emit-llvm -o - | FileCheck %s // llvm.sqrt has undefined behavior on negative inputs, so it is // inappropriate to translate C/C++ sqrt to this. float sqrtf(float x); diff --git a/test/CodeGen/2007-02-25-C-DotDotDot.c b/test/CodeGen/2007-02-25-C-DotDotDot.c index 7b2e418..abc4668 100644 --- a/test/CodeGen/2007-02-25-C-DotDotDot.c +++ b/test/CodeGen/2007-02-25-C-DotDotDot.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -O0 %s -emit-llvm -o - | FileCheck %s +// RUN: %clang_cc1 -triple x86_64-apple-darwin -O0 %s -emit-llvm -o - | FileCheck %s // Make sure the call to foo is compiled as: // call float @foo() diff --git a/test/CodeGen/2008-01-25-ByValReadNone.c b/test/CodeGen/2008-01-25-ByValReadNone.c index 06ad1ee..d977139 100644 --- a/test/CodeGen/2008-01-25-ByValReadNone.c +++ b/test/CodeGen/2008-01-25-ByValReadNone.c @@ -1,7 +1,7 @@ // RUN: %clang_cc1 -emit-llvm -o - %s | not grep readonly // RUN: %clang_cc1 -emit-llvm -o - %s | not grep readnone -// XFAIL: arm +// XFAIL: arm,mips // The struct being passed byval means that we cannot mark the // function readnone. Readnone would allow stores to the arg to diff --git a/test/CodeGen/2008-03-05-syncPtr.c b/test/CodeGen/2008-03-05-syncPtr.c index 784295c..93f328a 100644 --- a/test/CodeGen/2008-03-05-syncPtr.c +++ b/test/CodeGen/2008-03-05-syncPtr.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 %s -emit-llvm -o - | FileCheck %s +// RUN: %clang_cc1 -triple x86_64-apple-darwin %s -emit-llvm -o - | FileCheck %s int* foo(int** a, int* b, int* c) { return __sync_val_compare_and_swap (a, b, c); diff --git a/test/CodeGen/2008-04-08-NoExceptions.c b/test/CodeGen/2008-04-08-NoExceptions.c index 6d5d20f..ab2781b 100644 --- a/test/CodeGen/2008-04-08-NoExceptions.c +++ b/test/CodeGen/2008-04-08-NoExceptions.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple x86_64-apple-darwin -emit-llvm -o - %s | FileCheck %s void f(void); void g(void) { diff --git a/test/CodeGen/2009-02-13-zerosize-union-field-ppc.c b/test/CodeGen/2009-02-13-zerosize-union-field-ppc.c index 8787bd4..2bcc7c3 100644 --- a/test/CodeGen/2009-02-13-zerosize-union-field-ppc.c +++ b/test/CodeGen/2009-02-13-zerosize-union-field-ppc.c @@ -1,3 +1,4 @@ +// REQUIRES: ppc32-registered-target // RUN: %clang_cc1 %s -triple powerpc-pc-linux -emit-llvm -o - | grep {i32 32} | count 3 // XFAIL: * // Every printf has 'i32 0' for the GEP of the string; no point counting those. diff --git a/test/CodeGen/2009-09-24-SqrtErrno.c b/test/CodeGen/2009-09-24-SqrtErrno.c index b4a04ff..6a33967 100644 --- a/test/CodeGen/2009-09-24-SqrtErrno.c +++ b/test/CodeGen/2009-09-24-SqrtErrno.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 %s -emit-llvm -o - -fmath-errno | FileCheck %s +// RUN: %clang_cc1 -triple x86_64-apple-darwin %s -emit-llvm -o - -fmath-errno | FileCheck %s // llvm.sqrt has undefined behavior on negative inputs, so it is // inappropriate to translate C/C++ sqrt to this. diff --git a/test/CodeGen/2009-10-20-GlobalDebug.c b/test/CodeGen/2009-10-20-GlobalDebug.c index 8828eef..8a9dfdd 100644 --- a/test/CodeGen/2009-10-20-GlobalDebug.c +++ b/test/CodeGen/2009-10-20-GlobalDebug.c @@ -6,5 +6,5 @@ int main() { return 0; } -// CHECK: !14 = metadata !{i32 {{.*}}, i32 0, metadata !5, metadata !"localstatic", metadata !"localstatic", metadata !"", metadata !6, i32 5, metadata !9, i32 1, i32 1, i32* @main.localstatic} ; [ DW_TAG_variable ] -// CHECK: !15 = metadata !{i32 {{.*}}, i32 0, null, metadata !"global", metadata !"global", metadata !"", metadata !6, i32 3, metadata !9, i32 0, i32 1, i32* @global} ; [ DW_TAG_variable ] +// CHECK: metadata !{i32 {{.*}}, i32 0, metadata !5, metadata !"localstatic", metadata !"localstatic", metadata !"", metadata !6, i32 5, metadata !9, i32 1, i32 1, i32* @main.localstatic} ; [ DW_TAG_variable ] +// CHECK: metadata !{i32 {{.*}}, i32 0, null, metadata !"global", metadata !"global", metadata !"", metadata !6, i32 3, metadata !9, i32 0, i32 1, i32* @global} ; [ DW_TAG_variable ] diff --git a/test/CodeGen/2010-02-10-PointerName.c b/test/CodeGen/2010-02-10-PointerName.c index 910dd30..2837de4 100644 --- a/test/CodeGen/2010-02-10-PointerName.c +++ b/test/CodeGen/2010-02-10-PointerName.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 %s -emit-llvm -g -o - | grep DW_TAG_pointer_type | grep -v char +// RUN: %clang_cc1 %s -emit-llvm -g -o - | grep DW_TAG_pointer_type | grep -v {"char"} char i = 1; void foo() { diff --git a/test/CodeGen/2010-05-26-AsmSideEffect.c b/test/CodeGen/2010-05-26-AsmSideEffect.c index 7dd86ae..8ae7cb5 100644 --- a/test/CodeGen/2010-05-26-AsmSideEffect.c +++ b/test/CodeGen/2010-05-26-AsmSideEffect.c @@ -1,3 +1,4 @@ +// REQUIRES: arm-registered-target // RUN: %clang_cc1 %s -emit-llvm -triple arm-apple-darwin -o - | FileCheck %s // Radar 8026855 diff --git a/test/CodeGen/Atomics.c b/test/CodeGen/Atomics.c index c440b6c..2bb38fd 100644 --- a/test/CodeGen/Atomics.c +++ b/test/CodeGen/Atomics.c @@ -1,6 +1,6 @@ // Test frontend handling of __sync builtins. // Modified from a gcc testcase. -// RUN: %clang_cc1 -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -triple x86_64-apple-darwin -emit-llvm %s -o - | FileCheck %s signed char sc; unsigned char uc; diff --git a/test/CodeGen/address-safety-attr.cpp b/test/CodeGen/address-safety-attr.cpp index 9d0fb95..da68b1d 100644 --- a/test/CodeGen/address-safety-attr.cpp +++ b/test/CodeGen/address-safety-attr.cpp @@ -33,3 +33,9 @@ int TemplateAddressSafetyOk() { return i; } int force_instance = TemplateAddressSafetyOk<42>() + TemplateNoAddressSafety<42>(); + +// Check that __cxx_global_var_init* get the address_safety attribute. +int global1 = 0; +int global2 = *(int*)((char*)&global1+1); +// CHECK-NOT: @__cxx_global_var_init{{.*}}address_safety +// ASAN: @__cxx_global_var_init{{.*}}address_safety diff --git a/test/CodeGen/address-space.c b/test/CodeGen/address-space.c index 04f88dc..9de0670 100644 --- a/test/CodeGen/address-space.c +++ b/test/CodeGen/address-space.c @@ -1,6 +1,6 @@ -// RUN: %clang_cc1 -emit-llvm < %s | FileCheck %s -// RUN: %clang_cc1 -emit-llvm < %s | grep 'load.*addrspace(2).. @A' -// RUN: %clang_cc1 -emit-llvm < %s | grep 'load.*addrspace(2).. @B' +// RUN: %clang_cc1 -triple x86_64-apple-darwin -emit-llvm < %s | FileCheck %s +// RUN: %clang_cc1 -triple x86_64-apple-darwin -emit-llvm < %s | grep 'load.*addrspace(2).. @A' +// RUN: %clang_cc1 -triple x86_64-apple-darwin -emit-llvm < %s | grep 'load.*addrspace(2).. @B' // CHECK: @foo = common addrspace(1) global diff --git a/test/CodeGen/2002-05-24-Alloca.c b/test/CodeGen/alloca.c index 30ba8bb..30ba8bb 100644 --- a/test/CodeGen/2002-05-24-Alloca.c +++ b/test/CodeGen/alloca.c diff --git a/test/CodeGen/altivec.c b/test/CodeGen/altivec.c index 2982303..6c924a7 100644 --- a/test/CodeGen/altivec.c +++ b/test/CodeGen/altivec.c @@ -1,3 +1,4 @@ +// REQUIRES: ppc32-registered-target // RUN: %clang_cc1 -faltivec -triple powerpc-unknown-unknown -emit-llvm %s -o - | FileCheck %s // Check initialization diff --git a/test/CodeGen/annotations-builtin.c b/test/CodeGen/annotations-builtin.c index 42421a0..7938e49 100644 --- a/test/CodeGen/annotations-builtin.c +++ b/test/CodeGen/annotations-builtin.c @@ -25,9 +25,7 @@ int main(int argc, char **argv) { // CHECK: call i32 @llvm.annotation.i32 long long lla = __builtin_annotation(llfoo, "annotation_a"); -// CHECK: trunc i64 {{.*}} to i32 -// CHECK-NEXT: call i32 @llvm.annotation.i32 -// CHECK-NEXT: zext i32 {{.*}} to i64 +// CHECK: call i64 @llvm.annotation.i64 int inta = __builtin_annotation(intfoo, "annotation_a"); // CHECK: load i32* @intfoo @@ -35,15 +33,11 @@ int main(int argc, char **argv) { // CHECK-NEXT: store short shorta = __builtin_annotation(shortfoo, "annotation_a"); -// CHECK: sext i16 {{.*}} to i32 -// CHECK-NEXT: call i32 @llvm.annotation.i32 -// CHECK-NEXT: trunc i32 {{.*}} to i16 +// CHECK: call i16 @llvm.annotation.i16 char chara = __builtin_annotation(charfoo, "annotation_a"); -// CHECK: sext i8 {{.*}} to i32 -// CHECK-NEXT: call i32 @llvm.annotation.i32 -// CHECK-NEXT: trunc i32 {{.*}} to i8 -// +// CHECK: call i8 @llvm.annotation.i8 + char **arg = (char**) __builtin_annotation((int) argv, "annotation_a"); // CHECK: ptrtoint i8** {{.*}} to // CHECK: call i32 @llvm.annotation.i32 diff --git a/test/CodeGen/arm-aapcs-vfp.c b/test/CodeGen/arm-aapcs-vfp.c index 017c145..614b52d 100644 --- a/test/CodeGen/arm-aapcs-vfp.c +++ b/test/CodeGen/arm-aapcs-vfp.c @@ -1,3 +1,4 @@ +// REQUIRES: arm-registered-target // RUN: %clang_cc1 -triple thumbv7-apple-darwin9 \ // RUN: -target-abi aapcs \ // RUN: -target-cpu cortex-a8 \ @@ -33,6 +34,13 @@ void test_complex(__complex__ double cd) { complex_callee(cd); } +// Long double is the same as double on AAPCS, it should be homogeneous. +extern void complex_long_callee(__complex__ long double); +// CHECK: define arm_aapcs_vfpcc void @test_complex_long(double %{{.*}}, double %{{.*}}) +void test_complex_long(__complex__ long double cd) { + complex_callee(cd); +} + // Structs with more than 4 elements of the base type are not treated // as homogeneous aggregates. Test that. @@ -80,3 +88,7 @@ extern void neon_callee(struct neon_struct); void test_neon(struct neon_struct arg) { neon_callee(arg); } + +// CHECK: define arm_aapcs_vfpcc void @f33(%struct.s33* byval %s) +struct s33 { char buf[32*32]; }; +void f33(struct s33 s) { } diff --git a/test/CodeGen/arm-aapcs-zerolength-bitfield.c b/test/CodeGen/arm-aapcs-zerolength-bitfield.c index 9fece19..140ff6c 100644 --- a/test/CodeGen/arm-aapcs-zerolength-bitfield.c +++ b/test/CodeGen/arm-aapcs-zerolength-bitfield.c @@ -1,3 +1,4 @@ +// REQUIRES: arm-registered-target // RUN: %clang_cc1 -target-abi aapcs -triple armv7-apple-darwin10 %s -verify #include <stddef.h> diff --git a/test/CodeGen/arm-apcs-zerolength-bitfield.c b/test/CodeGen/arm-apcs-zerolength-bitfield.c index 3f94525..049ffae 100644 --- a/test/CodeGen/arm-apcs-zerolength-bitfield.c +++ b/test/CodeGen/arm-apcs-zerolength-bitfield.c @@ -1,3 +1,4 @@ +// REQUIRES: arm-registered-target // RUN: %clang_cc1 -target-abi apcs-gnu -triple armv7-apple-darwin10 %s -verify // // Note: gcc forces the alignment to 4 bytes, regardless of the type of the diff --git a/test/CodeGen/arm-arguments.c b/test/CodeGen/arm-arguments.c index 4686d4a..2ec729e 100644 --- a/test/CodeGen/arm-arguments.c +++ b/test/CodeGen/arm-arguments.c @@ -1,3 +1,4 @@ +// REQUIRES: arm-registered-target // RUN: %clang_cc1 -triple armv7-apple-darwin9 -target-abi apcs-gnu -emit-llvm -w -o - %s | FileCheck -check-prefix=APCS-GNU %s // RUN: %clang_cc1 -triple armv7-apple-darwin9 -target-abi aapcs -emit-llvm -w -o - %s | FileCheck -check-prefix=AAPCS %s @@ -165,3 +166,15 @@ void f31(struct s31 s) { } // APCS-GNU: %s = alloca %struct.s31, align 4 // APCS-GNU: alloca [1 x i32] // APCS-GNU: store [1 x i32] %s.coerce, [1 x i32]* + +// PR13562 +struct s32 { double x; }; +void f32(struct s32 s) { } +// AAPCS: @f32([1 x i64] %s.coerce) +// APCS-GNU: @f32([2 x i32] %s.coerce) + +// PR13350 +struct s33 { char buf[32*32]; }; +void f33(struct s33 s) { } +// APCS-GNU: define void @f33(%struct.s33* byval %s) +// AAPCS: define arm_aapcscc void @f33(%struct.s33* byval %s) diff --git a/test/CodeGen/arm-asm-variable.c b/test/CodeGen/arm-asm-variable.c index 865d197..f874269 100644 --- a/test/CodeGen/arm-asm-variable.c +++ b/test/CodeGen/arm-asm-variable.c @@ -1,3 +1,4 @@ +// REQUIRES: arm-registered-target // RUN: %clang_cc1 -triple armv7-apple-darwin9 -emit-llvm -w -o - %s | FileCheck %s typedef long long int64_t; diff --git a/test/CodeGen/arm-asm.c b/test/CodeGen/arm-asm.c index 9b1082a..bd2fe11 100644 --- a/test/CodeGen/arm-asm.c +++ b/test/CodeGen/arm-asm.c @@ -1,3 +1,4 @@ +// REQUIRES: arm-registered-target // RUN: %clang_cc1 -triple thumb %s -emit-llvm -o - | FileCheck %s int t1() { static float k = 1.0f; diff --git a/test/CodeGen/arm-cc.c b/test/CodeGen/arm-cc.c index 74eecc7..80ebe68 100644 --- a/test/CodeGen/arm-cc.c +++ b/test/CodeGen/arm-cc.c @@ -1,3 +1,4 @@ +// REQUIRES: arm-registered-target // RUN: %clang_cc1 -triple armv7-apple-darwin9 -target-abi apcs-gnu -emit-llvm -w -o - %s | FileCheck -check-prefix=DARWIN-APCS %s // RUN: %clang_cc1 -triple armv7-apple-darwin9 -target-abi aapcs -emit-llvm -w -o - %s | FileCheck -check-prefix=DARWIN-AAPCS %s // RUN: %clang_cc1 -triple arm-none-linux-gnueabi -target-abi apcs-gnu -emit-llvm -w -o - %s | FileCheck -check-prefix=LINUX-APCS %s diff --git a/test/CodeGen/arm-clear.c b/test/CodeGen/arm-clear.c index eda64ce..51506df 100644 --- a/test/CodeGen/arm-clear.c +++ b/test/CodeGen/arm-clear.c @@ -1,3 +1,4 @@ +// REQUIRES: arm-registered-target // RUN: %clang_cc1 -triple armv7-apple-darwin9 -emit-llvm -w -o - %s | FileCheck %s void clear0(void *ptr) { diff --git a/test/CodeGen/arm-homogenous.c b/test/CodeGen/arm-homogenous.c index eb3d5a6..b8d046a 100644 --- a/test/CodeGen/arm-homogenous.c +++ b/test/CodeGen/arm-homogenous.c @@ -1,3 +1,4 @@ +// REQUIRES: arm-registered-target // RUN: %clang_cc1 -triple armv7---eabi -target-abi aapcs -mfloat-abi hard -emit-llvm %s -o - | FileCheck %s typedef long long int64_t; @@ -157,4 +158,4 @@ void test_return_union_with_struct_with_fundamental_elems(void) { // FIXME: Tests necessary: // - Vectors -// - C++ stuff
\ No newline at end of file +// - C++ stuff diff --git a/test/CodeGen/arm-inline-asm.c b/test/CodeGen/arm-inline-asm.c index 0152b05..95bb507 100644 --- a/test/CodeGen/arm-inline-asm.c +++ b/test/CodeGen/arm-inline-asm.c @@ -1,3 +1,4 @@ +// REQUIRES: arm-registered-target // RUN: %clang_cc1 -triple armv7-apple-darwin9 -emit-llvm -w -o - %s | FileCheck %s void t1 (void *f, int g) { diff --git a/test/CodeGen/arm-pcs.c b/test/CodeGen/arm-pcs.c index d722f84..fc658c3 100644 --- a/test/CodeGen/arm-pcs.c +++ b/test/CodeGen/arm-pcs.c @@ -1,3 +1,4 @@ +// REQUIRES: arm-registered-target // RUN: %clang_cc1 -triple arm-none-linux-gnueabi -emit-llvm -w -o - < %s | FileCheck %s typedef int __attribute__((pcs("aapcs"))) (*aapcs_fn)(void); typedef int __attribute__((pcs("aapcs-vfp"))) (*aapcs_vfp_fn)(void); diff --git a/test/CodeGen/arm-vaarg-align.c b/test/CodeGen/arm-vaarg-align.c index 1187c02..2270c8b 100644 --- a/test/CodeGen/arm-vaarg-align.c +++ b/test/CodeGen/arm-vaarg-align.c @@ -1,3 +1,4 @@ +// REQUIRES: arm-registered-target // RUN: %clang_cc1 -triple arm -target-abi aapcs %s -emit-llvm -o - | FileCheck -check-prefix=AAPCS %s // RUN: %clang_cc1 -triple arm -target-abi apcs-gnu %s -emit-llvm -o - | FileCheck -check-prefix=APCS-GNU %s /* diff --git a/test/CodeGen/arm-vector-align.c b/test/CodeGen/arm-vector-align.c index b481a0c..9e1ae5d 100644 --- a/test/CodeGen/arm-vector-align.c +++ b/test/CodeGen/arm-vector-align.c @@ -1,3 +1,4 @@ +// REQUIRES: arm-registered-target // RUN: %clang_cc1 -triple thumbv7-apple-darwin \ // RUN: -target-abi apcs-gnu \ // RUN: -target-cpu cortex-a8 \ diff --git a/test/CodeGen/arm-vector-arguments.c b/test/CodeGen/arm-vector-arguments.c index 6bfb2f4..9bdddb7 100644 --- a/test/CodeGen/arm-vector-arguments.c +++ b/test/CodeGen/arm-vector-arguments.c @@ -1,3 +1,4 @@ +// REQUIRES: arm-registered-target // RUN: %clang_cc1 -triple thumbv7-apple-darwin9 \ // RUN: -target-abi apcs-gnu \ // RUN: -target-cpu cortex-a8 \ diff --git a/test/CodeGen/asm.c b/test/CodeGen/asm.c index 84f26e1..b009736 100644 --- a/test/CodeGen/asm.c +++ b/test/CodeGen/asm.c @@ -220,3 +220,13 @@ typedef long long __m256i __attribute__((__vector_size__(32))); void t26 (__m256i *p) { __asm__ volatile("vmovaps %0, %%ymm0" :: "m" (*(__m256i*)p) : "ymm0"); } + +// Check to make sure the inline asm non-standard dialect attribute _not_ is +// emitted. +void t27(void) { + asm volatile("nop"); +// CHECK: @t27 +// CHECK: call void asm sideeffect "nop" +// CHECK-NOT: ia_nsdialect +// CHECK: ret void +} diff --git a/test/CodeGen/asm_arm.c b/test/CodeGen/asm_arm.c index 633bf55..4b764b7 100644 --- a/test/CodeGen/asm_arm.c +++ b/test/CodeGen/asm_arm.c @@ -1,3 +1,4 @@ +// REQUIRES: arm-registered-target // RUN: %clang_cc1 -triple armv6-unknown-unknown -emit-llvm -o - %s | FileCheck %s void test0(void) { diff --git a/test/CodeGen/atomic_ops.c b/test/CodeGen/atomic_ops.c index 9a18c9e..481d1e0 100644 --- a/test/CodeGen/atomic_ops.c +++ b/test/CodeGen/atomic_ops.c @@ -1,11 +1,20 @@ // RUN: %clang_cc1 -emit-llvm %s -o - | FileCheck %s -void foo(void) +void foo(int x) { _Atomic(int) i = 0; + _Atomic(short) j = 0; // Check that multiply / divides on atomics produce a cmpxchg loop - i *= 2; // CHECK: cmpxchg - i /= 2; // CHECK: cmpxchg + i *= 2; + // CHECK: mul nsw i32 + // CHECK: cmpxchg i32* + i /= 2; + // CHECK: sdiv i32 + // CHECK: cmpxchg i32* + j /= x; + // CHECK: sdiv i32 + // CHECK: cmpxchg i16* + // These should be emitting atomicrmw instructions, but they aren't yet i += 2; // CHECK: cmpxchg i -= 2; // CHECK: cmpxchg diff --git a/test/CodeGen/attr-coldhot.c b/test/CodeGen/attr-coldhot.c new file mode 100644 index 0000000..b9bb299 --- /dev/null +++ b/test/CodeGen/attr-coldhot.c @@ -0,0 +1,9 @@ +// RUN: %clang_cc1 -emit-llvm %s -o - | FileCheck %s + +int test1() __attribute__((__cold__)) { + return 42; + +// Check that we set the optsize attribute on the function. +// CHECK: @test1{{.*}}optsize +// CHECK: ret +} diff --git a/test/CodeGen/attributes.c b/test/CodeGen/attributes.c index 4e73af6..e971a79 100644 --- a/test/CodeGen/attributes.c +++ b/test/CodeGen/attributes.c @@ -81,3 +81,11 @@ void t21(void) { } // CHECK: [[FPTRVAR:%[a-z0-9]+]] = load void (i32)** @fptr // CHECK-NEXT: call x86_fastcallcc void [[FPTRVAR]](i32 10) + + +// PR9356: We might want to err on this, but for now at least make sure we +// use the section in the definition. +void __attribute__((section(".foo"))) t22(void); +void __attribute__((section(".bar"))) t22(void) {} + +// CHECK: define void @t22() nounwind section ".bar" diff --git a/test/CodeGen/avx-builtins.c b/test/CodeGen/avx-builtins.c index b963c97..0e5a741 100644 --- a/test/CodeGen/avx-builtins.c +++ b/test/CodeGen/avx-builtins.c @@ -23,3 +23,73 @@ __m256i test__mm256_loadu_si256(void* p) { // CHECK: load <4 x i64>* %{{.+}}, align 1 return _mm256_loadu_si256(p); } + +__m128i test_mm_cmpestrm(__m128i A, int LA, __m128i B, int LB) { + // CHECK: @llvm.x86.sse42.pcmpestrm128 + return _mm_cmpestrm(A, LA, B, LB, 7); +} + +int test_mm_cmpestri(__m128i A, int LA, __m128i B, int LB) { + // CHECK: @llvm.x86.sse42.pcmpestri128 + return _mm_cmpestri(A, LA, B, LB, 7); +} + +int test_mm_cmpestra(__m128i A, int LA, __m128i B, int LB) { + // CHECK: @llvm.x86.sse42.pcmpestria128 + return _mm_cmpestra(A, LA, B, LB, 7); +} + +int test_mm_cmpestrc(__m128i A, int LA, __m128i B, int LB) { + // CHECK: @llvm.x86.sse42.pcmpestric128 + return _mm_cmpestrc(A, LA, B, LB, 7); +} + +int test_mm_cmpestro(__m128i A, int LA, __m128i B, int LB) { + // CHECK: @llvm.x86.sse42.pcmpestrio128 + return _mm_cmpestro(A, LA, B, LB, 7); +} + +int test_mm_cmpestrs(__m128i A, int LA, __m128i B, int LB) { + // CHECK: @llvm.x86.sse42.pcmpestris128 + return _mm_cmpestrs(A, LA, B, LB, 7); +} + +int test_mm_cmpestrz(__m128i A, int LA, __m128i B, int LB) { + // CHECK: @llvm.x86.sse42.pcmpestriz128 + return _mm_cmpestrz(A, LA, B, LB, 7); +} + +__m128i test_mm_cmpistrm(__m128i A, __m128i B) { + // CHECK: @llvm.x86.sse42.pcmpistrm128 + return _mm_cmpistrm(A, B, 7); +} + +int test_mm_cmpistri(__m128i A, __m128i B) { + // CHECK: @llvm.x86.sse42.pcmpistri128 + return _mm_cmpistri(A, B, 7); +} + +int test_mm_cmpistra(__m128i A, __m128i B) { + // CHECK: @llvm.x86.sse42.pcmpistria128 + return _mm_cmpistra(A, B, 7); +} + +int test_mm_cmpistrc(__m128i A, __m128i B) { + // CHECK: @llvm.x86.sse42.pcmpistric128 + return _mm_cmpistrc(A, B, 7); +} + +int test_mm_cmpistro(__m128i A, __m128i B) { + // CHECK: @llvm.x86.sse42.pcmpistrio128 + return _mm_cmpistro(A, B, 7); +} + +int test_mm_cmpistrs(__m128i A, __m128i B) { + // CHECK: @llvm.x86.sse42.pcmpistris128 + return _mm_cmpistrs(A, B, 7); +} + +int test_mm_cmpistrz(__m128i A, __m128i B) { + // CHECK: @llvm.x86.sse42.pcmpistriz128 + return _mm_cmpistrz(A, B, 7); +} diff --git a/test/CodeGen/avx2-builtins.c b/test/CodeGen/avx2-builtins.c index 7d166b5..b5bc605 100644 --- a/test/CodeGen/avx2-builtins.c +++ b/test/CodeGen/avx2-builtins.c @@ -10,6 +10,11 @@ __m256i test_mm256_mpsadbw_epu8(__m256i x, __m256i y) { return _mm256_mpsadbw_epu8(x, y, 3); } +__m256i test_mm256_sad_epu8(__m256i x, __m256i y) { + // CHECK: @llvm.x86.avx2.psad.bw + return _mm256_sad_epu8(x, y); +} + __m256i test_mm256_abs_epi8(__m256i a) { // CHECK: @llvm.x86.avx2.pabs.b return _mm256_abs_epi8(a); @@ -780,3 +785,154 @@ __m128i test_mm_srlv_epi64(__m128i a, __m128i b) { // CHECK: @llvm.x86.avx2.psrlv.q return _mm_srlv_epi64(a, b); } + +__m128d test_mm_mask_i32gather_pd(__m128d a, double const *b, __m128i c, + __m128d d) { + // CHECK: @llvm.x86.avx2.gather.d.pd + return _mm_mask_i32gather_pd(a, b, c, d, 2); +} + +__m256d test_mm256_mask_i32gather_pd(__m256d a, double const *b, __m128i c, + __m256d d) { + // CHECK: @llvm.x86.avx2.gather.d.pd.256 + return _mm256_mask_i32gather_pd(a, b, c, d, 2); +} +__m128d test_mm_mask_i64gather_pd(__m128d a, double const *b, __m128i c, + __m128d d) { + // CHECK: @llvm.x86.avx2.gather.q.pd + return _mm_mask_i64gather_pd(a, b, c, d, 2); +} +__m256d test_mm256_mask_i64gather_pd(__m256d a, double const *b, __m256i c, + __m256d d) { + // CHECK: @llvm.x86.avx2.gather.q.pd.256 + return _mm256_mask_i64gather_pd(a, b, c, d, 2); +} + +__m128 test_mm_mask_i32gather_ps(__m128 a, float const *b, __m128i c, + __m128 d) { + // CHECK: @llvm.x86.avx2.gather.d.ps + return _mm_mask_i32gather_ps(a, b, c, d, 2); +} +__m256 test_mm256_mask_i32gather_ps(__m256 a, float const *b, __m256i c, + __m256 d) { + // CHECK: @llvm.x86.avx2.gather.d.ps.256 + return _mm256_mask_i32gather_ps(a, b, c, d, 2); +} +__m128 test_mm_mask_i64gather_ps(__m128 a, float const *b, __m128i c, + __m128 d) { + // CHECK: @llvm.x86.avx2.gather.q.ps + return _mm_mask_i64gather_ps(a, b, c, d, 2); +} +__m128 test_mm256_mask_i64gather_ps(__m128 a, float const *b, __m256i c, + __m128 d) { + // CHECK: @llvm.x86.avx2.gather.q.ps.256 + return _mm256_mask_i64gather_ps(a, b, c, d, 2); +} + +__m128i test_mm_mask_i32gather_epi32(__m128i a, int const *b, __m128i c, + __m128i d) { + // CHECK: @llvm.x86.avx2.gather.d.d + return _mm_mask_i32gather_epi32(a, b, c, d, 2); +} +__m256i test_mm256_mask_i32gather_epi32(__m256i a, int const *b, __m256i c, + __m256i d) { + // CHECK: @llvm.x86.avx2.gather.d.d.256 + return _mm256_mask_i32gather_epi32(a, b, c, d, 2); +} +__m128i test_mm_mask_i64gather_epi32(__m128i a, int const *b, __m128i c, + __m128i d) { + // CHECK: @llvm.x86.avx2.gather.q.d + return _mm_mask_i64gather_epi32(a, b, c, d, 2); +} +__m128i test_mm256_mask_i64gather_epi32(__m128i a, int const *b, __m256i c, + __m128i d) { + // CHECK: @llvm.x86.avx2.gather.q.d.256 + return _mm256_mask_i64gather_epi32(a, b, c, d, 2); +} + +__m128i test_mm_mask_i32gather_epi64(__m128i a, int const *b, __m128i c, + __m128i d) { + // CHECK: @llvm.x86.avx2.gather.d.q + return _mm_mask_i32gather_epi64(a, b, c, d, 2); +} +__m256i test_mm256_mask_i32gather_epi64(__m256i a, int const *b, __m128i c, + __m256i d) { + // CHECK: @llvm.x86.avx2.gather.d.q.256 + return _mm256_mask_i32gather_epi64(a, b, c, d, 2); +} +__m128i test_mm_mask_i64gather_epi64(__m128i a, int const *b, __m128i c, + __m128i d) { + // CHECK: @llvm.x86.avx2.gather.q.q + return _mm_mask_i64gather_epi64(a, b, c, d, 2); +} +__m256i test_mm256_mask_i64gather_epi64(__m256i a, int const *b, __m256i c, + __m256i d) { + // CHECK: @llvm.x86.avx2.gather.q.q.256 + return _mm256_mask_i64gather_epi64(a, b, c, d, 2); +} + +__m128d test_mm_i32gather_pd(double const *b, __m128i c) { + // CHECK: @llvm.x86.avx2.gather.d.pd + return _mm_i32gather_pd(b, c, 2); +} +__m256d test_mm256_i32gather_pd(double const *b, __m128i c) { + // CHECK: @llvm.x86.avx2.gather.d.pd.256 + return _mm256_i32gather_pd(b, c, 2); +} +__m128d test_mm_i64gather_pd(double const *b, __m128i c) { + // CHECK: @llvm.x86.avx2.gather.q.pd + return _mm_i64gather_pd(b, c, 2); +} +__m256d test_mm256_i64gather_pd(double const *b, __m256i c) { + // CHECK: @llvm.x86.avx2.gather.q.pd.256 + return _mm256_i64gather_pd(b, c, 2); +} +__m128 test_mm_i32gather_ps(float const *b, __m128i c) { + // CHECK: @llvm.x86.avx2.gather.d.ps + return _mm_i32gather_ps(b, c, 2); +} +__m256 test_mm256_i32gather_ps(float const *b, __m256i c) { + // CHECK: @llvm.x86.avx2.gather.d.ps.256 + return _mm256_i32gather_ps(b, c, 2); +} +__m128 test_mm_i64gather_ps(float const *b, __m128i c) { + // CHECK: @llvm.x86.avx2.gather.q.ps + return _mm_i64gather_ps(b, c, 2); +} +__m128 test_mm256_i64gather_ps(float const *b, __m256i c) { + // CHECK: @llvm.x86.avx2.gather.q.ps.256 + return _mm256_i64gather_ps(b, c, 2); +} + +__m128i test_mm_i32gather_epi32(int const *b, __m128i c) { + // CHECK: @llvm.x86.avx2.gather.d.d + return _mm_i32gather_epi32(b, c, 2); +} +__m256i test_mm256_i32gather_epi32(int const *b, __m256i c) { + // CHECK: @llvm.x86.avx2.gather.d.d.256 + return _mm256_i32gather_epi32(b, c, 2); +} +__m128i test_mm_i64gather_epi32(int const *b, __m128i c) { + // CHECK: @llvm.x86.avx2.gather.q.d + return _mm_i64gather_epi32(b, c, 2); +} +__m128i test_mm256_i64gather_epi32(int const *b, __m256i c) { + // CHECK: @llvm.x86.avx2.gather.q.d.256 + return _mm256_i64gather_epi32(b, c, 2); +} +__m128i test_mm_i32gather_epi64(int const *b, __m128i c) { + // CHECK: @llvm.x86.avx2.gather.d.q + return _mm_i32gather_epi64(b, c, 2); +} +__m256i test_mm256_i32gather_epi64(int const *b, __m128i c) { + // CHECK: @llvm.x86.avx2.gather.d.q.256 + return _mm256_i32gather_epi64(b, c, 2); +} +__m128i test_mm_i64gather_epi64(int const *b, __m128i c) { + // CHECK: @llvm.x86.avx2.gather.q.q + return _mm_i64gather_epi64(b, c, 2); +} +__m256i test_mm256_i64gather_epi64(int const *b, __m256i c) { + // CHECK: @llvm.x86.avx2.gather.q.q.256 + return _mm256_i64gather_epi64(b, c, 2); +} diff --git a/test/CodeGen/block-3.c b/test/CodeGen/block-3.c index 95cb6a7..29c1bb5 100644 --- a/test/CodeGen/block-3.c +++ b/test/CodeGen/block-3.c @@ -6,3 +6,15 @@ int main() { __attribute__((__blocks__(byref))) int index = ({ int __a; int __b; __a < __b ? __b : __a; }); }; } + +// PR13229 +// rdar://11777609 +typedef struct {} Z; + +typedef int (^B)(Z); + +void testPR13229() { + Z z1; + B b1 = ^(Z z1) { return 1; }; + b1(z1); +} diff --git a/test/CodeGen/block-byref-aggr.c b/test/CodeGen/block-byref-aggr.c index 3027df0..eb342b8 100644 --- a/test/CodeGen/block-byref-aggr.c +++ b/test/CodeGen/block-byref-aggr.c @@ -1,17 +1,66 @@ // RUN: %clang_cc1 %s -emit-llvm -o - -fblocks -triple x86_64-apple-darwin10 | FileCheck %s -// rdar://9309454 -typedef struct { int v; } RetType; +// CHECK: [[AGG:%.*]] = type { i32 } +typedef struct { int v; } Agg; +Agg makeAgg(void); -RetType func(); +// When assigning into a __block variable, ensure that we compute that +// address *after* evaluating the RHS when the RHS has the capacity to +// cause a block copy. rdar://9309454 +void test0() { + __block Agg a = {100}; -int main () { - __attribute__((__blocks__(byref))) RetType a = {100}; + a = makeAgg(); +} +// CHECK: define void @test0() +// CHECK: [[A:%.*]] = alloca [[BYREF:%.*]], align 8 +// CHECK-NEXT: [[TEMP:%.*]] = alloca [[AGG]], align 4 +// CHECK: [[RESULT:%.*]] = call i32 @makeAgg() +// CHECK-NEXT: [[T0:%.*]] = getelementptr [[AGG]]* [[TEMP]], i32 0, i32 0 +// CHECK-NEXT: store i32 [[RESULT]], i32* [[T0]] +// Check that we properly assign into the forwarding pointer. +// CHECK-NEXT: [[A_FORWARDING:%.*]] = getelementptr inbounds [[BYREF]]* [[A]], i32 0, i32 1 +// CHECK-NEXT: [[T0:%.*]] = load [[BYREF]]** [[A_FORWARDING]] +// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[BYREF]]* [[T0]], i32 0, i32 4 +// CHECK-NEXT: [[T2:%.*]] = bitcast [[AGG]]* [[T1]] to i8* +// CHECK-NEXT: [[T3:%.*]] = bitcast [[AGG]]* [[TEMP]] to i8* +// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[T2]], i8* [[T3]], i64 4, i32 4, i1 false) +// Verify that there's nothing else significant in the function. +// CHECK-NEXT: [[T0:%.*]] = bitcast [[BYREF]]* [[A]] to i8* +// CHECK-NEXT: call void @_Block_object_dispose(i8* [[T0]], i32 8) +// CHECK-NEXT: ret void - a = func(); +// When chaining assignments into __block variables, make sure we +// propagate the actual value into the outer variable. +// rdar://11757470 +void test1() { + __block Agg a, b; + a = b = makeAgg(); } -// CHECK: [[C1:%.*]] = call i32 (...)* @func() -// CHECK-NEXT: [[CO:%.*]] = getelementptr -// CHECK-NEXT: store i32 [[C1]], i32* [[CO]] -// CHECK-NEXT: [[FORWARDING:%.*]] = getelementptr inbounds [[BR:%.*]]* [[A:%.*]], i32 0, i32 1 -// CHECK-NEXT: [[O:%.*]] = load [[BR]]** [[FORWARDING]] +// CHECK: define void @test1() +// CHECK: [[A:%.*]] = alloca [[A_BYREF:%.*]], align 8 +// CHECK-NEXT: [[B:%.*]] = alloca [[B_BYREF:%.*]], align 8 +// CHECK-NEXT: [[TEMP:%.*]] = alloca [[AGG]], align 4 +// CHECK: [[RESULT:%.*]] = call i32 @makeAgg() +// CHECK-NEXT: [[T0:%.*]] = getelementptr [[AGG]]* [[TEMP]], i32 0, i32 0 +// CHECK-NEXT: store i32 [[RESULT]], i32* [[T0]] +// Check that we properly assign into the forwarding pointer, first for b: +// CHECK-NEXT: [[B_FORWARDING:%.*]] = getelementptr inbounds [[B_BYREF]]* [[B]], i32 0, i32 1 +// CHECK-NEXT: [[T0:%.*]] = load [[B_BYREF]]** [[B_FORWARDING]] +// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[B_BYREF]]* [[T0]], i32 0, i32 4 +// CHECK-NEXT: [[T2:%.*]] = bitcast [[AGG]]* [[T1]] to i8* +// CHECK-NEXT: [[T3:%.*]] = bitcast [[AGG]]* [[TEMP]] to i8* +// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[T2]], i8* [[T3]], i64 4, i32 4, i1 false) +// Then for 'a': +// CHECK-NEXT: [[A_FORWARDING:%.*]] = getelementptr inbounds [[A_BYREF]]* [[A]], i32 0, i32 1 +// CHECK-NEXT: [[T0:%.*]] = load [[A_BYREF]]** [[A_FORWARDING]] +// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[A_BYREF]]* [[T0]], i32 0, i32 4 +// CHECK-NEXT: [[T2:%.*]] = bitcast [[AGG]]* [[T1]] to i8* +// CHECK-NEXT: [[T3:%.*]] = bitcast [[AGG]]* [[TEMP]] to i8* +// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[T2]], i8* [[T3]], i64 4, i32 4, i1 false) +// Verify that there's nothing else significant in the function. +// CHECK-NEXT: [[T0:%.*]] = bitcast [[B_BYREF]]* [[B]] to i8* +// CHECK-NEXT: call void @_Block_object_dispose(i8* [[T0]], i32 8) +// CHECK-NEXT: [[T0:%.*]] = bitcast [[A_BYREF]]* [[A]] to i8* +// CHECK-NEXT: call void @_Block_object_dispose(i8* [[T0]], i32 8) +// CHECK-NEXT: ret void diff --git a/test/CodeGen/blocks.c b/test/CodeGen/blocks.c index bef44c3..71f7171 100644 --- a/test/CodeGen/blocks.c +++ b/test/CodeGen/blocks.c @@ -12,7 +12,7 @@ struct s0 { int a[64]; }; -// CHECK: define internal void @__f2_block_invoke_0(%struct.s0* noalias sret {{%.*}}, i8* {{%.*}}, %struct.s0* byval align 4 {{.*}}) +// CHECK: define internal void @__f2_block_invoke(%struct.s0* noalias sret {{%.*}}, i8* {{%.*}}, %struct.s0* byval align 4 {{.*}}) struct s0 f2(struct s0 a0) { return ^(struct s0 a1){ return a1; }(a0); } @@ -40,3 +40,29 @@ void f3() { _Bool b = 0; f3_helper(^{ if (b) {} }); } + +// rdar://problem/11322251 +// The bool can fill in between the header and the long long. +// Add the appropriate amount of padding between them. +void f4_helper(long long (^)(void)); +// CHECK: define void @f4() +void f4(void) { + _Bool b = 0; + long long ll = 0; + // CHECK: alloca <{ i8*, i32, i32, i8*, {{%.*}}*, i8, [3 x i8], i64 }>, align 8 + f4_helper(^{ if (b) return ll; return 0LL; }); +} + +// rdar://problem/11354538 +// The alignment after rounding up to the align of F5 is actually +// greater than the required alignment. Don't assert. +struct F5 { + char buffer[32] __attribute((aligned)); +}; +void f5_helper(void (^)(struct F5 *)); +// CHECK: define void @f5() +void f5(void) { + struct F5 value; + // CHECK: alloca <{ i8*, i32, i32, i8*, {{%.*}}*, [12 x i8], [[F5:%.*]] }>, align 16 + f5_helper(^(struct F5 *slot) { *slot = value; }); +} diff --git a/test/CodeGen/blocksignature.c b/test/CodeGen/blocksignature.c index 63fe124..fd586eb 100644 --- a/test/CodeGen/blocksignature.c +++ b/test/CodeGen/blocksignature.c @@ -8,7 +8,7 @@ // X32: [[STR1:@.*]] = private unnamed_addr constant [6 x i8] c"v4@?0\00" // X32: @__block_descriptor_tmp = internal constant [[FULL_DESCRIPTOR_T:.*]] { i32 0, i32 20, i8* getelementptr inbounds ([6 x i8]* [[STR1]], i32 0, i32 0), i8* null } -// X32: @__block_literal_global = internal constant [[GLOBAL_LITERAL_T:.*]] { i8** @_NSConcreteGlobalBlock, i32 1342177280, i32 0, i8* bitcast (void (i8*)* @__block_global_{{.*}} to i8*), [[DESCRIPTOR_T:%.*]]* bitcast ([[FULL_DESCRIPTOR_T]]* @__block_descriptor_tmp to {{%.*}}*) } +// X32: @__block_literal_global = internal constant [[GLOBAL_LITERAL_T:.*]] { i8** @_NSConcreteGlobalBlock, i32 1342177280, i32 0, i8* bitcast (void (i8*)* @global_block_invoke{{.*}} to i8*), [[DESCRIPTOR_T:%.*]]* bitcast ([[FULL_DESCRIPTOR_T]]* @__block_descriptor_tmp to {{%.*}}*) } // X32: [[STR2:@.*]] = private unnamed_addr constant [11 x i8] c"i12@?0c4f8\00" // X32: @__block_descriptor_tmp{{.*}} = internal constant [[FULL_DESCRIPTOR_T]] { i32 0, i32 24, i8* getelementptr inbounds ([11 x i8]* [[STR2]], i32 0, i32 0), i8* null } // X32: store i32 1073741824, i32* diff --git a/test/CodeGen/blockwithlocalstatic.c b/test/CodeGen/blockwithlocalstatic.c index 1fdaaf37a..8b4210e 100644 --- a/test/CodeGen/blockwithlocalstatic.c +++ b/test/CodeGen/blockwithlocalstatic.c @@ -1,17 +1,17 @@ // RUN: %clang_cc1 -triple x86_64-apple-darwin10 -fblocks -emit-llvm -o - %s | FileCheck %s // pr8707 -// CHECK: @__block_global_0.test = internal global i32 +// CHECK: @block_block_invoke.test = internal global i32 int (^block)(void) = ^ { static int test=0; return test; }; -// CHECK: @__block_global_1.test = internal global i32 +// CHECK: @block1_block_invoke_2.test = internal global i32 void (^block1)(void) = ^ { static int test = 2; return; }; -// CHECK: @__block_global_2.test = internal global i32 +// CHECK: @block2_block_invoke_3.test = internal global i32 int (^block2)(void) = ^ { static int test = 5; return test; diff --git a/test/CodeGen/bmi-builtins.c b/test/CodeGen/bmi-builtins.c index 47b0da2..2e1ba12 100644 --- a/test/CodeGen/bmi-builtins.c +++ b/test/CodeGen/bmi-builtins.c @@ -5,9 +5,9 @@ #include <x86intrin.h> -unsigned short test__tzcnt16(unsigned short __X) { +unsigned short test__tzcnt_u16(unsigned short __X) { // CHECK: @llvm.cttz.i16 - return __tzcnt16(__X); + return __tzcnt_u16(__X); } unsigned int test__andn_u32(unsigned int __X, unsigned int __Y) { @@ -39,9 +39,9 @@ unsigned int test__blsr_u32(unsigned int __X) { return __blsr_u32(__X); } -unsigned int test_tzcnt32(unsigned int __X) { +unsigned int test_tzcnt_u32(unsigned int __X) { // CHECK: @llvm.cttz.i32 - return __tzcnt32(__X); + return __tzcnt_u32(__X); } unsigned long long test__andn_u64(unsigned long __X, unsigned long __Y) { @@ -73,7 +73,7 @@ unsigned long long test__blsr_u64(unsigned long long __X) { return __blsr_u64(__X); } -unsigned long long test__tzcnt64(unsigned long long __X) { +unsigned long long test__tzcnt_u64(unsigned long long __X) { // CHECK: @llvm.cttz.i64 - return __tzcnt64(__X); + return __tzcnt_u64(__X); } diff --git a/test/CodeGen/bool_test.c b/test/CodeGen/bool_test.c index ffaaef8..715f846 100644 --- a/test/CodeGen/bool_test.c +++ b/test/CodeGen/bool_test.c @@ -1,3 +1,4 @@ +// REQUIRES: ppc32-registered-target // RUN: %clang_cc1 -triple powerpc-apple-darwin -emit-llvm -o - %s| FileCheck -check-prefix=DARWINPPC-CHECK %s int boolsize = sizeof(_Bool); diff --git a/test/CodeGen/bounds-checking.c b/test/CodeGen/bounds-checking.c new file mode 100644 index 0000000..e278620 --- /dev/null +++ b/test/CodeGen/bounds-checking.c @@ -0,0 +1,26 @@ +// RUN: %clang_cc1 -fbounds-checking=4 -emit-llvm -triple x86_64-apple-darwin10 < %s | FileCheck %s + +// CHECK: @f +double f(int b, int i) { + double a[b]; + // CHECK: trap + return a[i]; +} + +// CHECK: @f2 +void f2() { + // everything is constant; no trap possible + // CHECK-NOT: trap + int a[2]; + a[1] = 42; + + short *b = malloc(64); + b[5] = *a + a[1] + 2; +} + +// CHECK: @f3 +void f3() { + int a[1]; + // CHECK: trap + a[2] = 1; +} diff --git a/test/CodeGen/branch-target-layout.c b/test/CodeGen/branch-target-layout.c new file mode 100644 index 0000000..a6475d7 --- /dev/null +++ b/test/CodeGen/branch-target-layout.c @@ -0,0 +1,40 @@ +// RUN: %clang_cc1 %s -O3 -emit-llvm -o - | FileCheck %s +// +// PR13214 +// No assumption may be made about the order that a frontend emits branch +// targets (basic blocks). However, the backend's basic block layout makes an +// attempt to preserve source order of control flow, and any bias toward source +// order must start with the frontend. +// +// Note that the frontend inverts branches to simplify the condition, so the +// order of a branch instruction's labels cannot be used as a source order bias. + +void calla(); +void callb(); +void callc(); + +// CHECK: @test1 +// CHECK: @calla +// CHECK: @callb +// CHECK: @callc +// CHECK: ret void +void test1(int a) { + if (a) + calla(); + else + callb(); + callc(); +} + +// CHECK: @test2 +// CHECK: @callb +// CHECK: @calla +// CHECK: @callc +// CHECK: ret void +void test2(int a) { + if (!a) + callb(); + else + calla(); + callc(); +} diff --git a/test/CodeGen/builtin-attributes.c b/test/CodeGen/builtin-attributes.c index 3781eba..1d3a943 100644 --- a/test/CodeGen/builtin-attributes.c +++ b/test/CodeGen/builtin-attributes.c @@ -1,3 +1,4 @@ +// REQUIRES: arm-registered-target // RUN: %clang_cc1 -triple arm-unknown-linux-gnueabi -emit-llvm -o - %s | FileCheck %s // CHECK: declare i32 @printf(i8*, ...) diff --git a/test/CodeGen/builtins-arm.c b/test/CodeGen/builtins-arm.c index 09df1ef..3611650 100644 --- a/test/CodeGen/builtins-arm.c +++ b/test/CodeGen/builtins-arm.c @@ -1,3 +1,4 @@ +// REQUIRES: arm-registered-target // RUN: %clang_cc1 -Wall -Werror -triple thumbv7-eabi -target-cpu cortex-a8 -O3 -emit-llvm -o - %s | FileCheck %s void *f0() diff --git a/test/CodeGen/builtins-mips-args.c b/test/CodeGen/builtins-mips-args.c new file mode 100644 index 0000000..a961b36 --- /dev/null +++ b/test/CodeGen/builtins-mips-args.c @@ -0,0 +1,14 @@ +// REQUIRES: mips-registered-target +// RUN: %clang_cc1 -triple mips-unknown-linux-gnu -fsyntax-only -verify %s + +void foo() { + // MIPS DSP Rev 1 + + int a = 3; + __builtin_mips_wrdsp(2052, a); // expected-error{{argument to '__builtin_mips_wrdsp' must be a constant integer}} + __builtin_mips_rddsp(a); // expected-error{{argument to '__builtin_mips_rddsp' must be a constant integer}} + __builtin_mips_wrdsp(2052, -1); // expected-error{{argument should be a value from 0 to 63}} + __builtin_mips_rddsp(-1); // expected-error{{argument should be a value from 0 to 63}} + __builtin_mips_wrdsp(2052, 64); // expected-error{{argument should be a value from 0 to 63}} + __builtin_mips_rddsp(64); // expected-error{{argument should be a value from 0 to 63}} +} diff --git a/test/CodeGen/builtins-mips.c b/test/CodeGen/builtins-mips.c new file mode 100644 index 0000000..8155a43 --- /dev/null +++ b/test/CodeGen/builtins-mips.c @@ -0,0 +1,324 @@ +// REQUIRES: mips-registered-target +// RUN: %clang_cc1 -triple mips-unknown-linux-gnu -emit-llvm %s -o - \ +// RUN: | FileCheck %s + +typedef int q31; +typedef int i32; +typedef unsigned int ui32; +typedef long long a64; + +typedef signed char v4i8 __attribute__ ((vector_size(4))); +typedef short v2q15 __attribute__ ((vector_size(4))); + +void foo() { + v2q15 v2q15_r, v2q15_a, v2q15_b, v2q15_c; + v4i8 v4i8_r, v4i8_a, v4i8_b, v4i8_c; + q31 q31_r, q31_a, q31_b, q31_c; + i32 i32_r, i32_a, i32_b, i32_c; + ui32 ui32_r, ui32_a, ui32_b, ui32_c; + a64 a64_r, a64_a, a64_b; + + // MIPS DSP Rev 1 + + v4i8_a = (v4i8) {1, 2, 3, 0xFF}; + v4i8_b = (v4i8) {2, 4, 6, 8}; + v4i8_r = __builtin_mips_addu_qb(v4i8_a, v4i8_b); +// CHECK: call <4 x i8> @llvm.mips.addu.qb + v4i8_r = __builtin_mips_addu_s_qb(v4i8_a, v4i8_b); +// CHECK: call <4 x i8> @llvm.mips.addu.s.qb + v4i8_r = __builtin_mips_subu_qb(v4i8_a, v4i8_b); +// CHECK: call <4 x i8> @llvm.mips.subu.qb + v4i8_r = __builtin_mips_subu_s_qb(v4i8_a, v4i8_b); +// CHECK: call <4 x i8> @llvm.mips.subu.s.qb + + v2q15_a = (v2q15) {0x0000, 0x8000}; + v2q15_b = (v2q15) {0x8000, 0x8000}; + v2q15_r = __builtin_mips_addq_ph(v2q15_a, v2q15_b); +// CHECK: call <2 x i16> @llvm.mips.addq.ph + v2q15_r = __builtin_mips_addq_s_ph(v2q15_a, v2q15_b); +// CHECK: call <2 x i16> @llvm.mips.addq.s.ph + v2q15_r = __builtin_mips_subq_ph(v2q15_a, v2q15_b); +// CHECK: call <2 x i16> @llvm.mips.subq.ph + v2q15_r = __builtin_mips_subq_s_ph(v2q15_a, v2q15_b); +// CHECK: call <2 x i16> @llvm.mips.subq.s.ph + + a64_a = 0x12345678; + i32_b = 0x80000000; + i32_c = 0x11112222; + a64_r = __builtin_mips_madd(a64_a, i32_b, i32_c); +// CHECK: call i64 @llvm.mips.madd + a64_a = 0x12345678; + ui32_b = 0x80000000; + ui32_c = 0x11112222; + a64_r = __builtin_mips_maddu(a64_a, ui32_b, ui32_c); +// CHECK: call i64 @llvm.mips.maddu + a64_a = 0x12345678; + i32_b = 0x80000000; + i32_c = 0x11112222; + a64_r = __builtin_mips_msub(a64_a, i32_b, i32_c); +// CHECK: call i64 @llvm.mips.msub + a64_a = 0x12345678; + ui32_b = 0x80000000; + ui32_c = 0x11112222; + a64_r = __builtin_mips_msubu(a64_a, ui32_b, ui32_c); +// CHECK: call i64 @llvm.mips.msubu + + q31_a = 0x12345678; + q31_b = 0x7FFFFFFF; + q31_r = __builtin_mips_addq_s_w(q31_a, q31_b); +// CHECK: call i32 @llvm.mips.addq.s.w + q31_r = __builtin_mips_subq_s_w(q31_a, q31_b); +// CHECK: call i32 @llvm.mips.subq.s.w + + i32_a = 0xFFFFFFFF; + i32_b = 1; + i32_r = __builtin_mips_addsc(i32_a, i32_b); +// CHECK: call i32 @llvm.mips.addsc + i32_a = 0; + i32_b = 1; + i32_r = __builtin_mips_addwc(i32_a, i32_b); +// CHECK: call i32 @llvm.mips.addwc + + i32_a = 20; + i32_b = 0x1402; + i32_r = __builtin_mips_modsub(i32_a, i32_b); +// CHECK: call i32 @llvm.mips.modsub + + v4i8_a = (v4i8) {1, 2, 3, 4}; + i32_r = __builtin_mips_raddu_w_qb(v4i8_a); +// CHECK: call i32 @llvm.mips.raddu.w.qb + + v2q15_a = (v2q15) {0xFFFF, 0x8000}; + v2q15_r = __builtin_mips_absq_s_ph(v2q15_a); +// CHECK: call <2 x i16> @llvm.mips.absq.s.ph + q31_a = 0x80000000; + q31_r = __builtin_mips_absq_s_w(q31_a); +// CHECK: call i32 @llvm.mips.absq.s.w + + v2q15_a = (v2q15) {0x1234, 0x5678}; + v2q15_b = (v2q15) {0x1111, 0x2222}; + v4i8_r = __builtin_mips_precrq_qb_ph(v2q15_a, v2q15_b); +// CHECK: call <4 x i8> @llvm.mips.precrq.qb.ph + + v2q15_a = (v2q15) {0x7F79, 0xFFFF}; + v2q15_b = (v2q15) {0x7F81, 0x2000}; + v4i8_r = __builtin_mips_precrqu_s_qb_ph(v2q15_a, v2q15_b); +// CHECK: call <4 x i8> @llvm.mips.precrqu.s.qb.ph + q31_a = 0x12345678; + q31_b = 0x11112222; + v2q15_r = __builtin_mips_precrq_ph_w(q31_a, q31_b); +// CHECK: call <2 x i16> @llvm.mips.precrq.ph.w + q31_a = 0x7000FFFF; + q31_b = 0x80000000; + v2q15_r = __builtin_mips_precrq_rs_ph_w(q31_a, q31_b); +// CHECK: call <2 x i16> @llvm.mips.precrq.rs.ph.w + v2q15_a = (v2q15) {0x1234, 0x5678}; + q31_r = __builtin_mips_preceq_w_phl(v2q15_a); +// CHECK: call i32 @llvm.mips.preceq.w.phl + q31_r = __builtin_mips_preceq_w_phr(v2q15_a); +// CHECK: call i32 @llvm.mips.preceq.w.phr + v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78}; + v2q15_r = __builtin_mips_precequ_ph_qbl(v4i8_a); +// CHECK: call <2 x i16> @llvm.mips.precequ.ph.qbl + v2q15_r = __builtin_mips_precequ_ph_qbr(v4i8_a); +// CHECK: call <2 x i16> @llvm.mips.precequ.ph.qbr + v2q15_r = __builtin_mips_precequ_ph_qbla(v4i8_a); +// CHECK: call <2 x i16> @llvm.mips.precequ.ph.qbla + v2q15_r = __builtin_mips_precequ_ph_qbra(v4i8_a); +// CHECK: call <2 x i16> @llvm.mips.precequ.ph.qbra + v2q15_r = __builtin_mips_preceu_ph_qbl(v4i8_a); +// CHECK: call <2 x i16> @llvm.mips.preceu.ph.qbl + v2q15_r = __builtin_mips_preceu_ph_qbr(v4i8_a); +// CHECK: call <2 x i16> @llvm.mips.preceu.ph.qbr + v2q15_r = __builtin_mips_preceu_ph_qbla(v4i8_a); +// CHECK: call <2 x i16> @llvm.mips.preceu.ph.qbla + v2q15_r = __builtin_mips_preceu_ph_qbra(v4i8_a); +// CHECK: call <2 x i16> @llvm.mips.preceu.ph.qbra + + v4i8_a = (v4i8) {1, 2, 3, 4}; + v4i8_r = __builtin_mips_shll_qb(v4i8_a, 2); +// CHECK: call <4 x i8> @llvm.mips.shll.qb + v4i8_a = (v4i8) {128, 64, 32, 16}; + v4i8_r = __builtin_mips_shrl_qb(v4i8_a, 2); +// CHECK: call <4 x i8> @llvm.mips.shrl.qb + v2q15_a = (v2q15) {0x0001, 0x8000}; + v2q15_r = __builtin_mips_shll_ph(v2q15_a, 2); +// CHECK: call <2 x i16> @llvm.mips.shll.ph + v2q15_r = __builtin_mips_shll_s_ph(v2q15_a, 2); +// CHECK: call <2 x i16> @llvm.mips.shll.s.ph + v2q15_a = (v2q15) {0x7FFF, 0x8000}; + v2q15_r = __builtin_mips_shra_ph(v2q15_a, 2); +// CHECK: call <2 x i16> @llvm.mips.shra.ph + v2q15_r = __builtin_mips_shra_r_ph(v2q15_a, 2); +// CHECK: call <2 x i16> @llvm.mips.shra.r.ph + q31_a = 0x70000000; + q31_r = __builtin_mips_shll_s_w(q31_a, 2); +// CHECK: call i32 @llvm.mips.shll.s.w + q31_a = 0x7FFFFFFF; + q31_r = __builtin_mips_shra_r_w(q31_a, 2); +// CHECK: call i32 @llvm.mips.shra.r.w + a64_a = 0x1234567887654321LL; + a64_r = __builtin_mips_shilo(a64_a, -8); +// CHECK: call i64 @llvm.mips.shilo + + v4i8_a = (v4i8) {0x1, 0x3, 0x5, 0x7}; + v2q15_b = (v2q15) {0x1234, 0x5678}; + v2q15_r = __builtin_mips_muleu_s_ph_qbl(v4i8_a, v2q15_b); +// CHECK: call <2 x i16> @llvm.mips.muleu.s.ph.qbl + v2q15_r = __builtin_mips_muleu_s_ph_qbr(v4i8_a, v2q15_b); +// CHECK: call <2 x i16> @llvm.mips.muleu.s.ph.qbr + v2q15_a = (v2q15) {0x7FFF, 0x8000}; + v2q15_b = (v2q15) {0x7FFF, 0x8000}; + v2q15_r = __builtin_mips_mulq_rs_ph(v2q15_a, v2q15_b); +// CHECK: call <2 x i16> @llvm.mips.mulq.rs.ph + v2q15_a = (v2q15) {0x1234, 0x8000}; + v2q15_b = (v2q15) {0x5678, 0x8000}; + q31_r = __builtin_mips_muleq_s_w_phl(v2q15_a, v2q15_b); +// CHECK: call i32 @llvm.mips.muleq.s.w.phl + q31_r = __builtin_mips_muleq_s_w_phr(v2q15_a, v2q15_b); +// CHECK: call i32 @llvm.mips.muleq.s.w.phr + a64_a = 0; + v2q15_a = (v2q15) {0x0001, 0x8000}; + v2q15_b = (v2q15) {0x0002, 0x8000}; + a64_r = __builtin_mips_mulsaq_s_w_ph(a64_a, v2q15_b, v2q15_c); +// CHECK: call i64 @llvm.mips.mulsaq.s.w.ph + a64_a = 0; + v2q15_b = (v2q15) {0x0001, 0x8000}; + v2q15_c = (v2q15) {0x0002, 0x8000}; + a64_r = __builtin_mips_maq_s_w_phl(a64_a, v2q15_b, v2q15_c); +// CHECK: call i64 @llvm.mips.maq.s.w.phl + a64_r = __builtin_mips_maq_s_w_phr(a64_a, v2q15_b, v2q15_c); +// CHECK: call i64 @llvm.mips.maq.s.w.phr + a64_a = 0x7FFFFFF0; + a64_r = __builtin_mips_maq_sa_w_phl(a64_a, v2q15_b, v2q15_c); +// CHECK: call i64 @llvm.mips.maq.sa.w.phl + a64_r = __builtin_mips_maq_sa_w_phr(a64_a, v2q15_b, v2q15_c); +// CHECK: call i64 @llvm.mips.maq.sa.w.phr + i32_a = 0x80000000; + i32_b = 0x11112222; + a64_r = __builtin_mips_mult(i32_a, i32_b); +// CHECK: call i64 @llvm.mips.mult + ui32_a = 0x80000000; + ui32_b = 0x11112222; + a64_r = __builtin_mips_multu(ui32_a, ui32_b); +// CHECK: call i64 @llvm.mips.multu + + a64_a = 0; + v4i8_b = (v4i8) {1, 2, 3, 4}; + v4i8_c = (v4i8) {4, 5, 6, 7}; + a64_r = __builtin_mips_dpau_h_qbl(a64_a, v4i8_b, v4i8_c); +// CHECK: call i64 @llvm.mips.dpau.h.qbl + a64_r = __builtin_mips_dpau_h_qbr(a64_a, v4i8_b, v4i8_c); +// CHECK: call i64 @llvm.mips.dpau.h.qbr + a64_r = __builtin_mips_dpsu_h_qbl(a64_a, v4i8_b, v4i8_c); +// CHECK: call i64 @llvm.mips.dpsu.h.qbl + a64_r = __builtin_mips_dpsu_h_qbr(a64_a, v4i8_b, v4i8_c); +// CHECK: call i64 @llvm.mips.dpsu.h.qbr + a64_a = 0; + v2q15_b = (v2q15) {0x0001, 0x8000}; + v2q15_c = (v2q15) {0x0002, 0x8000}; + a64_r = __builtin_mips_dpaq_s_w_ph(a64_a, v2q15_b, v2q15_c); +// CHECK: call i64 @llvm.mips.dpaq.s.w.ph + a64_r = __builtin_mips_dpsq_s_w_ph(a64_a, v2q15_b, v2q15_c); +// CHECK: call i64 @llvm.mips.dpsq.s.w.ph + a64_a = 0; + q31_b = 0x80000000; + q31_c = 0x80000000; + a64_r = __builtin_mips_dpaq_sa_l_w(a64_a, q31_b, q31_c); +// CHECK: call i64 @llvm.mips.dpaq.sa.l.w + a64_r = __builtin_mips_dpsq_sa_l_w(a64_a, q31_b, q31_c); +// CHECK: call i64 @llvm.mips.dpsq.sa.l.w + + v4i8_a = (v4i8) {1, 4, 10, 8}; + v4i8_b = (v4i8) {1, 2, 100, 8}; + __builtin_mips_cmpu_eq_qb(v4i8_a, v4i8_b); +// CHECK: call void @llvm.mips.cmpu.eq.qb + __builtin_mips_cmpu_lt_qb(v4i8_a, v4i8_b); +// CHECK: call void @llvm.mips.cmpu.lt.qb + __builtin_mips_cmpu_le_qb(v4i8_a, v4i8_b); +// CHECK: call void @llvm.mips.cmpu.le.qb + i32_r = __builtin_mips_cmpgu_eq_qb(v4i8_a, v4i8_b); +// CHECK: call i32 @llvm.mips.cmpgu.eq.qb + i32_r = __builtin_mips_cmpgu_lt_qb(v4i8_a, v4i8_b); +// CHECK: call i32 @llvm.mips.cmpgu.lt.qb + i32_r = __builtin_mips_cmpgu_le_qb(v4i8_a, v4i8_b); +// CHECK: call i32 @llvm.mips.cmpgu.le.qb + v2q15_a = (v2q15) {0x1111, 0x1234}; + v2q15_b = (v2q15) {0x4444, 0x1234}; + __builtin_mips_cmp_eq_ph(v2q15_a, v2q15_b); +// CHECK: call void @llvm.mips.cmp.eq.ph + __builtin_mips_cmp_lt_ph(v2q15_a, v2q15_b); +// CHECK: call void @llvm.mips.cmp.lt.ph + __builtin_mips_cmp_le_ph(v2q15_a, v2q15_b); +// CHECK: call void @llvm.mips.cmp.le.ph + + a64_a = 0xFFFFF81230000000LL; + i32_r = __builtin_mips_extr_s_h(a64_a, 4); +// CHECK: call i32 @llvm.mips.extr.s.h + a64_a = 0x8123456712345678LL; + i32_r = __builtin_mips_extr_w(a64_a, 31); +// CHECK: call i32 @llvm.mips.extr.w + i32_r = __builtin_mips_extr_rs_w(a64_a, 31); +// CHECK: call i32 @llvm.mips.extr.rs.w + i32_r = __builtin_mips_extr_r_w(a64_a, 31); +// CHECK: call i32 @llvm.mips.extr.r.w + a64_a = 0x1234567887654321LL; + i32_r = __builtin_mips_extp(a64_a, 3); +// CHECK: call i32 @llvm.mips.extp + a64_a = 0x123456789ABCDEF0LL; + i32_r = __builtin_mips_extpdp(a64_a, 7); +// CHECK: call i32 @llvm.mips.extpdp + + __builtin_mips_wrdsp(2052, 3); +// CHECK: call void @llvm.mips.wrdsp + i32_r = __builtin_mips_rddsp(3); +// CHECK: call i32 @llvm.mips.rddsp + i32_a = 0xFFFFFFFF; + i32_b = 0x12345678; + __builtin_mips_wrdsp((16<<7) + 4, 3); +// CHECK: call void @llvm.mips.wrdsp + i32_r = __builtin_mips_insv(i32_a, i32_b); +// CHECK: call i32 @llvm.mips.insv + i32_a = 0x1234; + i32_r = __builtin_mips_bitrev(i32_a); +// CHECK: call i32 @llvm.mips.bitrev + v2q15_a = (v2q15) {0x1111, 0x2222}; + v2q15_b = (v2q15) {0x3333, 0x4444}; + v2q15_r = __builtin_mips_packrl_ph(v2q15_a, v2q15_b); +// CHECK: call <2 x i16> @llvm.mips.packrl.ph + i32_a = 100; + v4i8_r = __builtin_mips_repl_qb(i32_a); +// CHECK: call <4 x i8> @llvm.mips.repl.qb + i32_a = 0x1234; + v2q15_r = __builtin_mips_repl_ph(i32_a); +// CHECK: call <2 x i16> @llvm.mips.repl.ph + v4i8_a = (v4i8) {1, 4, 10, 8}; + v4i8_b = (v4i8) {1, 2, 100, 8}; + __builtin_mips_cmpu_eq_qb(v4i8_a, v4i8_b); +// CHECK: call void @llvm.mips.cmpu.eq.qb + v4i8_r = __builtin_mips_pick_qb(v4i8_a, v4i8_b); +// CHECK: call <4 x i8> @llvm.mips.pick.qb + v2q15_a = (v2q15) {0x1111, 0x1234}; + v2q15_b = (v2q15) {0x4444, 0x1234}; + __builtin_mips_cmp_eq_ph(v2q15_a, v2q15_b); +// CHECK: call void @llvm.mips.cmp.eq.ph + v2q15_r = __builtin_mips_pick_ph(v2q15_a, v2q15_b); +// CHECK: call <2 x i16> @llvm.mips.pick.ph + a64_a = 0x1234567887654321LL; + i32_b = 0x11112222; + __builtin_mips_wrdsp(0, 1); +// CHECK: call void @llvm.mips.wrdsp + a64_r = __builtin_mips_mthlip(a64_a, i32_b); +// CHECK: call i64 @llvm.mips.mthlip + i32_r = __builtin_mips_bposge32(); +// CHECK: call i32 @llvm.mips.bposge32 + char array_a[100]; + i32_r = __builtin_mips_lbux(array_a, 20); +// CHECK: call i32 @llvm.mips.lbux + short array_b[100]; + i32_r = __builtin_mips_lhx(array_b, 20); +// CHECK: call i32 @llvm.mips.lhx + int array_c[100]; + i32_r = __builtin_mips_lwx(array_c, 20); +// CHECK: call i32 @llvm.mips.lwx +} diff --git a/test/CodeGen/builtins-ptx.c b/test/CodeGen/builtins-nvptx.c index 6dd1018..fa6b14c 100644 --- a/test/CodeGen/builtins-ptx.c +++ b/test/CodeGen/builtins-nvptx.c @@ -1,6 +1,5 @@ -// RUN: %clang_cc1 -triple ptx32-unknown-unknown -emit-llvm -o %t %s -// RUN: %clang_cc1 -triple ptx64-unknown-unknown -emit-llvm -o %t %s - +// RUN: %clang_cc1 -triple nvptx-unknown-unknown -emit-llvm -o %t %s +// RUN: %clang_cc1 -triple nvptx64-unknown-unknown -emit-llvm -o %t %s int read_tid() { diff --git a/test/CodeGen/builtins-ppc-altivec.c b/test/CodeGen/builtins-ppc-altivec.c index b12ff01..e885cb0 100644 --- a/test/CodeGen/builtins-ppc-altivec.c +++ b/test/CodeGen/builtins-ppc-altivec.c @@ -1,3 +1,4 @@ +// REQUIRES: ppc32-registered-target // RUN: %clang_cc1 -faltivec -triple powerpc-unknown-unknown -emit-llvm %s -o - | FileCheck %s vector bool char vbc = { 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0 }; diff --git a/test/CodeGen/builtins-x86.c b/test/CodeGen/builtins-x86.c index acb5554..fcf1512 100644 --- a/test/CodeGen/builtins-x86.c +++ b/test/CodeGen/builtins-x86.c @@ -344,7 +344,6 @@ void f0() { tmp_V16c = __builtin_ia32_lddqu(tmp_cCp); tmp_V2LLi = __builtin_ia32_palignr128(tmp_V2LLi, tmp_V2LLi, imm_i); tmp_V1LLi = __builtin_ia32_palignr(tmp_V1LLi, tmp_V1LLi, imm_i); - (void) __builtin_ia32_storelv4si(tmp_V2ip, tmp_V2LLi); #ifdef USE_SSE4 tmp_V16c = __builtin_ia32_pblendvb128(tmp_V16c, tmp_V16c, tmp_V16c); tmp_V8s = __builtin_ia32_pblendw128(tmp_V8s, tmp_V8s, imm_i_0_256); diff --git a/test/CodeGen/builtins.c b/test/CodeGen/builtins.c index fca087e..65b9ad1 100644 --- a/test/CodeGen/builtins.c +++ b/test/CodeGen/builtins.c @@ -203,3 +203,9 @@ void test_builtin_longjmp(void **buffer) { __builtin_longjmp(buffer, 1); // CHECK-NEXT: unreachable } + +// CHECK: define i64 @test_builtin_readcyclecounter +long long test_builtin_readcyclecounter() { + // CHECK: call i64 @llvm.readcyclecounter() + return __builtin_readcyclecounter(); +} diff --git a/test/CodeGen/capture-complex-expr-in-block.c b/test/CodeGen/capture-complex-expr-in-block.c index 9ce7570..86c93d0 100644 --- a/test/CodeGen/capture-complex-expr-in-block.c +++ b/test/CodeGen/capture-complex-expr-in-block.c @@ -12,7 +12,7 @@ int main () b(); } -// CHECK: define internal void @__main_block_invoke_0 +// CHECK: define internal void @__main_block_invoke // CHECK: [[C1:%.*]] = alloca { double, double }, align 8 // CHECK: [[RP:%.*]] = getelementptr inbounds { double, double }* [[C1]], i32 0, i32 0 // CHECK-NEXT: [[R:%.*]] = load double* [[RP]] diff --git a/test/CodeGen/catch-undef-behavior.c b/test/CodeGen/catch-undef-behavior.c index fef1587..ee0b658 100644 --- a/test/CodeGen/catch-undef-behavior.c +++ b/test/CodeGen/catch-undef-behavior.c @@ -1,7 +1,17 @@ -// RUN: %clang_cc1 -fcatch-undefined-behavior -emit-llvm-only %s +// RUN: %clang_cc1 -fcatch-undefined-behavior -emit-llvm %s -o - | FileCheck %s // PR6805 +// CHECK: @foo void foo() { union { int i; } u; + // CHECK: objectsize + // CHECK: icmp uge u.i=1; } + +// CHECK: @bar +int bar(int *a) { + // CHECK: objectsize + // CHECK: icmp uge + return *a; +} diff --git a/test/CodeGen/compound-literal.c b/test/CodeGen/compound-literal.c index 969c5af..a8eec61 100644 --- a/test/CodeGen/compound-literal.c +++ b/test/CodeGen/compound-literal.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -triple x86_64-apple-darwin -emit-llvm %s -o - | FileCheck %s int* a = &(int){1}; struct s {int a, b, c;} * b = &(struct s) {1, 2, 3}; diff --git a/test/CodeGen/debug-info-gline-tables-only.c b/test/CodeGen/debug-info-gline-tables-only.c new file mode 100644 index 0000000..067d8e7 --- /dev/null +++ b/test/CodeGen/debug-info-gline-tables-only.c @@ -0,0 +1,33 @@ +// RUN: %clang_cc1 %s -gline-tables-only -S -emit-llvm -o - | FileCheck %s +// Checks that clang with "-gline-tables-only" doesn't emit debug info +// for variables and types. + +// CHECK-NOT: DW_TAG_variable +int global = 42; + +// CHECK-NOT: DW_TAG_typedef +// CHECK-NOT: DW_TAG_const_type +// CHECK-NOT: DW_TAG_pointer_type +// CHECK-NOT: DW_TAG_array_type +typedef const char* constCharPtrArray[10]; + +// CHECK-NOT: DW_TAG_structure_type +struct S { + // CHECK-NOT: DW_TAG_member + char a; + double b; + constCharPtrArray c; +}; + +// CHECK-NOT: DW_TAG_enumerator +// CHECK-NOT: DW_TAG_enumeration_type +enum E { ZERO = 0, ONE = 1 }; + +// CHECK-NOT: DW_TAG_arg_variable +int sum(int p, int q) { + // CHECK-NOT: DW_TAG_auto_variable + int r = p + q; + struct S s; + enum E e; + return r; +} diff --git a/test/CodeGen/debug-info-gline-tables-only2.c b/test/CodeGen/debug-info-gline-tables-only2.c new file mode 100644 index 0000000..8e9cc64 --- /dev/null +++ b/test/CodeGen/debug-info-gline-tables-only2.c @@ -0,0 +1,13 @@ +// RUN: %clang_cc1 %s -gline-tables-only -S -emit-llvm -o - | FileCheck %s +// Checks that clang with "-gline-tables-only" emits metadata for +// compile unit, subprogram and file. + +int main() { + // CHECK: ret i32 0, !dbg + return 0; +} + +// CHECK: !llvm.dbg.cu = !{!0} +// CHECK: DW_TAG_compile_unit +// CHECK: {{.*main.* DW_TAG_subprogram}} +// CHECK: DW_TAG_file_type diff --git a/test/CodeGen/debug-info-line2.c b/test/CodeGen/debug-info-line2.c index b5eba8a..893b021 100644 --- a/test/CodeGen/debug-info-line2.c +++ b/test/CodeGen/debug-info-line2.c @@ -6,11 +6,12 @@ int foo(int i) { int j = 0; if (i) { j = bar(); -//CHECK: store i32 -//CHECK-NOT: br label %{{%[a-zA-Z0-9\.]+}}, !dbg } else { + // CHECK: add nsw + // CHECK-NEXT: store i32 %{{[a-zA-Z0-9]+}} + // CHECK-NOT: br label %{{[a-zA-Z0-9\.]+}}, !dbg j = bar() + 2; } return j; diff --git a/test/CodeGen/debug-info-line3.c b/test/CodeGen/debug-info-line3.c index 645ffb9..a4e35e7 100644 --- a/test/CodeGen/debug-info-line3.c +++ b/test/CodeGen/debug-info-line3.c @@ -12,5 +12,5 @@ void func(char c, char* d) } -// CHECK: ret void, !dbg !19 -// CHECK: !19 = metadata !{i32 6, +// CHECK: ret void, !dbg !17 +// CHECK: !17 = metadata !{i32 6, diff --git a/test/CodeGen/debug-info-vla.c b/test/CodeGen/debug-info-vla.c new file mode 100644 index 0000000..20fb6aa --- /dev/null +++ b/test/CodeGen/debug-info-vla.c @@ -0,0 +1,12 @@ +// RUN: %clang_cc1 -emit-llvm -g -triple x86_64-apple-darwin %s -o - | FileCheck %s + +// CHECK: metadata !{i32 {{.*}}, metadata {{.*}}, metadata !"vla", metadata {{.*}}, i32 7, metadata {{.*}}, i32 0, i32 0, i64 2} ; [ DW_TAG_auto_variable ] + +void testVLAwithSize(int s) +{ + int vla[s]; + int i; + for (i = 0; i < s; i++) { + vla[i] = i*i; + } +} diff --git a/test/CodeGen/debug-line-1.c b/test/CodeGen/debug-line-1.c index 00d4f42..0c2d185 100644 --- a/test/CodeGen/debug-line-1.c +++ b/test/CodeGen/debug-line-1.c @@ -4,7 +4,7 @@ // Check to make sure that we emit the block for the break so that we can count the line. // CHECK: sw.bb: ; preds = %entry -// CHECK: br label %sw.epilog, !dbg !21 +// CHECK: br label %sw.epilog, !dbg !19 extern int atoi(const char *); diff --git a/test/CodeGen/fma-builtins.c b/test/CodeGen/fma-builtins.c new file mode 100644 index 0000000..3424616 --- /dev/null +++ b/test/CodeGen/fma-builtins.c @@ -0,0 +1,166 @@ +// RUN: %clang_cc1 %s -O3 -triple=x86_64-apple-darwin -target-feature +fma -emit-llvm -o - | FileCheck %s + +// Don't include mm_malloc.h, it's system specific. +#define __MM_MALLOC_H + +#include <immintrin.h> + +__m128 test_mm_fmadd_ps(__m128 a, __m128 b, __m128 c) { + // CHECK: @llvm.x86.fma.vfmadd.ps + return _mm_fmadd_ps(a, b, c); +} + +__m128d test_mm_fmadd_pd(__m128d a, __m128d b, __m128d c) { + // CHECK: @llvm.x86.fma.vfmadd.pd + return _mm_fmadd_pd(a, b, c); +} + +__m128 test_mm_fmadd_ss(__m128 a, __m128 b, __m128 c) { + // CHECK: @llvm.x86.fma.vfmadd.ss + return _mm_fmadd_ss(a, b, c); +} + +__m128d test_mm_fmadd_sd(__m128d a, __m128d b, __m128d c) { + // CHECK: @llvm.x86.fma.vfmadd.sd + return _mm_fmadd_sd(a, b, c); +} + +__m128 test_mm_fmsub_ps(__m128 a, __m128 b, __m128 c) { + // CHECK: @llvm.x86.fma.vfmsub.ps + return _mm_fmsub_ps(a, b, c); +} + +__m128d test_mm_fmsub_pd(__m128d a, __m128d b, __m128d c) { + // CHECK: @llvm.x86.fma.vfmsub.pd + return _mm_fmsub_pd(a, b, c); +} + +__m128 test_mm_fmsub_ss(__m128 a, __m128 b, __m128 c) { + // CHECK: @llvm.x86.fma.vfmsub.ss + return _mm_fmsub_ss(a, b, c); +} + +__m128d test_mm_fmsub_sd(__m128d a, __m128d b, __m128d c) { + // CHECK: @llvm.x86.fma.vfmsub.sd + return _mm_fmsub_sd(a, b, c); +} + +__m128 test_mm_fnmadd_ps(__m128 a, __m128 b, __m128 c) { + // CHECK: @llvm.x86.fma.vfnmadd.ps + return _mm_fnmadd_ps(a, b, c); +} + +__m128d test_mm_fnmadd_pd(__m128d a, __m128d b, __m128d c) { + // CHECK: @llvm.x86.fma.vfnmadd.pd + return _mm_fnmadd_pd(a, b, c); +} + +__m128 test_mm_fnmadd_ss(__m128 a, __m128 b, __m128 c) { + // CHECK: @llvm.x86.fma.vfnmadd.ss + return _mm_fnmadd_ss(a, b, c); +} + +__m128d test_mm_fnmadd_sd(__m128d a, __m128d b, __m128d c) { + // CHECK: @llvm.x86.fma.vfnmadd.sd + return _mm_fnmadd_sd(a, b, c); +} + +__m128 test_mm_fnmsub_ps(__m128 a, __m128 b, __m128 c) { + // CHECK: @llvm.x86.fma.vfnmsub.ps + return _mm_fnmsub_ps(a, b, c); +} + +__m128d test_mm_fnmsub_pd(__m128d a, __m128d b, __m128d c) { + // CHECK: @llvm.x86.fma.vfnmsub.pd + return _mm_fnmsub_pd(a, b, c); +} + +__m128 test_mm_fnmsub_ss(__m128 a, __m128 b, __m128 c) { + // CHECK: @llvm.x86.fma.vfnmsub.ss + return _mm_fnmsub_ss(a, b, c); +} + +__m128d test_mm_fnmsub_sd(__m128d a, __m128d b, __m128d c) { + // CHECK: @llvm.x86.fma.vfnmsub.sd + return _mm_fnmsub_sd(a, b, c); +} + +__m128 test_mm_fmaddsub_ps(__m128 a, __m128 b, __m128 c) { + // CHECK: @llvm.x86.fma.vfmaddsub.ps + return _mm_fmaddsub_ps(a, b, c); +} + +__m128d test_mm_fmaddsub_pd(__m128d a, __m128d b, __m128d c) { + // CHECK: @llvm.x86.fma.vfmaddsub.pd + return _mm_fmaddsub_pd(a, b, c); +} + +__m128 test_mm_fmsubadd_ps(__m128 a, __m128 b, __m128 c) { + // CHECK: @llvm.x86.fma.vfmsubadd.ps + return _mm_fmsubadd_ps(a, b, c); +} + +__m128d test_mm_fmsubadd_pd(__m128d a, __m128d b, __m128d c) { + // CHECK: @llvm.x86.fma.vfmsubadd.pd + return _mm_fmsubadd_pd(a, b, c); +} + +__m256 test_mm256_fmadd_ps(__m256 a, __m256 b, __m256 c) { + // CHECK: @llvm.x86.fma.vfmadd.ps.256 + return _mm256_fmadd_ps(a, b, c); +} + +__m256d test_mm256_fmadd_pd(__m256d a, __m256d b, __m256d c) { + // CHECK: @llvm.x86.fma.vfmadd.pd.256 + return _mm256_fmadd_pd(a, b, c); +} + +__m256 test_mm256_fmsub_ps(__m256 a, __m256 b, __m256 c) { + // CHECK: @llvm.x86.fma.vfmsub.ps.256 + return _mm256_fmsub_ps(a, b, c); +} + +__m256d test_mm256_fmsub_pd(__m256d a, __m256d b, __m256d c) { + // CHECK: @llvm.x86.fma.vfmsub.pd.256 + return _mm256_fmsub_pd(a, b, c); +} + +__m256 test_mm256_fnmadd_ps(__m256 a, __m256 b, __m256 c) { + // CHECK: @llvm.x86.fma.vfnmadd.ps.256 + return _mm256_fnmadd_ps(a, b, c); +} + +__m256d test_mm256_fnmadd_pd(__m256d a, __m256d b, __m256d c) { + // CHECK: @llvm.x86.fma.vfnmadd.pd.256 + return _mm256_fnmadd_pd(a, b, c); +} + +__m256 test_mm256_fnmsub_ps(__m256 a, __m256 b, __m256 c) { + // CHECK: @llvm.x86.fma.vfnmsub.ps.256 + return _mm256_fnmsub_ps(a, b, c); +} + +__m256d test_mm256_fnmsub_pd(__m256d a, __m256d b, __m256d c) { + // CHECK: @llvm.x86.fma.vfnmsub.pd.256 + return _mm256_fnmsub_pd(a, b, c); +} + +__m256 test_mm256_fmaddsub_ps(__m256 a, __m256 b, __m256 c) { + // CHECK: @llvm.x86.fma.vfmaddsub.ps.256 + return _mm256_fmaddsub_ps(a, b, c); +} + +__m256d test_mm256_fmaddsub_pd(__m256d a, __m256d b, __m256d c) { + // CHECK: @llvm.x86.fma.vfmaddsub.pd.256 + return _mm256_fmaddsub_pd(a, b, c); +} + +__m256 test_mm256_fmsubadd_ps(__m256 a, __m256 b, __m256 c) { + // CHECK: @llvm.x86.fma.vfmsubadd.ps.256 + return _mm256_fmsubadd_ps(a, b, c); +} + +__m256d test_mm256_fmsubadd_pd(__m256d a, __m256d b, __m256d c) { + // CHECK: @llvm.x86.fma.vfmsubadd.pd.256 + return _mm256_fmsubadd_pd(a, b, c); +} diff --git a/test/CodeGen/fma4-builtins.c b/test/CodeGen/fma4-builtins.c index ddbaba7..b805e9a 100644 --- a/test/CodeGen/fma4-builtins.c +++ b/test/CodeGen/fma4-builtins.c @@ -6,161 +6,161 @@ #include <x86intrin.h> __m128 test_mm_macc_ps(__m128 a, __m128 b, __m128 c) { - // CHECK: @llvm.x86.fma4.vfmadd.ps + // CHECK: @llvm.x86.fma.vfmadd.ps return _mm_macc_ps(a, b, c); } __m128d test_mm_macc_pd(__m128d a, __m128d b, __m128d c) { - // CHECK: @llvm.x86.fma4.vfmadd.pd + // CHECK: @llvm.x86.fma.vfmadd.pd return _mm_macc_pd(a, b, c); } __m128 test_mm_macc_ss(__m128 a, __m128 b, __m128 c) { - // CHECK: @llvm.x86.fma4.vfmadd.ss + // CHECK: @llvm.x86.fma.vfmadd.ss return _mm_macc_ss(a, b, c); } __m128d test_mm_macc_sd(__m128d a, __m128d b, __m128d c) { - // CHECK: @llvm.x86.fma4.vfmadd.sd + // CHECK: @llvm.x86.fma.vfmadd.sd return _mm_macc_sd(a, b, c); } __m128 test_mm_msub_ps(__m128 a, __m128 b, __m128 c) { - // CHECK: @llvm.x86.fma4.vfmsub.ps + // CHECK: @llvm.x86.fma.vfmsub.ps return _mm_msub_ps(a, b, c); } __m128d test_mm_msub_pd(__m128d a, __m128d b, __m128d c) { - // CHECK: @llvm.x86.fma4.vfmsub.pd + // CHECK: @llvm.x86.fma.vfmsub.pd return _mm_msub_pd(a, b, c); } __m128 test_mm_msub_ss(__m128 a, __m128 b, __m128 c) { - // CHECK: @llvm.x86.fma4.vfmsub.ss + // CHECK: @llvm.x86.fma.vfmsub.ss return _mm_msub_ss(a, b, c); } __m128d test_mm_msub_sd(__m128d a, __m128d b, __m128d c) { - // CHECK: @llvm.x86.fma4.vfmsub.sd + // CHECK: @llvm.x86.fma.vfmsub.sd return _mm_msub_sd(a, b, c); } __m128 test_mm_nmacc_ps(__m128 a, __m128 b, __m128 c) { - // CHECK: @llvm.x86.fma4.vfnmadd.ps + // CHECK: @llvm.x86.fma.vfnmadd.ps return _mm_nmacc_ps(a, b, c); } __m128d test_mm_nmacc_pd(__m128d a, __m128d b, __m128d c) { - // CHECK: @llvm.x86.fma4.vfnmadd.pd + // CHECK: @llvm.x86.fma.vfnmadd.pd return _mm_nmacc_pd(a, b, c); } __m128 test_mm_nmacc_ss(__m128 a, __m128 b, __m128 c) { - // CHECK: @llvm.x86.fma4.vfnmadd.ss + // CHECK: @llvm.x86.fma.vfnmadd.ss return _mm_nmacc_ss(a, b, c); } __m128d test_mm_nmacc_sd(__m128d a, __m128d b, __m128d c) { - // CHECK: @llvm.x86.fma4.vfnmadd.sd + // CHECK: @llvm.x86.fma.vfnmadd.sd return _mm_nmacc_sd(a, b, c); } __m128 test_mm_nmsub_ps(__m128 a, __m128 b, __m128 c) { - // CHECK: @llvm.x86.fma4.vfnmsub.ps + // CHECK: @llvm.x86.fma.vfnmsub.ps return _mm_nmsub_ps(a, b, c); } __m128d test_mm_nmsub_pd(__m128d a, __m128d b, __m128d c) { - // CHECK: @llvm.x86.fma4.vfnmsub.pd + // CHECK: @llvm.x86.fma.vfnmsub.pd return _mm_nmsub_pd(a, b, c); } __m128 test_mm_nmsub_ss(__m128 a, __m128 b, __m128 c) { - // CHECK: @llvm.x86.fma4.vfnmsub.ss + // CHECK: @llvm.x86.fma.vfnmsub.ss return _mm_nmsub_ss(a, b, c); } __m128d test_mm_nmsub_sd(__m128d a, __m128d b, __m128d c) { - // CHECK: @llvm.x86.fma4.vfnmsub.sd + // CHECK: @llvm.x86.fma.vfnmsub.sd return _mm_nmsub_sd(a, b, c); } __m128 test_mm_maddsub_ps(__m128 a, __m128 b, __m128 c) { - // CHECK: @llvm.x86.fma4.vfmaddsub.ps + // CHECK: @llvm.x86.fma.vfmaddsub.ps return _mm_maddsub_ps(a, b, c); } __m128d test_mm_maddsub_pd(__m128d a, __m128d b, __m128d c) { - // CHECK: @llvm.x86.fma4.vfmaddsub.pd + // CHECK: @llvm.x86.fma.vfmaddsub.pd return _mm_maddsub_pd(a, b, c); } __m128 test_mm_msubadd_ps(__m128 a, __m128 b, __m128 c) { - // CHECK: @llvm.x86.fma4.vfmsubadd.ps + // CHECK: @llvm.x86.fma.vfmsubadd.ps return _mm_msubadd_ps(a, b, c); } __m128d test_mm_msubadd_pd(__m128d a, __m128d b, __m128d c) { - // CHECK: @llvm.x86.fma4.vfmsubadd.pd + // CHECK: @llvm.x86.fma.vfmsubadd.pd return _mm_msubadd_pd(a, b, c); } __m256 test_mm256_macc_ps(__m256 a, __m256 b, __m256 c) { - // CHECK: @llvm.x86.fma4.vfmadd.ps.256 + // CHECK: @llvm.x86.fma.vfmadd.ps.256 return _mm256_macc_ps(a, b, c); } __m256d test_mm256_macc_pd(__m256d a, __m256d b, __m256d c) { - // CHECK: @llvm.x86.fma4.vfmadd.pd.256 + // CHECK: @llvm.x86.fma.vfmadd.pd.256 return _mm256_macc_pd(a, b, c); } __m256 test_mm256_msub_ps(__m256 a, __m256 b, __m256 c) { - // CHECK: @llvm.x86.fma4.vfmsub.ps.256 + // CHECK: @llvm.x86.fma.vfmsub.ps.256 return _mm256_msub_ps(a, b, c); } __m256d test_mm256_msub_pd(__m256d a, __m256d b, __m256d c) { - // CHECK: @llvm.x86.fma4.vfmsub.pd.256 + // CHECK: @llvm.x86.fma.vfmsub.pd.256 return _mm256_msub_pd(a, b, c); } __m256 test_mm256_nmacc_ps(__m256 a, __m256 b, __m256 c) { - // CHECK: @llvm.x86.fma4.vfnmadd.ps.256 + // CHECK: @llvm.x86.fma.vfnmadd.ps.256 return _mm256_nmacc_ps(a, b, c); } __m256d test_mm256_nmacc_pd(__m256d a, __m256d b, __m256d c) { - // CHECK: @llvm.x86.fma4.vfnmadd.pd.256 + // CHECK: @llvm.x86.fma.vfnmadd.pd.256 return _mm256_nmacc_pd(a, b, c); } __m256 test_mm256_nmsub_ps(__m256 a, __m256 b, __m256 c) { - // CHECK: @llvm.x86.fma4.vfnmsub.ps.256 + // CHECK: @llvm.x86.fma.vfnmsub.ps.256 return _mm256_nmsub_ps(a, b, c); } __m256d test_mm256_nmsub_pd(__m256d a, __m256d b, __m256d c) { - // CHECK: @llvm.x86.fma4.vfnmsub.pd.256 + // CHECK: @llvm.x86.fma.vfnmsub.pd.256 return _mm256_nmsub_pd(a, b, c); } __m256 test_mm256_maddsub_ps(__m256 a, __m256 b, __m256 c) { - // CHECK: @llvm.x86.fma4.vfmaddsub.ps.256 + // CHECK: @llvm.x86.fma.vfmaddsub.ps.256 return _mm256_maddsub_ps(a, b, c); } __m256d test_mm256_maddsub_pd(__m256d a, __m256d b, __m256d c) { - // CHECK: @llvm.x86.fma4.vfmaddsub.pd.256 + // CHECK: @llvm.x86.fma.vfmaddsub.pd.256 return _mm256_maddsub_pd(a, b, c); } __m256 test_mm256_msubadd_ps(__m256 a, __m256 b, __m256 c) { - // CHECK: @llvm.x86.fma4.vfmsubadd.ps.256 + // CHECK: @llvm.x86.fma.vfmsubadd.ps.256 return _mm256_msubadd_ps(a, b, c); } __m256d test_mm256_msubadd_pd(__m256d a, __m256d b, __m256d c) { - // CHECK: @llvm.x86.fma4.vfmsubadd.pd.256 + // CHECK: @llvm.x86.fma.vfmsubadd.pd.256 return _mm256_msubadd_pd(a, b, c); } diff --git a/test/CodeGen/forceinline.c b/test/CodeGen/forceinline.c new file mode 100644 index 0000000..9a21c0d --- /dev/null +++ b/test/CodeGen/forceinline.c @@ -0,0 +1,14 @@ +// RUN: %clang_cc1 -triple i686-win32 -emit-llvm -fms-extensions < %s | FileCheck %s + +void bar() { +} + +// CHECK-NOT: foo +__forceinline void foo() { + bar(); +} + +void i_want_bar() { +// CHECK: call void @bar + foo(); +} diff --git a/test/CodeGen/fp-contract.c b/test/CodeGen/fp-contract.c new file mode 100644 index 0000000..eb95f1e --- /dev/null +++ b/test/CodeGen/fp-contract.c @@ -0,0 +1,9 @@ +// RUN: %clang_cc1 -O3 -ffp-contract=fast -triple=powerpc-apple-darwin10 -S -o - %s | FileCheck %s +// REQUIRES: ppc32-registered-target + +float fma_test1(float a, float b, float c) { +// CHECK: fmadds + float x = a * b; + float y = x + c; + return y; +} diff --git a/test/CodeGen/fp16-ops.c b/test/CodeGen/fp16-ops.c index cbbfb88..e506513 100644 --- a/test/CodeGen/fp16-ops.c +++ b/test/CodeGen/fp16-ops.c @@ -1,3 +1,4 @@ +// REQUIRES: arm-registered-target // RUN: %clang_cc1 -emit-llvm -o - -triple arm-none-linux-gnueabi %s | FileCheck %s typedef unsigned cond_t; diff --git a/test/CodeGen/func-aligned.c b/test/CodeGen/func-aligned.c index f8a4a29..64b7293 100644 --- a/test/CodeGen/func-aligned.c +++ b/test/CodeGen/func-aligned.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 %s -emit-llvm -o - | FileCheck %s +// RUN: %clang_cc1 -triple x86_64-apple-darwin %s -emit-llvm -o - | FileCheck %s // rdar://7270273 void foo() __attribute__((aligned (64))); diff --git a/test/CodeGen/func-in-block.c b/test/CodeGen/func-in-block.c index 1900135..503695f 100644 --- a/test/CodeGen/func-in-block.c +++ b/test/CodeGen/func-in-block.c @@ -15,5 +15,5 @@ int main() return 0; // not reached } -// CHECK: @__func__.__main_block_invoke_0 = private unnamed_addr constant [22 x i8] c"__main_block_invoke_0\00" -// CHECK: call void @PRINTF({{.*}}@__func__.__main_block_invoke_ +// CHECK: @__func__.__main_block_invoke = private unnamed_addr constant [20 x i8] c"__main_block_invoke\00" +// CHECK: call void @PRINTF({{.*}}@__func__.__main_block_invoke diff --git a/test/CodeGen/func-return-member.c b/test/CodeGen/func-return-member.c index 8c55a96..14ecac5 100644 --- a/test/CodeGen/func-return-member.c +++ b/test/CodeGen/func-return-member.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple x86_64-apple-darwin -emit-llvm -o - %s | FileCheck %s struct frk { float _Complex c; int x; }; struct faz { struct frk f; }; diff --git a/test/CodeGen/incomplete-function-type.c b/test/CodeGen/incomplete-function-type.c index 0ba6633..b630947 100644 --- a/test/CodeGen/incomplete-function-type.c +++ b/test/CodeGen/incomplete-function-type.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple x86_64-apple-darwin -emit-llvm -o - %s | FileCheck %s // CHECK: ModuleID // CHECK-NOT: opaque // CHECK: define void @f0 diff --git a/test/CodeGen/integer-overflow.c b/test/CodeGen/integer-overflow.c index 1d46065..d7fff4e 100644 --- a/test/CodeGen/integer-overflow.c +++ b/test/CodeGen/integer-overflow.c @@ -1,7 +1,7 @@ -// RUN: %clang_cc1 %s -emit-llvm -o - | FileCheck %s --check-prefix=DEFAULT -// RUN: %clang_cc1 %s -emit-llvm -o - -fwrapv | FileCheck %s --check-prefix=WRAPV -// RUN: %clang_cc1 %s -emit-llvm -o - -ftrapv | FileCheck %s --check-prefix=TRAPV -// RUN: %clang_cc1 %s -emit-llvm -o - -ftrapv -ftrapv-handler foo | FileCheck %s --check-prefix=TRAPV_HANDLER +// RUN: %clang_cc1 -triple x86_64-apple-darwin %s -emit-llvm -o - | FileCheck %s --check-prefix=DEFAULT +// RUN: %clang_cc1 -triple x86_64-apple-darwin %s -emit-llvm -o - -fwrapv | FileCheck %s --check-prefix=WRAPV +// RUN: %clang_cc1 -triple x86_64-apple-darwin %s -emit-llvm -o - -ftrapv | FileCheck %s --check-prefix=TRAPV +// RUN: %clang_cc1 -triple x86_64-apple-darwin %s -emit-llvm -o - -ftrapv -ftrapv-handler foo | FileCheck %s --check-prefix=TRAPV_HANDLER // Tests for signed integer overflow stuff. diff --git a/test/CodeGen/libcalls.c b/test/CodeGen/libcalls.c index 458c591..ec895ac 100644 --- a/test/CodeGen/libcalls.c +++ b/test/CodeGen/libcalls.c @@ -73,3 +73,48 @@ void test_fma(float a0, double a1, long double a2) { // CHECK-NO: declare float @llvm.fma.f32(float, float, float) nounwind readnone // CHECK-NO: declare double @llvm.fma.f64(double, double, double) nounwind readnone // CHECK-NO: declare x86_fp80 @llvm.fma.f80(x86_fp80, x86_fp80, x86_fp80) nounwind readnone + +// Just checking to make sure these library functions are marked readnone +void test_builtins(double d, float f, long double ld) { +// CHEC-NO: @test_builtins +// CHEC-YES: @test_builtins + double atan_ = atan(d); + long double atanl_ = atanl(ld); + float atanf_ = atanf(f); +// CHECK-NO: declare double @atan(double) nounwind readnone +// CHECK-NO: declare x86_fp80 @atanl(x86_fp80) nounwind readnone +// CHECK-NO: declare float @atanf(float) nounwind readnone +// CHECK-YES-NOT: declare double @atan(double) nounwind readnone +// CHECK-YES-NOT: declare x86_fp80 @atanl(x86_fp80) nounwind readnone +// CHECK-YES-NOT: declare float @atanf(float) nounwind readnone + + double atan2_ = atan2(d, 2); + long double atan2l_ = atan2l(ld, ld); + float atan2f_ = atan2f(f, f); +// CHECK-NO: declare double @atan2(double, double) nounwind readnone +// CHECK-NO: declare x86_fp80 @atan2l(x86_fp80, x86_fp80) nounwind readnone +// CHECK-NO: declare float @atan2f(float, float) nounwind readnone +// CHECK-YES-NOT: declare double @atan2(double, double) nounwind readnone +// CHECK-YES-NOT: declare x86_fp80 @atan2l(x86_fp80, x86_fp80) nounwind readnone +// CHECK-YES-NOT: declare float @atan2f(float, float) nounwind readnone + + double exp_ = exp(d); + long double expl_ = expl(ld); + float expf_ = expf(f); +// CHECK-NO: declare double @exp(double) nounwind readnone +// CHECK-NO: declare x86_fp80 @expl(x86_fp80) nounwind readnone +// CHECK-NO: declare float @expf(float) nounwind readnone +// CHECK-YES-NOT: declare double @exp(double) nounwind readnone +// CHECK-YES-NOT: declare x86_fp80 @expl(x86_fp80) nounwind readnone +// CHECK-YES-NOT: declare float @expf(float) nounwind readnone + + double log_ = log(d); + long double logl_ = logl(ld); + float logf_ = logf(f); +// CHECK-NO: declare double @log(double) nounwind readnone +// CHECK-NO: declare x86_fp80 @logl(x86_fp80) nounwind readnone +// CHECK-NO: declare float @logf(float) nounwind readnone +// CHECK-YES-NOT: declare double @log(double) nounwind readnone +// CHECK-YES-NOT: declare x86_fp80 @logl(x86_fp80) nounwind readnone +// CHECK-YES-NOT: declare float @logf(float) nounwind readnone +} diff --git a/test/CodeGen/mips-byval-arg.c b/test/CodeGen/mips-byval-arg.c new file mode 100644 index 0000000..4e5f41a --- /dev/null +++ b/test/CodeGen/mips-byval-arg.c @@ -0,0 +1,15 @@ +// RUN: %clang -target mipsel-unknown-linux -ccc-clang-archs mipsel -O3 -S -o - -emit-llvm %s | FileCheck %s -check-prefix=O32 +// RUN: %clang -target mips64el-unknown-linux -ccc-clang-archs mips64el -O3 -S -mabi=n64 -o - -emit-llvm %s | FileCheck %s -check-prefix=N64 + +typedef struct { + float f[3]; +} S0; + +extern void foo2(S0); + +// O32: define void @foo1(i32 %a0.coerce0, i32 %a0.coerce1, i32 %a0.coerce2) +// N64: define void @foo1(i64 %a0.coerce0, i32 %a0.coerce1) + +void foo1(S0 a0) { + foo2(a0); +} diff --git a/test/CodeGen/mips-vector-arg.c b/test/CodeGen/mips-vector-arg.c new file mode 100644 index 0000000..39998d9 --- /dev/null +++ b/test/CodeGen/mips-vector-arg.c @@ -0,0 +1,28 @@ +// RUN: %clang -target mipsel-unknown-linux -ccc-clang-archs mipsel -O3 -S -o - -emit-llvm %s | FileCheck %s -check-prefix=O32 +// RUN: %clang -target mips64el-unknown-linux -ccc-clang-archs mips64el -O3 -S -mabi=n64 -o - -emit-llvm %s | FileCheck %s -check-prefix=N64 + +// check that +// 1. vector arguments are passed in integer registers +// 2. argument alignment is no larger than 8-byte for O32 and 16-byte for N64. + +typedef float v4sf __attribute__ ((__vector_size__ (16))); +typedef int v4i32 __attribute__ ((__vector_size__ (16))); + +// O32: define void @test_v4sf(i32 %a1.coerce0, i32 %a1.coerce1, i32 %a1.coerce2, i32 %a1.coerce3, i32 %a2, i32, i32 %a3.coerce0, i32 %a3.coerce1, i32 %a3.coerce2, i32 %a3.coerce3) nounwind +// O32: declare i32 @test_v4sf_2(i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) +// N64: define void @test_v4sf(i64 %a1.coerce0, i64 %a1.coerce1, i32 %a2, i64, i64 %a3.coerce0, i64 %a3.coerce1) nounwind +// N64: declare i32 @test_v4sf_2(i64, i64, i32, i64, i64, i64) +extern test_v4sf_2(v4sf, int, v4sf); +void test_v4sf(v4sf a1, int a2, v4sf a3) { + test_v4sf_2(a3, a2, a1); +} + +// O32: define void @test_v4i32(i32 %a1.coerce0, i32 %a1.coerce1, i32 %a1.coerce2, i32 %a1.coerce3, i32 %a2, i32, i32 %a3.coerce0, i32 %a3.coerce1, i32 %a3.coerce2, i32 %a3.coerce3) nounwind +// O32: declare i32 @test_v4i32_2(i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) +// N64: define void @test_v4i32(i64 %a1.coerce0, i64 %a1.coerce1, i32 %a2, i64, i64 %a3.coerce0, i64 %a3.coerce1) nounwind +// N64: declare i32 @test_v4i32_2(i64, i64, i32, i64, i64, i64) +extern test_v4i32_2(v4i32, int, v4i32); +void test_v4i32(v4i32 a1, int a2, v4i32 a3) { + test_v4i32_2(a3, a2, a1); +} + diff --git a/test/CodeGen/mips-vector-return.c b/test/CodeGen/mips-vector-return.c new file mode 100644 index 0000000..12e71fa --- /dev/null +++ b/test/CodeGen/mips-vector-return.c @@ -0,0 +1,31 @@ +// RUN: %clang -target mipsel-unknown-linux -ccc-clang-archs mipsel -O3 -S -o - -emit-llvm %s | FileCheck %s -check-prefix=O32 +// RUN: %clang -target mips64el-unknown-linux -ccc-clang-archs mips64el -O3 -S -mabi=n64 -o - -emit-llvm %s | FileCheck %s -check-prefix=N64 + +// vectors larger than 16-bytes are returned via the hidden pointer argument. +// N64/N32 returns vectors whose size is equal to or smaller than 16-bytes in +// integer registers. +typedef float v4sf __attribute__ ((__vector_size__ (16))); +typedef double v4df __attribute__ ((__vector_size__ (32))); +typedef int v4i32 __attribute__ ((__vector_size__ (16))); + +// O32: define void @test_v4sf(<4 x float>* noalias nocapture sret +// N64: define { i64, i64 } @test_v4sf +v4sf test_v4sf(float a) { + return (v4sf){0.0f, a, 0.0f, 0.0f}; +} + +// O32: define void @test_v4df(<4 x double>* noalias nocapture sret +// N64: define void @test_v4df(<4 x double>* noalias nocapture sret +v4df test_v4df(double a) { + return (v4df){0.0, a, 0.0, 0.0}; +} + +// O32 returns integer vectors whose size is equal to or smaller than 16-bytes +// in integer registers. +// +// O32: define { i32, i32, i32, i32 } @test_v4i32 +// N64: define { i64, i64 } @test_v4i32 +v4i32 test_v4i32(int a) { + return (v4i32){0, a, 0, 0}; +} + diff --git a/test/CodeGen/mips64-class-return.cpp b/test/CodeGen/mips64-class-return.cpp index dc9ec0f..8e32d5c 100644 --- a/test/CodeGen/mips64-class-return.cpp +++ b/test/CodeGen/mips64-class-return.cpp @@ -39,7 +39,7 @@ void foo3(D2 a0) { gd2 = a0; } -// CHECK: define void @_Z4foo42D0(%class.D0* nocapture byval %a0) +// CHECK: define void @_Z4foo42D0(i64 %a0.coerce0, i64 %a0.coerce1) void foo4(D0 a0) { gd0 = a0; } diff --git a/test/CodeGen/ms-declspecs.c b/test/CodeGen/ms-declspecs.c index d3235ae..91862a7 100644 --- a/test/CodeGen/ms-declspecs.c +++ b/test/CodeGen/ms-declspecs.c @@ -1,5 +1,13 @@ // RUN: %clang_cc1 -triple i386-pc-win32 %s -emit-llvm -fms-compatibility -o - | FileCheck %s +struct __declspec(align(16)) S { + char x; +}; +union { struct S s; } u; + +// CHECK: @u = {{.*}}zeroinitializer, align 16 + + // CHECK: define void @t3() nounwind noinline naked { __declspec(naked) void t3() {} diff --git a/test/CodeGen/ms-inline-asm.c b/test/CodeGen/ms-inline-asm.c new file mode 100644 index 0000000..8c3e5f7 --- /dev/null +++ b/test/CodeGen/ms-inline-asm.c @@ -0,0 +1,40 @@ +// RUN: %clang_cc1 %s -triple x86_64-apple-darwin10 -O0 -fms-extensions -fenable-experimental-ms-inline-asm -w -emit-llvm -o - | FileCheck %s + +void t1() { +// CHECK: @t1 +// CHECK: call void asm sideeffect "", "~{dirflag},~{fpsr},~{flags}"() nounwind ia_nsdialect +// CHECK: ret void + __asm {} +} + +void t2() { +// CHECK: @t2 +// CHECK: call void asm sideeffect "nop\0Anop\0Anop", "~{dirflag},~{fpsr},~{flags}"() nounwind ia_nsdialect +// CHECK: ret void + __asm nop + __asm nop + __asm nop +} + +void t3() { +// CHECK: @t3 +// CHECK: call void asm sideeffect "nop\0Anop\0Anop", "~{dirflag},~{fpsr},~{flags}"() nounwind ia_nsdialect +// CHECK: ret void + __asm nop __asm nop __asm nop +} + +void t4(void) { +// CHECK: @t4 +// CHECK: call void asm sideeffect "mov ebx, eax\0Amov ecx, ebx", "~{dirflag},~{fpsr},~{flags}"() nounwind ia_nsdialect +// CHECK: ret void + __asm mov ebx, eax + __asm mov ecx, ebx +} + +void t5(void) { +// CHECK: @t5 +// CHECK: call void asm sideeffect "mov ebx, eax\0Amov ecx, ebx", "~{dirflag},~{fpsr},~{flags}"() nounwind ia_nsdialect +// CHECK: ret void + __asm mov ebx, eax __asm mov ecx, ebx +} + diff --git a/test/CodeGen/no-common.c b/test/CodeGen/no-common.c index 7beefc7..8d2c4d7 100644 --- a/test/CodeGen/no-common.c +++ b/test/CodeGen/no-common.c @@ -12,4 +12,4 @@ fn_t ABC __attribute__ ((nocommon)); // CHECK-DEFAULT: @y = common global // CHECK-NOCOMMON: @y = common global -int y __attribute__((common));
\ No newline at end of file +int y __attribute__((common)); diff --git a/test/CodeGen/nobuiltin.c b/test/CodeGen/nobuiltin.c new file mode 100644 index 0000000..0a8e8bb --- /dev/null +++ b/test/CodeGen/nobuiltin.c @@ -0,0 +1,8 @@ +// RUN: %clang_cc1 -fno-builtin -O1 -S -o - %s | FileCheck %s + +void PR13497() { + char content[2]; + // make sure we don't optimize this call to strcpy() + // CHECK: __strcpy_chk + __builtin___strcpy_chk(content, "", 1); +} diff --git a/test/CodeGen/ptx-cc.c b/test/CodeGen/nvptx-cc.c index 2212d42..1c0d943 100644 --- a/test/CodeGen/ptx-cc.c +++ b/test/CodeGen/nvptx-cc.c @@ -1,7 +1,7 @@ -// RUN: %clang_cc1 -triple ptx32-unknown-unknown -O3 -S -o %t %s -emit-llvm -// RUN: %clang_cc1 -triple ptx64-unknown-unknown -O3 -S -o %t %s -emit-llvm +// RUN: %clang_cc1 -triple nvptx-unknown-unknown -O3 -S -o %t %s -emit-llvm +// RUN: %clang_cc1 -triple nvptx64-unknown-unknown -O3 -S -o %t %s -emit-llvm -// Just make sure Clang uses the proper calling convention for the PTX back-end. +// Just make sure Clang uses the proper calling convention for the NVPTX back-end. // If something is wrong, the back-end will fail. void foo(float* a, float* b) { diff --git a/test/CodeGen/nvptx-inlineasm.c b/test/CodeGen/nvptx-inlineasm.c new file mode 100644 index 0000000..860b50f --- /dev/null +++ b/test/CodeGen/nvptx-inlineasm.c @@ -0,0 +1,15 @@ +// RUN: %clang_cc1 -triple nvptx-unknown-unknown -O3 -S -o - %s -emit-llvm | FileCheck %s +// RUN: %clang_cc1 -triple nvptx64-unknown-unknown -O3 -S -o - %s -emit-llvm | FileCheck %s + +int bar(int a) { + int result; + // CHECK: call i32 asm sideeffect "{ {{.*}} + asm __volatile__ ("{ \n\t" + ".reg .pred \t%%p1; \n\t" + ".reg .pred \t%%p2; \n\t" + "setp.ne.u32 \t%%p1, %1, 0; \n\t" + "vote.any.pred \t%%p2, %%p1; \n\t" + "selp.s32 \t%0, 1, 0, %%p2; \n\t" + "}" : "=r"(result) : "r"(a)); + return result; +} diff --git a/test/CodeGen/object-size.c b/test/CodeGen/object-size.c index 1f16d02..f6c7db8 100644 --- a/test/CodeGen/object-size.c +++ b/test/CodeGen/object-size.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -triple x86_64-apple-darwin -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -triple x86_64-apple-darwin -emit-llvm %s -o - 2>&1 | FileCheck %s #define strcpy(dest, src) \ ((__builtin_object_size(dest, 0) != -1ULL) \ @@ -55,7 +55,10 @@ void test6() { // CHECK: define void @test7 void test7() { int i; - // CHECK: = call i64 @llvm.objectsize.i64(i8* {{.*}}@gbuf{{.*}}, i1 false) + // Ensure we only evaluate the side-effect once. + // CHECK: = add + // CHECK-NOT: = add + // CHECK: = call i8* @__strcpy_chk(i8* getelementptr inbounds ([63 x i8]* @gbuf, i32 0, i32 0), i8* getelementptr inbounds ([9 x i8]* @.str, i32 0, i32 0), i64 63) strcpy((++i, gbuf), "Hi there"); } @@ -124,6 +127,7 @@ void test16() { strcpy(gp += 1, "Hi there"); } +// CHECK: @test17 void test17() { // CHECK: store i32 -1 gi = __builtin_object_size(gp++, 0); @@ -134,3 +138,11 @@ void test17() { // CHECK: store i32 0 gi = __builtin_object_size(gp++, 3); } + +// CHECK: @test18 +unsigned test18(int cond) { + int a[4], b[4]; + // CHECK: phi i32* + // CHECK: call i64 @llvm.objectsize.i64 + return __builtin_object_size(cond ? a : b, 0); +} diff --git a/test/CodeGen/packed-nest-unpacked.c b/test/CodeGen/packed-nest-unpacked.c index 0ccc0c4..6097e3f 100644 --- a/test/CodeGen/packed-nest-unpacked.c +++ b/test/CodeGen/packed-nest-unpacked.c @@ -45,3 +45,21 @@ void test6() { // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* bitcast (%struct.X* getelementptr inbounds (%struct.Y* @g, i32 0, i32 1) to i8*), i8* %{{.*}}, i64 24, i32 1, i1 false) g.y = foo(); } + + +struct XBitfield { + unsigned b1 : 10; + unsigned b2 : 12; + unsigned b3 : 10; +}; +struct YBitfield { + char x; + struct XBitfield y; +} __attribute((packed)); +struct YBitfield gbitfield; + +unsigned test7() { + // CHECK: @test7 + // CHECK: load i32* bitcast (%struct.XBitfield* getelementptr inbounds (%struct.YBitfield* @gbitfield, i32 0, i32 1) to i32*), align 1 + return gbitfield.y.b2; +} diff --git a/test/CodeGen/pclmul-builtins.c b/test/CodeGen/pclmul-builtins.c new file mode 100644 index 0000000..cb0af28 --- /dev/null +++ b/test/CodeGen/pclmul-builtins.c @@ -0,0 +1,11 @@ +// RUN: %clang_cc1 %s -O3 -triple=x86_64-apple-darwin -target-feature +pclmul -emit-llvm -o - | FileCheck %s + +// Don't include mm_malloc.h, it's system specific. +#define __MM_MALLOC_H + +#include <wmmintrin.h> + +__m128i test_mm_clmulepi64_si128(__m128i a, __m128i b) { + // CHECK: @llvm.x86.pclmulqdq + return _mm_clmulepi64_si128(a, b, 0); +} diff --git a/test/CodeGen/powerpc_types.c b/test/CodeGen/powerpc_types.c index b7d0f5d..b4de318 100644 --- a/test/CodeGen/powerpc_types.c +++ b/test/CodeGen/powerpc_types.c @@ -1,3 +1,4 @@ +// REQUIRES: ppc32-registered-target // RUN: %clang_cc1 -triple powerpc-unknown-freebsd -emit-llvm -o - %s| FileCheck -check-prefix=SVR4-CHECK %s #include <stdarg.h> diff --git a/test/CodeGen/pr12251.c b/test/CodeGen/pr12251.c index a644bb7..b017131 100644 --- a/test/CodeGen/pr12251.c +++ b/test/CodeGen/pr12251.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 %s -emit-llvm -O1 -relaxed-aliasing -o - | FileCheck %s +// RUN: %clang_cc1 -triple x86_64-apple-darwin %s -emit-llvm -O1 -relaxed-aliasing -o - | FileCheck %s enum e1 {e1_a = -1 }; enum e1 g1(enum e1 *x) { diff --git a/test/CodeGen/pr13168.c b/test/CodeGen/pr13168.c new file mode 100644 index 0000000..a848af4 --- /dev/null +++ b/test/CodeGen/pr13168.c @@ -0,0 +1,7 @@ +// RUN: %clang_cc1 -emit-llvm %s -o - + +typedef int (*_MD_Open64)(int oflag, ...); +_MD_Open64 _open64; +void PR_OpenFile(int mode) { +_open64(0, mode); +} diff --git a/test/CodeGen/pr5406.c b/test/CodeGen/pr5406.c index da74d6b..2d19822 100644 --- a/test/CodeGen/pr5406.c +++ b/test/CodeGen/pr5406.c @@ -1,3 +1,4 @@ +// REQUIRES: arm-registered-target // RUN: %clang_cc1 %s -emit-llvm -triple arm-apple-darwin -o - | FileCheck %s // PR 5406 diff --git a/test/CodeGen/pragma-visibility.c b/test/CodeGen/pragma-visibility.c index 16460a2..a7fceb3 100644 --- a/test/CodeGen/pragma-visibility.c +++ b/test/CodeGen/pragma-visibility.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple x86_64-apple-darwin -emit-llvm -o - %s | FileCheck %s #pragma GCC visibility push(hidden) int x = 2; diff --git a/test/CodeGen/rdrand-builtins.c b/test/CodeGen/rdrand-builtins.c new file mode 100644 index 0000000..b7970f4 --- /dev/null +++ b/test/CodeGen/rdrand-builtins.c @@ -0,0 +1,27 @@ +// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-feature +rdrnd -emit-llvm -S -emit-llvm -o - %s | FileCheck %s + +// Don't include mm_malloc.h, it's system specific. +#define __MM_MALLOC_H + +#include <immintrin.h> + +int rdrand16(unsigned short *p) { + return _rdrand16_step(p); +// CHECK: @rdrand16 +// CHECK: call { i16, i32 } @llvm.x86.rdrand.16 +// CHECK: store i16 +} + +int rdrand32(unsigned *p) { + return _rdrand32_step(p); +// CHECK: @rdrand32 +// CHECK: call { i32, i32 } @llvm.x86.rdrand.32 +// CHECK: store i32 +} + +int rdrand64(unsigned long long *p) { + return _rdrand64_step(p); +// CHECK: @rdrand64 +// CHECK: call { i64, i32 } @llvm.x86.rdrand.64 +// CHECK: store i64 +} diff --git a/test/CodeGen/regparm-flag.c b/test/CodeGen/regparm-flag.c index 8ecf539..1330663 100644 --- a/test/CodeGen/regparm-flag.c +++ b/test/CodeGen/regparm-flag.c @@ -1,5 +1,4 @@ -// RUN: %clang_cc1 -triple i386-unknown-unknown -mregparm 4 %s -emit-llvm -o %t -// RUN: FileCheck < %t %s +// RUN: %clang_cc1 -triple i386-unknown-unknown -mregparm 4 %s -emit-llvm -o - | FileCheck %s void f1(int a, int b, int c, int d, int e, int f, int g, int h); diff --git a/test/CodeGen/regparm-struct.c b/test/CodeGen/regparm-struct.c new file mode 100644 index 0000000..b319012 --- /dev/null +++ b/test/CodeGen/regparm-struct.c @@ -0,0 +1,177 @@ +// RUN: %clang_cc1 -triple i386-unknown-unknown %s -emit-llvm -o - | FileCheck %s + +__attribute__((regparm(3))) void f1(int a, int b, int c, int d); +// CHECK: declare void @f1(i32 inreg, i32 inreg, i32 inreg, i32) +void g1() { + f1(41, 42, 43, 44); +} + +struct s1 { + int x1; +}; +__attribute__((regparm(3))) void f2(int a, int b, struct s1 c, int d); +// CHECK: declare void @f2(i32 inreg, i32 inreg, i32 inreg, i32) +void g2() { + struct s1 x = {43}; + f2(41, 42, x, 44); +} + +struct s2 { + int x1; + int x2; +}; +__attribute__((regparm(3))) void f3(int a, int b, struct s2 c, int d); +// CHECK: declare void @f3(i32 inreg, i32 inreg, i32, i32, i32) +void g3() { + struct s2 x = {43, 44}; + f3(41, 42, x, 45); +} +__attribute__((regparm(3))) void f4(int a, struct s2 b, int c); +// CHECK: declare void @f4(i32 inreg, i32 inreg, i32 inreg, i32) +void g4() { + struct s2 x = {42, 43}; + f4(41, x, 44); +} + +struct s3 { + int x1; + int x2; + int x3; +}; +__attribute__((regparm(3))) void f5(int a, struct s3 b, int c); +// CHECK: declare void @f5(i32 inreg, i32, i32, i32, i32) +void g5() { + struct s3 x = {42, 43, 44}; + f5(41, x, 45); +} +__attribute__((regparm(3))) void f6(struct s3 a, int b); +// CHECK: declare void @f6(i32 inreg, i32 inreg, i32 inreg, i32) +void g6() { + struct s3 x = {41, 42, 43}; + f6(x, 44); +} + +struct s4 { + int x1; + int x2; + int x3; + int x4; +}; +__attribute__((regparm(3))) void f7(struct s4 a, int b); +// CHECK: declare void @f7(i32, i32, i32, i32, i32) +void g7() { + struct s4 x = {41, 42, 43, 44}; + f7(x, 45); +} + +__attribute__((regparm(3))) void f8(float a, int b); +// CHECK: declare void @f8(float, i32 inreg) +void g8(void) { + f8(41, 42); +} + +struct s5 { + float x1; +}; +__attribute__((regparm(3))) void f9(struct s5 a, int b); +// CHECK: declare void @f9(float, i32 inreg) +void g9(void) { + struct s5 x = {41}; + f9(x, 42); +} + +struct s6 { + float x1; + int x2; +}; +__attribute__((regparm(3))) void f10(struct s6 a, int b); +// CHECK: declare void @f10(i32 inreg, i32 inreg, i32 inreg) +void g10(void) { + struct s6 x = {41, 42}; + f10(x, 43); +} + +struct s7 { + float x1; + int x2; + float x3; +}; +__attribute__((regparm(3))) void f11(struct s7 a, int b); +// CHECK: declare void @f11(i32 inreg, i32 inreg, i32 inreg, i32) +void g11(void) { + struct s7 x = {41, 42, 43}; + f11(x, 44); +} + +struct s8 { + float x1; + float x2; +}; +__attribute__((regparm(3))) void f12(struct s8 a, int b); +// CHECK: declare void @f12(i32 inreg, i32 inreg, i32 inreg) +void g12(void) { + struct s8 x = {41, 42}; + f12(x, 43); +} + +struct s9 { + float x1; + float x2; + float x3; +}; +__attribute__((regparm(3))) void f13(struct s9 a, int b); +// CHECK: declare void @f13(i32 inreg, i32 inreg, i32 inreg, i32) +void g13(void) { + struct s9 x = {41, 42, 43}; + f13(x, 44); +} + +struct s10 { + double x1; +}; +__attribute__((regparm(3))) void f14(struct s10 a, int b, int c); +// CHECK: declare void @f14(double, i32 inreg, i32 inreg) +void g14(void) { + struct s10 x = { 41 }; + f14(x, 42, 43); +} + +struct s11 { + double x1; + double x2; +}; +__attribute__((regparm(3))) void f15(struct s11 a, int b); +// CHECK: declare void @f15(double, double, i32) +void g15(void) { + struct s11 x = { 41, 42 }; + f15(x, 43); +} + +struct s12 { + double x1; + float x2; +}; +__attribute__((regparm(3))) void f16(struct s12 a, int b); +// CHECK: declare void @f16(i32 inreg, i32 inreg, i32 inreg, i32) +void g16(void) { + struct s12 x = { 41, 42 }; + f16(x, 43); +} + +__attribute__((regparm(3))) struct s12 f17(int a, int b, int c); +// CHECK: declare void @f17(%struct.s12* inreg sret, i32 inreg, i32 inreg, i32) +void g17(void) { + f17(41, 42, 43); +} + +struct s13 { + struct inner { + float x; + } y; +}; +__attribute__((regparm(3))) void f18(struct s13 a, int b, int c, int d); +// CHECK: declare void @f18(%struct.s13* byval align 4, i32 inreg, i32 inreg, i32 inreg) +void g18(void) { + struct s13 x = {{41}}; + f18(x, 42, 43, 44); +} diff --git a/test/CodeGen/sse-builtins.c b/test/CodeGen/sse-builtins.c index 2d57425..0e48560 100644 --- a/test/CodeGen/sse-builtins.c +++ b/test/CodeGen/sse-builtins.c @@ -151,3 +151,9 @@ __m128d test_mm_round_sd(__m128d x, __m128d y) { // CHECK: @llvm.x86.sse41.round.sd return _mm_round_sd(x, y, 2); } + +void test_storel_epi64(__m128i x, void* y) { + // CHECK: define void @test_storel_epi64 + // CHECK: store {{.*}} i64* {{.*}}, align 1{{$}} + _mm_storel_epi64(y, x); +} diff --git a/test/CodeGen/sse4a-builtins.c b/test/CodeGen/sse4a-builtins.c new file mode 100644 index 0000000..e1d7e8f --- /dev/null +++ b/test/CodeGen/sse4a-builtins.c @@ -0,0 +1,39 @@ +// RUN: %clang_cc1 -ffreestanding -triple i386-apple-darwin9 -target-cpu pentium4 -target-feature +sse4a -g -emit-llvm %s -o - | FileCheck %s + +#include <ammintrin.h> + +__m128i test_extracti_si64(__m128i x) { + return _mm_extracti_si64(x, 3, 2); +// CHECK: @test_extracti_si64 +// CHECK: @llvm.x86.sse4a.extrqi(<2 x i64> %{{[^,]+}}, i8 3, i8 2) +} + +__m128i test_extract_si64(__m128i x, __m128i y) { + return _mm_extract_si64(x, y); +// CHECK: @test_extract_si64 +// CHECK: @llvm.x86.sse4a.extrq(<2 x i64> %{{[^,]+}}, <16 x i8> %{{[^,]+}}) +} + +__m128i test_inserti_si64(__m128i x, __m128i y) { + return _mm_inserti_si64(x, y, 5, 6); +// CHECK: @test_inserti_si64 +// CHECK: @llvm.x86.sse4a.insertqi(<2 x i64> %{{[^,]+}}, <2 x i64> %{{[^,]+}}, i8 5, i8 6) +} + +__m128i test_insert_si64(__m128i x, __m128i y) { + return _mm_insert_si64(x, y); +// CHECK: @test_insert_si64 +// CHECK: @llvm.x86.sse4a.insertq(<2 x i64> %{{[^,]+}}, <2 x i64> %{{[^,]+}}) +} + +void test_stream_sd(double *p, __m128d a) { + _mm_stream_sd(p, a); +// CHECK: @test_stream_sd +// CHECK: @llvm.x86.sse4a.movnt.sd(i8* %{{[^,]+}}, <2 x double> %{{[^,]+}}) +} + +void test_stream_ss(float *p, __m128 a) { + _mm_stream_ss(p, a); +// CHECK: @test_stream_ss +// CHECK: @llvm.x86.sse4a.movnt.ss(i8* %{{[^,]+}}, <4 x float> %{{[^,]+}}) +} diff --git a/test/CodeGen/struct-init.c b/test/CodeGen/struct-init.c index 6247729..5273138 100644 --- a/test/CodeGen/struct-init.c +++ b/test/CodeGen/struct-init.c @@ -1,3 +1,4 @@ +// REQUIRES: arm-registered-target // RUN: %clang_cc1 -S -triple armv7-apple-darwin %s -emit-llvm -o - | FileCheck %s typedef struct _zend_ini_entry zend_ini_entry; diff --git a/test/CodeGen/struct-matching-constraint.c b/test/CodeGen/struct-matching-constraint.c index 40c444f..bdd11c8 100644 --- a/test/CodeGen/struct-matching-constraint.c +++ b/test/CodeGen/struct-matching-constraint.c @@ -1,3 +1,4 @@ +// REQUIRES: arm-registered-target // RUN: %clang_cc1 -S -emit-llvm -triple armv7a-apple-darwin %s -o /dev/null typedef unsigned short uint16_t; typedef __attribute__((neon_vector_type(8))) uint16_t uint16x8_t; diff --git a/test/CodeGen/tbaa-for-vptr.cpp b/test/CodeGen/tbaa-for-vptr.cpp index 5ce6bf3..b9a68fe 100644 --- a/test/CodeGen/tbaa-for-vptr.cpp +++ b/test/CodeGen/tbaa-for-vptr.cpp @@ -1,5 +1,13 @@ +// RUN: %clang_cc1 -emit-llvm -o - -O0 -fthread-sanitizer %s | FileCheck %s // RUN: %clang_cc1 -emit-llvm -o - -O1 %s | FileCheck %s +// RUN: %clang_cc1 -emit-llvm -o - -O1 -relaxed-aliasing -fthread-sanitizer %s | FileCheck %s +// +// RUN: %clang_cc1 -emit-llvm -o - -O0 %s | FileCheck %s --check-prefix=NOTBAA +// RUN: %clang_cc1 -emit-llvm -o - -O2 -relaxed-aliasing %s | FileCheck %s --check-prefix=NOTBAA +// // Check that we generate TBAA for vtable pointer loads and stores. +// When -fthread-sanitizer is used TBAA should be generated at all opt levels +// even if -relaxed-aliasing is present. struct A { virtual int foo() const ; virtual ~A(); @@ -15,5 +23,5 @@ void CallFoo(A *a) { // CHECK: %{{.*}} = load {{.*}} !tbaa !0 // CHECK: store {{.*}} !tbaa !0 -// CHECK: !0 = metadata !{metadata !"vtable pointer", metadata !1} -// CHECK: !1 = metadata !{metadata !"Simple C/C++ TBAA"} +// CHECK: = metadata !{metadata !"vtable pointer", metadata !{{.*}}} +// NOTBAA-NOT: = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/CodeGen/thread-specifier.c b/test/CodeGen/thread-specifier.c index a1f3e16..a2d3e62 100644 --- a/test/CodeGen/thread-specifier.c +++ b/test/CodeGen/thread-specifier.c @@ -3,7 +3,13 @@ // CHECK: @b = external thread_local global // CHECK: @d.e = internal thread_local global // CHECK: @d.f = internal thread_local global +// CHECK: @f.a = internal thread_local(initialexec) global // CHECK: @a = thread_local global +// CHECK: @g = thread_local global +// CHECK: @h = thread_local(localdynamic) global +// CHECK: @i = thread_local(initialexec) global +// CHECK: @j = thread_local(localexec) global + __thread int a; extern __thread int b; int c() { return *&b; } @@ -13,3 +19,12 @@ int d() { return 0; } +__thread int g __attribute__((tls_model("global-dynamic"))); +__thread int h __attribute__((tls_model("local-dynamic"))); +__thread int i __attribute__((tls_model("initial-exec"))); +__thread int j __attribute__((tls_model("local-exec"))); + +int f() { + __thread static int a __attribute__((tls_model("initial-exec"))); + return a++; +} diff --git a/test/CodeGen/tls-model.c b/test/CodeGen/tls-model.c new file mode 100644 index 0000000..b5bae77 --- /dev/null +++ b/test/CodeGen/tls-model.c @@ -0,0 +1,28 @@ +// RUN: %clang_cc1 %s -triple x86_64-pc-linux-gnu -emit-llvm -o - | FileCheck %s -check-prefix=CHECK-GD +// RUN: %clang_cc1 %s -triple x86_64-pc-linux-gnu -ftls-model=global-dynamic -emit-llvm -o - | FileCheck %s -check-prefix=CHECK-GD +// RUN: %clang_cc1 %s -triple x86_64-pc-linux-gnu -ftls-model=local-dynamic -emit-llvm -o - | FileCheck %s -check-prefix=CHECK-LD +// RUN: %clang_cc1 %s -triple x86_64-pc-linux-gnu -ftls-model=initial-exec -emit-llvm -o - | FileCheck %s -check-prefix=CHECK-IE +// RUN: %clang_cc1 %s -triple x86_64-pc-linux-gnu -ftls-model=local-exec -emit-llvm -o - | FileCheck %s -check-prefix=CHECK-LE + +int __thread x; +int f() { + static int __thread y; + return y++; +} +int __thread __attribute__((tls_model("initial-exec"))) z; + +// CHECK-GD: @f.y = internal thread_local global i32 0 +// CHECK-GD: @x = thread_local global i32 0 +// CHECK-GD: @z = thread_local(initialexec) global i32 0 + +// CHECK-LD: @f.y = internal thread_local(localdynamic) global i32 0 +// CHECK-LD: @x = thread_local(localdynamic) global i32 0 +// CHECK-LD: @z = thread_local(initialexec) global i32 0 + +// CHECK-IE: @f.y = internal thread_local(initialexec) global i32 0 +// CHECK-IE: @x = thread_local(initialexec) global i32 0 +// CHECK-IE: @z = thread_local(initialexec) global i32 0 + +// CHECK-LE: @f.y = internal thread_local(localexec) global i32 0 +// CHECK-LE: @x = thread_local(localexec) global i32 0 +// CHECK-LE: @z = thread_local(initialexec) global i32 0 diff --git a/test/CodeGen/varargs.c b/test/CodeGen/varargs.c index b3dba24..b6973d8 100644 --- a/test/CodeGen/varargs.c +++ b/test/CodeGen/varargs.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -emit-llvm -o - %s +// RUN: %clang_cc1 -emit-llvm -o - %s | FileCheck %s // PR6433 - Don't crash on va_arg(typedef). @@ -9,3 +9,9 @@ void focus_changed_cb () { mfloat = __builtin_va_arg((pa), gdouble); } +void vararg(int, ...); +void function_as_vararg() { + // CHECK: define {{.*}}function_as_vararg + // CHECK-NOT: llvm.trap + vararg(0, focus_changed_cb); +} diff --git a/test/CodeGen/vector-alignment.c b/test/CodeGen/vector-alignment.c new file mode 100644 index 0000000..92d1ae7 --- /dev/null +++ b/test/CodeGen/vector-alignment.c @@ -0,0 +1,38 @@ +// RUN: %clang_cc1 -w -triple x86_64-apple-darwin10 -emit-llvm -o - %s | FileCheck %s +// rdar://11759609 + +// At or below target max alignment with no aligned attribute should align based +// on the size of vector. +double __attribute__((vector_size(16))) v1; +// CHECK: @v1 {{.*}}, align 16 +double __attribute__((vector_size(32))) v2; +// CHECK: @v2 {{.*}}, align 32 + +// Alignment above target max alignment with no aligned attribute should align +// based on the target max. +double __attribute__((vector_size(64))) v3; +// CHECK: @v3 {{.*}}, align 32 +double __attribute__((vector_size(1024))) v4; +// CHECK: @v4 {{.*}}, align 32 + +// Aliged attribute should always override. +double __attribute__((vector_size(16), aligned(16))) v5; +// CHECK: @v5 {{.*}}, align 16 +double __attribute__((vector_size(16), aligned(64))) v6; +// CHECK: @v6 {{.*}}, align 64 +double __attribute__((vector_size(32), aligned(16))) v7; +// CHECK: @v7 {{.*}}, align 16 +double __attribute__((vector_size(32), aligned(64))) v8; +// CHECK: @v8 {{.*}}, align 64 + +// Check non-power of 2 widths. +double __attribute__((vector_size(24))) v9; +// CHECK: @v9 {{.*}}, align 32 +double __attribute__((vector_size(40))) v10; +// CHECK: @v10 {{.*}}, align 32 + +// Check non-power of 2 widths with aligned attribute. +double __attribute__((vector_size(24), aligned(64))) v11; +// CHECK: @v11 {{.*}}, align 64 +double __attribute__((vector_size(80), aligned(16))) v12; +// CHECK: @v12 {{.*}}, align 16 diff --git a/test/CodeGen/vla.c b/test/CodeGen/vla.c index 9e62da5..e151827 100644 --- a/test/CodeGen/vla.c +++ b/test/CodeGen/vla.c @@ -142,3 +142,52 @@ int test4(unsigned n, char (*p)[n][n+1][6]) { // CHECK-NEXT: ret i32 [[T7]] return p2 - p; } + +// rdar://11485774 +void test5(void) +{ + // CHECK: define void @test5( + int a[5], i = 0; + // CHECK: [[A:%.*]] = alloca [5 x i32], align 4 + // CHECK-NEXT: [[I:%.*]] = alloca i32, align 4 + // CHECK-NEXT: [[CL:%.*]] = alloca i32*, align 4 + // CHECK-NEXT: store i32 0, i32* [[I]], align 4 + + (typeof(++i, (int (*)[i])a)){&a} += 0; + // CHECK-NEXT: [[Z:%.*]] = load i32* [[I]], align 4 + // CHECK-NEXT: [[INC:%.*]] = add nsw i32 [[Z]], 1 + // CHECK-NEXT: store i32 [[INC]], i32* [[I]], align 4 + // CHECK-NEXT: [[O:%.*]] = load i32* [[I]], align 4 + // CHECK-NEXT: [[AR:%.*]] = getelementptr inbounds [5 x i32]* [[A]], i32 0, i32 0 + // CHECK-NEXT: [[T:%.*]] = bitcast [5 x i32]* [[A]] to i32* + // CHECK-NEXT: store i32* [[T]], i32** [[CL]] + // CHECK-NEXT: [[TH:%.*]] = load i32** [[CL]] + // CHECK-NEXT: [[VLAIX:%.*]] = mul nsw i32 0, [[O]] + // CHECK-NEXT: [[ADDPTR:%.*]] = getelementptr inbounds i32* [[TH]], i32 [[VLAIX]] + // CHECK-NEXT: store i32* [[ADDPTR]], i32** [[CL]] +} + +void test6(void) +{ + // CHECK: define void @test6( + int n = 20, **a, i=0; + // CHECK: [[N:%.*]] = alloca i32, align 4 + // CHECK-NEXT: [[A:%.*]] = alloca i32**, align 4 + // CHECK-NEXT: [[I:%.*]] = alloca i32, align 4 + (int (**)[i]){&a}[0][1][5] = 0; + // CHECK-NEXT: [[CL:%.*]] = alloca i32**, align 4 + // CHECK-NEXT: store i32 20, i32* [[N]], align 4 + // CHECK-NEXT: store i32 0, i32* [[I]], align 4 + // CHECK-NEXT: [[Z:%.*]] = load i32* [[I]], align 4 + // CHECK-NEXT: [[O:%.*]] = bitcast i32*** [[A]] to i32** + // CHECK-NEXT: store i32** [[O]], i32*** [[CL]] + // CHECK-NEXT: [[T:%.*]] = load i32*** [[CL]] + // CHECK-NEXT: [[IX:%.*]] = getelementptr inbounds i32** [[T]], i32 0 + // CHECK-NEXT: [[TH:%.*]] = load i32** [[IX]], align 4 + // CHECK-NEXT: [[F:%.*]] = mul nsw i32 1, [[Z]] + // CHECK-NEXT: [[IX1:%.*]] = getelementptr inbounds i32* [[TH]], i32 [[F]] + // CHECK-NEXT: [[IX2:%.*]] = getelementptr inbounds i32* [[IX1]], i32 5 + // CHECK-NEXT: store i32 0, i32* [[IX2]], align 4 +} + + diff --git a/test/CodeGen/vld_dup.c b/test/CodeGen/vld_dup.c index e1d63cc..2bc2519 100644 --- a/test/CodeGen/vld_dup.c +++ b/test/CodeGen/vld_dup.c @@ -1,3 +1,4 @@ +// REQUIRES: arm-registered-target // RUN: %clang_cc1 -triple armv7a-linux-gnueabi \ // RUN: -target-cpu cortex-a8 \ // RUN: -emit-llvm -O0 -o - %s | FileCheck %s diff --git a/test/CodeGen/x86_32-arguments-darwin.c b/test/CodeGen/x86_32-arguments-darwin.c index 0ac18b7..5bbc80b 100644 --- a/test/CodeGen/x86_32-arguments-darwin.c +++ b/test/CodeGen/x86_32-arguments-darwin.c @@ -324,3 +324,16 @@ void f64(struct s64 x) {} // CHECK: define float @f65() struct s65 { signed char a[0]; float b; }; struct s65 f65() { return (struct s65){{},2}; } + +// CHECK: define <2 x i64> @f66 +// CHECK: ptrtoint +// CHECK: and {{.*}}, -16 +// CHECK: inttoptr +typedef int T66 __attribute((vector_size(16))); +T66 f66(int i, ...) { + __builtin_va_list ap; + __builtin_va_start(ap, i); + T66 v = __builtin_va_arg(ap, T66); + __builtin_va_end(ap); + return v; +} diff --git a/test/CodeGen/xop-builtins.c b/test/CodeGen/xop-builtins.c new file mode 100644 index 0000000..436deaa --- /dev/null +++ b/test/CodeGen/xop-builtins.c @@ -0,0 +1,326 @@ +// RUN: %clang_cc1 %s -O3 -triple=x86_64-apple-darwin -target-feature +xop -emit-llvm -o - | FileCheck %s + +// Don't include mm_malloc.h, it's system specific. +#define __MM_MALLOC_H + +#include <x86intrin.h> + +__m128i test_mm_maccs_epi16(__m128i a, __m128i b, __m128i c) { + // CHECK: @llvm.x86.xop.vpmacssww + return _mm_maccs_epi16(a, b, c); +} + +__m128i test_mm_macc_epi16(__m128i a, __m128i b, __m128i c) { + // CHECK: @llvm.x86.xop.vpmacsww + return _mm_macc_epi16(a, b, c); +} + +__m128i test_mm_maccsd_epi16(__m128i a, __m128i b, __m128i c) { + // CHECK: @llvm.x86.xop.vpmacsswd + return _mm_maccsd_epi16(a, b, c); +} + +__m128i test_mm_maccd_epi16(__m128i a, __m128i b, __m128i c) { + // CHECK: @llvm.x86.xop.vpmacswd + return _mm_maccd_epi16(a, b, c); +} + +__m128i test_mm_maccs_epi32(__m128i a, __m128i b, __m128i c) { + // CHECK: @llvm.x86.xop.vpmacssdd + return _mm_maccs_epi32(a, b, c); +} + +__m128i test_mm_macc_epi32(__m128i a, __m128i b, __m128i c) { + // CHECK: @llvm.x86.xop.vpmacsdd + return _mm_macc_epi32(a, b, c); +} + +__m128i test_mm_maccslo_epi32(__m128i a, __m128i b, __m128i c) { + // CHECK: @llvm.x86.xop.vpmacssdql + return _mm_maccslo_epi32(a, b, c); +} + +__m128i test_mm_macclo_epi32(__m128i a, __m128i b, __m128i c) { + // CHECK: @llvm.x86.xop.vpmacsdql + return _mm_macclo_epi32(a, b, c); +} + +__m128i test_mm_maccshi_epi32(__m128i a, __m128i b, __m128i c) { + // CHECK: @llvm.x86.xop.vpmacssdqh + return _mm_maccshi_epi32(a, b, c); +} + +__m128i test_mm_macchi_epi32(__m128i a, __m128i b, __m128i c) { + // CHECK: @llvm.x86.xop.vpmacsdqh + return _mm_macchi_epi32(a, b, c); +} + +__m128i test_mm_maddsd_epi16(__m128i a, __m128i b, __m128i c) { + // CHECK: @llvm.x86.xop.vpmadcsswd + return _mm_maddsd_epi16(a, b, c); +} + +__m128i test_mm_maddd_epi16(__m128i a, __m128i b, __m128i c) { + // CHECK: @llvm.x86.xop.vpmadcswd + return _mm_maddd_epi16(a, b, c); +} + +__m128i test_mm_haddw_epi8(__m128i a) { + // CHECK: @llvm.x86.xop.vphaddbw + return _mm_haddw_epi8(a); +} + +__m128i test_mm_haddd_epi8(__m128i a) { + // CHECK: @llvm.x86.xop.vphaddbd + return _mm_haddd_epi8(a); +} + +__m128i test_mm_haddq_epi8(__m128i a) { + // CHECK: @llvm.x86.xop.vphaddbq + return _mm_haddq_epi8(a); +} + +__m128i test_mm_haddd_epi16(__m128i a) { + // CHECK: @llvm.x86.xop.vphaddwd + return _mm_haddd_epi16(a); +} + +__m128i test_mm_haddq_epi16(__m128i a) { + // CHECK: @llvm.x86.xop.vphaddwq + return _mm_haddq_epi16(a); +} + +__m128i test_mm_haddq_epi32(__m128i a) { + // CHECK: @llvm.x86.xop.vphadddq + return _mm_haddq_epi32(a); +} + +__m128i test_mm_haddw_epu8(__m128i a) { + // CHECK: @llvm.x86.xop.vphaddubw + return _mm_haddw_epu8(a); +} + +__m128i test_mm_haddd_epu8(__m128i a) { + // CHECK: @llvm.x86.xop.vphaddubd + return _mm_haddd_epu8(a); +} + +__m128i test_mm_haddq_epu8(__m128i a) { + // CHECK: @llvm.x86.xop.vphaddubq + return _mm_haddq_epu8(a); +} + +__m128i test_mm_haddd_epu16(__m128i a) { + // CHECK: @llvm.x86.xop.vphadduwd + return _mm_haddd_epu16(a); +} + +__m128i test_mm_haddq_epu16(__m128i a) { + // CHECK: @llvm.x86.xop.vphadduwq + return _mm_haddq_epu16(a); +} + +__m128i test_mm_haddq_epu32(__m128i a) { + // CHECK: @llvm.x86.xop.vphaddudq + return _mm_haddq_epu32(a); +} + +__m128i test_mm_hsubw_epi8(__m128i a) { + // CHECK: @llvm.x86.xop.vphsubbw + return _mm_hsubw_epi8(a); +} + +__m128i test_mm_hsubd_epi16(__m128i a) { + // CHECK: @llvm.x86.xop.vphsubwd + return _mm_hsubd_epi16(a); +} + +__m128i test_mm_hsubq_epi32(__m128i a) { + // CHECK: @llvm.x86.xop.vphsubdq + return _mm_hsubq_epi32(a); +} + +__m128i test_mm_cmov_si128(__m128i a, __m128i b, __m128i c) { + // CHECK: @llvm.x86.xop.vpcmov + return _mm_cmov_si128(a, b, c); +} + +__m256i test_mm256_cmov_si256(__m256i a, __m256i b, __m256i c) { + // CHECK: @llvm.x86.xop.vpcmov.256 + return _mm256_cmov_si256(a, b, c); +} + +__m128i test_mm_perm_epi8(__m128i a, __m128i b, __m128i c) { + // CHECK: @llvm.x86.xop.vpperm + return _mm_perm_epi8(a, b, c); +} + +__m128i test_mm_rot_epi8(__m128i a, __m128i b) { + // CHECK: @llvm.x86.xop.vprotb + return _mm_rot_epi8(a, b); +} + +__m128i test_mm_rot_epi16(__m128i a, __m128i b) { + // CHECK: @llvm.x86.xop.vprotw + return _mm_rot_epi16(a, b); +} + +__m128i test_mm_rot_epi32(__m128i a, __m128i b) { + // CHECK: @llvm.x86.xop.vprotd + return _mm_rot_epi32(a, b); +} + +__m128i test_mm_rot_epi64(__m128i a, __m128i b) { + // CHECK: @llvm.x86.xop.vprotq + return _mm_rot_epi64(a, b); +} + +__m128i test_mm_roti_epi8(__m128i a) { + // CHECK: @llvm.x86.xop.vprotbi + return _mm_roti_epi8(a, 1); +} + +__m128i test_mm_roti_epi16(__m128i a) { + // CHECK: @llvm.x86.xop.vprotwi + return _mm_roti_epi16(a, 50); +} + +__m128i test_mm_roti_epi32(__m128i a) { + // CHECK: @llvm.x86.xop.vprotdi + return _mm_roti_epi32(a, -30); +} + +__m128i test_mm_roti_epi64(__m128i a) { + // CHECK: @llvm.x86.xop.vprotqi + return _mm_roti_epi64(a, 100); +} + +__m128i test_mm_shl_epi8(__m128i a, __m128i b) { + // CHECK: @llvm.x86.xop.vpshlb + return _mm_shl_epi8(a, b); +} + +__m128i test_mm_shl_epi16(__m128i a, __m128i b) { + // CHECK: @llvm.x86.xop.vpshlw + return _mm_shl_epi16(a, b); +} + +__m128i test_mm_shl_epi32(__m128i a, __m128i b) { + // CHECK: @llvm.x86.xop.vpshld + return _mm_shl_epi32(a, b); +} + +__m128i test_mm_shl_epi64(__m128i a, __m128i b) { + // CHECK: @llvm.x86.xop.vpshlq + return _mm_shl_epi64(a, b); +} + +__m128i test_mm_sha_epi8(__m128i a, __m128i b) { + // CHECK: @llvm.x86.xop.vpshab + return _mm_sha_epi8(a, b); +} + +__m128i test_mm_sha_epi16(__m128i a, __m128i b) { + // CHECK: @llvm.x86.xop.vpshaw + return _mm_sha_epi16(a, b); +} + +__m128i test_mm_sha_epi32(__m128i a, __m128i b) { + // CHECK: @llvm.x86.xop.vpshad + return _mm_sha_epi32(a, b); +} + +__m128i test_mm_sha_epi64(__m128i a, __m128i b) { + // CHECK: @llvm.x86.xop.vpshaq + return _mm_sha_epi64(a, b); +} + +__m128i test_mm_com_epu8(__m128i a, __m128i b) { + // CHECK: @llvm.x86.xop.vpcomub + return _mm_com_epu8(a, b, 0); +} + +__m128i test_mm_com_epu16(__m128i a, __m128i b) { + // CHECK: @llvm.x86.xop.vpcomuw + return _mm_com_epu16(a, b, 0); +} + +__m128i test_mm_com_epu32(__m128i a, __m128i b) { + // CHECK: @llvm.x86.xop.vpcomud + return _mm_com_epu32(a, b, 0); +} + +__m128i test_mm_com_epu64(__m128i a, __m128i b) { + // CHECK: @llvm.x86.xop.vpcomuq + return _mm_com_epu64(a, b, 0); +} + +__m128i test_mm_com_epi8(__m128i a, __m128i b) { + // CHECK: @llvm.x86.xop.vpcomb + return _mm_com_epi8(a, b, 0); +} + +__m128i test_mm_com_epi16(__m128i a, __m128i b) { + // CHECK: @llvm.x86.xop.vpcomw + return _mm_com_epi16(a, b, 0); +} + +__m128i test_mm_com_epi32(__m128i a, __m128i b) { + // CHECK: @llvm.x86.xop.vpcomd + return _mm_com_epi32(a, b, 0); +} + +__m128i test_mm_com_epi64(__m128i a, __m128i b) { + // CHECK: @llvm.x86.xop.vpcomq + return _mm_com_epi64(a, b, 0); +} + +__m128d test_mm_permute2_pd(__m128d a, __m128d b, __m128i c) { + // CHECK: @llvm.x86.xop.vpermil2pd + return _mm_permute2_pd(a, b, c, 0); +} + +__m256d test_mm256_permute2_pd(__m256d a, __m256d b, __m256i c) { + // CHECK: @llvm.x86.xop.vpermil2pd.256 + return _mm256_permute2_pd(a, b, c, 0); +} + +__m128 test_mm_permute2_ps(__m128 a, __m128 b, __m128i c) { + // CHECK: @llvm.x86.xop.vpermil2ps + return _mm_permute2_ps(a, b, c, 0); +} + +__m256 test_mm256_permute2_ps(__m256 a, __m256 b, __m256i c) { + // CHECK: @llvm.x86.xop.vpermil2ps.256 + return _mm256_permute2_ps(a, b, c, 0); +} + +__m128 test_mm_frcz_ss(__m128 a) { + // CHECK: @llvm.x86.xop.vfrcz.ss + return _mm_frcz_ss(a); +} + +__m128d test_mm_frcz_sd(__m128d a) { + // CHECK: @llvm.x86.xop.vfrcz.sd + return _mm_frcz_sd(a); +} + +__m128 test_mm_frcz_ps(__m128 a) { + // CHECK: @llvm.x86.xop.vfrcz.ps + return _mm_frcz_ps(a); +} + +__m128d test_mm_frcz_pd(__m128d a) { + // CHECK: @llvm.x86.xop.vfrcz.pd + return _mm_frcz_pd(a); +} + +__m256 test_mm256_frcz_ps(__m256 a) { + // CHECK: @llvm.x86.xop.vfrcz.ps.256 + return _mm256_frcz_ps(a); +} + +__m256d test_mm256_frcz_pd(__m256d a) { + // CHECK: @llvm.x86.xop.vfrcz.pd.256 + return _mm256_frcz_pd(a); +} |
