diff options
Diffstat (limited to 'test/CodeGen')
88 files changed, 2203 insertions, 301 deletions
diff --git a/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll b/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll index ff01506..f775c61 100644 --- a/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll +++ b/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -mtriple=arm-linux-gnueabi -regalloc=local +; RUN: llc < %s -mtriple=arm-linux-gnueabi -regalloc=fast ; PR1925 %struct.encode_aux_nearestmatch = type { i32*, i32*, i32*, i32*, i32, i32 } diff --git a/test/CodeGen/ARM/2008-02-29-RegAllocLocal.ll b/test/CodeGen/ARM/2008-02-29-RegAllocLocal.ll index 06bc987..8ef8c7b 100644 --- a/test/CodeGen/ARM/2008-02-29-RegAllocLocal.ll +++ b/test/CodeGen/ARM/2008-02-29-RegAllocLocal.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -mtriple=arm-apple-darwin -regalloc=local +; RUN: llc < %s -mtriple=arm-apple-darwin -regalloc=fast ; PR1925 %"struct.kc::impl_Ccode_option" = type { %"struct.kc::impl_abstract_phylum" } diff --git a/test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll b/test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll index 670d204..a48e41f 100644 --- a/test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll +++ b/test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=arm-linuxeabi-unknown-gnu -mattr=+v6 +; RUN: llc < %s -mtriple=arm-unknown-linux-gnueabi -mattr=+v6 ; PR4166 %"byte[]" = type { i32, i8* } diff --git a/test/CodeGen/ARM/2009-05-07-RegAllocLocal.ll b/test/CodeGen/ARM/2009-05-07-RegAllocLocal.ll index 75610ff..912e6f9 100644 --- a/test/CodeGen/ARM/2009-05-07-RegAllocLocal.ll +++ b/test/CodeGen/ARM/2009-05-07-RegAllocLocal.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -mtriple=armv5-unknown-linux-gnueabi -O0 -regalloc=local +; RUN: llc < %s -mtriple=armv5-unknown-linux-gnueabi -O0 -regalloc=fast ; PR4100 @.str = external constant [30 x i8] ; <[30 x i8]*> [#uses=1] diff --git a/test/CodeGen/ARM/2009-11-02-NegativeLane.ll b/test/CodeGen/ARM/2009-11-02-NegativeLane.ll index f2288c3..89c9037 100644 --- a/test/CodeGen/ARM/2009-11-02-NegativeLane.ll +++ b/test/CodeGen/ARM/2009-11-02-NegativeLane.ll @@ -1,4 +1,4 @@ -; RUN: llc -mcpu=cortex-a8 < %s | grep vdup.32 +; RUN: llc -mcpu=cortex-a8 < %s | grep vdup.16 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" target triple = "armv7-eabi" @@ -7,12 +7,12 @@ entry: br i1 undef, label %return, label %bb bb: ; preds = %bb, %entry - %0 = load float* undef, align 4 ; <float> [#uses=1] - %1 = insertelement <4 x float> undef, float %0, i32 2 ; <<4 x float>> [#uses=1] - %2 = insertelement <4 x float> %1, float undef, i32 3 ; <<4 x float>> [#uses=1] - %3 = fmul <4 x float> undef, %2 ; <<4 x float>> [#uses=1] - %4 = extractelement <4 x float> %3, i32 1 ; <float> [#uses=1] - store float %4, float* undef, align 4 + %0 = load i16* undef, align 2 + %1 = insertelement <8 x i16> undef, i16 %0, i32 2 + %2 = insertelement <8 x i16> %1, i16 undef, i32 3 + %3 = mul <8 x i16> %2, %2 + %4 = extractelement <8 x i16> %3, i32 2 + store i16 %4, i16* undef, align 2 br i1 undef, label %return, label %bb return: ; preds = %bb, %entry diff --git a/test/CodeGen/ARM/2010-05-14-IllegalType.ll b/test/CodeGen/ARM/2010-05-14-IllegalType.ll new file mode 100644 index 0000000..99e5b09 --- /dev/null +++ b/test/CodeGen/ARM/2010-05-14-IllegalType.ll @@ -0,0 +1,10 @@ +; RUN: llc -march=thumb -mcpu=cortex-a8 -mtriple=thumbv7-eabi -float-abi=hard < %s | FileCheck %s + +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32" +target triple = "thumbv7-apple-darwin10" + +define <4 x i64> @f_4_i64(<4 x i64> %a, <4 x i64> %b) nounwind { +; CHECK: vadd.i64 + %y = add <4 x i64> %a, %b + ret <4 x i64> %y +} diff --git a/test/CodeGen/ARM/2010-05-17-DAGCombineAssert.ll b/test/CodeGen/ARM/2010-05-17-DAGCombineAssert.ll new file mode 100644 index 0000000..2a4bbd1 --- /dev/null +++ b/test/CodeGen/ARM/2010-05-17-DAGCombineAssert.ll @@ -0,0 +1,17 @@ +; RUN: llc < %s -mtriple=armv7-eabi -mcpu=cortex-a8 +; PR7158 + +define arm_aapcs_vfpcc i32 @main() nounwind { +bb.nph55.bb.nph55.split_crit_edge: + br label %bb3 + +bb3: ; preds = %bb3, %bb.nph55.bb.nph55.split_crit_edge + br i1 undef, label %bb.i19, label %bb3 + +bb.i19: ; preds = %bb.i19, %bb3 + %0 = insertelement <4 x float> undef, float undef, i32 3 ; <<4 x float>> [#uses=3] + %1 = fmul <4 x float> %0, %0 ; <<4 x float>> [#uses=1] + %2 = bitcast <4 x float> %1 to <2 x double> ; <<2 x double>> [#uses=0] + %3 = fmul <4 x float> %0, undef ; <<4 x float>> [#uses=0] + br label %bb.i19 +} diff --git a/test/CodeGen/ARM/2010-05-17-FastAllocCrash.ll b/test/CodeGen/ARM/2010-05-17-FastAllocCrash.ll new file mode 100644 index 0000000..813bf3c --- /dev/null +++ b/test/CodeGen/ARM/2010-05-17-FastAllocCrash.ll @@ -0,0 +1,105 @@ +; RUN: llc < %s -regalloc=fast -verify-machineinstrs +target triple = "arm-pc-linux-gnu" + +; This test case would accidentally use the same physreg for two virtregs +; because allocVirtReg forgot to check if registers were already used in the +; instruction. +; This caused the RegScavenger to complain, but -verify-machineinstrs also +; catches it. + +%struct.CHESS_POSITION = type { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i32, i32, i8, i8, [64 x i8], i8, i8, i8, i8, i8 } + +@search = external global %struct.CHESS_POSITION ; <%struct.CHESS_POSITION*> [#uses=1] +@bishop_mobility_rr45 = external global [64 x [256 x i32]] ; <[64 x [256 x i32]]*> [#uses=1] + +declare fastcc i32 @FirstOne() + +define fastcc void @Evaluate() { +entry: + br i1 false, label %cond_false186, label %cond_true + +cond_true: ; preds = %entry + ret void + +cond_false186: ; preds = %entry + br i1 false, label %cond_true293, label %bb203 + +bb203: ; preds = %cond_false186 + ret void + +cond_true293: ; preds = %cond_false186 + br i1 false, label %cond_true298, label %cond_next317 + +cond_true298: ; preds = %cond_true293 + br i1 false, label %cond_next518, label %cond_true397.preheader + +cond_next317: ; preds = %cond_true293 + ret void + +cond_true397.preheader: ; preds = %cond_true298 + ret void + +cond_next518: ; preds = %cond_true298 + br i1 false, label %bb1069, label %cond_true522 + +cond_true522: ; preds = %cond_next518 + ret void + +bb1069: ; preds = %cond_next518 + br i1 false, label %cond_next1131, label %bb1096 + +bb1096: ; preds = %bb1069 + ret void + +cond_next1131: ; preds = %bb1069 + br i1 false, label %cond_next1207, label %cond_true1150 + +cond_true1150: ; preds = %cond_next1131 + ret void + +cond_next1207: ; preds = %cond_next1131 + br i1 false, label %cond_next1219, label %cond_true1211 + +cond_true1211: ; preds = %cond_next1207 + ret void + +cond_next1219: ; preds = %cond_next1207 + br i1 false, label %cond_true1223, label %cond_next1283 + +cond_true1223: ; preds = %cond_next1219 + br i1 false, label %cond_true1254, label %cond_true1264 + +cond_true1254: ; preds = %cond_true1223 + br i1 false, label %bb1567, label %cond_true1369.preheader + +cond_true1264: ; preds = %cond_true1223 + ret void + +cond_next1283: ; preds = %cond_next1219 + ret void + +cond_true1369.preheader: ; preds = %cond_true1254 + ret void + +bb1567: ; preds = %cond_true1254 + %tmp1591 = load i64* getelementptr inbounds (%struct.CHESS_POSITION* @search, i32 0, i32 4) ; <i64> [#uses=1] + %tmp1572 = tail call fastcc i32 @FirstOne() ; <i32> [#uses=1] + %tmp1594 = load i32* undef ; <i32> [#uses=1] + %tmp1594.upgrd.5 = trunc i32 %tmp1594 to i8 ; <i8> [#uses=1] + %shift.upgrd.6 = zext i8 %tmp1594.upgrd.5 to i64 ; <i64> [#uses=1] + %tmp1595 = lshr i64 %tmp1591, %shift.upgrd.6 ; <i64> [#uses=1] + %tmp1595.upgrd.7 = trunc i64 %tmp1595 to i32 ; <i32> [#uses=1] + %tmp1596 = and i32 %tmp1595.upgrd.7, 255 ; <i32> [#uses=1] + %gep.upgrd.8 = zext i32 %tmp1596 to i64 ; <i64> [#uses=1] + %tmp1598 = getelementptr [64 x [256 x i32]]* @bishop_mobility_rr45, i32 0, i32 %tmp1572, i64 %gep.upgrd.8 ; <i32*> [#uses=1] + %tmp1599 = load i32* %tmp1598 ; <i32> [#uses=1] + %tmp1602 = sub i32 0, %tmp1599 ; <i32> [#uses=1] + br i1 undef, label %cond_next1637, label %cond_true1607 + +cond_true1607: ; preds = %bb1567 + ret void + +cond_next1637: ; preds = %bb1567 + %tmp1662 = sub i32 %tmp1602, 0 ; <i32> [#uses=0] + ret void +} diff --git a/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll b/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll new file mode 100644 index 0000000..b158afd --- /dev/null +++ b/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll @@ -0,0 +1,37 @@ +; RUN: llc < %s -O0 -verify-machineinstrs -regalloc=local +; RUN: llc < %s -O0 -verify-machineinstrs -regalloc=fast +; rdar://problem/7948106 +;; This test would spill %R4 before the call to zz, but it forgot to move the +; 'last use' marker to the spill. + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64-n32" +target triple = "armv6-apple-darwin" + +%struct.q = type { i32, i32 } + +@.str = external constant [1 x i8] ; <[1 x i8]*> [#uses=1] + +define arm_apcscc void @yy(%struct.q* %qq) nounwind { +entry: + %vla6 = alloca i8, i32 undef, align 1 ; <i8*> [#uses=1] + %vla10 = alloca i8, i32 undef, align 1 ; <i8*> [#uses=1] + %vla14 = alloca i8, i32 undef, align 1 ; <i8*> [#uses=1] + %vla18 = alloca i8, i32 undef, align 1 ; <i8*> [#uses=1] + %tmp21 = load i32* undef ; <i32> [#uses=1] + %0 = mul i32 1, %tmp21 ; <i32> [#uses=1] + %vla22 = alloca i8, i32 %0, align 1 ; <i8*> [#uses=1] + call arm_apcscc void (...)* @zz(i8* getelementptr inbounds ([1 x i8]* @.str, i32 0, i32 0), i32 2, i32 1) + br i1 undef, label %if.then, label %if.end36 + +if.then: ; preds = %entry + %call = call arm_apcscc i32 (...)* @x(%struct.q* undef, i8* undef, i8* %vla6, i8* %vla10, i32 undef) ; <i32> [#uses=0] + %call35 = call arm_apcscc i32 (...)* @x(%struct.q* undef, i8* %vla14, i8* %vla18, i8* %vla22, i32 undef) ; <i32> [#uses=0] + unreachable + +if.end36: ; preds = %entry + ret void +} + +declare arm_apcscc void @zz(...) + +declare arm_apcscc i32 @x(...) diff --git a/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll b/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll new file mode 100644 index 0000000..9907228 --- /dev/null +++ b/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll @@ -0,0 +1,25 @@ +; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s -check-prefix=ARM +; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s -check-prefix=THUMB +; rdar://7998649 + +%struct.foo = type { i64, i64 } + +define arm_apcscc zeroext i8 @t(%struct.foo* %this) noreturn optsize { +entry: +; ARM: t: +; ARM: str r0, [r1], r0 + +; THUMB: t: +; THUMB-NOT: str r0, [r1], r0 +; THUMB: str r0, [r1] + %0 = getelementptr inbounds %struct.foo* %this, i32 0, i32 1 ; <i64*> [#uses=1] + store i32 undef, i32* inttoptr (i32 8 to i32*), align 8 + br i1 undef, label %bb.nph96, label %bb3 + +bb3: ; preds = %entry + %1 = load i64* %0, align 4 ; <i64> [#uses=0] + unreachable + +bb.nph96: ; preds = %entry + unreachable +} diff --git a/test/CodeGen/ARM/2010-05-19-Shuffles.ll b/test/CodeGen/ARM/2010-05-19-Shuffles.ll new file mode 100644 index 0000000..587c0af --- /dev/null +++ b/test/CodeGen/ARM/2010-05-19-Shuffles.ll @@ -0,0 +1,21 @@ +; RUN: llc < %s -mtriple=armv7-eabi -mcpu=cortex-a8 +; pr7167 + +define <8 x i8> @f1(<8 x i8> %x) nounwind { + %y = shufflevector <8 x i8> %x, <8 x i8> undef, + <8 x i32> <i32 2, i32 3, i32 0, i32 1, i32 6, i32 7, i32 4, i32 5> + ret <8 x i8> %y +} + +define <8 x i8> @f2(<8 x i8> %x) nounwind { + %y = shufflevector <8 x i8> %x, <8 x i8> undef, + <8 x i32> <i32 1, i32 2, i32 0, i32 5, i32 3, i32 6, i32 7, i32 4> + ret <8 x i8> %y +} + +define void @f3(<4 x i64>* %xp) nounwind { + %x = load <4 x i64>* %xp + %y = shufflevector <4 x i64> %x, <4 x i64> undef, <4 x i32> <i32 0, i32 3, i32 2, i32 1> + store <4 x i64> %y, <4 x i64>* %xp + ret void +} diff --git a/test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll b/test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll new file mode 100644 index 0000000..b6fbf9b --- /dev/null +++ b/test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll @@ -0,0 +1,45 @@ +; RUN: llc < %s -march=arm -mattr=+neon -O0 + +; This test would crash the rewriter when trying to handle a spill after one of +; the @llvm.arm.neon.vld3.v8i8 defined three parts of a register. + +%struct.__neon_int8x8x3_t = type { <8 x i8>, <8 x i8>, <8 x i8> } + +declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8*) nounwind readonly + +declare void @llvm.arm.neon.vst3.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>) nounwind + +define <8 x i8> @t3(i8* %A1, i8* %A2, i8* %A3, i8* %A4, i8* %A5, i8* %A6, i8* %A7, i8* %A8, i8* %B) nounwind { + %tmp1b = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A2) ; <%struct.__neon_int8x8x3_t> [#uses=2] + %tmp2b = extractvalue %struct.__neon_int8x8x3_t %tmp1b, 0 ; <<8 x i8>> [#uses=1] + %tmp4b = extractvalue %struct.__neon_int8x8x3_t %tmp1b, 1 ; <<8 x i8>> [#uses=1] + %tmp1d = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A4) ; <%struct.__neon_int8x8x3_t> [#uses=2] + %tmp2d = extractvalue %struct.__neon_int8x8x3_t %tmp1d, 0 ; <<8 x i8>> [#uses=1] + %tmp4d = extractvalue %struct.__neon_int8x8x3_t %tmp1d, 1 ; <<8 x i8>> [#uses=1] + %tmp1e = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A5) ; <%struct.__neon_int8x8x3_t> [#uses=1] + %tmp2e = extractvalue %struct.__neon_int8x8x3_t %tmp1e, 0 ; <<8 x i8>> [#uses=1] + %tmp1f = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A6) ; <%struct.__neon_int8x8x3_t> [#uses=1] + %tmp2f = extractvalue %struct.__neon_int8x8x3_t %tmp1f, 0 ; <<8 x i8>> [#uses=1] + %tmp1g = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A7) ; <%struct.__neon_int8x8x3_t> [#uses=2] + %tmp2g = extractvalue %struct.__neon_int8x8x3_t %tmp1g, 0 ; <<8 x i8>> [#uses=1] + %tmp4g = extractvalue %struct.__neon_int8x8x3_t %tmp1g, 1 ; <<8 x i8>> [#uses=1] + %tmp1h = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A8) ; <%struct.__neon_int8x8x3_t> [#uses=2] + %tmp2h = extractvalue %struct.__neon_int8x8x3_t %tmp1h, 0 ; <<8 x i8>> [#uses=1] + %tmp3h = extractvalue %struct.__neon_int8x8x3_t %tmp1h, 2 ; <<8 x i8>> [#uses=1] + %tmp2bd = add <8 x i8> %tmp2b, %tmp2d ; <<8 x i8>> [#uses=1] + %tmp4bd = add <8 x i8> %tmp4b, %tmp4d ; <<8 x i8>> [#uses=1] + %tmp2abcd = mul <8 x i8> undef, %tmp2bd ; <<8 x i8>> [#uses=1] + %tmp4abcd = mul <8 x i8> undef, %tmp4bd ; <<8 x i8>> [#uses=2] + call void @llvm.arm.neon.vst3.v8i8(i8* %A1, <8 x i8> %tmp4abcd, <8 x i8> zeroinitializer, <8 x i8> %tmp2abcd) + %tmp2ef = sub <8 x i8> %tmp2e, %tmp2f ; <<8 x i8>> [#uses=1] + %tmp2gh = sub <8 x i8> %tmp2g, %tmp2h ; <<8 x i8>> [#uses=1] + %tmp3gh = sub <8 x i8> zeroinitializer, %tmp3h ; <<8 x i8>> [#uses=1] + %tmp4ef = sub <8 x i8> zeroinitializer, %tmp4g ; <<8 x i8>> [#uses=1] + %tmp2efgh = mul <8 x i8> %tmp2ef, %tmp2gh ; <<8 x i8>> [#uses=1] + %tmp3efgh = mul <8 x i8> undef, %tmp3gh ; <<8 x i8>> [#uses=1] + %tmp4efgh = mul <8 x i8> %tmp4ef, undef ; <<8 x i8>> [#uses=2] + call void @llvm.arm.neon.vst3.v8i8(i8* %A2, <8 x i8> %tmp4efgh, <8 x i8> %tmp3efgh, <8 x i8> %tmp2efgh) + %tmp4 = sub <8 x i8> %tmp4efgh, %tmp4abcd ; <<8 x i8>> [#uses=1] + tail call void @llvm.arm.neon.vst3.v8i8(i8* %B, <8 x i8> zeroinitializer, <8 x i8> undef, <8 x i8> undef) + ret <8 x i8> %tmp4 +} diff --git a/test/CodeGen/ARM/2010-05-21-BuildVector.ll b/test/CodeGen/ARM/2010-05-21-BuildVector.ll new file mode 100644 index 0000000..6b19490 --- /dev/null +++ b/test/CodeGen/ARM/2010-05-21-BuildVector.ll @@ -0,0 +1,43 @@ +; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s +; Radar 7872877 + +define arm_apcscc void @test(float* %fltp, i32 %packedValue, float* %table) nounwind { +entry: + %0 = load float* %fltp + %1 = insertelement <4 x float> undef, float %0, i32 0 + %2 = shufflevector <4 x float> %1, <4 x float> undef, <4 x i32> zeroinitializer + %3 = shl i32 %packedValue, 16 + %4 = ashr i32 %3, 30 + %.sum = add i32 %4, 4 + %5 = getelementptr inbounds float* %table, i32 %.sum +;CHECK: vldr.32 s + %6 = load float* %5, align 4 + %tmp11 = insertelement <4 x float> undef, float %6, i32 0 + %7 = shl i32 %packedValue, 18 + %8 = ashr i32 %7, 30 + %.sum12 = add i32 %8, 4 + %9 = getelementptr inbounds float* %table, i32 %.sum12 +;CHECK: vldr.32 s + %10 = load float* %9, align 4 + %tmp9 = insertelement <4 x float> %tmp11, float %10, i32 1 + %11 = shl i32 %packedValue, 20 + %12 = ashr i32 %11, 30 + %.sum13 = add i32 %12, 4 + %13 = getelementptr inbounds float* %table, i32 %.sum13 +;CHECK: vldr.32 s + %14 = load float* %13, align 4 + %tmp7 = insertelement <4 x float> %tmp9, float %14, i32 2 + %15 = shl i32 %packedValue, 22 + %16 = ashr i32 %15, 30 + %.sum14 = add i32 %16, 4 + %17 = getelementptr inbounds float* %table, i32 %.sum14 +;CHECK: vldr.32 s + %18 = load float* %17, align 4 + %tmp5 = insertelement <4 x float> %tmp7, float %18, i32 3 + %19 = fmul <4 x float> %tmp5, %2 + %20 = bitcast float* %fltp to i8* + tail call void @llvm.arm.neon.vst1.v4f32(i8* %20, <4 x float> %19) + ret void +} + +declare void @llvm.arm.neon.vst1.v4f32(i8*, <4 x float>) nounwind diff --git a/test/CodeGen/ARM/arm-frameaddr.ll b/test/CodeGen/ARM/arm-frameaddr.ll index 2739860..1c7ac25 100644 --- a/test/CodeGen/ARM/arm-frameaddr.ll +++ b/test/CodeGen/ARM/arm-frameaddr.ll @@ -1,10 +1,15 @@ -; RUN: llc < %s -mtriple=arm-apple-darwin | grep mov | grep r7 -; RUN: llc < %s -mtriple=arm-linux-gnueabi | grep mov | grep r11 +; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s -check-prefix=DARWIN +; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s -check-prefix=LINUX ; PR4344 ; PR4416 define arm_aapcscc i8* @t() nounwind { entry: +; DARWIN: t: +; DARWIN: mov r0, r7 + +; LINUX: t: +; LINUX: mov r0, r11 %0 = call i8* @llvm.frameaddress(i32 0) ret i8* %0 } diff --git a/test/CodeGen/ARM/arm-returnaddr.ll b/test/CodeGen/ARM/arm-returnaddr.ll new file mode 100644 index 0000000..2c8f2ab --- /dev/null +++ b/test/CodeGen/ARM/arm-returnaddr.ll @@ -0,0 +1,24 @@ +; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s +; RUN: llc < %s -mtriple=thumbv6-apple-darwin +; rdar://8015977 +; rdar://8020118 + +define arm_apcscc i8* @rt0(i32 %x) nounwind readnone { +entry: +; CHECK: rt0: +; CHECK: mov r0, lr + %0 = tail call i8* @llvm.returnaddress(i32 0) + ret i8* %0 +} + +define arm_apcscc i8* @rt2() nounwind readnone { +entry: +; CHECK: rt2: +; CHECK: ldr r0, [r7] +; CHECK: ldr r0, [r0] +; CHECK: ldr r0, [r0, #4] + %0 = tail call i8* @llvm.returnaddress(i32 2) + ret i8* %0 +} + +declare i8* @llvm.returnaddress(i32) nounwind readnone diff --git a/test/CodeGen/ARM/div.ll b/test/CodeGen/ARM/div.ll index 2f724e7..d833afa 100644 --- a/test/CodeGen/ARM/div.ll +++ b/test/CodeGen/ARM/div.ll @@ -1,29 +1,43 @@ -; RUN: llc < %s -march=arm > %t -; RUN: grep __divsi3 %t -; RUN: grep __udivsi3 %t -; RUN: grep __modsi3 %t -; RUN: grep __umodsi3 %t +; RUN: llc < %s -march=arm | FileCheck %s -check-prefix=CHECK-ARM +; RUN: llc < %s -march=arm -mcpu=cortex-m3 \ +; RUN: | FileCheck %s -check-prefix=CHECK-ARMV7M define i32 @f1(i32 %a, i32 %b) { entry: +; CHECK-ARM: f1 +; CHECK-ARM: __divsi3 +; CHECK-ARMV7M: f1 +; CHECK-ARMV7M: sdiv %tmp1 = sdiv i32 %a, %b ; <i32> [#uses=1] ret i32 %tmp1 } define i32 @f2(i32 %a, i32 %b) { entry: +; CHECK-ARM: f2 +; CHECK-ARM: __udivsi3 +; CHECK-ARMV7M: f2 +; CHECK-ARMV7M: udiv %tmp1 = udiv i32 %a, %b ; <i32> [#uses=1] ret i32 %tmp1 } define i32 @f3(i32 %a, i32 %b) { entry: +; CHECK-ARM: f3 +; CHECK-ARM: __modsi3 +; CHECK-ARMV7M: f3 +; CHECK-ARMV7M: sdiv %tmp1 = srem i32 %a, %b ; <i32> [#uses=1] ret i32 %tmp1 } define i32 @f4(i32 %a, i32 %b) { entry: +; CHECK-ARM: f4 +; CHECK-ARM: __umodsi3 +; CHECK-ARMV7M: f4 +; CHECK-ARMV7M: udiv %tmp1 = urem i32 %a, %b ; <i32> [#uses=1] ret i32 %tmp1 } diff --git a/test/CodeGen/ARM/fabss.ll b/test/CodeGen/ARM/fabss.ll index f03282b..dfc1e0a 100644 --- a/test/CodeGen/ARM/fabss.ll +++ b/test/CodeGen/ARM/fabss.ll @@ -24,4 +24,4 @@ declare float @fabsf(float) ; CORTEXA8: test: ; CORTEXA8: vabs.f32 d1, d1 ; CORTEXA9: test: -; CORTEXA9: vabs.f32 s1, s1 +; CORTEXA9: vabs.f32 s0, s0 diff --git a/test/CodeGen/ARM/fadds.ll b/test/CodeGen/ARM/fadds.ll index 749690e..113f0e2 100644 --- a/test/CodeGen/ARM/fadds.ll +++ b/test/CodeGen/ARM/fadds.ll @@ -20,4 +20,4 @@ entry: ; CORTEXA8: test: ; CORTEXA8: vadd.f32 d0, d1, d0 ; CORTEXA9: test: -; CORTEXA9: vadd.f32 s0, s1, s0 +; CORTEXA9: vadd.f32 s0, s0, s1 diff --git a/test/CodeGen/ARM/fdivs.ll b/test/CodeGen/ARM/fdivs.ll index 0c31495..9af1217 100644 --- a/test/CodeGen/ARM/fdivs.ll +++ b/test/CodeGen/ARM/fdivs.ll @@ -20,4 +20,4 @@ entry: ; CORTEXA8: test: ; CORTEXA8: vdiv.f32 s0, s1, s0 ; CORTEXA9: test: -; CORTEXA9: vdiv.f32 s0, s1, s0 +; CORTEXA9: vdiv.f32 s0, s0, s1 diff --git a/test/CodeGen/ARM/fmacs.ll b/test/CodeGen/ARM/fmacs.ll index f8b47b5..c4ceca9 100644 --- a/test/CodeGen/ARM/fmacs.ll +++ b/test/CodeGen/ARM/fmacs.ll @@ -21,4 +21,4 @@ entry: ; CORTEXA8: test: ; CORTEXA8: vmul.f32 d0, d1, d0 ; CORTEXA9: test: -; CORTEXA9: vmla.f32 s2, s1, s0 +; CORTEXA9: vmla.f32 s0, s1, s2 diff --git a/test/CodeGen/ARM/fmscs.ll b/test/CodeGen/ARM/fmscs.ll index 7a70543..103ce33 100644 --- a/test/CodeGen/ARM/fmscs.ll +++ b/test/CodeGen/ARM/fmscs.ll @@ -21,4 +21,4 @@ entry: ; CORTEXA8: test: ; CORTEXA8: vnmls.f32 s2, s1, s0 ; CORTEXA9: test: -; CORTEXA9: vnmls.f32 s2, s1, s0 +; CORTEXA9: vnmls.f32 s0, s1, s2 diff --git a/test/CodeGen/ARM/fmuls.ll b/test/CodeGen/ARM/fmuls.ll index ef4e3e5..bfafd20 100644 --- a/test/CodeGen/ARM/fmuls.ll +++ b/test/CodeGen/ARM/fmuls.ll @@ -20,4 +20,4 @@ entry: ; CORTEXA8: test: ; CORTEXA8: vmul.f32 d0, d1, d0 ; CORTEXA9: test: -; CORTEXA9: vmul.f32 s0, s1, s0 +; CORTEXA9: vmul.f32 s0, s0, s1 diff --git a/test/CodeGen/ARM/fnmscs.ll b/test/CodeGen/ARM/fnmscs.ll index 6b7cefa..0b47edd 100644 --- a/test/CodeGen/ARM/fnmscs.ll +++ b/test/CodeGen/ARM/fnmscs.ll @@ -4,7 +4,7 @@ ; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s define float @test1(float %acc, float %a, float %b) nounwind { -; CHECK: vnmla.f32 s2, s1, s0 +; CHECK: vnmla.f32 s{{.*}}, s{{.*}}, s{{.*}} entry: %0 = fmul float %a, %b %1 = fsub float -0.0, %0 @@ -13,7 +13,7 @@ entry: } define float @test2(float %acc, float %a, float %b) nounwind { -; CHECK: vnmla.f32 s2, s1, s0 +; CHECK: vnmla.f32 s{{.*}}, s{{.*}}, s{{.*}} entry: %0 = fmul float %a, %b %1 = fmul float -1.0, %0 diff --git a/test/CodeGen/ARM/lsr-on-unrolled-loops.ll b/test/CodeGen/ARM/lsr-on-unrolled-loops.ll new file mode 100644 index 0000000..2ac4084 --- /dev/null +++ b/test/CodeGen/ARM/lsr-on-unrolled-loops.ll @@ -0,0 +1,642 @@ +; RUN: llc -mtriple=thumbv7-apple-darwin10 -mcpu=cortex-a8 < %s | FileCheck %s + +; LSR should recognize that this is an unrolled loop which can use +; constant offset addressing, so that each of the following stores +; uses the same register. + +; CHECK: vstr.32 s0, [r12, #-128] +; CHECK: vstr.32 s0, [r12, #-96] +; CHECK: vstr.32 s0, [r12, #-64] +; CHECK: vstr.32 s0, [r12, #-32] +; CHECK: vstr.32 s0, [r12] +; CHECK: vstr.32 s0, [r12, #32] +; CHECK: vstr.32 s0, [r12, #64] +; CHECK: vstr.32 s0, [r12, #96] + +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32" + +%0 = type { %1*, %3*, %6*, i8*, i32, i32, %8*, i32, i32, i32, i32, i32, i32, i32, double, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8**, i32, i32, i32, i32, i32, [64 x i32]*, [4 x %9*], [4 x %10*], [4 x %10*], i32, %11*, i32, i32, [16 x i8], [16 x i8], [16 x i8], i32, i32, i8, i8, i8, i16, i16, i32, i8, i32, %12*, i32, i32, i32, i32, i8*, i32, [4 x %11*], i32, i32, i32, [10 x i32], i32, i32, i32, i32, i32, %13*, %14*, %15*, %16*, %17*, %18*, %19*, %20*, %21*, %22*, %23* } +%1 = type { void (%2*)*, void (%2*, i32)*, void (%2*)*, void (%2*, i8*)*, void (%2*)*, i32, %7, i32, i32, i8**, i32, i8**, i32, i32 } +%2 = type { %1*, %3*, %6*, i8*, i32, i32 } +%3 = type { i8* (%2*, i32, i32)*, i8* (%2*, i32, i32)*, i8** (%2*, i32, i32, i32)*, [64 x i16]** (%2*, i32, i32, i32)*, %4* (%2*, i32, i32, i32, i32, i32)*, %5* (%2*, i32, i32, i32, i32, i32)*, void (%2*)*, i8** (%2*, %4*, i32, i32, i32)*, [64 x i16]** (%2*, %5*, i32, i32, i32)*, void (%2*, i32)*, void (%2*)*, i32, i32 } +%4 = type opaque +%5 = type opaque +%6 = type { void (%2*)*, i32, i32, i32, i32 } +%7 = type { [8 x i32], [12 x i32] } +%8 = type { i8*, i32, void (%0*)*, i32 (%0*)*, void (%0*, i32)*, i32 (%0*, i32)*, void (%0*)* } +%9 = type { [64 x i16], i32 } +%10 = type { [17 x i8], [256 x i8], i32 } +%11 = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %9*, i8* } +%12 = type { %12*, i8, i32, i32, i8* } +%13 = type { void (%0*)*, void (%0*)*, i32 } +%14 = type { void (%0*, i32)*, void (%0*, i8**, i32*, i32)* } +%15 = type { void (%0*)*, i32 (%0*)*, void (%0*)*, i32 (%0*, i8***)*, %5** } +%16 = type { void (%0*, i32)*, void (%0*, i8***, i32*, i32, i8**, i32*, i32)* } +%17 = type { i32 (%0*)*, void (%0*)*, void (%0*)*, void (%0*)*, i32, i32 } +%18 = type { void (%0*)*, i32 (%0*)*, i32 (%0*)*, i32, i32, i32, i32 } +%19 = type { void (%0*)*, i32 (%0*, [64 x i16]**)*, i32 } +%20 = type { void (%0*)*, [10 x void (%0*, %11*, i16*, i8**, i32)*] } +%21 = type { void (%0*)*, void (%0*, i8***, i32*, i32, i8**, i32*, i32)*, i32 } +%22 = type { void (%0*)*, void (%0*, i8***, i32, i8**, i32)* } +%23 = type { void (%0*, i32)*, void (%0*, i8**, i8**, i32)*, void (%0*)*, void (%0*)* } + +define arm_apcscc void @test(%0* nocapture %a0, %11* nocapture %a1, i16* nocapture %a2, i8** nocapture %a3, i32 %a4) nounwind { +bb: + %t = alloca [64 x float], align 4 + %t5 = getelementptr inbounds %0* %a0, i32 0, i32 65 + %t6 = load i8** %t5, align 4 + %t7 = getelementptr inbounds %11* %a1, i32 0, i32 20 + %t8 = load i8** %t7, align 4 + br label %bb9 + +bb9: + %t10 = phi i32 [ 0, %bb ], [ %t157, %bb156 ] + %t11 = add i32 %t10, 8 + %t12 = getelementptr [64 x float]* %t, i32 0, i32 %t11 + %t13 = add i32 %t10, 16 + %t14 = getelementptr [64 x float]* %t, i32 0, i32 %t13 + %t15 = add i32 %t10, 24 + %t16 = getelementptr [64 x float]* %t, i32 0, i32 %t15 + %t17 = add i32 %t10, 32 + %t18 = getelementptr [64 x float]* %t, i32 0, i32 %t17 + %t19 = add i32 %t10, 40 + %t20 = getelementptr [64 x float]* %t, i32 0, i32 %t19 + %t21 = add i32 %t10, 48 + %t22 = getelementptr [64 x float]* %t, i32 0, i32 %t21 + %t23 = add i32 %t10, 56 + %t24 = getelementptr [64 x float]* %t, i32 0, i32 %t23 + %t25 = getelementptr [64 x float]* %t, i32 0, i32 %t10 + %t26 = shl i32 %t10, 5 + %t27 = or i32 %t26, 8 + %t28 = getelementptr i8* %t8, i32 %t27 + %t29 = bitcast i8* %t28 to float* + %t30 = or i32 %t26, 16 + %t31 = getelementptr i8* %t8, i32 %t30 + %t32 = bitcast i8* %t31 to float* + %t33 = or i32 %t26, 24 + %t34 = getelementptr i8* %t8, i32 %t33 + %t35 = bitcast i8* %t34 to float* + %t36 = or i32 %t26, 4 + %t37 = getelementptr i8* %t8, i32 %t36 + %t38 = bitcast i8* %t37 to float* + %t39 = or i32 %t26, 12 + %t40 = getelementptr i8* %t8, i32 %t39 + %t41 = bitcast i8* %t40 to float* + %t42 = or i32 %t26, 20 + %t43 = getelementptr i8* %t8, i32 %t42 + %t44 = bitcast i8* %t43 to float* + %t45 = or i32 %t26, 28 + %t46 = getelementptr i8* %t8, i32 %t45 + %t47 = bitcast i8* %t46 to float* + %t48 = getelementptr i8* %t8, i32 %t26 + %t49 = bitcast i8* %t48 to float* + %t50 = shl i32 %t10, 3 + %t51 = or i32 %t50, 1 + %t52 = getelementptr i16* %a2, i32 %t51 + %t53 = or i32 %t50, 2 + %t54 = getelementptr i16* %a2, i32 %t53 + %t55 = or i32 %t50, 3 + %t56 = getelementptr i16* %a2, i32 %t55 + %t57 = or i32 %t50, 4 + %t58 = getelementptr i16* %a2, i32 %t57 + %t59 = or i32 %t50, 5 + %t60 = getelementptr i16* %a2, i32 %t59 + %t61 = or i32 %t50, 6 + %t62 = getelementptr i16* %a2, i32 %t61 + %t63 = or i32 %t50, 7 + %t64 = getelementptr i16* %a2, i32 %t63 + %t65 = getelementptr i16* %a2, i32 %t50 + %t66 = load i16* %t52, align 2 + %t67 = icmp eq i16 %t66, 0 + %t68 = load i16* %t54, align 2 + %t69 = icmp eq i16 %t68, 0 + %t70 = and i1 %t67, %t69 + br i1 %t70, label %bb71, label %bb91 + +bb71: + %t72 = load i16* %t56, align 2 + %t73 = icmp eq i16 %t72, 0 + br i1 %t73, label %bb74, label %bb91 + +bb74: + %t75 = load i16* %t58, align 2 + %t76 = icmp eq i16 %t75, 0 + br i1 %t76, label %bb77, label %bb91 + +bb77: + %t78 = load i16* %t60, align 2 + %t79 = icmp eq i16 %t78, 0 + br i1 %t79, label %bb80, label %bb91 + +bb80: + %t81 = load i16* %t62, align 2 + %t82 = icmp eq i16 %t81, 0 + br i1 %t82, label %bb83, label %bb91 + +bb83: + %t84 = load i16* %t64, align 2 + %t85 = icmp eq i16 %t84, 0 + br i1 %t85, label %bb86, label %bb91 + +bb86: + %t87 = load i16* %t65, align 2 + %t88 = sitofp i16 %t87 to float + %t89 = load float* %t49, align 4 + %t90 = fmul float %t88, %t89 + store float %t90, float* %t25, align 4 + store float %t90, float* %t12, align 4 + store float %t90, float* %t14, align 4 + store float %t90, float* %t16, align 4 + store float %t90, float* %t18, align 4 + store float %t90, float* %t20, align 4 + store float %t90, float* %t22, align 4 + store float %t90, float* %t24, align 4 + br label %bb156 + +bb91: + %t92 = load i16* %t65, align 2 + %t93 = sitofp i16 %t92 to float + %t94 = load float* %t49, align 4 + %t95 = fmul float %t93, %t94 + %t96 = sitofp i16 %t68 to float + %t97 = load float* %t29, align 4 + %t98 = fmul float %t96, %t97 + %t99 = load i16* %t58, align 2 + %t100 = sitofp i16 %t99 to float + %t101 = load float* %t32, align 4 + %t102 = fmul float %t100, %t101 + %t103 = load i16* %t62, align 2 + %t104 = sitofp i16 %t103 to float + %t105 = load float* %t35, align 4 + %t106 = fmul float %t104, %t105 + %t107 = fadd float %t95, %t102 + %t108 = fsub float %t95, %t102 + %t109 = fadd float %t98, %t106 + %t110 = fsub float %t98, %t106 + %t111 = fmul float %t110, 0x3FF6A09E60000000 + %t112 = fsub float %t111, %t109 + %t113 = fadd float %t107, %t109 + %t114 = fsub float %t107, %t109 + %t115 = fadd float %t108, %t112 + %t116 = fsub float %t108, %t112 + %t117 = sitofp i16 %t66 to float + %t118 = load float* %t38, align 4 + %t119 = fmul float %t117, %t118 + %t120 = load i16* %t56, align 2 + %t121 = sitofp i16 %t120 to float + %t122 = load float* %t41, align 4 + %t123 = fmul float %t121, %t122 + %t124 = load i16* %t60, align 2 + %t125 = sitofp i16 %t124 to float + %t126 = load float* %t44, align 4 + %t127 = fmul float %t125, %t126 + %t128 = load i16* %t64, align 2 + %t129 = sitofp i16 %t128 to float + %t130 = load float* %t47, align 4 + %t131 = fmul float %t129, %t130 + %t132 = fadd float %t127, %t123 + %t133 = fsub float %t127, %t123 + %t134 = fadd float %t119, %t131 + %t135 = fsub float %t119, %t131 + %t136 = fadd float %t134, %t132 + %t137 = fsub float %t134, %t132 + %t138 = fmul float %t137, 0x3FF6A09E60000000 + %t139 = fadd float %t133, %t135 + %t140 = fmul float %t139, 0x3FFD906BC0000000 + %t141 = fmul float %t135, 0x3FF1517A80000000 + %t142 = fsub float %t141, %t140 + %t143 = fmul float %t133, 0xC004E7AEA0000000 + %t144 = fadd float %t143, %t140 + %t145 = fsub float %t144, %t136 + %t146 = fsub float %t138, %t145 + %t147 = fadd float %t142, %t146 + %t148 = fadd float %t113, %t136 + store float %t148, float* %t25, align 4 + %t149 = fsub float %t113, %t136 + store float %t149, float* %t24, align 4 + %t150 = fadd float %t115, %t145 + store float %t150, float* %t12, align 4 + %t151 = fsub float %t115, %t145 + store float %t151, float* %t22, align 4 + %t152 = fadd float %t116, %t146 + store float %t152, float* %t14, align 4 + %t153 = fsub float %t116, %t146 + store float %t153, float* %t20, align 4 + %t154 = fadd float %t114, %t147 + store float %t154, float* %t18, align 4 + %t155 = fsub float %t114, %t147 + store float %t155, float* %t16, align 4 + br label %bb156 + +bb156: + %t157 = add i32 %t10, 1 + %t158 = icmp eq i32 %t157, 8 + br i1 %t158, label %bb159, label %bb9 + +bb159: + %t160 = add i32 %a4, 7 + %t161 = add i32 %a4, 1 + %t162 = add i32 %a4, 6 + %t163 = add i32 %a4, 2 + %t164 = add i32 %a4, 5 + %t165 = add i32 %a4, 4 + %t166 = add i32 %a4, 3 + br label %bb167 + +bb167: + %t168 = phi i32 [ 0, %bb159 ], [ %t293, %bb167 ] + %t169 = getelementptr i8** %a3, i32 %t168 + %t170 = shl i32 %t168, 3 + %t171 = or i32 %t170, 4 + %t172 = getelementptr [64 x float]* %t, i32 0, i32 %t171 + %t173 = or i32 %t170, 2 + %t174 = getelementptr [64 x float]* %t, i32 0, i32 %t173 + %t175 = or i32 %t170, 6 + %t176 = getelementptr [64 x float]* %t, i32 0, i32 %t175 + %t177 = or i32 %t170, 5 + %t178 = getelementptr [64 x float]* %t, i32 0, i32 %t177 + %t179 = or i32 %t170, 3 + %t180 = getelementptr [64 x float]* %t, i32 0, i32 %t179 + %t181 = or i32 %t170, 1 + %t182 = getelementptr [64 x float]* %t, i32 0, i32 %t181 + %t183 = or i32 %t170, 7 + %t184 = getelementptr [64 x float]* %t, i32 0, i32 %t183 + %t185 = getelementptr [64 x float]* %t, i32 0, i32 %t170 + %t186 = load i8** %t169, align 4 + %t187 = getelementptr inbounds i8* %t186, i32 %a4 + %t188 = load float* %t185, align 4 + %t189 = load float* %t172, align 4 + %t190 = fadd float %t188, %t189 + %t191 = fsub float %t188, %t189 + %t192 = load float* %t174, align 4 + %t193 = load float* %t176, align 4 + %t194 = fadd float %t192, %t193 + %t195 = fsub float %t192, %t193 + %t196 = fmul float %t195, 0x3FF6A09E60000000 + %t197 = fsub float %t196, %t194 + %t198 = fadd float %t190, %t194 + %t199 = fsub float %t190, %t194 + %t200 = fadd float %t191, %t197 + %t201 = fsub float %t191, %t197 + %t202 = load float* %t178, align 4 + %t203 = load float* %t180, align 4 + %t204 = fadd float %t202, %t203 + %t205 = fsub float %t202, %t203 + %t206 = load float* %t182, align 4 + %t207 = load float* %t184, align 4 + %t208 = fadd float %t206, %t207 + %t209 = fsub float %t206, %t207 + %t210 = fadd float %t208, %t204 + %t211 = fsub float %t208, %t204 + %t212 = fmul float %t211, 0x3FF6A09E60000000 + %t213 = fadd float %t205, %t209 + %t214 = fmul float %t213, 0x3FFD906BC0000000 + %t215 = fmul float %t209, 0x3FF1517A80000000 + %t216 = fsub float %t215, %t214 + %t217 = fmul float %t205, 0xC004E7AEA0000000 + %t218 = fadd float %t217, %t214 + %t219 = fsub float %t218, %t210 + %t220 = fsub float %t212, %t219 + %t221 = fadd float %t216, %t220 + %t222 = fadd float %t198, %t210 + %t223 = fptosi float %t222 to i32 + %t224 = add nsw i32 %t223, 4 + %t225 = lshr i32 %t224, 3 + %t226 = and i32 %t225, 1023 + %t227 = add i32 %t226, 128 + %t228 = getelementptr inbounds i8* %t6, i32 %t227 + %t229 = load i8* %t228, align 1 + store i8 %t229, i8* %t187, align 1 + %t230 = fsub float %t198, %t210 + %t231 = fptosi float %t230 to i32 + %t232 = add nsw i32 %t231, 4 + %t233 = lshr i32 %t232, 3 + %t234 = and i32 %t233, 1023 + %t235 = add i32 %t234, 128 + %t236 = getelementptr inbounds i8* %t6, i32 %t235 + %t237 = load i8* %t236, align 1 + %t238 = getelementptr inbounds i8* %t186, i32 %t160 + store i8 %t237, i8* %t238, align 1 + %t239 = fadd float %t200, %t219 + %t240 = fptosi float %t239 to i32 + %t241 = add nsw i32 %t240, 4 + %t242 = lshr i32 %t241, 3 + %t243 = and i32 %t242, 1023 + %t244 = add i32 %t243, 128 + %t245 = getelementptr inbounds i8* %t6, i32 %t244 + %t246 = load i8* %t245, align 1 + %t247 = getelementptr inbounds i8* %t186, i32 %t161 + store i8 %t246, i8* %t247, align 1 + %t248 = fsub float %t200, %t219 + %t249 = fptosi float %t248 to i32 + %t250 = add nsw i32 %t249, 4 + %t251 = lshr i32 %t250, 3 + %t252 = and i32 %t251, 1023 + %t253 = add i32 %t252, 128 + %t254 = getelementptr inbounds i8* %t6, i32 %t253 + %t255 = load i8* %t254, align 1 + %t256 = getelementptr inbounds i8* %t186, i32 %t162 + store i8 %t255, i8* %t256, align 1 + %t257 = fadd float %t201, %t220 + %t258 = fptosi float %t257 to i32 + %t259 = add nsw i32 %t258, 4 + %t260 = lshr i32 %t259, 3 + %t261 = and i32 %t260, 1023 + %t262 = add i32 %t261, 128 + %t263 = getelementptr inbounds i8* %t6, i32 %t262 + %t264 = load i8* %t263, align 1 + %t265 = getelementptr inbounds i8* %t186, i32 %t163 + store i8 %t264, i8* %t265, align 1 + %t266 = fsub float %t201, %t220 + %t267 = fptosi float %t266 to i32 + %t268 = add nsw i32 %t267, 4 + %t269 = lshr i32 %t268, 3 + %t270 = and i32 %t269, 1023 + %t271 = add i32 %t270, 128 + %t272 = getelementptr inbounds i8* %t6, i32 %t271 + %t273 = load i8* %t272, align 1 + %t274 = getelementptr inbounds i8* %t186, i32 %t164 + store i8 %t273, i8* %t274, align 1 + %t275 = fadd float %t199, %t221 + %t276 = fptosi float %t275 to i32 + %t277 = add nsw i32 %t276, 4 + %t278 = lshr i32 %t277, 3 + %t279 = and i32 %t278, 1023 + %t280 = add i32 %t279, 128 + %t281 = getelementptr inbounds i8* %t6, i32 %t280 + %t282 = load i8* %t281, align 1 + %t283 = getelementptr inbounds i8* %t186, i32 %t165 + store i8 %t282, i8* %t283, align 1 + %t284 = fsub float %t199, %t221 + %t285 = fptosi float %t284 to i32 + %t286 = add nsw i32 %t285, 4 + %t287 = lshr i32 %t286, 3 + %t288 = and i32 %t287, 1023 + %t289 = add i32 %t288, 128 + %t290 = getelementptr inbounds i8* %t6, i32 %t289 + %t291 = load i8* %t290, align 1 + %t292 = getelementptr inbounds i8* %t186, i32 %t166 + store i8 %t291, i8* %t292, align 1 + %t293 = add nsw i32 %t168, 1 + %t294 = icmp eq i32 %t293, 8 + br i1 %t294, label %bb295, label %bb167 + +bb295: + ret void +} + +%struct.ct_data_s = type { %union.anon, %union.anon } +%struct.gz_header = type { i32, i32, i32, i32, i8*, i32, i32, i8*, i32, i8*, i32, i32, i32 } +%struct.internal_state = type { %struct.z_stream*, i32, i8*, i32, i8*, i32, i32, %struct.gz_header*, i32, i8, i32, i32, i32, i32, i8*, i32, i16*, i16*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [573 x %struct.ct_data_s], [61 x %struct.ct_data_s], [39 x %struct.ct_data_s], %struct.tree_desc_s, %struct.tree_desc_s, %struct.tree_desc_s, [16 x i16], [573 x i32], i32, i32, [573 x i8], i8*, i32, i32, i16*, i32, i32, i32, i32, i16, i32 } +%struct.static_tree_desc = type { i32 } +%struct.tree_desc_s = type { %struct.ct_data_s*, i32, %struct.static_tree_desc* } +%struct.z_stream = type { i8*, i32, i32, i8*, i32, i32, i8*, %struct.internal_state*, i8* (i8*, i32, i32)*, void (i8*, i8*)*, i8*, i32, i32, i32 } +%union.anon = type { i16 } + +define arm_apcscc i32 @longest_match(%struct.internal_state* %s, i32 %cur_match) nounwind optsize { +entry: + %0 = getelementptr inbounds %struct.internal_state* %s, i32 0, i32 31 ; <i32*> [#uses=1] + %1 = load i32* %0, align 4 ; <i32> [#uses=2] + %2 = getelementptr inbounds %struct.internal_state* %s, i32 0, i32 14 ; <i8**> [#uses=1] + %3 = load i8** %2, align 4 ; <i8*> [#uses=27] + %4 = getelementptr inbounds %struct.internal_state* %s, i32 0, i32 27 ; <i32*> [#uses=1] + %5 = load i32* %4, align 4 ; <i32> [#uses=17] + %6 = getelementptr inbounds i8* %3, i32 %5 ; <i8*> [#uses=1] + %7 = getelementptr inbounds %struct.internal_state* %s, i32 0, i32 30 ; <i32*> [#uses=1] + %8 = load i32* %7, align 4 ; <i32> [#uses=4] + %9 = getelementptr inbounds %struct.internal_state* %s, i32 0, i32 36 ; <i32*> [#uses=1] + %10 = load i32* %9, align 4 ; <i32> [#uses=2] + %11 = getelementptr inbounds %struct.internal_state* %s, i32 0, i32 11 ; <i32*> [#uses=1] + %12 = load i32* %11, align 4 ; <i32> [#uses=2] + %13 = add i32 %12, -262 ; <i32> [#uses=1] + %14 = icmp ugt i32 %5, %13 ; <i1> [#uses=1] + br i1 %14, label %bb, label %bb2 + +bb: ; preds = %entry + %15 = add i32 %5, 262 ; <i32> [#uses=1] + %16 = sub i32 %15, %12 ; <i32> [#uses=1] + br label %bb2 + +bb2: ; preds = %bb, %entry + %iftmp.48.0 = phi i32 [ %16, %bb ], [ 0, %entry ] ; <i32> [#uses=1] + %17 = getelementptr inbounds %struct.internal_state* %s, i32 0, i32 16 ; <i16**> [#uses=1] + %18 = load i16** %17, align 4 ; <i16*> [#uses=1] + %19 = getelementptr inbounds %struct.internal_state* %s, i32 0, i32 13 ; <i32*> [#uses=1] + %20 = load i32* %19, align 4 ; <i32> [#uses=1] + %.sum = add i32 %5, 258 ; <i32> [#uses=2] + %21 = getelementptr inbounds i8* %3, i32 %.sum ; <i8*> [#uses=1] + %22 = add nsw i32 %5, -1 ; <i32> [#uses=1] + %.sum30 = add i32 %22, %8 ; <i32> [#uses=1] + %23 = getelementptr inbounds i8* %3, i32 %.sum30 ; <i8*> [#uses=1] + %24 = load i8* %23, align 1 ; <i8> [#uses=1] + %.sum31 = add i32 %8, %5 ; <i32> [#uses=1] + %25 = getelementptr inbounds i8* %3, i32 %.sum31 ; <i8*> [#uses=1] + %26 = load i8* %25, align 1 ; <i8> [#uses=1] + %27 = getelementptr inbounds %struct.internal_state* %s, i32 0, i32 35 ; <i32*> [#uses=1] + %28 = load i32* %27, align 4 ; <i32> [#uses=1] + %29 = lshr i32 %1, 2 ; <i32> [#uses=1] + %30 = icmp ult i32 %8, %28 ; <i1> [#uses=1] + %. = select i1 %30, i32 %1, i32 %29 ; <i32> [#uses=1] + %31 = getelementptr inbounds %struct.internal_state* %s, i32 0, i32 29 ; <i32*> [#uses=1] + %32 = load i32* %31, align 4 ; <i32> [#uses=4] + %33 = icmp ugt i32 %10, %32 ; <i1> [#uses=1] + %nice_match.0.ph = select i1 %33, i32 %32, i32 %10 ; <i32> [#uses=1] + %34 = getelementptr inbounds %struct.internal_state* %s, i32 0, i32 28 ; <i32*> [#uses=1] + %35 = ptrtoint i8* %21 to i32 ; <i32> [#uses=1] + %36 = add nsw i32 %5, 257 ; <i32> [#uses=1] + %tmp81 = add i32 %., -1 ; <i32> [#uses=1] + br label %bb6 + +bb6: ; preds = %bb24, %bb2 + %indvar78 = phi i32 [ 0, %bb2 ], [ %indvar.next79, %bb24 ] ; <i32> [#uses=2] + %best_len.2 = phi i32 [ %8, %bb2 ], [ %best_len.0, %bb24 ] ; <i32> [#uses=8] + %scan_end1.1 = phi i8 [ %24, %bb2 ], [ %scan_end1.0, %bb24 ] ; <i8> [#uses=6] + %cur_match_addr.0 = phi i32 [ %cur_match, %bb2 ], [ %90, %bb24 ] ; <i32> [#uses=14] + %scan_end.1 = phi i8 [ %26, %bb2 ], [ %scan_end.0, %bb24 ] ; <i8> [#uses=6] + %37 = getelementptr inbounds i8* %3, i32 %cur_match_addr.0 ; <i8*> [#uses=1] + %.sum32 = add i32 %cur_match_addr.0, %best_len.2 ; <i32> [#uses=1] + %38 = getelementptr inbounds i8* %3, i32 %.sum32 ; <i8*> [#uses=1] + %39 = load i8* %38, align 1 ; <i8> [#uses=1] + %40 = icmp eq i8 %39, %scan_end.1 ; <i1> [#uses=1] + br i1 %40, label %bb7, label %bb23 + +bb7: ; preds = %bb6 + %41 = add nsw i32 %best_len.2, -1 ; <i32> [#uses=1] + %.sum33 = add i32 %41, %cur_match_addr.0 ; <i32> [#uses=1] + %42 = getelementptr inbounds i8* %3, i32 %.sum33 ; <i8*> [#uses=1] + %43 = load i8* %42, align 1 ; <i8> [#uses=1] + %44 = icmp eq i8 %43, %scan_end1.1 ; <i1> [#uses=1] + br i1 %44, label %bb8, label %bb23 + +bb8: ; preds = %bb7 + %45 = load i8* %37, align 1 ; <i8> [#uses=1] + %46 = load i8* %6, align 1 ; <i8> [#uses=1] + %47 = icmp eq i8 %45, %46 ; <i1> [#uses=1] + br i1 %47, label %bb9, label %bb23 + +bb9: ; preds = %bb8 + %.sum34 = add i32 %cur_match_addr.0, 1 ; <i32> [#uses=1] + %48 = getelementptr inbounds i8* %3, i32 %.sum34 ; <i8*> [#uses=1] + %49 = load i8* %48, align 1 ; <i8> [#uses=1] + %.sum88 = add i32 %5, 1 ; <i32> [#uses=1] + %50 = getelementptr inbounds i8* %3, i32 %.sum88 ; <i8*> [#uses=1] + %51 = load i8* %50, align 1 ; <i8> [#uses=1] + %52 = icmp eq i8 %49, %51 ; <i1> [#uses=1] + br i1 %52, label %bb10, label %bb23 + +bb10: ; preds = %bb9 + %tmp39 = add i32 %cur_match_addr.0, 10 ; <i32> [#uses=1] + %tmp41 = add i32 %cur_match_addr.0, 9 ; <i32> [#uses=1] + %tmp44 = add i32 %cur_match_addr.0, 8 ; <i32> [#uses=1] + %tmp47 = add i32 %cur_match_addr.0, 7 ; <i32> [#uses=1] + %tmp50 = add i32 %cur_match_addr.0, 6 ; <i32> [#uses=1] + %tmp53 = add i32 %cur_match_addr.0, 5 ; <i32> [#uses=1] + %tmp56 = add i32 %cur_match_addr.0, 4 ; <i32> [#uses=1] + %tmp59 = add i32 %cur_match_addr.0, 3 ; <i32> [#uses=1] + br label %bb11 + +bb11: ; preds = %bb18, %bb10 + %indvar = phi i32 [ %indvar.next, %bb18 ], [ 0, %bb10 ] ; <i32> [#uses=2] + %tmp = shl i32 %indvar, 3 ; <i32> [#uses=16] + %tmp40 = add i32 %tmp39, %tmp ; <i32> [#uses=1] + %scevgep = getelementptr i8* %3, i32 %tmp40 ; <i8*> [#uses=1] + %tmp42 = add i32 %tmp41, %tmp ; <i32> [#uses=1] + %scevgep43 = getelementptr i8* %3, i32 %tmp42 ; <i8*> [#uses=1] + %tmp45 = add i32 %tmp44, %tmp ; <i32> [#uses=1] + %scevgep46 = getelementptr i8* %3, i32 %tmp45 ; <i8*> [#uses=1] + %tmp48 = add i32 %tmp47, %tmp ; <i32> [#uses=1] + %scevgep49 = getelementptr i8* %3, i32 %tmp48 ; <i8*> [#uses=1] + %tmp51 = add i32 %tmp50, %tmp ; <i32> [#uses=1] + %scevgep52 = getelementptr i8* %3, i32 %tmp51 ; <i8*> [#uses=1] + %tmp54 = add i32 %tmp53, %tmp ; <i32> [#uses=1] + %scevgep55 = getelementptr i8* %3, i32 %tmp54 ; <i8*> [#uses=1] + %tmp60 = add i32 %tmp59, %tmp ; <i32> [#uses=1] + %scevgep61 = getelementptr i8* %3, i32 %tmp60 ; <i8*> [#uses=1] + %tmp62 = add i32 %tmp, 10 ; <i32> [#uses=1] + %.sum89 = add i32 %5, %tmp62 ; <i32> [#uses=2] + %scevgep63 = getelementptr i8* %3, i32 %.sum89 ; <i8*> [#uses=2] + %tmp64 = add i32 %tmp, 9 ; <i32> [#uses=1] + %.sum90 = add i32 %5, %tmp64 ; <i32> [#uses=1] + %scevgep65 = getelementptr i8* %3, i32 %.sum90 ; <i8*> [#uses=2] + %tmp66 = add i32 %tmp, 8 ; <i32> [#uses=1] + %.sum91 = add i32 %5, %tmp66 ; <i32> [#uses=1] + %scevgep67 = getelementptr i8* %3, i32 %.sum91 ; <i8*> [#uses=2] + %tmp6883 = or i32 %tmp, 7 ; <i32> [#uses=1] + %.sum92 = add i32 %5, %tmp6883 ; <i32> [#uses=1] + %scevgep69 = getelementptr i8* %3, i32 %.sum92 ; <i8*> [#uses=2] + %tmp7084 = or i32 %tmp, 6 ; <i32> [#uses=1] + %.sum93 = add i32 %5, %tmp7084 ; <i32> [#uses=1] + %scevgep71 = getelementptr i8* %3, i32 %.sum93 ; <i8*> [#uses=2] + %tmp7285 = or i32 %tmp, 5 ; <i32> [#uses=1] + %.sum94 = add i32 %5, %tmp7285 ; <i32> [#uses=1] + %scevgep73 = getelementptr i8* %3, i32 %.sum94 ; <i8*> [#uses=2] + %tmp7486 = or i32 %tmp, 4 ; <i32> [#uses=1] + %.sum95 = add i32 %5, %tmp7486 ; <i32> [#uses=1] + %scevgep75 = getelementptr i8* %3, i32 %.sum95 ; <i8*> [#uses=2] + %tmp7687 = or i32 %tmp, 3 ; <i32> [#uses=1] + %.sum96 = add i32 %5, %tmp7687 ; <i32> [#uses=1] + %scevgep77 = getelementptr i8* %3, i32 %.sum96 ; <i8*> [#uses=2] + %53 = load i8* %scevgep77, align 1 ; <i8> [#uses=1] + %54 = load i8* %scevgep61, align 1 ; <i8> [#uses=1] + %55 = icmp eq i8 %53, %54 ; <i1> [#uses=1] + br i1 %55, label %bb12, label %bb20 + +bb12: ; preds = %bb11 + %tmp57 = add i32 %tmp56, %tmp ; <i32> [#uses=1] + %scevgep58 = getelementptr i8* %3, i32 %tmp57 ; <i8*> [#uses=1] + %56 = load i8* %scevgep75, align 1 ; <i8> [#uses=1] + %57 = load i8* %scevgep58, align 1 ; <i8> [#uses=1] + %58 = icmp eq i8 %56, %57 ; <i1> [#uses=1] + br i1 %58, label %bb13, label %bb20 + +bb13: ; preds = %bb12 + %59 = load i8* %scevgep73, align 1 ; <i8> [#uses=1] + %60 = load i8* %scevgep55, align 1 ; <i8> [#uses=1] + %61 = icmp eq i8 %59, %60 ; <i1> [#uses=1] + br i1 %61, label %bb14, label %bb20 + +bb14: ; preds = %bb13 + %62 = load i8* %scevgep71, align 1 ; <i8> [#uses=1] + %63 = load i8* %scevgep52, align 1 ; <i8> [#uses=1] + %64 = icmp eq i8 %62, %63 ; <i1> [#uses=1] + br i1 %64, label %bb15, label %bb20 + +bb15: ; preds = %bb14 + %65 = load i8* %scevgep69, align 1 ; <i8> [#uses=1] + %66 = load i8* %scevgep49, align 1 ; <i8> [#uses=1] + %67 = icmp eq i8 %65, %66 ; <i1> [#uses=1] + br i1 %67, label %bb16, label %bb20 + +bb16: ; preds = %bb15 + %68 = load i8* %scevgep67, align 1 ; <i8> [#uses=1] + %69 = load i8* %scevgep46, align 1 ; <i8> [#uses=1] + %70 = icmp eq i8 %68, %69 ; <i1> [#uses=1] + br i1 %70, label %bb17, label %bb20 + +bb17: ; preds = %bb16 + %71 = load i8* %scevgep65, align 1 ; <i8> [#uses=1] + %72 = load i8* %scevgep43, align 1 ; <i8> [#uses=1] + %73 = icmp eq i8 %71, %72 ; <i1> [#uses=1] + br i1 %73, label %bb18, label %bb20 + +bb18: ; preds = %bb17 + %74 = load i8* %scevgep63, align 1 ; <i8> [#uses=1] + %75 = load i8* %scevgep, align 1 ; <i8> [#uses=1] + %76 = icmp eq i8 %74, %75 ; <i1> [#uses=1] + %77 = icmp slt i32 %.sum89, %.sum ; <i1> [#uses=1] + %or.cond = and i1 %76, %77 ; <i1> [#uses=1] + %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=1] + br i1 %or.cond, label %bb11, label %bb20 + +bb20: ; preds = %bb18, %bb17, %bb16, %bb15, %bb14, %bb13, %bb12, %bb11 + %scan.3 = phi i8* [ %scevgep77, %bb11 ], [ %scevgep75, %bb12 ], [ %scevgep73, %bb13 ], [ %scevgep71, %bb14 ], [ %scevgep69, %bb15 ], [ %scevgep67, %bb16 ], [ %scevgep65, %bb17 ], [ %scevgep63, %bb18 ] ; <i8*> [#uses=1] + %78 = ptrtoint i8* %scan.3 to i32 ; <i32> [#uses=1] + %79 = sub nsw i32 %78, %35 ; <i32> [#uses=2] + %80 = add i32 %79, 258 ; <i32> [#uses=5] + %81 = icmp sgt i32 %80, %best_len.2 ; <i1> [#uses=1] + br i1 %81, label %bb21, label %bb23 + +bb21: ; preds = %bb20 + store i32 %cur_match_addr.0, i32* %34, align 4 + %82 = icmp slt i32 %80, %nice_match.0.ph ; <i1> [#uses=1] + br i1 %82, label %bb22, label %bb25 + +bb22: ; preds = %bb21 + %.sum37 = add i32 %36, %79 ; <i32> [#uses=1] + %83 = getelementptr inbounds i8* %3, i32 %.sum37 ; <i8*> [#uses=1] + %84 = load i8* %83, align 1 ; <i8> [#uses=1] + %.sum38 = add i32 %80, %5 ; <i32> [#uses=1] + %85 = getelementptr inbounds i8* %3, i32 %.sum38 ; <i8*> [#uses=1] + %86 = load i8* %85, align 1 ; <i8> [#uses=1] + br label %bb23 + +bb23: ; preds = %bb22, %bb20, %bb9, %bb8, %bb7, %bb6 + %best_len.0 = phi i32 [ %best_len.2, %bb6 ], [ %best_len.2, %bb7 ], [ %best_len.2, %bb8 ], [ %best_len.2, %bb9 ], [ %80, %bb22 ], [ %best_len.2, %bb20 ] ; <i32> [#uses=3] + %scan_end1.0 = phi i8 [ %scan_end1.1, %bb6 ], [ %scan_end1.1, %bb7 ], [ %scan_end1.1, %bb8 ], [ %scan_end1.1, %bb9 ], [ %84, %bb22 ], [ %scan_end1.1, %bb20 ] ; <i8> [#uses=1] + %scan_end.0 = phi i8 [ %scan_end.1, %bb6 ], [ %scan_end.1, %bb7 ], [ %scan_end.1, %bb8 ], [ %scan_end.1, %bb9 ], [ %86, %bb22 ], [ %scan_end.1, %bb20 ] ; <i8> [#uses=1] + %87 = and i32 %cur_match_addr.0, %20 ; <i32> [#uses=1] + %88 = getelementptr inbounds i16* %18, i32 %87 ; <i16*> [#uses=1] + %89 = load i16* %88, align 2 ; <i16> [#uses=1] + %90 = zext i16 %89 to i32 ; <i32> [#uses=2] + %91 = icmp ugt i32 %90, %iftmp.48.0 ; <i1> [#uses=1] + br i1 %91, label %bb24, label %bb25 + +bb24: ; preds = %bb23 + +; LSR should use count-down iteration to avoid requiring the trip count +; in a register, and it shouldn't require any reloads here. + +; CHECK: sub.w r9, r9, #1 +; CHECK-NEXT: cmp.w r9, #0 +; CHECK-NEXT: bne.w + + %92 = icmp eq i32 %tmp81, %indvar78 ; <i1> [#uses=1] + %indvar.next79 = add i32 %indvar78, 1 ; <i32> [#uses=1] + br i1 %92, label %bb25, label %bb6 + +bb25: ; preds = %bb24, %bb23, %bb21 + %best_len.1 = phi i32 [ %best_len.0, %bb23 ], [ %best_len.0, %bb24 ], [ %80, %bb21 ] ; <i32> [#uses=2] + %93 = icmp ugt i32 %best_len.1, %32 ; <i1> [#uses=1] + %merge = select i1 %93, i32 %32, i32 %best_len.1 ; <i32> [#uses=1] + ret i32 %merge +} diff --git a/test/CodeGen/ARM/mul_const.ll b/test/CodeGen/ARM/mul_const.ll index 93188cd..8c10246 100644 --- a/test/CodeGen/ARM/mul_const.ll +++ b/test/CodeGen/ARM/mul_const.ll @@ -1,17 +1,43 @@ ; RUN: llc < %s -march=arm | FileCheck %s -define i32 @t1(i32 %v) nounwind readnone { +define i32 @t9(i32 %v) nounwind readnone { entry: -; CHECK: t1: +; CHECK: t9: ; CHECK: add r0, r0, r0, lsl #3 %0 = mul i32 %v, 9 ret i32 %0 } -define i32 @t2(i32 %v) nounwind readnone { +define i32 @t7(i32 %v) nounwind readnone { entry: -; CHECK: t2: +; CHECK: t7: ; CHECK: rsb r0, r0, r0, lsl #3 %0 = mul i32 %v, 7 ret i32 %0 } + +define i32 @t5(i32 %v) nounwind readnone { +entry: +; CHECK: t5: +; CHECK: add r0, r0, r0, lsl #2 + %0 = mul i32 %v, 5 + ret i32 %0 +} + +define i32 @t3(i32 %v) nounwind readnone { +entry: +; CHECK: t3: +; CHECK: add r0, r0, r0, lsl #1 + %0 = mul i32 %v, 3 + ret i32 %0 +} + +define i32 @t12288(i32 %v) nounwind readnone { +entry: +; CHECK: t12288: +; CHECK: add r0, r0, r0, lsl #1 +; CHECK: mov r0, r0, lsl #12 + %0 = mul i32 %v, 12288 + ret i32 %0 +} + diff --git a/test/CodeGen/ARM/reg_sequence.ll b/test/CodeGen/ARM/reg_sequence.ll new file mode 100644 index 0000000..3ba82cc --- /dev/null +++ b/test/CodeGen/ARM/reg_sequence.ll @@ -0,0 +1,348 @@ +; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s +; Implementing vld / vst as REG_SEQUENCE eliminates the extra vmov's. + +%struct.int16x8_t = type { <8 x i16> } +%struct.int32x4_t = type { <4 x i32> } +%struct.__neon_int8x8x2_t = type { <8 x i8>, <8 x i8> } +%struct.__neon_int8x8x3_t = type { <8 x i8>, <8 x i8>, <8 x i8> } +%struct.__neon_int16x8x2_t = type { <8 x i16>, <8 x i16> } +%struct.__neon_int32x4x2_t = type { <4 x i32>, <4 x i32> } + +define arm_apcscc void @t1(i16* %i_ptr, i16* %o_ptr, %struct.int32x4_t* nocapture %vT0ptr, %struct.int32x4_t* nocapture %vT1ptr) nounwind { +entry: +; CHECK: t1: +; CHECK: vld1.16 +; CHECK-NOT: vmov d +; CHECK: vmovl.s16 +; CHECK: vshrn.i32 +; CHECK: vshrn.i32 +; CHECK-NOT: vmov d +; CHECK-NEXT: vst1.16 + %0 = getelementptr inbounds %struct.int32x4_t* %vT0ptr, i32 0, i32 0 ; <<4 x i32>*> [#uses=1] + %1 = load <4 x i32>* %0, align 16 ; <<4 x i32>> [#uses=1] + %2 = getelementptr inbounds %struct.int32x4_t* %vT1ptr, i32 0, i32 0 ; <<4 x i32>*> [#uses=1] + %3 = load <4 x i32>* %2, align 16 ; <<4 x i32>> [#uses=1] + %4 = bitcast i16* %i_ptr to i8* ; <i8*> [#uses=1] + %5 = tail call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %4) ; <<8 x i16>> [#uses=1] + %6 = bitcast <8 x i16> %5 to <2 x double> ; <<2 x double>> [#uses=2] + %7 = extractelement <2 x double> %6, i32 0 ; <double> [#uses=1] + %8 = bitcast double %7 to <4 x i16> ; <<4 x i16>> [#uses=1] + %9 = tail call <4 x i32> @llvm.arm.neon.vmovls.v4i32(<4 x i16> %8) ; <<4 x i32>> [#uses=1] + %10 = extractelement <2 x double> %6, i32 1 ; <double> [#uses=1] + %11 = bitcast double %10 to <4 x i16> ; <<4 x i16>> [#uses=1] + %12 = tail call <4 x i32> @llvm.arm.neon.vmovls.v4i32(<4 x i16> %11) ; <<4 x i32>> [#uses=1] + %13 = mul <4 x i32> %1, %9 ; <<4 x i32>> [#uses=1] + %14 = mul <4 x i32> %3, %12 ; <<4 x i32>> [#uses=1] + %15 = tail call <4 x i16> @llvm.arm.neon.vshiftn.v4i16(<4 x i32> %13, <4 x i32> <i32 -12, i32 -12, i32 -12, i32 -12>) ; <<4 x i16>> [#uses=1] + %16 = tail call <4 x i16> @llvm.arm.neon.vshiftn.v4i16(<4 x i32> %14, <4 x i32> <i32 -12, i32 -12, i32 -12, i32 -12>) ; <<4 x i16>> [#uses=1] + %17 = shufflevector <4 x i16> %15, <4 x i16> %16, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> ; <<8 x i16>> [#uses=1] + %18 = bitcast i16* %o_ptr to i8* ; <i8*> [#uses=1] + tail call void @llvm.arm.neon.vst1.v8i16(i8* %18, <8 x i16> %17) + ret void +} + +define arm_apcscc void @t2(i16* %i_ptr, i16* %o_ptr, %struct.int16x8_t* nocapture %vT0ptr, %struct.int16x8_t* nocapture %vT1ptr) nounwind { +entry: +; CHECK: t2: +; CHECK: vld1.16 +; CHECK: vld1.16 +; CHECK-NOT: vmov +; CHECK: vmul.i16 +; CHECK: vmul.i16 +; CHECK-NOT: vmov +; CHECK: vst1.16 +; CHECK: vst1.16 + %0 = getelementptr inbounds %struct.int16x8_t* %vT0ptr, i32 0, i32 0 ; <<8 x i16>*> [#uses=1] + %1 = load <8 x i16>* %0, align 16 ; <<8 x i16>> [#uses=1] + %2 = getelementptr inbounds %struct.int16x8_t* %vT1ptr, i32 0, i32 0 ; <<8 x i16>*> [#uses=1] + %3 = load <8 x i16>* %2, align 16 ; <<8 x i16>> [#uses=1] + %4 = bitcast i16* %i_ptr to i8* ; <i8*> [#uses=1] + %5 = tail call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %4) ; <<8 x i16>> [#uses=1] + %6 = getelementptr inbounds i16* %i_ptr, i32 8 ; <i16*> [#uses=1] + %7 = bitcast i16* %6 to i8* ; <i8*> [#uses=1] + %8 = tail call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %7) ; <<8 x i16>> [#uses=1] + %9 = mul <8 x i16> %1, %5 ; <<8 x i16>> [#uses=1] + %10 = mul <8 x i16> %3, %8 ; <<8 x i16>> [#uses=1] + %11 = bitcast i16* %o_ptr to i8* ; <i8*> [#uses=1] + tail call void @llvm.arm.neon.vst1.v8i16(i8* %11, <8 x i16> %9) + %12 = getelementptr inbounds i16* %o_ptr, i32 8 ; <i16*> [#uses=1] + %13 = bitcast i16* %12 to i8* ; <i8*> [#uses=1] + tail call void @llvm.arm.neon.vst1.v8i16(i8* %13, <8 x i16> %10) + ret void +} + +define <8 x i8> @t3(i8* %A, i8* %B) nounwind { +; CHECK: t3: +; CHECK: vld3.8 +; CHECK: vmul.i8 +; CHECK-NOT: vmov +; CHECK: vst3.8 + %tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A) ; <%struct.__neon_int8x8x3_t> [#uses=2] + %tmp2 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 0 ; <<8 x i8>> [#uses=1] + %tmp3 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 2 ; <<8 x i8>> [#uses=1] + %tmp4 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 1 ; <<8 x i8>> [#uses=1] + %tmp5 = sub <8 x i8> %tmp3, %tmp4 + %tmp6 = add <8 x i8> %tmp2, %tmp3 ; <<8 x i8>> [#uses=1] + %tmp7 = mul <8 x i8> %tmp4, %tmp2 + tail call void @llvm.arm.neon.vst3.v8i8(i8* %B, <8 x i8> %tmp5, <8 x i8> %tmp6, <8 x i8> %tmp7) + ret <8 x i8> %tmp4 +} + +define arm_apcscc void @t4(i32* %in, i32* %out) nounwind { +entry: +; CHECK: t4: +; CHECK: vld2.32 +; CHECK-NOT: vmov +; CHECK: vld2.32 +; CHECK-NOT: vmov +; CHECK: bne + %tmp1 = bitcast i32* %in to i8* ; <i8*> [#uses=1] + %tmp2 = tail call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i8* %tmp1) ; <%struct.__neon_int32x4x2_t> [#uses=2] + %tmp3 = getelementptr inbounds i32* %in, i32 8 ; <i32*> [#uses=1] + %tmp4 = bitcast i32* %tmp3 to i8* ; <i8*> [#uses=1] + %tmp5 = tail call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i8* %tmp4) ; <%struct.__neon_int32x4x2_t> [#uses=2] + %tmp8 = bitcast i32* %out to i8* ; <i8*> [#uses=1] + br i1 undef, label %return1, label %return2 + +return1: +; CHECK: %return1 +; CHECK-NOT: vmov +; CHECK-NEXT: vadd.i32 +; CHECK-NEXT: vadd.i32 +; CHECK-NEXT: vst2.32 + %tmp52 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 0 ; <<4 x i32>> [#uses=1] + %tmp57 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 1 ; <<4 x i32>> [#uses=1] + %tmp = extractvalue %struct.__neon_int32x4x2_t %tmp5, 0 ; <<4 x i32>> [#uses=1] + %tmp39 = extractvalue %struct.__neon_int32x4x2_t %tmp5, 1 ; <<4 x i32>> [#uses=1] + %tmp6 = add <4 x i32> %tmp52, %tmp ; <<4 x i32>> [#uses=1] + %tmp7 = add <4 x i32> %tmp57, %tmp39 ; <<4 x i32>> [#uses=1] + tail call void @llvm.arm.neon.vst2.v4i32(i8* %tmp8, <4 x i32> %tmp6, <4 x i32> %tmp7) + ret void + +return2: +; CHECK: %return2 +; CHECK: vadd.i32 +; CHECK: vmov q1, q3 +; CHECK-NOT: vmov +; CHECK: vst2.32 {d0, d1, d2, d3} + %tmp100 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 0 ; <<4 x i32>> [#uses=1] + %tmp101 = extractvalue %struct.__neon_int32x4x2_t %tmp5, 1 ; <<4 x i32>> [#uses=1] + %tmp102 = add <4 x i32> %tmp100, %tmp101 ; <<4 x i32>> [#uses=1] + tail call void @llvm.arm.neon.vst2.v4i32(i8* %tmp8, <4 x i32> %tmp102, <4 x i32> %tmp101) + call void @llvm.trap() + unreachable +} + +define <8 x i16> @t5(i16* %A, <8 x i16>* %B) nounwind { +; CHECK: t5: +; CHECK: vldmia +; CHECK: vmov q1, q0 +; CHECK-NOT: vmov +; CHECK: vld2.16 {d0[1], d2[1]}, [r0] +; CHECK-NOT: vmov +; CHECK: vadd.i16 + %tmp0 = bitcast i16* %A to i8* ; <i8*> [#uses=1] + %tmp1 = load <8 x i16>* %B ; <<8 x i16>> [#uses=2] + %tmp2 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1) ; <%struct.__neon_int16x8x2_t> [#uses=2] + %tmp3 = extractvalue %struct.__neon_int16x8x2_t %tmp2, 0 ; <<8 x i16>> [#uses=1] + %tmp4 = extractvalue %struct.__neon_int16x8x2_t %tmp2, 1 ; <<8 x i16>> [#uses=1] + %tmp5 = add <8 x i16> %tmp3, %tmp4 ; <<8 x i16>> [#uses=1] + ret <8 x i16> %tmp5 +} + +define <8 x i8> @t6(i8* %A, <8 x i8>* %B) nounwind { +; CHECK: t6: +; CHECK: vldr.64 +; CHECK: vmov d1, d0 +; CHECK-NEXT: vld2.8 {d0[1], d1[1]} + %tmp1 = load <8 x i8>* %B ; <<8 x i8>> [#uses=2] + %tmp2 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1) ; <%struct.__neon_int8x8x2_t> [#uses=2] + %tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 0 ; <<8 x i8>> [#uses=1] + %tmp4 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 1 ; <<8 x i8>> [#uses=1] + %tmp5 = add <8 x i8> %tmp3, %tmp4 ; <<8 x i8>> [#uses=1] + ret <8 x i8> %tmp5 +} + +define arm_apcscc void @t7(i32* %iptr, i32* %optr) nounwind { +entry: +; CHECK: t7: +; CHECK: vld2.32 +; CHECK: vst2.32 +; CHECK: vld1.32 {d0, d1}, +; CHECK: vmov q1, q0 +; CHECK-NOT: vmov +; CHECK: vuzp.32 q0, q1 +; CHECK: vst1.32 + %0 = bitcast i32* %iptr to i8* ; <i8*> [#uses=2] + %1 = tail call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i8* %0) ; <%struct.__neon_int32x4x2_t> [#uses=2] + %tmp57 = extractvalue %struct.__neon_int32x4x2_t %1, 0 ; <<4 x i32>> [#uses=1] + %tmp60 = extractvalue %struct.__neon_int32x4x2_t %1, 1 ; <<4 x i32>> [#uses=1] + %2 = bitcast i32* %optr to i8* ; <i8*> [#uses=2] + tail call void @llvm.arm.neon.vst2.v4i32(i8* %2, <4 x i32> %tmp57, <4 x i32> %tmp60) + %3 = tail call <4 x i32> @llvm.arm.neon.vld1.v4i32(i8* %0) ; <<4 x i32>> [#uses=1] + %4 = shufflevector <4 x i32> %3, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 0, i32 2> ; <<4 x i32>> [#uses=1] + tail call void @llvm.arm.neon.vst1.v4i32(i8* %2, <4 x i32> %4) + ret void +} + +; PR7156 +define arm_aapcs_vfpcc i32 @t8() nounwind { +; CHECK: t8: +; CHECK: vrsqrte.f32 q0, q0 +bb.nph55.bb.nph55.split_crit_edge: + br label %bb3 + +bb3: ; preds = %bb3, %bb.nph55.bb.nph55.split_crit_edge + br i1 undef, label %bb5, label %bb3 + +bb5: ; preds = %bb3 + br label %bb.i25 + +bb.i25: ; preds = %bb.i25, %bb5 + %0 = shufflevector <2 x float> undef, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1] + %1 = call <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float> %0) nounwind ; <<4 x float>> [#uses=1] + %2 = fmul <4 x float> %1, undef ; <<4 x float>> [#uses=1] + %3 = fmul <4 x float> undef, %2 ; <<4 x float>> [#uses=1] + %tmp26.i = bitcast <4 x float> %3 to <2 x double> ; <<2 x double>> [#uses=1] + %4 = extractelement <2 x double> %tmp26.i, i32 0 ; <double> [#uses=1] + %5 = bitcast double %4 to <2 x float> ; <<2 x float>> [#uses=1] + %6 = extractelement <2 x float> %5, i32 1 ; <float> [#uses=1] + store float %6, float* undef, align 4 + br i1 undef, label %bb6, label %bb.i25 + +bb6: ; preds = %bb.i25 + br i1 undef, label %bb7, label %bb14 + +bb7: ; preds = %bb6 + br label %bb.i49 + +bb.i49: ; preds = %bb.i49, %bb7 + br i1 undef, label %bb.i19, label %bb.i49 + +bb.i19: ; preds = %bb.i19, %bb.i49 + br i1 undef, label %exit, label %bb.i19 + +exit: ; preds = %bb.i19 + unreachable + +bb14: ; preds = %bb6 + ret i32 0 +} + +%0 = type { %1, %1, %1, %1 } +%1 = type { %2 } +%2 = type { <4 x float> } +%3 = type { %0, %1 } + +; PR7157 +define arm_aapcs_vfpcc float @t9(%0* nocapture, %3* nocapture) nounwind { +; CHECK: t9: +; CHECK: vldr.64 +; CHECK: vmov.i8 d1 +; CHECK-NEXT: vstmia r0, {d2,d3} +; CHECK-NEXT: vstmia r0, {d0,d1} + %3 = bitcast double 0.000000e+00 to <2 x float> ; <<2 x float>> [#uses=2] + %4 = shufflevector <2 x float> %3, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1] + store <4 x float> %4, <4 x float>* undef, align 16 + %5 = shufflevector <2 x float> %3, <2 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1] + store <4 x float> %5, <4 x float>* undef, align 16 + br label %8 + +; <label>:6 ; preds = %8 + br i1 undef, label %7, label %10 + +; <label>:7 ; preds = %6 + br label %8 + +; <label>:8 ; preds = %7, %2 + br i1 undef, label %6, label %9 + +; <label>:9 ; preds = %8 + ret float undef + +; <label>:10 ; preds = %6 + ret float 9.990000e+02 +} + +; PR7162 +define arm_aapcs_vfpcc i32 @t10() nounwind { +entry: +; CHECK: t10: +; CHECK: vmov.i32 q1, #0x3F000000 +; CHECK: vdup.32 q0, d0[0] +; CHECK: vmov d0, d1 +; CHECK: vmla.f32 q0, q0, d0[0] + %0 = shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1] + %1 = insertelement <4 x float> %0, float undef, i32 1 ; <<4 x float>> [#uses=1] + %2 = insertelement <4 x float> %1, float undef, i32 2 ; <<4 x float>> [#uses=1] + %3 = insertelement <4 x float> %2, float undef, i32 3 ; <<4 x float>> [#uses=1] + %tmp54.i = bitcast <4 x float> %3 to <2 x double> ; <<2 x double>> [#uses=1] + %4 = extractelement <2 x double> %tmp54.i, i32 1 ; <double> [#uses=1] + %5 = bitcast double %4 to <2 x float> ; <<2 x float>> [#uses=1] + %6 = shufflevector <2 x float> %5, <2 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1] + %7 = fmul <4 x float> undef, %6 ; <<4 x float>> [#uses=1] + %8 = fadd <4 x float> %7, undef ; <<4 x float>> [#uses=1] + %9 = fadd <4 x float> %8, undef ; <<4 x float>> [#uses=1] + %10 = shufflevector <4 x float> undef, <4 x float> %9, <4 x i32> <i32 0, i32 1, i32 2, i32 7> ; <<4 x float>> [#uses=1] + %11 = fmul <4 x float> %10, <float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01> ; <<4 x float>> [#uses=1] + %12 = shufflevector <4 x float> %11, <4 x float> undef, <4 x i32> <i32 3, i32 undef, i32 undef, i32 undef> ; <<4 x float>> [#uses=1] + %13 = shufflevector <4 x float> %12, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1] + %14 = fmul <4 x float> %13, undef ; <<4 x float>> [#uses=1] + %15 = fadd <4 x float> undef, %14 ; <<4 x float>> [#uses=1] + %16 = shufflevector <4 x float> undef, <4 x float> %15, <4 x i32> <i32 0, i32 1, i32 6, i32 3> ; <<4 x float>> [#uses=1] + %17 = fmul <4 x float> %16, undef ; <<4 x float>> [#uses=1] + %18 = extractelement <4 x float> %17, i32 2 ; <float> [#uses=1] + store float %18, float* undef, align 4 + br i1 undef, label %exit, label %bb14 + +exit: ; preds = %bb.i19 + unreachable + +bb14: ; preds = %bb6 + ret i32 0 +} + +; This test crashes the coalescer because live variables were not updated properly. +define <8 x i8> @t11(i8* %A1, i8* %A2, i8* %A3, i8* %A4, i8* %A5, i8* %A6, i8* %A7, i8* %A8, i8* %B) nounwind { + %tmp1d = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A4) ; <%struct.__neon_int8x8x3_t> [#uses=1] + %tmp2d = extractvalue %struct.__neon_int8x8x3_t %tmp1d, 0 ; <<8 x i8>> [#uses=1] + %tmp1f = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A6) ; <%struct.__neon_int8x8x3_t> [#uses=1] + %tmp2f = extractvalue %struct.__neon_int8x8x3_t %tmp1f, 0 ; <<8 x i8>> [#uses=1] + %tmp2bd = add <8 x i8> zeroinitializer, %tmp2d ; <<8 x i8>> [#uses=1] + %tmp2abcd = mul <8 x i8> zeroinitializer, %tmp2bd ; <<8 x i8>> [#uses=1] + %tmp2ef = sub <8 x i8> zeroinitializer, %tmp2f ; <<8 x i8>> [#uses=1] + %tmp2efgh = mul <8 x i8> %tmp2ef, undef ; <<8 x i8>> [#uses=2] + call void @llvm.arm.neon.vst3.v8i8(i8* %A2, <8 x i8> undef, <8 x i8> undef, <8 x i8> %tmp2efgh) + %tmp2 = sub <8 x i8> %tmp2efgh, %tmp2abcd ; <<8 x i8>> [#uses=1] + %tmp7 = mul <8 x i8> undef, %tmp2 ; <<8 x i8>> [#uses=1] + tail call void @llvm.arm.neon.vst3.v8i8(i8* %B, <8 x i8> undef, <8 x i8> undef, <8 x i8> %tmp7) + ret <8 x i8> undef +} + +declare <4 x i32> @llvm.arm.neon.vld1.v4i32(i8*) nounwind readonly + +declare <8 x i16> @llvm.arm.neon.vld1.v8i16(i8*) nounwind readonly + +declare <4 x i32> @llvm.arm.neon.vmovls.v4i32(<4 x i16>) nounwind readnone + +declare <4 x i16> @llvm.arm.neon.vshiftn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone + +declare void @llvm.arm.neon.vst1.v4i32(i8*, <4 x i32>) nounwind + +declare void @llvm.arm.neon.vst1.v8i16(i8*, <8 x i16>) nounwind + +declare void @llvm.arm.neon.vst3.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>) nounwind + +declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8*) nounwind readonly + +declare %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i8*) nounwind readonly + +declare %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8(i8*, <8 x i8>, <8 x i8>, i32) nounwind readonly + +declare %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16(i8*, <8 x i16>, <8 x i16>, i32) nounwind readonly + +declare void @llvm.arm.neon.vst2.v4i32(i8*, <4 x i32>, <4 x i32>) nounwind + +declare <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float>) nounwind readnone + +declare void @llvm.trap() nounwind diff --git a/test/CodeGen/ARM/spill-q.ll b/test/CodeGen/ARM/spill-q.ll index 5ad7ecc..03de0c8 100644 --- a/test/CodeGen/ARM/spill-q.ll +++ b/test/CodeGen/ARM/spill-q.ll @@ -46,7 +46,8 @@ bb4: ; preds = %bb193, %entry %20 = shufflevector <2 x float> %19, <2 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1] %21 = fadd <4 x float> zeroinitializer, %20 ; <<4 x float>> [#uses=2] %22 = fcmp ogt <4 x float> %besterror.0.2264, %21 ; <<4 x i1>> [#uses=0] - br i1 undef, label %bb193, label %bb186 + %tmp = extractelement <4 x i1> %22, i32 0 + br i1 %tmp, label %bb193, label %bb186 bb186: ; preds = %bb4 br label %bb193 diff --git a/test/CodeGen/ARM/trap.ll b/test/CodeGen/ARM/trap.ll new file mode 100644 index 0000000..763dff3 --- /dev/null +++ b/test/CodeGen/ARM/trap.ll @@ -0,0 +1,12 @@ +; RUN: llc < %s -march=arm | FileCheck %s +; rdar://7961298 + +define arm_apcscc void @t() nounwind { +entry: +; CHECK: t: +; CHECK: trap + call void @llvm.trap() + unreachable +} + +declare void @llvm.trap() nounwind diff --git a/test/CodeGen/ARM/vcgt.ll b/test/CodeGen/ARM/vcgt.ll index 6b11ba5..194093c 100644 --- a/test/CodeGen/ARM/vcgt.ll +++ b/test/CodeGen/ARM/vcgt.ll @@ -158,5 +158,18 @@ define <4 x i32> @vacgtQf32(<4 x float>* %A, <4 x float>* %B) nounwind { ret <4 x i32> %tmp3 } +; rdar://7923010 +define <4 x i32> @vcgt_zext(<4 x float>* %A, <4 x float>* %B) nounwind { +;CHECK: vcgt_zext: +;CHECK: vcgt.f32 q0 +;CHECK: vmov.i32 q1, #0x1 +;CHECK: vand q0, q0, q1 + %tmp1 = load <4 x float>* %A + %tmp2 = load <4 x float>* %B + %tmp3 = fcmp ogt <4 x float> %tmp1, %tmp2 + %tmp4 = zext <4 x i1> %tmp3 to <4 x i32> + ret <4 x i32> %tmp4 +} + declare <2 x i32> @llvm.arm.neon.vacgtd(<2 x float>, <2 x float>) nounwind readnone declare <4 x i32> @llvm.arm.neon.vacgtq(<4 x float>, <4 x float>) nounwind readnone diff --git a/test/CodeGen/CellSPU/jumptable.ll b/test/CodeGen/CellSPU/jumptable.ll new file mode 100644 index 0000000..d7d1ef4 --- /dev/null +++ b/test/CodeGen/CellSPU/jumptable.ll @@ -0,0 +1,21 @@ +;RUN: llc --march=cellspu %s -o - | FileCheck %s +; This is to check that emitting jumptables doesn't crash llc +define i32 @test(i32 %param) { +entry: +;CHECK: ai $4, $3, -1 +;CHECK: clgti $5, $4, 3 +;CHECK: brnz $5,.LBB0_2 + switch i32 %param, label %bb1 [ + i32 1, label %bb3 + i32 2, label %bb2 + i32 3, label %bb3 + i32 4, label %bb1 + ] + +bb1: + ret i32 1 +bb2: + ret i32 2 +bb3: + ret i32 3 +} diff --git a/test/CodeGen/CellSPU/sub_ops.ll b/test/CodeGen/CellSPU/sub_ops.ll new file mode 100644 index 0000000..f0c40d3 --- /dev/null +++ b/test/CodeGen/CellSPU/sub_ops.ll @@ -0,0 +1,26 @@ +; RUN: llc < %s -march=cellspu | FileCheck %s + +define i32 @subword( i32 %param1, i32 %param2) { +; Check ordering of registers ret=param1-param2 -> rt=rb-ra +; CHECK-NOT: sf $3, $3, $4 +; CHECK: sf $3, $4, $3 + %1 = sub i32 %param1, %param2 + ret i32 %1 +} + +define i16 @subhword( i16 %param1, i16 %param2) { +; Check ordering of registers ret=param1-param2 -> rt=rb-ra +; CHECK-NOT: sfh $3, $3, $4 +; CHECK: sfh $3, $4, $3 + %1 = sub i16 %param1, %param2 + ret i16 %1 +} + +define float @subfloat( float %param1, float %param2) { +; Check ordering of registers ret=param1-param2 -> rt=ra-rb +; (yes this is reverse of i32 instruction) +; CHECK-NOT: fs $3, $4, $3 +; CHECK: fs $3, $3, $4 + %1 = fsub float %param1, %param2 + ret float %1 +} diff --git a/test/CodeGen/Generic/2006-09-02-LocalAllocCrash.ll b/test/CodeGen/Generic/2006-09-02-LocalAllocCrash.ll index 4b332b3..d5a4d6a 100644 --- a/test/CodeGen/Generic/2006-09-02-LocalAllocCrash.ll +++ b/test/CodeGen/Generic/2006-09-02-LocalAllocCrash.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -regalloc=local +; RUN: llc < %s -regalloc=fast %struct.CHESS_POSITION = type { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i32, i32, i8, i8, [64 x i8], i8, i8, i8, i8, i8 } @search = external global %struct.CHESS_POSITION ; <%struct.CHESS_POSITION*> [#uses=2] diff --git a/test/CodeGen/Generic/legalize-dbg-value.ll b/test/CodeGen/Generic/legalize-dbg-value.ll new file mode 100644 index 0000000..b71aa8a --- /dev/null +++ b/test/CodeGen/Generic/legalize-dbg-value.ll @@ -0,0 +1,25 @@ +; RUN: llc < %s -o /dev/null + +; llvm.dbg.value instructions can have types which are not legal for the +; target. CodeGen should handle this. + +define i128 @__mulvti3(i128 %a, i128 %b) nounwind { +entry: + tail call void @llvm.dbg.value(metadata !0, i64 0, metadata !1), !dbg !11 + unreachable +} + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone + +!0 = metadata !{i128 170141183460469231731687303715884105727} +!1 = metadata !{i32 524544, metadata !2, metadata !"MAX", metadata !4, i32 29, metadata !8} ; [ DW_TAG_auto_variable ] +!2 = metadata !{i32 524299, metadata !3, i32 26, i32 0} ; [ DW_TAG_lexical_block ] +!3 = metadata !{i32 524334, i32 0, metadata !4, metadata !"__mulvti3", metadata !"__mulvti3", metadata !"__mulvti3", metadata !4, i32 26, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i1 false} ; [ DW_TAG_subprogram ] +!4 = metadata !{i32 524329, metadata !"mulvti3.c", metadata !"/Volumes/Sandbox/llvm/swb/Libcompiler_rt-6.roots/Libcompiler_rt-6/lib", metadata !5} ; [ DW_TAG_file_type ] +!5 = metadata !{i32 524305, i32 0, i32 1, metadata !"mulvti3.c", metadata !"/Volumes/Sandbox/llvm/swb/Libcompiler_rt-6.roots/Libcompiler_rt-6/lib", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build 2328)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!6 = metadata !{i32 524309, metadata !4, metadata !"", metadata !4, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, null} ; [ DW_TAG_subroutine_type ] +!7 = metadata !{metadata !8, metadata !8, metadata !8} +!8 = metadata !{i32 524310, metadata !4, metadata !"ti_int", metadata !9, i32 78, i64 0, i64 0, i64 0, i32 0, metadata !10} ; [ DW_TAG_typedef ] +!9 = metadata !{i32 524329, metadata !"int_lib.h", metadata !"/Volumes/Sandbox/llvm/swb/Libcompiler_rt-6.roots/Libcompiler_rt-6/lib", metadata !5} ; [ DW_TAG_file_type ] +!10 = metadata !{i32 524324, metadata !4, metadata !"", metadata !4, i32 0, i64 128, i64 128, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!11 = metadata !{i32 29, i32 0, metadata !2, null} diff --git a/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll b/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll index be28a9a..9c28da8 100644 --- a/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll +++ b/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll @@ -1,9 +1,11 @@ -; RUN: llc < %s | grep {subfc r3,r5,r4} -; RUN: llc < %s | grep {subfze r4,r6} -; RUN: llc < %s -regalloc=local | grep {subfc r6,r5,r4} -; RUN: llc < %s -regalloc=local | grep {subfze r3,r3} +; RUN: llc < %s | FileCheck %s +; RUN: llc < %s -regalloc=local | FileCheck %s +; RUN: llc < %s -regalloc=fast | FileCheck %s ; The first argument of subfc must not be the same as any other register. +; CHECK: subfc [[REG:r.]], +; CHECK-NOT: [[REG]] +; CHECK: InlineAsm End ; PR1357 target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64" diff --git a/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll b/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll index ee61478..3cfe603 100644 --- a/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll +++ b/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -mtriple=powerpc64-apple-darwin9 -regalloc=local -relocation-model=pic +; RUN: llc < %s -mtriple=powerpc64-apple-darwin9 -regalloc=fast -relocation-model=pic %struct.NSError = type opaque %struct.NSManagedObjectContext = type opaque diff --git a/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll b/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll index 5a07a9b..8339a0b 100644 --- a/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll +++ b/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -mtriple=powerpc64-apple-darwin9 -regalloc=local -relocation-model=pic +; RUN: llc < %s -mtriple=powerpc64-apple-darwin9 -regalloc=fast -relocation-model=pic %struct.NSError = type opaque %struct.NSManagedObjectContext = type opaque diff --git a/test/CodeGen/PowerPC/2008-02-09-LocalRegAllocAssert.ll b/test/CodeGen/PowerPC/2008-02-09-LocalRegAllocAssert.ll index cfa1b10..45dfdc8 100644 --- a/test/CodeGen/PowerPC/2008-02-09-LocalRegAllocAssert.ll +++ b/test/CodeGen/PowerPC/2008-02-09-LocalRegAllocAssert.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -mtriple=powerpc-apple-darwin -regalloc=local +; RUN: llc < %s -mtriple=powerpc-apple-darwin -regalloc=fast define i32 @bork(i64 %foo, i64 %bar) { entry: diff --git a/test/CodeGen/PowerPC/cr_spilling.ll b/test/CodeGen/PowerPC/cr_spilling.ll index b215868..9ed2614 100644 --- a/test/CodeGen/PowerPC/cr_spilling.ll +++ b/test/CodeGen/PowerPC/cr_spilling.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -march=ppc32 -regalloc=local -O0 -relocation-model=pic -o - +; RUN: llc < %s -march=ppc32 -regalloc=fast -O0 -relocation-model=pic -o - ; PR1638 @.str242 = external constant [3 x i8] ; <[3 x i8]*> [#uses=1] diff --git a/test/CodeGen/SystemZ/2009-07-10-BadIncomingArgOffset.ll b/test/CodeGen/SystemZ/2009-07-10-BadIncomingArgOffset.ll index 6a76a8e..b37f7e9 100644 --- a/test/CodeGen/SystemZ/2009-07-10-BadIncomingArgOffset.ll +++ b/test/CodeGen/SystemZ/2009-07-10-BadIncomingArgOffset.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s | grep 168 +; RUN: llc < %s | FileCheck %s target datalayout = "E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-a0:16:16" target triple = "s390x-linux" @@ -8,6 +8,8 @@ declare void @rdft(i32 signext, i32 signext, double*, i32* nocapture, double*) n declare double @mp_mul_d2i_test(i32 signext, i32 signext, double* nocapture) nounwind define void @mp_mul_radix_test_bb3(i32 %radix, i32 %nfft, double* %tmpfft, i32* %ip, double* %w, double* %arrayidx44.reload, double* %call.out) nounwind { +; CHECK: lg %r11, 328(%r15) + newFuncRoot: br label %bb3 diff --git a/test/CodeGen/Thumb/2010-01-15-local-alloc-spill-physical.ll b/test/CodeGen/Thumb/2010-01-15-local-alloc-spill-physical.ll index d676369..300e66c 100644 --- a/test/CodeGen/Thumb/2010-01-15-local-alloc-spill-physical.ll +++ b/test/CodeGen/Thumb/2010-01-15-local-alloc-spill-physical.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -regalloc=local -relocation-model=pic | FileCheck %s +; RUN: llc < %s -regalloc=fast -relocation-model=pic | FileCheck %s target triple = "thumbv6-apple-darwin10" @@ -6,10 +7,10 @@ target triple = "thumbv6-apple-darwin10" define arm_apcscc void @foo() nounwind { entry: -; CHECK: str r0, [sp] +; CHECK: str r0, [sp %0 = call arm_apcscc i32 (...)* @bar() nounwind ; <i32> [#uses=1] ; CHECK: blx _bar -; CHECK: ldr r1, [sp] +; CHECK: ldr r1, [sp store i32 %0, i32* @fred, align 4 br label %return diff --git a/test/CodeGen/Thumb/trap.ll b/test/CodeGen/Thumb/trap.ll new file mode 100644 index 0000000..76a0589 --- /dev/null +++ b/test/CodeGen/Thumb/trap.ll @@ -0,0 +1,12 @@ +; RUN: llc < %s -march=thumb | FileCheck %s +; rdar://7961298 + +define arm_apcscc void @t() nounwind { +entry: +; CHECK: t: +; CHECK: trap + call void @llvm.trap() + unreachable +} + +declare void @llvm.trap() nounwind diff --git a/test/CodeGen/Thumb2/2010-05-24-rsbs.ll b/test/CodeGen/Thumb2/2010-05-24-rsbs.ll new file mode 100644 index 0000000..7a40aa9 --- /dev/null +++ b/test/CodeGen/Thumb2/2010-05-24-rsbs.ll @@ -0,0 +1,9 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s +; Radar 8017376: Missing 's' suffix for t2RSBS instructions. +; CHECK: rsbs + +define arm_apcscc i64 @test(i64 %x) nounwind readnone { +entry: + %0 = sub nsw i64 1, %x ; <i64> [#uses=1] + ret i64 %0 +} diff --git a/test/CodeGen/Thumb2/div.ll b/test/CodeGen/Thumb2/div.ll new file mode 100644 index 0000000..0cddd48 --- /dev/null +++ b/test/CodeGen/Thumb2/div.ll @@ -0,0 +1,45 @@ +; RUN: llc < %s -march=thumb -mattr=+thumb2 \ +; RUN: | FileCheck %s -check-prefix=CHECK-THUMB +; RUN: llc < %s -march=arm -mcpu=cortex-m3 -mattr=+thumb2 \ +; RUN: | FileCheck %s -check-prefix=CHECK-THUMBV7M + +define i32 @f1(i32 %a, i32 %b) { +entry: +; CHECK-THUMB: f1 +; CHECK-THUMB: __divsi3 +; CHECK-THUMBV7M: f1 +; CHECK-THUMBV7M: sdiv + %tmp1 = sdiv i32 %a, %b ; <i32> [#uses=1] + ret i32 %tmp1 +} + +define i32 @f2(i32 %a, i32 %b) { +entry: +; CHECK-THUMB: f2 +; CHECK-THUMB: __udivsi3 +; CHECK-THUMBV7M: f2 +; CHECK-THUMBV7M: udiv + %tmp1 = udiv i32 %a, %b ; <i32> [#uses=1] + ret i32 %tmp1 +} + +define i32 @f3(i32 %a, i32 %b) { +entry: +; CHECK-THUMB: f3 +; CHECK-THUMB: __modsi3 +; CHECK-THUMBV7M: f3 +; CHECK-THUMBV7M: sdiv + %tmp1 = srem i32 %a, %b ; <i32> [#uses=1] + ret i32 %tmp1 +} + +define i32 @f4(i32 %a, i32 %b) { +entry: +; CHECK-THUMB: f4 +; CHECK-THUMB: __umodsi3 +; CHECK-THUMBV7M: f4 +; CHECK-THUMBV7M: udiv + %tmp1 = urem i32 %a, %b ; <i32> [#uses=1] + ret i32 %tmp1 +} + diff --git a/test/CodeGen/Thumb2/machine-licm.ll b/test/CodeGen/Thumb2/machine-licm.ll index c298aa2..98acc28 100644 --- a/test/CodeGen/Thumb2/machine-licm.ll +++ b/test/CodeGen/Thumb2/machine-licm.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin -disable-fp-elim | FileCheck %s -; RUN: llc < %s -mtriple=thumbv7-apple-darwin -relocation-model=pic -disable-fp-elim | FileCheck %s --check-prefix=PIC +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -disable-fp-elim | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -relocation-model=pic -disable-fp-elim | FileCheck %s --check-prefix=PIC ; rdar://7353541 ; rdar://7354376 @@ -8,9 +8,9 @@ @GV = external global i32 ; <i32*> [#uses=2] -define arm_apcscc void @t(i32* nocapture %vals, i32 %c) nounwind { +define arm_apcscc void @t1(i32* nocapture %vals, i32 %c) nounwind { entry: -; CHECK: t: +; CHECK: t1: ; CHECK: cbz %0 = icmp eq i32 %c, 0 ; <i1> [#uses=1] br i1 %0, label %return, label %bb.nph @@ -22,8 +22,7 @@ bb.nph: ; preds = %entry ; CHECK: ldr r3, [r2] ; CHECK: LBB0_2 ; CHECK: LCPI0_0: -; CHECK-NOT: LCPI1_1: -; CHECK: .section +; CHECK-NOT: LCPI0_1: ; PIC: BB#1 ; PIC: ldr.n r2, LCPI0_0 @@ -51,3 +50,37 @@ bb: ; preds = %bb, %bb.nph return: ; preds = %bb, %entry ret void } + +; rdar://8001136 +define arm_apcscc void @t2(i8* %ptr1, i8* %ptr2) nounwind { +entry: +; CHECK: t2: +; CHECK: adr r{{.}}, #LCPI1_0 +; CHECK: vldmia r3, {d0,d1} + br i1 undef, label %bb1, label %bb2 + +bb1: +; CHECK-NEXT: %bb1 + %indvar = phi i32 [ %indvar.next, %bb1 ], [ 0, %entry ] + %tmp1 = shl i32 %indvar, 2 + %gep1 = getelementptr i8* %ptr1, i32 %tmp1 + %tmp2 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %gep1) + %tmp3 = call <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, <4 x float> %tmp2) + %gep2 = getelementptr i8* %ptr2, i32 %tmp1 + call void @llvm.arm.neon.vst1.v4f32(i8* %gep2, <4 x float> %tmp3) + %indvar.next = add i32 %indvar, 1 + %cond = icmp eq i32 %indvar.next, 10 + br i1 %cond, label %bb2, label %bb1 + +bb2: + ret void +} + +; CHECK: LCPI1_0: +; CHECK: .section + +declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*) nounwind readonly + +declare void @llvm.arm.neon.vst1.v4f32(i8*, <4 x float>) nounwind + +declare <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float>, <4 x float>) nounwind readnone diff --git a/test/CodeGen/Thumb2/sign_extend_inreg.ll b/test/CodeGen/Thumb2/sign_extend_inreg.ll new file mode 100644 index 0000000..9a02c1c --- /dev/null +++ b/test/CodeGen/Thumb2/sign_extend_inreg.ll @@ -0,0 +1,22 @@ +; RUN: llc < %s -mcpu=cortex-a8 | FileCheck %s -check-prefix=CHECK-A8 +; RUN: llc < %s -mcpu=cortex-m3 | FileCheck %s -check-prefix=CHECK-M3 + +target triple = "thumbv7-apple-darwin10" + +define arm_apcscc i32 @f1(i16* %ptr) nounwind { +; CHECK-A8: f1 +; CHECK-A8: sxth +; CHECK-M3: f1 +; CHECK-M3-NOT: sxth +; CHECK-M3: bx lr + %1 = load i16* %ptr + %2 = icmp eq i16 %1, 1 + %3 = sext i16 %1 to i32 + br i1 %2, label %.next, label %.exit + +.next: + br label %.exit + +.exit: + ret i32 %3 +} diff --git a/test/CodeGen/Thumb2/thumb2-pack.ll b/test/CodeGen/Thumb2/thumb2-pack.ll index a982249..c8302df 100644 --- a/test/CodeGen/Thumb2/thumb2-pack.ll +++ b/test/CodeGen/Thumb2/thumb2-pack.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | \ +; RUN: llc < %s -march=thumb -mattr=+thumb2,+t2xtpk | \ ; RUN: grep pkhbt | count 5 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | \ +; RUN: llc < %s -march=thumb -mattr=+thumb2,+t2xtpk | \ ; RUN: grep pkhtb | count 4 define i32 @test1(i32 %X, i32 %Y) { diff --git a/test/CodeGen/Thumb2/thumb2-rev.ll b/test/CodeGen/Thumb2/thumb2-rev.ll index 27b1672..2cee2e3 100644 --- a/test/CodeGen/Thumb2/thumb2-rev.ll +++ b/test/CodeGen/Thumb2/thumb2-rev.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2,+v7a | FileCheck %s +; RUN: llc < %s -march=thumb -mattr=+thumb2,+v7a,+t2xtpk | FileCheck %s define i32 @f1(i32 %a) { ; CHECK: f1: diff --git a/test/CodeGen/Thumb2/thumb2-shifter.ll b/test/CodeGen/Thumb2/thumb2-shifter.ll index b106ced..98854a1 100644 --- a/test/CodeGen/Thumb2/thumb2-shifter.ll +++ b/test/CodeGen/Thumb2/thumb2-shifter.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s +; RUN: llc < %s -march=thumb -mattr=+thumb2,+t2xtpk | FileCheck %s define i32 @t2ADDrs_lsl(i32 %X, i32 %Y) { ; CHECK: t2ADDrs_lsl diff --git a/test/CodeGen/Thumb2/thumb2-smla.ll b/test/CodeGen/Thumb2/thumb2-smla.ll index 092ec27..bd4dcbe 100644 --- a/test/CodeGen/Thumb2/thumb2-smla.ll +++ b/test/CodeGen/Thumb2/thumb2-smla.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s +; RUN: llc < %s -march=thumb -mattr=+thumb2,+t2xtpk | FileCheck %s define i32 @f3(i32 %a, i16 %x, i32 %y) { ; CHECK: f3 diff --git a/test/CodeGen/Thumb2/thumb2-smul.ll b/test/CodeGen/Thumb2/thumb2-smul.ll index 16ea85d..ae17535 100644 --- a/test/CodeGen/Thumb2/thumb2-smul.ll +++ b/test/CodeGen/Thumb2/thumb2-smul.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s +; RUN: llc < %s -march=thumb -mattr=+thumb2,+t2xtpk | FileCheck %s @x = weak global i16 0 ; <i16*> [#uses=1] @y = weak global i16 0 ; <i16*> [#uses=0] diff --git a/test/CodeGen/Thumb2/thumb2-spill-q.ll b/test/CodeGen/Thumb2/thumb2-spill-q.ll index ff178b4..bf9c052 100644 --- a/test/CodeGen/Thumb2/thumb2-spill-q.ll +++ b/test/CodeGen/Thumb2/thumb2-spill-q.ll @@ -46,7 +46,8 @@ bb4: ; preds = %bb193, %entry %20 = shufflevector <2 x float> %19, <2 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1] %21 = fadd <4 x float> zeroinitializer, %20 ; <<4 x float>> [#uses=2] %22 = fcmp ogt <4 x float> %besterror.0.2264, %21 ; <<4 x i1>> [#uses=0] - br i1 undef, label %bb193, label %bb186 + %tmp = extractelement <4 x i1> %22, i32 0 + br i1 %tmp, label %bb193, label %bb186 bb186: ; preds = %bb4 br label %bb193 diff --git a/test/CodeGen/Thumb2/thumb2-sxt_rot.ll b/test/CodeGen/Thumb2/thumb2-sxt_rot.ll index 054d5df..4b685a8 100644 --- a/test/CodeGen/Thumb2/thumb2-sxt_rot.ll +++ b/test/CodeGen/Thumb2/thumb2-sxt_rot.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s +; RUN: llc < %s -march=thumb -mattr=+thumb2,+t2xtpk | FileCheck %s define i32 @test0(i8 %A) { ; CHECK: test0 diff --git a/test/CodeGen/Thumb2/thumb2-uxt_rot.ll b/test/CodeGen/Thumb2/thumb2-uxt_rot.ll index 75e1d70..b8e4381 100644 --- a/test/CodeGen/Thumb2/thumb2-uxt_rot.ll +++ b/test/CodeGen/Thumb2/thumb2-uxt_rot.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s +; RUN: llc < %s -march=thumb -mattr=+thumb2,+t2xtpk | FileCheck %s define i8 @test1(i32 %A.u) zeroext { ; CHECK: test1 diff --git a/test/CodeGen/Thumb2/thumb2-uxtb.ll b/test/CodeGen/Thumb2/thumb2-uxtb.ll index 91598cd..5411914 100644 --- a/test/CodeGen/Thumb2/thumb2-uxtb.ll +++ b/test/CodeGen/Thumb2/thumb2-uxtb.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s +; RUN: llc < %s -march=thumb -mattr=+thumb2,+t2xtpk | FileCheck %s define i32 @test1(i32 %x) { ; CHECK: test1 diff --git a/test/CodeGen/X86/2008-01-16-FPStackifierAssert.ll b/test/CodeGen/X86/2008-01-16-FPStackifierAssert.ll index d795610..8aabb52 100644 --- a/test/CodeGen/X86/2008-01-16-FPStackifierAssert.ll +++ b/test/CodeGen/X86/2008-01-16-FPStackifierAssert.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -march=x86 -mattr=+sse2 -regalloc=local +; RUN: llc < %s -march=x86 -mattr=+sse2 -regalloc=fast define void @SolveCubic(double %a, double %b, double %c, double %d, i32* %solutions, double* %x) { entry: diff --git a/test/CodeGen/X86/2008-02-22-LocalRegAllocBug.ll b/test/CodeGen/X86/2008-02-22-LocalRegAllocBug.ll index 6b1eefe..d294885 100644 --- a/test/CodeGen/X86/2008-02-22-LocalRegAllocBug.ll +++ b/test/CodeGen/X86/2008-02-22-LocalRegAllocBug.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -regalloc=local -march=x86 -mattr=+mmx | grep esi +; RUN: llc < %s -regalloc=fast -march=x86 -mattr=+mmx | grep esi ; PR2082 ; Local register allocator was refusing to use ESI, EDI, and EBP so it ran out of ; registers. diff --git a/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll b/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll index 2aea9c5..716563b 100644 --- a/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll +++ b/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll @@ -1,5 +1,6 @@ ; RUN: llc < %s -mtriple=x86_64-apple-darwin ; RUN: llc < %s -mtriple=x86_64-apple-darwin -relocation-model=pic -disable-fp-elim -O0 -regalloc=local +; RUN: llc < %s -mtriple=x86_64-apple-darwin -relocation-model=pic -disable-fp-elim -O0 -regalloc=fast ; PR5534 %struct.CGPoint = type { double, double } diff --git a/test/CodeGen/X86/2008-05-28-LocalRegAllocBug.ll b/test/CodeGen/X86/2008-05-28-LocalRegAllocBug.ll index f1a19ec..5929aff 100644 --- a/test/CodeGen/X86/2008-05-28-LocalRegAllocBug.ll +++ b/test/CodeGen/X86/2008-05-28-LocalRegAllocBug.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -mtriple=i386-apple-darwin -regalloc=local +; RUN: llc < %s -mtriple=i386-apple-darwin -regalloc=fast @_ZTVN10Evaluation10GridOutputILi3EEE = external constant [5 x i32 (...)*] ; <[5 x i32 (...)*]*> [#uses=1] diff --git a/test/CodeGen/X86/2008-09-17-inline-asm-1.ll b/test/CodeGen/X86/2008-09-17-inline-asm-1.ll index 74429c3..dd83336 100644 --- a/test/CodeGen/X86/2008-09-17-inline-asm-1.ll +++ b/test/CodeGen/X86/2008-09-17-inline-asm-1.ll @@ -1,18 +1,19 @@ -; RUN: llc < %s -march=x86 | not grep "movl %eax, %eax" -; RUN: llc < %s -march=x86 | not grep "movl %edx, %edx" -; RUN: llc < %s -march=x86 | not grep "movl (%eax), %eax" -; RUN: llc < %s -march=x86 | not grep "movl (%edx), %edx" -; RUN: llc < %s -march=x86 -regalloc=local | not grep "movl %eax, %eax" -; RUN: llc < %s -march=x86 -regalloc=local | not grep "movl %edx, %edx" -; RUN: llc < %s -march=x86 -regalloc=local | not grep "movl (%eax), %eax" -; RUN: llc < %s -march=x86 -regalloc=local | not grep "movl (%edx), %edx" +; RUN: llc < %s -march=x86 | FileCheck %s +; RUN: llc < %s -march=x86 -regalloc=local | FileCheck %s +; RUN: llc < %s -march=x86 -regalloc=fast | FileCheck %s ; %0 must not be put in EAX or EDX. ; In the first asm, $0 and $2 must not be put in EAX. +; CHECK: InlineAsm Start +; CHECK-NOT: movl %eax, %eax +; CHECK-NOT: movl (%eax), %eax +; CHECK: InlineAsm End ; In the second asm, $0 and $2 must not be put in EDX. -; This is kind of hard to test thoroughly, but the things above should continue -; to pass, I think. -; ModuleID = '<stdin>' +; CHECK: InlineAsm Start +; CHECK-NOT: movl %edx, %edx +; CHECK-NOT: movl (%edx), %edx +; CHECK: InlineAsm End + target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target triple = "i386-apple-darwin8" @x = common global i32 0 ; <i32*> [#uses=1] diff --git a/test/CodeGen/X86/2008-09-18-inline-asm-2.ll b/test/CodeGen/X86/2008-09-18-inline-asm-2.ll index e3b6fdf..4400940 100644 --- a/test/CodeGen/X86/2008-09-18-inline-asm-2.ll +++ b/test/CodeGen/X86/2008-09-18-inline-asm-2.ll @@ -1,5 +1,7 @@ ; RUN: llc < %s -march=x86 | grep "#%ebp %esi %edi 8(%edx) %eax (%ebx)" ; RUN: llc < %s -march=x86 -regalloc=local | grep "#%edi %ebp %edx 8(%ebx) %eax (%esi)" +; RUN: llc < %s -march=x86 -regalloc=fast | grep "#%edi %ebp %edx 8(%ebx) %eax (%esi)" + ; The 1st, 2nd, 3rd and 5th registers above must all be different. The registers ; referenced in the 4th and 6th operands must not be the same as the 1st or 5th ; operand. There are many combinations that work; this is what llc puts out now. diff --git a/test/CodeGen/X86/2009-01-29-LocalRegAllocBug.ll b/test/CodeGen/X86/2009-01-29-LocalRegAllocBug.ll index ce3ea82..21b43fb 100644 --- a/test/CodeGen/X86/2009-01-29-LocalRegAllocBug.ll +++ b/test/CodeGen/X86/2009-01-29-LocalRegAllocBug.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -mtriple=i386-apple-darwin9.6 -regalloc=local -disable-fp-elim +; RUN: llc < %s -mtriple=i386-apple-darwin9.6 -regalloc=fast -disable-fp-elim ; rdar://6538384 %struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 } diff --git a/test/CodeGen/X86/2009-04-14-IllegalRegs.ll b/test/CodeGen/X86/2009-04-14-IllegalRegs.ll index bfa3eaa..e5d46f9 100644 --- a/test/CodeGen/X86/2009-04-14-IllegalRegs.ll +++ b/test/CodeGen/X86/2009-04-14-IllegalRegs.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -mtriple=i386-apple-darwin -O0 -regalloc=local | not grep sil +; RUN: llc < %s -mtriple=i386-apple-darwin -O0 -regalloc=fast | not grep sil ; rdar://6787136 %struct.X = type { i8, [32 x i8] } diff --git a/test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll b/test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll index e6f3008..c598228 100644 --- a/test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll +++ b/test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s | grep "subq.*\\\$40, \\\%rsp" -target triple = "x86_64-mingw64" +target triple = "x86_64-pc-mingw64" define x86_fp80 @a(i64 %x) nounwind readnone { entry: diff --git a/test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll b/test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll index cb64bf2..810a6f4 100644 --- a/test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll +++ b/test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll @@ -2,7 +2,7 @@ ; RUN: grep "subq.*\\\$72, \\\%rsp" %t1 ; RUN: grep "movaps \\\%xmm8, 32\\\(\\\%rsp\\\)" %t1 ; RUN: grep "movaps \\\%xmm7, 48\\\(\\\%rsp\\\)" %t1 -target triple = "x86_64-mingw64" +target triple = "x86_64-pc-mingw64" define i32 @a() nounwind { entry: diff --git a/test/CodeGen/X86/2009-08-08-CastError.ll b/test/CodeGen/X86/2009-08-08-CastError.ll index 9456d91..2dc812d 100644 --- a/test/CodeGen/X86/2009-08-08-CastError.ll +++ b/test/CodeGen/X86/2009-08-08-CastError.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-mingw64 | grep movabsq +; RUN: llc < %s -mtriple=x86_64-pc-mingw64 | grep movabsq target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" diff --git a/test/CodeGen/X86/2010-04-30-LocalAlloc-LandingPad.ll b/test/CodeGen/X86/2010-04-30-LocalAlloc-LandingPad.ll index f5048af..4c95179 100644 --- a/test/CodeGen/X86/2010-04-30-LocalAlloc-LandingPad.ll +++ b/test/CodeGen/X86/2010-04-30-LocalAlloc-LandingPad.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -O0 -regalloc=local -relocation-model=pic -disable-fp-elim | FileCheck %s +; RUN: llc < %s -O0 -regalloc=fast -relocation-model=pic -disable-fp-elim | FileCheck %s target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32" target triple = "i386-apple-darwin10.0.0" diff --git a/test/CodeGen/X86/2010-05-05-LocalAllocEarlyClobber.ll b/test/CodeGen/X86/2010-05-05-LocalAllocEarlyClobber.ll new file mode 100644 index 0000000..375f424 --- /dev/null +++ b/test/CodeGen/X86/2010-05-05-LocalAllocEarlyClobber.ll @@ -0,0 +1,33 @@ +; RUN-XFAIL: llc < %s -O0 -regalloc=local | FileCheck %s +; RUN: llc < %s -O0 -regalloc=fast | FileCheck %s +; PR6520 + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32" +target triple = "i386-apple-darwin10.0.0" + +%0 = type { i8*, i8*, i32 } + +define i8* @func() nounwind ssp { +entry: + %retval = alloca i8*, align 4 ; <i8**> [#uses=2] + %ret = alloca i8*, align 4 ; <i8**> [#uses=2] + %p = alloca i8*, align 4 ; <i8**> [#uses=1] + %t = alloca i32, align 4 ; <i32*> [#uses=1] +; The earlyclobber $1 should only appear once. It should not be shared. +; CHECK: deafbeef, [[REG:%e.x]] +; CHECK-NOT: [[REG]] +; CHECK: InlineAsm End + %0 = call %0 asm "mov $$0xdeafbeef, $1\0A\09mov $$0xcafebabe, $0\0A\09mov $0, $2\0A\09", "=&r,=&r,=&{cx},~{dirflag},~{fpsr},~{flags}"() nounwind, !srcloc !0 ; <%0> [#uses=3] + %asmresult = extractvalue %0 %0, 0 ; <i8*> [#uses=1] + %asmresult1 = extractvalue %0 %0, 1 ; <i8*> [#uses=1] + %asmresult2 = extractvalue %0 %0, 2 ; <i32> [#uses=1] + store i8* %asmresult, i8** %ret + store i8* %asmresult1, i8** %p + store i32 %asmresult2, i32* %t + %tmp = load i8** %ret ; <i8*> [#uses=1] + store i8* %tmp, i8** %retval + %1 = load i8** %retval ; <i8*> [#uses=1] + ret i8* %1 +} + +!0 = metadata !{i32 79} diff --git a/test/CodeGen/X86/2010-05-06-LocalInlineAsmClobber.ll b/test/CodeGen/X86/2010-05-06-LocalInlineAsmClobber.ll new file mode 100644 index 0000000..e554f9f --- /dev/null +++ b/test/CodeGen/X86/2010-05-06-LocalInlineAsmClobber.ll @@ -0,0 +1,11 @@ +; RUN: llc -regalloc=local %s -o %t +; RUN: llc -regalloc=fast %s -o %t +; PR7066 + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-unknown-linux-gnu" + +define i32 @sys_clone(i32 (i8*)* %fn, i8* %child_stack, i32 %flags, i8* %arg, i32* %parent_tidptr, i8* %newtls, i32* %child_tidptr) nounwind { + call i64 asm sideeffect "", "={ax},0,i,i,r,{si},{di},r,{dx},imr,imr,~{sp},~{memory},~{r8},~{r10},~{r11},~{cx},~{dirflag},~{fpsr},~{flags}"(i64 4294967274, i32 56, i32 60, i32 (i8*)* undef, i8* undef, i32 undef, i8* undef, i32* undef, i8* undef, i32* undef) nounwind ; <i64> [#uses=0] + ret i32 undef +} diff --git a/test/CodeGen/X86/2010-05-07-ldconvert.ll b/test/CodeGen/X86/2010-05-07-ldconvert.ll new file mode 100644 index 0000000..0ba6a8f --- /dev/null +++ b/test/CodeGen/X86/2010-05-07-ldconvert.ll @@ -0,0 +1,27 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin11 +; PR 7087 - used to crash + +define i32 @main() ssp { +entry: + %retval = alloca i32, align 4 ; <i32*> [#uses=2] + %r = alloca i32, align 4 ; <i32*> [#uses=2] + store i32 0, i32* %retval + %tmp = call x86_fp80 @llvm.powi.f80(x86_fp80 0xK3FFF8000000000000000, i32 -64) ; <x86_fp80> [#uses=1] + %conv = fptosi x86_fp80 %tmp to i32 ; <i32> [#uses=1] + store i32 %conv, i32* %r + %tmp1 = load i32* %r ; <i32> [#uses=1] + %tobool = icmp ne i32 %tmp1, 0 ; <i1> [#uses=1] + br i1 %tobool, label %if.then, label %if.end + +if.then: ; preds = %entry + call void @_Z1fv() + br label %if.end + +if.end: ; preds = %if.then, %entry + %0 = load i32* %retval ; <i32> [#uses=1] + ret i32 %0 +} + +declare x86_fp80 @llvm.powi.f80(x86_fp80, i32) nounwind readonly + +declare void @_Z1fv() diff --git a/test/CodeGen/X86/2010-05-10-DAGCombinerBug.ll b/test/CodeGen/X86/2010-05-10-DAGCombinerBug.ll new file mode 100644 index 0000000..e719da3 --- /dev/null +++ b/test/CodeGen/X86/2010-05-10-DAGCombinerBug.ll @@ -0,0 +1,11 @@ +; RUN: llc < %s -mtriple=i386-apple-darwin10 +; PR7018 +; rdar://7939869 + +define i32 @CXB30130(i32 %num1, i16* nocapture %num2, float* nocapture %num3, double* nocapture %num4) nounwind ssp { +entry: + %0 = load i16* %num2, align 2 ; <i16> [#uses=2] + %1 = mul nsw i16 %0, %0 ; <i16> [#uses=1] + store i16 %1, i16* %num2, align 2 + ret i32 undef +} diff --git a/test/CodeGen/X86/2010-05-12-FastAllocKills.ll b/test/CodeGen/X86/2010-05-12-FastAllocKills.ll new file mode 100644 index 0000000..36a99d6 --- /dev/null +++ b/test/CodeGen/X86/2010-05-12-FastAllocKills.ll @@ -0,0 +1,59 @@ +; RUN: llc -regalloc=fast -verify-machineinstrs < %s +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin" + +; This test causes a virtual FP register to be redefined while it is live: +;BB#5: derived from LLVM BB %bb10 +; Predecessors according to CFG: BB#4 BB#5 +; %reg1024<def> = MOV_Fp8080 %reg1034 +; %reg1025<def> = MUL_Fp80m32 %reg1024, %RIP, 1, %reg0, <cp#0>, %reg0; mem:LD4[ConstantPool] +; %reg1034<def> = MOV_Fp8080 %reg1025 +; FP_REG_KILL %FP0<imp-def>, %FP1<imp-def>, %FP2<imp-def>, %FP3<imp-def>, %FP4<imp-def>, %FP5<imp-def>, %FP6<imp-def> +; JMP_4 <BB#5> +; Successors according to CFG: BB#5 +; +; The X86FP pass needs good kill flags, like on %FP0 representing %reg1034: +;BB#5: derived from LLVM BB %bb10 +; Predecessors according to CFG: BB#4 BB#5 +; %FP0<def> = LD_Fp80m <fi#3>, 1, %reg0, 0, %reg0; mem:LD10[FixedStack3](align=4) +; %FP1<def> = MOV_Fp8080 %FP0<kill> +; %FP2<def> = MUL_Fp80m32 %FP1, %RIP, 1, %reg0, <cp#0>, %reg0; mem:LD4[ConstantPool] +; %FP0<def> = MOV_Fp8080 %FP2 +; ST_FpP80m <fi#3>, 1, %reg0, 0, %reg0, %FP0<kill>; mem:ST10[FixedStack3](align=4) +; ST_FpP80m <fi#4>, 1, %reg0, 0, %reg0, %FP1<kill>; mem:ST10[FixedStack4](align=4) +; ST_FpP80m <fi#5>, 1, %reg0, 0, %reg0, %FP2<kill>; mem:ST10[FixedStack5](align=4) +; FP_REG_KILL %FP0<imp-def>, %FP1<imp-def>, %FP2<imp-def>, %FP3<imp-def>, %FP4<imp-def>, %FP5<imp-def>, %FP6<imp-def> +; JMP_4 <BB#5> +; Successors according to CFG: BB#5 + +define fastcc i32 @sqlite3AtoF(i8* %z, double* nocapture %pResult) nounwind ssp { +entry: + br i1 undef, label %bb2, label %bb1.i.i + +bb1.i.i: ; preds = %entry + unreachable + +bb2: ; preds = %entry + br i1 undef, label %isdigit339.exit11.preheader, label %bb13 + +isdigit339.exit11.preheader: ; preds = %bb2 + br i1 undef, label %bb12, label %bb10 + +bb10: ; preds = %bb10, %isdigit339.exit11.preheader + %divisor.041 = phi x86_fp80 [ %0, %bb10 ], [ 0xK3FFF8000000000000000, %isdigit339.exit11.preheader ] ; <x86_fp80> [#uses=1] + %0 = fmul x86_fp80 %divisor.041, 0xK4002A000000000000000 ; <x86_fp80> [#uses=2] + br i1 false, label %bb12, label %bb10 + +bb12: ; preds = %bb10, %isdigit339.exit11.preheader + %divisor.0.lcssa = phi x86_fp80 [ 0xK3FFF8000000000000000, %isdigit339.exit11.preheader ], [ %0, %bb10 ] ; <x86_fp80> [#uses=0] + br label %bb13 + +bb13: ; preds = %bb12, %bb2 + br i1 undef, label %bb34, label %bb36 + +bb34: ; preds = %bb13 + br label %bb36 + +bb36: ; preds = %bb34, %bb13 + ret i32 undef +} diff --git a/test/CodeGen/X86/2010-05-16-nosseconversion.ll b/test/CodeGen/X86/2010-05-16-nosseconversion.ll new file mode 100644 index 0000000..889575c --- /dev/null +++ b/test/CodeGen/X86/2010-05-16-nosseconversion.ll @@ -0,0 +1,12 @@ +; RUN: llc -mtriple=x86_64-apple-darwin -mattr=-sse < %s +; PR 7135 + +@x = common global i64 0 ; <i64*> [#uses=1] + +define i32 @foo() nounwind readonly ssp { +entry: + %0 = load i64* @x, align 8 ; <i64> [#uses=1] + %1 = uitofp i64 %0 to double ; <double> [#uses=1] + %2 = fptosi double %1 to i32 ; <i32> [#uses=1] + ret i32 %2 +} diff --git a/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll b/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll new file mode 100644 index 0000000..13f72a9 --- /dev/null +++ b/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll @@ -0,0 +1,66 @@ +; RUN: llc -O2 < %s | FileCheck %s +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin" + +%struct.a = type { i32, %struct.a* } + +@llvm.used = appending global [1 x i8*] [i8* bitcast (i8* (%struct.a*)* @bar to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] + +define i8* @bar(%struct.a* %myvar) nounwind optsize noinline ssp { +entry: + tail call void @llvm.dbg.value(metadata !{%struct.a* %myvar}, i64 0, metadata !8) + %0 = getelementptr inbounds %struct.a* %myvar, i64 0, i32 0, !dbg !28 ; <i32*> [#uses=1] + %1 = load i32* %0, align 8, !dbg !28 ; <i32> [#uses=1] + tail call void @foo(i32 %1) nounwind optsize noinline ssp, !dbg !28 + %2 = bitcast %struct.a* %myvar to i8*, !dbg !30 ; <i8*> [#uses=1] + ret i8* %2, !dbg !30 +} + +declare void @foo(i32) nounwind optsize noinline ssp + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone + +!llvm.dbg.gv = !{!0} +!llvm.dbg.lv = !{!4, !8, !18, !25, !26} + +!0 = metadata !{i32 524340, i32 0, metadata !1, metadata !"ret", metadata !"ret", metadata !"", metadata !1, i32 7, metadata !3, i1 false, i1 true, null} ; [ DW_TAG_variable ] +!1 = metadata !{i32 524329, metadata !"foo.c", metadata !"/tmp/", metadata !2} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 524305, i32 0, i32 1, metadata !"foo.c", metadata !"/tmp/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 524324, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!4 = metadata !{i32 524545, metadata !5, metadata !"x", metadata !1, i32 12, metadata !3} ; [ DW_TAG_arg_variable ] +!5 = metadata !{i32 524334, i32 0, metadata !1, metadata !"foo", metadata !"foo", metadata !"foo", metadata !1, i32 13, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true} ; [ DW_TAG_subprogram ] +!6 = metadata !{i32 524309, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, null} ; [ DW_TAG_subroutine_type ] +!7 = metadata !{null, metadata !3} +!8 = metadata !{i32 524545, metadata !9, metadata !"myvar", metadata !1, i32 17, metadata !13} ; [ DW_TAG_arg_variable ] +!9 = metadata !{i32 524334, i32 0, metadata !1, metadata !"bar", metadata !"bar", metadata !"bar", metadata !1, i32 17, metadata !10, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true} ; [ DW_TAG_subprogram ] +!10 = metadata !{i32 524309, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !11, i32 0, null} ; [ DW_TAG_subroutine_type ] +!11 = metadata !{metadata !12, metadata !13} +!12 = metadata !{i32 524303, metadata !1, metadata !"", metadata !1, i32 0, i64 64, i64 64, i64 0, i32 0, null} ; [ DW_TAG_pointer_type ] +!13 = metadata !{i32 524303, metadata !1, metadata !"", metadata !1, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !14} ; [ DW_TAG_pointer_type ] +!14 = metadata !{i32 524307, metadata !1, metadata !"a", metadata !1, i32 2, i64 128, i64 64, i64 0, i32 0, null, metadata !15, i32 0, null} ; [ DW_TAG_structure_type ] +!15 = metadata !{metadata !16, metadata !17} +!16 = metadata !{i32 524301, metadata !14, metadata !"c", metadata !1, i32 3, i64 32, i64 32, i64 0, i32 0, metadata !3} ; [ DW_TAG_member ] +!17 = metadata !{i32 524301, metadata !14, metadata !"d", metadata !1, i32 4, i64 64, i64 64, i64 64, i32 0, metadata !13} ; [ DW_TAG_member ] +!18 = metadata !{i32 524545, metadata !19, metadata !"argc", metadata !1, i32 22, metadata !3} ; [ DW_TAG_arg_variable ] +!19 = metadata !{i32 524334, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"main", metadata !1, i32 22, metadata !20, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true} ; [ DW_TAG_subprogram ] +!20 = metadata !{i32 524309, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !21, i32 0, null} ; [ DW_TAG_subroutine_type ] +!21 = metadata !{metadata !3, metadata !3, metadata !22} +!22 = metadata !{i32 524303, metadata !1, metadata !"", metadata !1, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !23} ; [ DW_TAG_pointer_type ] +!23 = metadata !{i32 524303, metadata !1, metadata !"", metadata !1, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !24} ; [ DW_TAG_pointer_type ] +!24 = metadata !{i32 524324, metadata !1, metadata !"char", metadata !1, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ] +!25 = metadata !{i32 524545, metadata !19, metadata !"argv", metadata !1, i32 22, metadata !22} ; [ DW_TAG_arg_variable ] +!26 = metadata !{i32 524544, metadata !27, metadata !"e", metadata !1, i32 23, metadata !14} ; [ DW_TAG_auto_variable ] +!27 = metadata !{i32 524299, metadata !19, i32 22, i32 0} ; [ DW_TAG_lexical_block ] +!28 = metadata !{i32 18, i32 0, metadata !29, null} +!29 = metadata !{i32 524299, metadata !9, i32 17, i32 0} ; [ DW_TAG_lexical_block ] +!30 = metadata !{i32 19, i32 0, metadata !29, null} + +; CHECK: Ldebug_loc0: +; CHECK-NEXT: .quad Lfunc_begin0 +; CHECK-NEXT: .quad Ltmp3 +; CHECK-NEXT: .short 1 +; CHECK-NEXT: .byte 85 +; CHECK-NEXT: .quad Ltmp3 +; CHECK-NEXT: .quad Lfunc_end +; CHECK-NEXT: .short 1 +; CHECK-NEXT: .byte 83 diff --git a/test/CodeGen/X86/2010-05-26-FP_TO_INT-crash.ll b/test/CodeGen/X86/2010-05-26-FP_TO_INT-crash.ll new file mode 100644 index 0000000..38dcb80 --- /dev/null +++ b/test/CodeGen/X86/2010-05-26-FP_TO_INT-crash.ll @@ -0,0 +1,16 @@ +; RUN: llc -O0 -mcpu=i386 -mattr=-sse,-mmx < %s +; ModuleID = '<stdin>' +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32" +target triple = "i386-pc-linux-gnu" + +module asm "\09.ident\09\22GCC: (GNU) 4.5.1 20100510 (prerelease) LLVM: 104604:104605\22" + +define i32 @f2(double %x) nounwind { +entry: + %0 = load double* undef, align 64 ; <double> [#uses=1] + %1 = fptoui double %0 to i16 ; <i16> [#uses=1] + %2 = zext i16 %1 to i32 ; <i32> [#uses=1] + %3 = add nsw i32 0, %2 ; <i32> [#uses=1] + store i32 %3, i32* undef, align 1 + ret i32 0 +} diff --git a/test/CodeGen/X86/call-imm.ll b/test/CodeGen/X86/call-imm.ll index 87785bc..255adfb 100644 --- a/test/CodeGen/X86/call-imm.ll +++ b/test/CodeGen/X86/call-imm.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -mtriple=i386-darwin-apple -relocation-model=static | grep {call.*12345678} -; RUN: llc < %s -mtriple=i386-darwin-apple -relocation-model=pic | not grep {call.*12345678} +; RUN: llc < %s -mtriple=i386-apple-darwin -relocation-model=static | grep {call.*12345678} +; RUN: llc < %s -mtriple=i386-apple-darwin -relocation-model=pic | not grep {call.*12345678} ; RUN: llc < %s -mtriple=i386-pc-linux -relocation-model=dynamic-no-pic | grep {call.*12345678} ; Call to immediate is not safe on x86-64 unless we *know* that the diff --git a/test/CodeGen/X86/fast-cc-callee-pops.ll b/test/CodeGen/X86/fast-cc-callee-pops.ll index 5e88ed7..ea10897 100644 --- a/test/CodeGen/X86/fast-cc-callee-pops.ll +++ b/test/CodeGen/X86/fast-cc-callee-pops.ll @@ -1,7 +1,13 @@ -; RUN: llc < %s -march=x86 -x86-asm-syntax=intel -mcpu=yonah | grep {ret 20} +; RUN: llc < %s -march=x86 -x86-asm-syntax=intel -mcpu=yonah | FileCheck %s ; Check that a fastcc function pops its stack variables before returning. define x86_fastcallcc void @func(i64 %X, i64 %Y, float %G, double %Z) nounwind { ret void +; CHECK: ret{{.*}}20 +} + +define x86_thiscallcc void @func2(i32 %X, i64 %Y, float %G, double %Z) nounwind { + ret void +; CHECK: ret{{.*}}20 } diff --git a/test/CodeGen/X86/fast-cc-pass-in-regs.ll b/test/CodeGen/X86/fast-cc-pass-in-regs.ll index fe96c0c..a96e504 100644 --- a/test/CodeGen/X86/fast-cc-pass-in-regs.ll +++ b/test/CodeGen/X86/fast-cc-pass-in-regs.ll @@ -1,15 +1,29 @@ -; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | \ -; RUN: grep {mov EDX, 1} +; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | FileCheck %s ; check that fastcc is passing stuff in regs. declare x86_fastcallcc i64 @callee(i64) define i64 @caller() { %X = call x86_fastcallcc i64 @callee( i64 4294967299 ) ; <i64> [#uses=1] +; CHECK: mov{{.*}}EDX, 1 ret i64 %X } define x86_fastcallcc i64 @caller2(i64 %X) { ret i64 %X +; CHECK: mov{{.*}}EAX, ECX +} + +declare x86_thiscallcc i64 @callee2(i32) + +define i64 @caller3() { + %X = call x86_thiscallcc i64 @callee2( i32 3 ) +; CHECK: mov{{.*}}ECX, 3 + ret i64 %X +} + +define x86_thiscallcc i32 @caller4(i32 %X) { + ret i32 %X +; CHECK: mov{{.*}}EAX, ECX } diff --git a/test/CodeGen/X86/fp-stack-O0-crash.ll b/test/CodeGen/X86/fp-stack-O0-crash.ll index 4768ea2..bbadca5 100644 --- a/test/CodeGen/X86/fp-stack-O0-crash.ll +++ b/test/CodeGen/X86/fp-stack-O0-crash.ll @@ -1,4 +1,5 @@ ; RUN: llc %s -O0 -fast-isel -regalloc=local -o - +; RUN: llc %s -O0 -fast-isel -regalloc=fast -o - ; PR4767 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" diff --git a/test/CodeGen/X86/fp-stack.ll b/test/CodeGen/X86/fp-stack.ll new file mode 100644 index 0000000..dca644d --- /dev/null +++ b/test/CodeGen/X86/fp-stack.ll @@ -0,0 +1,25 @@ +; RUN: llc %s -o - -mcpu=pentium +; PR6828 +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32" +target triple = "i386-pc-linux-gnu" + +define void @foo() nounwind { +entry: + %tmp6 = load x86_fp80* undef ; <x86_fp80> [#uses=2] + %tmp15 = load x86_fp80* undef ; <x86_fp80> [#uses=2] + %tmp24 = load x86_fp80* undef ; <x86_fp80> [#uses=1] + br i1 undef, label %return, label %bb.nph + +bb.nph: ; preds = %entry + %cmp139 = fcmp ogt x86_fp80 %tmp15, %tmp6 ; <i1> [#uses=1] + %maxdiag.0 = select i1 %cmp139, x86_fp80 %tmp15, x86_fp80 %tmp6 ; <x86_fp80> [#uses=1] + %cmp139.1 = fcmp ogt x86_fp80 %tmp24, %maxdiag.0 ; <i1> [#uses=1] + br i1 %cmp139.1, label %sw.bb372, label %return + +sw.bb372: ; preds = %for.end + ret void + +return: ; preds = %for.end + ret void +} + diff --git a/test/CodeGen/X86/label-redefinition.ll b/test/CodeGen/X86/label-redefinition.ll new file mode 100644 index 0000000..9ad33e0 --- /dev/null +++ b/test/CodeGen/X86/label-redefinition.ll @@ -0,0 +1,15 @@ +; PR7054 +; RUN: not llc %s -o - |& grep {'_foo' label emitted multiple times to assembly} +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32" +target triple = "i386-apple-darwin10.0.0" + +define i32 @"\01_foo"() { + unreachable +} + +define i32 @foo() { +entry: + unreachable +} + +declare i32 @xstat64(i32, i8*, i8*) diff --git a/test/CodeGen/X86/liveness-local-regalloc.ll b/test/CodeGen/X86/liveness-local-regalloc.ll index 17e65d8..8cac3f8 100644 --- a/test/CodeGen/X86/liveness-local-regalloc.ll +++ b/test/CodeGen/X86/liveness-local-regalloc.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -O3 -regalloc=local -mtriple=x86_64-apple-darwin10 +; RUN: llc < %s -O3 -regalloc=fast -mtriple=x86_64-apple-darwin10 ; <rdar://problem/7755473> %0 = type { i32, i8*, i8*, %1*, i8*, i64, i64, i32, i32, i32, i32, [1024 x i8] } diff --git a/test/CodeGen/X86/lsr-delayed-fold.ll b/test/CodeGen/X86/lsr-delayed-fold.ll index 17d6a4c..8afbb0d 100644 --- a/test/CodeGen/X86/lsr-delayed-fold.ll +++ b/test/CodeGen/X86/lsr-delayed-fold.ll @@ -49,3 +49,86 @@ lbl_264: ; preds = %if.end, %lbl_264.pr %tobool12 = icmp eq i8 %mul.i18, 0 ; <i1> [#uses=1] unreachable } + +; LSR ends up going into conservative pruning mode; don't prune the solution +; so far that it becomes unsolvable though. +; PR7077 + +%struct.Bu = type { i32, i32, i32 } + +define void @_Z3fooP2Bui(%struct.Bu* nocapture %bu) { +entry: + br label %for.body + +for.body: ; preds = %for.inc131, %entry + %indvar = phi i64 [ %indvar.next, %for.inc131 ], [ 0, %entry ] ; <i64> [#uses=3] + br i1 undef, label %for.inc131, label %lor.lhs.false + +lor.lhs.false: ; preds = %for.body + %tmp15 = add i64 %indvar, 1 ; <i64> [#uses=1] + %tmp17 = add i64 %indvar, 2 ; <i64> [#uses=1] + %tmp19 = add i64 %indvar, 3 ; <i64> [#uses=1] + %tmp21 = add i64 %indvar, 4 ; <i64> [#uses=1] + %tmp23 = add i64 %indvar, 5 ; <i64> [#uses=1] + %tmp25 = add i64 %indvar, 6 ; <i64> [#uses=1] + %tmp27 = add i64 %indvar, 7 ; <i64> [#uses=1] + %tmp29 = add i64 %indvar, 8 ; <i64> [#uses=1] + %tmp31 = add i64 %indvar, 9 ; <i64> [#uses=1] + %tmp35 = add i64 %indvar, 11 ; <i64> [#uses=1] + %tmp37 = add i64 %indvar, 12 ; <i64> [#uses=1] + %tmp39 = add i64 %indvar, 13 ; <i64> [#uses=1] + %tmp41 = add i64 %indvar, 14 ; <i64> [#uses=1] + %tmp43 = add i64 %indvar, 15 ; <i64> [#uses=1] + %tmp45 = add i64 %indvar, 16 ; <i64> [#uses=1] + %tmp47 = add i64 %indvar, 17 ; <i64> [#uses=1] + %mul = trunc i64 %indvar to i32 ; <i32> [#uses=1] + %add22 = trunc i64 %tmp15 to i32 ; <i32> [#uses=1] + %add28 = trunc i64 %tmp17 to i32 ; <i32> [#uses=1] + %add34 = trunc i64 %tmp19 to i32 ; <i32> [#uses=1] + %add40 = trunc i64 %tmp21 to i32 ; <i32> [#uses=1] + %add46 = trunc i64 %tmp23 to i32 ; <i32> [#uses=1] + %add52 = trunc i64 %tmp25 to i32 ; <i32> [#uses=1] + %add58 = trunc i64 %tmp27 to i32 ; <i32> [#uses=1] + %add64 = trunc i64 %tmp29 to i32 ; <i32> [#uses=1] + %add70 = trunc i64 %tmp31 to i32 ; <i32> [#uses=1] + %add82 = trunc i64 %tmp35 to i32 ; <i32> [#uses=1] + %add88 = trunc i64 %tmp37 to i32 ; <i32> [#uses=1] + %add94 = trunc i64 %tmp39 to i32 ; <i32> [#uses=1] + %add100 = trunc i64 %tmp41 to i32 ; <i32> [#uses=1] + %add106 = trunc i64 %tmp43 to i32 ; <i32> [#uses=1] + %add112 = trunc i64 %tmp45 to i32 ; <i32> [#uses=1] + %add118 = trunc i64 %tmp47 to i32 ; <i32> [#uses=1] + %tmp10 = getelementptr %struct.Bu* %bu, i64 %indvar, i32 2 ; <i32*> [#uses=1] + %tmp11 = load i32* %tmp10 ; <i32> [#uses=0] + tail call void undef(i32 %add22) + tail call void undef(i32 %add28) + tail call void undef(i32 %add34) + tail call void undef(i32 %add40) + tail call void undef(i32 %add46) + tail call void undef(i32 %add52) + tail call void undef(i32 %add58) + tail call void undef(i32 %add64) + tail call void undef(i32 %add70) + tail call void undef(i32 %add82) + tail call void undef(i32 %add88) + tail call void undef(i32 %add94) + tail call void undef(i32 %add100) + tail call void undef(i32 %add106) + tail call void undef(i32 %add112) + tail call void undef(i32 %add118) + br label %for.body123 + +for.body123: ; preds = %for.body123, %lor.lhs.false + %j.03 = phi i32 [ 0, %lor.lhs.false ], [ %inc, %for.body123 ] ; <i32> [#uses=2] + %add129 = add i32 %mul, %j.03 ; <i32> [#uses=1] + tail call void undef(i32 %add129) + %inc = add nsw i32 %j.03, 1 ; <i32> [#uses=1] + br i1 undef, label %for.inc131, label %for.body123 + +for.inc131: ; preds = %for.body123, %for.body + %indvar.next = add i64 %indvar, 1 ; <i64> [#uses=1] + br i1 undef, label %for.end134, label %for.body + +for.end134: ; preds = %for.inc131 + ret void +} diff --git a/test/CodeGen/X86/mcinst-lowering-cmp0.ll b/test/CodeGen/X86/mcinst-lowering-cmp0.ll new file mode 100644 index 0000000..756be1f --- /dev/null +++ b/test/CodeGen/X86/mcinst-lowering-cmp0.ll @@ -0,0 +1,68 @@ +; RUN: llc --show-mc-encoding -relocation-model=pic -disable-fp-elim -O3 < %s | FileCheck %s + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32" +target triple = "i386-apple-darwin10.0.0" + +%struct.NSConstantString = type { i32*, i32, i8*, i32 } +%struct._objc_module = type { i32, i32, i8*, %struct._objc_symtab* } +%struct._objc_symtab = type { i32, i8*, i16, i16, [0 x i8*] } + +@"\01L_OBJC_IMAGE_INFO" = internal constant [2 x i32] [i32 0, i32 16], section "__OBJC, __image_info,regular" ; <[2 x i32]*> [#uses=1] +@"\01L_OBJC_METH_VAR_NAME_" = internal global [4 x i8] c"foo\00", section "__TEXT,__cstring,cstring_literals", align 1 ; <[4 x i8]*> [#uses=1] +@"\01L_OBJC_SELECTOR_REFERENCES_" = internal global i8* getelementptr inbounds ([4 x i8]* @"\01L_OBJC_METH_VAR_NAME_", i32 0, i32 0), section "__OBJC,__message_refs,literal_pointers,no_dead_strip", align 4 ; <i8**> [#uses=3] +@__CFConstantStringClassReference = external global [0 x i32] ; <[0 x i32]*> [#uses=1] +@.str = private constant [3 x i8] c"||\00" ; <[3 x i8]*> [#uses=1] +@_unnamed_cfstring_ = private constant %struct.NSConstantString { i32* getelementptr inbounds ([0 x i32]* @__CFConstantStringClassReference, i32 0, i32 0), i32 1992, i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0), i32 2 }, section "__DATA,__cfstring" ; <%struct.NSConstantString*> [#uses=1] +@"\01L_OBJC_METH_VAR_NAME_1" = internal global [5 x i8] c"baz:\00", section "__TEXT,__cstring,cstring_literals", align 1 ; <[5 x i8]*> [#uses=1] +@"\01L_OBJC_SELECTOR_REFERENCES_2" = internal global i8* getelementptr inbounds ([5 x i8]* @"\01L_OBJC_METH_VAR_NAME_1", i32 0, i32 0), section "__OBJC,__message_refs,literal_pointers,no_dead_strip", align 4 ; <i8**> [#uses=2] +@"\01L_OBJC_METH_VAR_NAME_3" = internal global [4 x i8] c"bar\00", section "__TEXT,__cstring,cstring_literals", align 1 ; <[4 x i8]*> [#uses=1] +@"\01L_OBJC_SELECTOR_REFERENCES_4" = internal global i8* getelementptr inbounds ([4 x i8]* @"\01L_OBJC_METH_VAR_NAME_3", i32 0, i32 0), section "__OBJC,__message_refs,literal_pointers,no_dead_strip", align 4 ; <i8**> [#uses=2] +@"\01L_OBJC_CLASS_NAME_" = internal global [1 x i8] zeroinitializer, section "__TEXT,__cstring,cstring_literals", align 1 ; <[1 x i8]*> [#uses=1] +@"\01L_OBJC_MODULES" = internal global %struct._objc_module { i32 7, i32 16, i8* getelementptr inbounds ([1 x i8]* @"\01L_OBJC_CLASS_NAME_", i32 0, i32 0), %struct._objc_symtab* null }, section "__OBJC,__module_info,regular,no_dead_strip", align 4 ; <%struct._objc_module*> [#uses=1] +@llvm.used = appending global [9 x i8*] [i8* bitcast ([2 x i32]* @"\01L_OBJC_IMAGE_INFO" to i8*), i8* getelementptr inbounds ([4 x i8]* @"\01L_OBJC_METH_VAR_NAME_", i32 0, i32 0), i8* bitcast (i8** @"\01L_OBJC_SELECTOR_REFERENCES_" to i8*), i8* getelementptr inbounds ([5 x i8]* @"\01L_OBJC_METH_VAR_NAME_1", i32 0, i32 0), i8* bitcast (i8** @"\01L_OBJC_SELECTOR_REFERENCES_2" to i8*), i8* getelementptr inbounds ([4 x i8]* @"\01L_OBJC_METH_VAR_NAME_3", i32 0, i32 0), i8* bitcast (i8** @"\01L_OBJC_SELECTOR_REFERENCES_4" to i8*), i8* getelementptr inbounds ([1 x i8]* @"\01L_OBJC_CLASS_NAME_", i32 0, i32 0), i8* bitcast (%struct._objc_module* @"\01L_OBJC_MODULES" to i8*)], section "llvm.metadata" ; <[9 x i8*]*> [#uses=0] + +define void @f0(i8* nocapture %a, i8* nocapture %b) nounwind optsize ssp { +entry: + %call = tail call i32 (...)* @get_name() nounwind optsize ; <i32> [#uses=2] + %conv = inttoptr i32 %call to i8* ; <i8*> [#uses=1] + %call1 = tail call i32 (...)* @get_dict() nounwind optsize ; <i32> [#uses=2] + %conv2 = inttoptr i32 %call1 to i8* ; <i8*> [#uses=2] + +; Check that we lower to the short form of cmpl, which has an 8-bit immediate. +; +; CHECK: cmpl $0, -16(%ebp) ## 4-byte Folded Reload +; CHECK: ## encoding: [0x83,0x7d,0xf0,0x00] +; rdar://7999130 + %cmp = icmp eq i32 %call1, 0 ; <i1> [#uses=1] + br i1 %cmp, label %if.end, label %if.then + +if.then: ; preds = %entry + %tmp5 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_" ; <i8*> [#uses=1] + %call6 = tail call i8* (i8*, i8*, ...)* @objc_msgSend(i8* %conv2, i8* %tmp5) nounwind optsize ; <i8*> [#uses=1] + %tmp7 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_2" ; <i8*> [#uses=1] + %call820 = tail call i8* (i8*, i8*, ...)* @objc_msgSend(i8* %call6, i8* %tmp7, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring_ to i8*)) nounwind optsize ; <i8*> [#uses=0] + br label %if.end + +if.end: ; preds = %entry, %if.then + %tmp10 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_" ; <i8*> [#uses=1] + %call11 = tail call i8* (i8*, i8*, ...)* @objc_msgSend(i8* %conv2, i8* %tmp10) nounwind optsize ; <i8*> [#uses=1] + %tmp12 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_4" ; <i8*> [#uses=1] + %call13 = tail call i8* (i8*, i8*, ...)* @objc_msgSend(i8* %call11, i8* %tmp12) nounwind optsize ; <i8*> [#uses=0] + %cmp15 = icmp eq i32 %call, 0 ; <i1> [#uses=1] + br i1 %cmp15, label %if.end19, label %if.then17 + +if.then17: ; preds = %if.end + tail call void (...)* @f1(i8* %conv) nounwind optsize + ret void + +if.end19: ; preds = %if.end + ret void +} + +declare i32 @get_name(...) optsize + +declare i32 @get_dict(...) optsize + +declare i8* @objc_msgSend(i8*, i8*, ...) + +declare void @f1(...) optsize diff --git a/test/CodeGen/X86/mcinst-lowering.ll b/test/CodeGen/X86/mcinst-lowering.ll new file mode 100644 index 0000000..1ef5a97 --- /dev/null +++ b/test/CodeGen/X86/mcinst-lowering.ll @@ -0,0 +1,26 @@ +; RUN: llc --show-mc-encoding < %s | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin10.0.0" + +define i32 @f0(i32* nocapture %x) nounwind readonly ssp { +entry: + %tmp1 = load i32* %x ; <i32> [#uses=2] + %tobool = icmp eq i32 %tmp1, 0 ; <i1> [#uses=1] + br i1 %tobool, label %if.end, label %return + +if.end: ; preds = %entry + +; Check that we lower to the short form of cmpl, which has a fixed %eax +; register. +; +; CHECK: cmpl $16777216, %eax +; CHECK: # encoding: [0x3d,0x00,0x00,0x00,0x01] + %cmp = icmp eq i32 %tmp1, 16777216 ; <i1> [#uses=1] + + %conv = zext i1 %cmp to i32 ; <i32> [#uses=1] + ret i32 %conv + +return: ; preds = %entry + ret i32 0 +} diff --git a/test/CodeGen/X86/sse-align-11.ll b/test/CodeGen/X86/sse-align-11.ll index aa1b437..3cc83ca 100644 --- a/test/CodeGen/X86/sse-align-11.ll +++ b/test/CodeGen/X86/sse-align-11.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=x86 -mcpu=yonah -mtriple=i686-apple-darwin8 | grep movaps -; RUN: llc < %s -march=x86 -mcpu=yonah -mtriple=linux | grep movups +; RUN: llc < %s -march=x86 -mcpu=yonah -mtriple=i686-linux-gnu | grep movups define <4 x float> @foo(float %a, float %b, float %c, float %d) nounwind { entry: diff --git a/test/CodeGen/X86/stack-color-with-reg-2.ll b/test/CodeGen/X86/stack-color-with-reg-2.ll deleted file mode 100644 index c1f2672..0000000 --- a/test/CodeGen/X86/stack-color-with-reg-2.ll +++ /dev/null @@ -1,230 +0,0 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin10 -relocation-model=pic -disable-fp-elim -color-ss-with-regs | grep {movl\[\[:space:\]\]%eax, %ebx} - - %"struct..0$_67" = type { i32, %"struct.llvm::MachineOperand"**, %"struct.llvm::MachineOperand"* } - %"struct..1$_69" = type { i32 } - %"struct.llvm::AbstractTypeUser" = type { i32 (...)** } - %"struct.llvm::AliasAnalysis" = type opaque - %"struct.llvm::AnalysisResolver" = type { %"struct.std::vector<std::pair<const llvm::PassInfo*, llvm::Pass*>,std::allocator<std::pair<const llvm::PassInfo*, llvm::Pass*> > >", %"struct.llvm::PMDataManager"* } - %"struct.llvm::Annotable" = type { %"struct.llvm::Annotation"* } - %"struct.llvm::Annotation" = type { i32 (...)**, %"struct..1$_69", %"struct.llvm::Annotation"* } - %"struct.llvm::Argument" = type { %"struct.llvm::Value", %"struct.llvm::ilist_node<llvm::Argument>", %"struct.llvm::Function"* } - %"struct.llvm::AttrListPtr" = type { %"struct.llvm::AttributeListImpl"* } - %"struct.llvm::AttributeListImpl" = type opaque - %"struct.llvm::BasicBlock" = type { %"struct.llvm::Value", %"struct.llvm::ilist_node<llvm::BasicBlock>", %"struct.llvm::iplist<llvm::Instruction,llvm::ilist_traits<llvm::Instruction> >", %"struct.llvm::Function"* } - %"struct.llvm::BitVector" = type { i32*, i32, i32 } - %"struct.llvm::BumpPtrAllocator" = type { i8* } - %"struct.llvm::CalleeSavedInfo" = type { i32, %"struct.llvm::TargetRegisterClass"*, i32 } - %"struct.llvm::Constant" = type { %"struct.llvm::User" } - %"struct.llvm::DebugLocTracker" = type { %"struct.std::vector<llvm::DebugLocTuple,std::allocator<llvm::DebugLocTuple> >", %"struct.llvm::DenseMap<llvm::DebugLocTuple,unsigned int,llvm::DenseMapInfo<llvm::DebugLocTuple>,llvm::DenseMapInfo<unsigned int> >" } - %"struct.llvm::DebugLocTuple" = type { %"struct.llvm::GlobalVariable"*, i32, i32 } - %"struct.llvm::DenseMap<llvm::DebugLocTuple,unsigned int,llvm::DenseMapInfo<llvm::DebugLocTuple>,llvm::DenseMapInfo<unsigned int> >" = type { i32, %"struct.std::pair<llvm::DebugLocTuple,unsigned int>"*, i32, i32 } - %"struct.llvm::DenseMap<llvm::MachineInstr*,unsigned int,llvm::DenseMapInfo<llvm::MachineInstr*>,llvm::DenseMapInfo<unsigned int> >" = type { i32, %"struct.std::pair<llvm::MachineInstr*,unsigned int>"*, i32, i32 } - %"struct.llvm::DenseMap<unsigned int,char,llvm::DenseMapInfo<unsigned int>,llvm::DenseMapInfo<char> >" = type { i32, %"struct.std::pair<unsigned int,char>"*, i32, i32 } - %"struct.llvm::DenseMap<unsigned int,llvm::LiveInterval*,llvm::DenseMapInfo<unsigned int>,llvm::DenseMapInfo<llvm::LiveInterval*> >" = type { i32, %"struct.std::pair<unsigned int,llvm::LiveInterval*>"*, i32, i32 } - %"struct.llvm::DenseSet<unsigned int,llvm::DenseMapInfo<unsigned int> >" = type { %"struct.llvm::DenseMap<unsigned int,char,llvm::DenseMapInfo<unsigned int>,llvm::DenseMapInfo<char> >" } - %"struct.llvm::Function" = type { %"struct.llvm::GlobalValue", %"struct.llvm::Annotable", %"struct.llvm::ilist_node<llvm::Function>", %"struct.llvm::iplist<llvm::BasicBlock,llvm::ilist_traits<llvm::BasicBlock> >", %"struct.llvm::iplist<llvm::Argument,llvm::ilist_traits<llvm::Argument> >", %"struct.llvm::ValueSymbolTable"*, %"struct.llvm::AttrListPtr" } - %"struct.llvm::FunctionPass" = type { %"struct.llvm::Pass" } - %"struct.llvm::GlobalValue" = type { %"struct.llvm::Constant", %"struct.llvm::Module"*, i32, %"struct.std::string" } - %"struct.llvm::GlobalVariable" = type opaque - %"struct.llvm::Instruction" = type { %"struct.llvm::User", %"struct.llvm::ilist_node<llvm::Instruction>", %"struct.llvm::BasicBlock"* } - %"struct.llvm::LiveInterval" = type <{ i32, float, i16, [6 x i8], %"struct.llvm::SmallVector<llvm::LiveRange,4u>", %"struct.llvm::SmallVector<llvm::MachineBasicBlock*,4u>" }> - %"struct.llvm::LiveIntervals" = type { %"struct.llvm::MachineFunctionPass", %"struct.llvm::MachineFunction"*, %"struct.llvm::MachineRegisterInfo"*, %"struct.llvm::TargetMachine"*, %"struct.llvm::TargetRegisterInfo"*, %"struct.llvm::TargetInstrInfo"*, %"struct.llvm::AliasAnalysis"*, %"struct.llvm::LiveVariables"*, %"struct.llvm::BumpPtrAllocator", %"struct.std::vector<std::pair<unsigned int, unsigned int>,std::allocator<std::pair<unsigned int, unsigned int> > >", %"struct.std::vector<std::pair<unsigned int, llvm::MachineBasicBlock*>,std::allocator<std::pair<unsigned int, llvm::MachineBasicBlock*> > >", i64, %"struct.llvm::DenseMap<llvm::MachineInstr*,unsigned int,llvm::DenseMapInfo<llvm::MachineInstr*>,llvm::DenseMapInfo<unsigned int> >", %"struct.std::vector<llvm::MachineInstr*,std::allocator<llvm::MachineInstr*> >", %"struct.llvm::DenseMap<unsigned int,llvm::LiveInterval*,llvm::DenseMapInfo<unsigned int>,llvm::DenseMapInfo<llvm::LiveInterval*> >", %"struct.llvm::BitVector", %"struct.std::vector<llvm::MachineInstr*,std::allocator<llvm::MachineInstr*> >" } - %"struct.llvm::LiveVariables" = type opaque - %"struct.llvm::MVT" = type { %"struct..1$_69" } - %"struct.llvm::MachineBasicBlock" = type { %"struct.llvm::ilist_node<llvm::MachineBasicBlock>", %"struct.llvm::ilist<llvm::MachineInstr>", %"struct.llvm::BasicBlock"*, i32, %"struct.llvm::MachineFunction"*, %"struct.std::vector<llvm::MachineBasicBlock*,std::allocator<llvm::MachineBasicBlock*> >", %"struct.std::vector<llvm::MachineBasicBlock*,std::allocator<llvm::MachineBasicBlock*> >", %"struct.std::vector<int,std::allocator<int> >", i32, i8 } - %"struct.llvm::MachineConstantPool" = type opaque - %"struct.llvm::MachineFrameInfo" = type { %"struct.std::vector<llvm::MachineFrameInfo::StackObject,std::allocator<llvm::MachineFrameInfo::StackObject> >", i32, i8, i8, i64, i32, i32, i8, i32, i32, %"struct.std::vector<llvm::CalleeSavedInfo,std::allocator<llvm::CalleeSavedInfo> >", %"struct.llvm::MachineModuleInfo"*, %"struct.llvm::TargetFrameInfo"* } - %"struct.llvm::MachineFrameInfo::StackObject" = type { i64, i32, i8, i64 } - %"struct.llvm::MachineFunction" = type { %"struct.llvm::Annotation", %"struct.llvm::Function"*, %"struct.llvm::TargetMachine"*, %"struct.llvm::MachineRegisterInfo"*, %"struct.llvm::AbstractTypeUser"*, %"struct.llvm::MachineFrameInfo"*, %"struct.llvm::MachineConstantPool"*, %"struct.llvm::MachineJumpTableInfo"*, %"struct.std::vector<llvm::MachineBasicBlock*,std::allocator<llvm::MachineBasicBlock*> >", %"struct.llvm::BumpPtrAllocator", %"struct.llvm::Recycler<llvm::MachineBasicBlock,80ul,4ul>", %"struct.llvm::Recycler<llvm::MachineBasicBlock,80ul,4ul>", %"struct.llvm::ilist<llvm::MachineBasicBlock>", %"struct..1$_69", %"struct.llvm::DebugLocTracker" } - %"struct.llvm::MachineFunctionPass" = type { %"struct.llvm::FunctionPass" } - %"struct.llvm::MachineInstr" = type { %"struct.llvm::ilist_node<llvm::MachineInstr>", %"struct.llvm::TargetInstrDesc"*, i16, %"struct.std::vector<llvm::MachineOperand,std::allocator<llvm::MachineOperand> >", %"struct.std::list<llvm::MachineMemOperand,std::allocator<llvm::MachineMemOperand> >", %"struct.llvm::MachineBasicBlock"*, %"struct..1$_69" } - %"struct.llvm::MachineJumpTableInfo" = type opaque - %"struct.llvm::MachineModuleInfo" = type opaque - %"struct.llvm::MachineOperand" = type { i8, i8, i8, %"struct.llvm::MachineInstr"*, %"struct.llvm::MachineOperand::$_66" } - %"struct.llvm::MachineOperand::$_66" = type { %"struct..0$_67" } - %"struct.llvm::MachineRegisterInfo" = type { %"struct.std::vector<std::pair<const llvm::TargetRegisterClass*, llvm::MachineOperand*>,std::allocator<std::pair<const llvm::TargetRegisterClass*, llvm::MachineOperand*> > >", %"struct.std::vector<std::vector<unsigned int, std::allocator<unsigned int> >,std::allocator<std::vector<unsigned int, std::allocator<unsigned int> > > >", %"struct.llvm::MachineOperand"**, %"struct.llvm::BitVector", %"struct.std::vector<std::pair<unsigned int, unsigned int>,std::allocator<std::pair<unsigned int, unsigned int> > >", %"struct.std::vector<int,std::allocator<int> >" } - %"struct.llvm::Module" = type opaque - %"struct.llvm::PATypeHandle" = type { %"struct.llvm::Type"*, %"struct.llvm::AbstractTypeUser"* } - %"struct.llvm::PATypeHolder" = type { %"struct.llvm::Type"* } - %"struct.llvm::PMDataManager" = type opaque - %"struct.llvm::Pass" = type { i32 (...)**, %"struct.llvm::AnalysisResolver"*, i32 } - %"struct.llvm::PassInfo" = type { i8*, i8*, i32, i8, i8, i8, %"struct.std::vector<const llvm::PassInfo*,std::allocator<const llvm::PassInfo*> >", %"struct.llvm::Pass"* ()* } - %"struct.llvm::Recycler<llvm::MachineBasicBlock,80ul,4ul>" = type { %"struct.llvm::iplist<llvm::RecyclerStruct,llvm::ilist_traits<llvm::RecyclerStruct> >" } - %"struct.llvm::RecyclerStruct" = type { %"struct.llvm::RecyclerStruct"*, %"struct.llvm::RecyclerStruct"* } - %"struct.llvm::SmallVector<llvm::LiveRange,4u>" = type <{ [17 x i8], [47 x i8] }> - %"struct.llvm::SmallVector<llvm::MachineBasicBlock*,4u>" = type <{ [17 x i8], [15 x i8] }> - %"struct.llvm::TargetAsmInfo" = type opaque - %"struct.llvm::TargetFrameInfo" = type opaque - %"struct.llvm::TargetInstrDesc" = type { i16, i16, i16, i16, i8*, i32, i32, i32*, i32*, %"struct.llvm::TargetRegisterClass"**, %"struct.llvm::TargetOperandInfo"* } - %"struct.llvm::TargetInstrInfo" = type { i32 (...)**, %"struct.llvm::TargetInstrDesc"*, i32 } - %"struct.llvm::TargetMachine" = type { i32 (...)**, %"struct.llvm::TargetAsmInfo"* } - %"struct.llvm::TargetOperandInfo" = type { i16, i16, i32 } - %"struct.llvm::TargetRegisterClass" = type { i32 (...)**, i32, i8*, %"struct.llvm::MVT"*, %"struct.llvm::TargetRegisterClass"**, %"struct.llvm::TargetRegisterClass"**, %"struct.llvm::TargetRegisterClass"**, %"struct.llvm::TargetRegisterClass"**, i32, i32, i32, i32*, i32*, %"struct.llvm::DenseSet<unsigned int,llvm::DenseMapInfo<unsigned int> >" } - %"struct.llvm::TargetRegisterDesc" = type { i8*, i8*, i32*, i32*, i32* } - %"struct.llvm::TargetRegisterInfo" = type { i32 (...)**, i32*, i32, i32*, i32, i32*, i32, %"struct.llvm::TargetRegisterDesc"*, i32, %"struct.llvm::TargetRegisterClass"**, %"struct.llvm::TargetRegisterClass"**, i32, i32 } - %"struct.llvm::Type" = type { %"struct.llvm::AbstractTypeUser", i8, [3 x i8], i32, %"struct.llvm::Type"*, %"struct.std::vector<llvm::AbstractTypeUser*,std::allocator<llvm::AbstractTypeUser*> >", i32, %"struct.llvm::PATypeHandle"* } - %"struct.llvm::Use" = type { %"struct.llvm::Value"*, %"struct.llvm::Use"*, %"struct..1$_69" } - %"struct.llvm::User" = type { %"struct.llvm::Value", %"struct.llvm::Use"*, i32 } - %"struct.llvm::Value" = type { i32 (...)**, i8, i8, i16, %"struct.llvm::PATypeHolder", %"struct.llvm::Use"*, %"struct.llvm::ValueName"* } - %"struct.llvm::ValueName" = type opaque - %"struct.llvm::ValueSymbolTable" = type opaque - %"struct.llvm::ilist<llvm::MachineBasicBlock>" = type { %"struct.llvm::iplist<llvm::MachineBasicBlock,llvm::ilist_traits<llvm::MachineBasicBlock> >" } - %"struct.llvm::ilist<llvm::MachineInstr>" = type { %"struct.llvm::iplist<llvm::MachineInstr,llvm::ilist_traits<llvm::MachineInstr> >" } - %"struct.llvm::ilist_node<llvm::Argument>" = type { %"struct.llvm::Argument"*, %"struct.llvm::Argument"* } - %"struct.llvm::ilist_node<llvm::BasicBlock>" = type { %"struct.llvm::BasicBlock"*, %"struct.llvm::BasicBlock"* } - %"struct.llvm::ilist_node<llvm::Function>" = type { %"struct.llvm::Function"*, %"struct.llvm::Function"* } - %"struct.llvm::ilist_node<llvm::Instruction>" = type { %"struct.llvm::Instruction"*, %"struct.llvm::Instruction"* } - %"struct.llvm::ilist_node<llvm::MachineBasicBlock>" = type { %"struct.llvm::MachineBasicBlock"*, %"struct.llvm::MachineBasicBlock"* } - %"struct.llvm::ilist_node<llvm::MachineInstr>" = type { %"struct.llvm::MachineInstr"*, %"struct.llvm::MachineInstr"* } - %"struct.llvm::ilist_traits<llvm::Argument>" = type { %"struct.llvm::ilist_node<llvm::Argument>" } - %"struct.llvm::ilist_traits<llvm::BasicBlock>" = type { %"struct.llvm::ilist_node<llvm::BasicBlock>" } - %"struct.llvm::ilist_traits<llvm::Instruction>" = type { %"struct.llvm::ilist_node<llvm::Instruction>" } - %"struct.llvm::ilist_traits<llvm::MachineBasicBlock>" = type { %"struct.llvm::ilist_node<llvm::MachineBasicBlock>" } - %"struct.llvm::ilist_traits<llvm::MachineInstr>" = type { %"struct.llvm::ilist_node<llvm::MachineInstr>", %"struct.llvm::MachineBasicBlock"* } - %"struct.llvm::ilist_traits<llvm::RecyclerStruct>" = type { %"struct.llvm::RecyclerStruct" } - %"struct.llvm::iplist<llvm::Argument,llvm::ilist_traits<llvm::Argument> >" = type { %"struct.llvm::ilist_traits<llvm::Argument>", %"struct.llvm::Argument"* } - %"struct.llvm::iplist<llvm::BasicBlock,llvm::ilist_traits<llvm::BasicBlock> >" = type { %"struct.llvm::ilist_traits<llvm::BasicBlock>", %"struct.llvm::BasicBlock"* } - %"struct.llvm::iplist<llvm::Instruction,llvm::ilist_traits<llvm::Instruction> >" = type { %"struct.llvm::ilist_traits<llvm::Instruction>", %"struct.llvm::Instruction"* } - %"struct.llvm::iplist<llvm::MachineBasicBlock,llvm::ilist_traits<llvm::MachineBasicBlock> >" = type { %"struct.llvm::ilist_traits<llvm::MachineBasicBlock>", %"struct.llvm::MachineBasicBlock"* } - %"struct.llvm::iplist<llvm::MachineInstr,llvm::ilist_traits<llvm::MachineInstr> >" = type { %"struct.llvm::ilist_traits<llvm::MachineInstr>", %"struct.llvm::MachineInstr"* } - %"struct.llvm::iplist<llvm::RecyclerStruct,llvm::ilist_traits<llvm::RecyclerStruct> >" = type { %"struct.llvm::ilist_traits<llvm::RecyclerStruct>", %"struct.llvm::RecyclerStruct"* } - %"struct.std::IdxMBBPair" = type { i32, %"struct.llvm::MachineBasicBlock"* } - %"struct.std::_List_base<llvm::MachineMemOperand,std::allocator<llvm::MachineMemOperand> >" = type { %"struct.llvm::ilist_traits<llvm::RecyclerStruct>" } - %"struct.std::_Vector_base<const llvm::PassInfo*,std::allocator<const llvm::PassInfo*> >" = type { %"struct.std::_Vector_base<const llvm::PassInfo*,std::allocator<const llvm::PassInfo*> >::_Vector_impl" } - %"struct.std::_Vector_base<const llvm::PassInfo*,std::allocator<const llvm::PassInfo*> >::_Vector_impl" = type { %"struct.llvm::PassInfo"**, %"struct.llvm::PassInfo"**, %"struct.llvm::PassInfo"** } - %"struct.std::_Vector_base<int,std::allocator<int> >" = type { %"struct.std::_Vector_base<int,std::allocator<int> >::_Vector_impl" } - %"struct.std::_Vector_base<int,std::allocator<int> >::_Vector_impl" = type { i32*, i32*, i32* } - %"struct.std::_Vector_base<llvm::AbstractTypeUser*,std::allocator<llvm::AbstractTypeUser*> >" = type { %"struct.std::_Vector_base<llvm::AbstractTypeUser*,std::allocator<llvm::AbstractTypeUser*> >::_Vector_impl" } - %"struct.std::_Vector_base<llvm::AbstractTypeUser*,std::allocator<llvm::AbstractTypeUser*> >::_Vector_impl" = type { %"struct.llvm::AbstractTypeUser"**, %"struct.llvm::AbstractTypeUser"**, %"struct.llvm::AbstractTypeUser"** } - %"struct.std::_Vector_base<llvm::CalleeSavedInfo,std::allocator<llvm::CalleeSavedInfo> >" = type { %"struct.std::_Vector_base<llvm::CalleeSavedInfo,std::allocator<llvm::CalleeSavedInfo> >::_Vector_impl" } - %"struct.std::_Vector_base<llvm::CalleeSavedInfo,std::allocator<llvm::CalleeSavedInfo> >::_Vector_impl" = type { %"struct.llvm::CalleeSavedInfo"*, %"struct.llvm::CalleeSavedInfo"*, %"struct.llvm::CalleeSavedInfo"* } - %"struct.std::_Vector_base<llvm::DebugLocTuple,std::allocator<llvm::DebugLocTuple> >" = type { %"struct.std::_Vector_base<llvm::DebugLocTuple,std::allocator<llvm::DebugLocTuple> >::_Vector_impl" } - %"struct.std::_Vector_base<llvm::DebugLocTuple,std::allocator<llvm::DebugLocTuple> >::_Vector_impl" = type { %"struct.llvm::DebugLocTuple"*, %"struct.llvm::DebugLocTuple"*, %"struct.llvm::DebugLocTuple"* } - %"struct.std::_Vector_base<llvm::MachineBasicBlock*,std::allocator<llvm::MachineBasicBlock*> >" = type { %"struct.std::_Vector_base<llvm::MachineBasicBlock*,std::allocator<llvm::MachineBasicBlock*> >::_Vector_impl" } - %"struct.std::_Vector_base<llvm::MachineBasicBlock*,std::allocator<llvm::MachineBasicBlock*> >::_Vector_impl" = type { %"struct.llvm::MachineBasicBlock"**, %"struct.llvm::MachineBasicBlock"**, %"struct.llvm::MachineBasicBlock"** } - %"struct.std::_Vector_base<llvm::MachineFrameInfo::StackObject,std::allocator<llvm::MachineFrameInfo::StackObject> >" = type { %"struct.std::_Vector_base<llvm::MachineFrameInfo::StackObject,std::allocator<llvm::MachineFrameInfo::StackObject> >::_Vector_impl" } - %"struct.std::_Vector_base<llvm::MachineFrameInfo::StackObject,std::allocator<llvm::MachineFrameInfo::StackObject> >::_Vector_impl" = type { %"struct.llvm::MachineFrameInfo::StackObject"*, %"struct.llvm::MachineFrameInfo::StackObject"*, %"struct.llvm::MachineFrameInfo::StackObject"* } - %"struct.std::_Vector_base<llvm::MachineInstr*,std::allocator<llvm::MachineInstr*> >" = type { %"struct.std::_Vector_base<llvm::MachineInstr*,std::allocator<llvm::MachineInstr*> >::_Vector_impl" } - %"struct.std::_Vector_base<llvm::MachineInstr*,std::allocator<llvm::MachineInstr*> >::_Vector_impl" = type { %"struct.llvm::MachineInstr"**, %"struct.llvm::MachineInstr"**, %"struct.llvm::MachineInstr"** } - %"struct.std::_Vector_base<llvm::MachineOperand,std::allocator<llvm::MachineOperand> >" = type { %"struct.std::_Vector_base<llvm::MachineOperand,std::allocator<llvm::MachineOperand> >::_Vector_impl" } - %"struct.std::_Vector_base<llvm::MachineOperand,std::allocator<llvm::MachineOperand> >::_Vector_impl" = type { %"struct.llvm::MachineOperand"*, %"struct.llvm::MachineOperand"*, %"struct.llvm::MachineOperand"* } - %"struct.std::_Vector_base<std::pair<const llvm::PassInfo*, llvm::Pass*>,std::allocator<std::pair<const llvm::PassInfo*, llvm::Pass*> > >" = type { %"struct.std::_Vector_base<std::pair<const llvm::PassInfo*, llvm::Pass*>,std::allocator<std::pair<const llvm::PassInfo*, llvm::Pass*> > >::_Vector_impl" } - %"struct.std::_Vector_base<std::pair<const llvm::PassInfo*, llvm::Pass*>,std::allocator<std::pair<const llvm::PassInfo*, llvm::Pass*> > >::_Vector_impl" = type { %"struct.std::pair<const llvm::PassInfo*,llvm::Pass*>"*, %"struct.std::pair<const llvm::PassInfo*,llvm::Pass*>"*, %"struct.std::pair<const llvm::PassInfo*,llvm::Pass*>"* } - %"struct.std::_Vector_base<std::pair<const llvm::TargetRegisterClass*, llvm::MachineOperand*>,std::allocator<std::pair<const llvm::TargetRegisterClass*, llvm::MachineOperand*> > >" = type { %"struct.std::_Vector_base<std::pair<const llvm::TargetRegisterClass*, llvm::MachineOperand*>,std::allocator<std::pair<const llvm::TargetRegisterClass*, llvm::MachineOperand*> > >::_Vector_impl" } - %"struct.std::_Vector_base<std::pair<const llvm::TargetRegisterClass*, llvm::MachineOperand*>,std::allocator<std::pair<const llvm::TargetRegisterClass*, llvm::MachineOperand*> > >::_Vector_impl" = type { %"struct.std::pair<const llvm::TargetRegisterClass*,llvm::MachineOperand*>"*, %"struct.std::pair<const llvm::TargetRegisterClass*,llvm::MachineOperand*>"*, %"struct.std::pair<const llvm::TargetRegisterClass*,llvm::MachineOperand*>"* } - %"struct.std::_Vector_base<std::pair<unsigned int, llvm::MachineBasicBlock*>,std::allocator<std::pair<unsigned int, llvm::MachineBasicBlock*> > >" = type { %"struct.std::_Vector_base<std::pair<unsigned int, llvm::MachineBasicBlock*>,std::allocator<std::pair<unsigned int, llvm::MachineBasicBlock*> > >::_Vector_impl" } - %"struct.std::_Vector_base<std::pair<unsigned int, llvm::MachineBasicBlock*>,std::allocator<std::pair<unsigned int, llvm::MachineBasicBlock*> > >::_Vector_impl" = type { %"struct.std::IdxMBBPair"*, %"struct.std::IdxMBBPair"*, %"struct.std::IdxMBBPair"* } - %"struct.std::_Vector_base<std::pair<unsigned int, unsigned int>,std::allocator<std::pair<unsigned int, unsigned int> > >" = type { %"struct.std::_Vector_base<std::pair<unsigned int, unsigned int>,std::allocator<std::pair<unsigned int, unsigned int> > >::_Vector_impl" } - %"struct.std::_Vector_base<std::pair<unsigned int, unsigned int>,std::allocator<std::pair<unsigned int, unsigned int> > >::_Vector_impl" = type { %"struct.std::pair<unsigned int,int>"*, %"struct.std::pair<unsigned int,int>"*, %"struct.std::pair<unsigned int,int>"* } - %"struct.std::_Vector_base<std::vector<unsigned int, std::allocator<unsigned int> >,std::allocator<std::vector<unsigned int, std::allocator<unsigned int> > > >" = type { %"struct.std::_Vector_base<std::vector<unsigned int, std::allocator<unsigned int> >,std::allocator<std::vector<unsigned int, std::allocator<unsigned int> > > >::_Vector_impl" } - %"struct.std::_Vector_base<std::vector<unsigned int, std::allocator<unsigned int> >,std::allocator<std::vector<unsigned int, std::allocator<unsigned int> > > >::_Vector_impl" = type { %"struct.std::vector<int,std::allocator<int> >"*, %"struct.std::vector<int,std::allocator<int> >"*, %"struct.std::vector<int,std::allocator<int> >"* } - %"struct.std::list<llvm::MachineMemOperand,std::allocator<llvm::MachineMemOperand> >" = type { %"struct.std::_List_base<llvm::MachineMemOperand,std::allocator<llvm::MachineMemOperand> >" } - %"struct.std::pair<const llvm::PassInfo*,llvm::Pass*>" = type { %"struct.llvm::PassInfo"*, %"struct.llvm::Pass"* } - %"struct.std::pair<const llvm::TargetRegisterClass*,llvm::MachineOperand*>" = type { %"struct.llvm::TargetRegisterClass"*, %"struct.llvm::MachineOperand"* } - %"struct.std::pair<llvm::DebugLocTuple,unsigned int>" = type { %"struct.llvm::DebugLocTuple", i32 } - %"struct.std::pair<llvm::MachineInstr*,unsigned int>" = type { %"struct.llvm::MachineInstr"*, i32 } - %"struct.std::pair<unsigned int,char>" = type { i32, i8 } - %"struct.std::pair<unsigned int,int>" = type { i32, i32 } - %"struct.std::pair<unsigned int,llvm::LiveInterval*>" = type { i32, %"struct.llvm::LiveInterval"* } - %"struct.std::string" = type { %"struct.llvm::BumpPtrAllocator" } - %"struct.std::vector<const llvm::PassInfo*,std::allocator<const llvm::PassInfo*> >" = type { %"struct.std::_Vector_base<const llvm::PassInfo*,std::allocator<const llvm::PassInfo*> >" } - %"struct.std::vector<int,std::allocator<int> >" = type { %"struct.std::_Vector_base<int,std::allocator<int> >" } - %"struct.std::vector<llvm::AbstractTypeUser*,std::allocator<llvm::AbstractTypeUser*> >" = type { %"struct.std::_Vector_base<llvm::AbstractTypeUser*,std::allocator<llvm::AbstractTypeUser*> >" } - %"struct.std::vector<llvm::CalleeSavedInfo,std::allocator<llvm::CalleeSavedInfo> >" = type { %"struct.std::_Vector_base<llvm::CalleeSavedInfo,std::allocator<llvm::CalleeSavedInfo> >" } - %"struct.std::vector<llvm::DebugLocTuple,std::allocator<llvm::DebugLocTuple> >" = type { %"struct.std::_Vector_base<llvm::DebugLocTuple,std::allocator<llvm::DebugLocTuple> >" } - %"struct.std::vector<llvm::MachineBasicBlock*,std::allocator<llvm::MachineBasicBlock*> >" = type { %"struct.std::_Vector_base<llvm::MachineBasicBlock*,std::allocator<llvm::MachineBasicBlock*> >" } - %"struct.std::vector<llvm::MachineFrameInfo::StackObject,std::allocator<llvm::MachineFrameInfo::StackObject> >" = type { %"struct.std::_Vector_base<llvm::MachineFrameInfo::StackObject,std::allocator<llvm::MachineFrameInfo::StackObject> >" } - %"struct.std::vector<llvm::MachineInstr*,std::allocator<llvm::MachineInstr*> >" = type { %"struct.std::_Vector_base<llvm::MachineInstr*,std::allocator<llvm::MachineInstr*> >" } - %"struct.std::vector<llvm::MachineOperand,std::allocator<llvm::MachineOperand> >" = type { %"struct.std::_Vector_base<llvm::MachineOperand,std::allocator<llvm::MachineOperand> >" } - %"struct.std::vector<std::pair<const llvm::PassInfo*, llvm::Pass*>,std::allocator<std::pair<const llvm::PassInfo*, llvm::Pass*> > >" = type { %"struct.std::_Vector_base<std::pair<const llvm::PassInfo*, llvm::Pass*>,std::allocator<std::pair<const llvm::PassInfo*, llvm::Pass*> > >" } - %"struct.std::vector<std::pair<const llvm::TargetRegisterClass*, llvm::MachineOperand*>,std::allocator<std::pair<const llvm::TargetRegisterClass*, llvm::MachineOperand*> > >" = type { %"struct.std::_Vector_base<std::pair<const llvm::TargetRegisterClass*, llvm::MachineOperand*>,std::allocator<std::pair<const llvm::TargetRegisterClass*, llvm::MachineOperand*> > >" } - %"struct.std::vector<std::pair<unsigned int, llvm::MachineBasicBlock*>,std::allocator<std::pair<unsigned int, llvm::MachineBasicBlock*> > >" = type { %"struct.std::_Vector_base<std::pair<unsigned int, llvm::MachineBasicBlock*>,std::allocator<std::pair<unsigned int, llvm::MachineBasicBlock*> > >" } - %"struct.std::vector<std::pair<unsigned int, unsigned int>,std::allocator<std::pair<unsigned int, unsigned int> > >" = type { %"struct.std::_Vector_base<std::pair<unsigned int, unsigned int>,std::allocator<std::pair<unsigned int, unsigned int> > >" } - %"struct.std::vector<std::vector<unsigned int, std::allocator<unsigned int> >,std::allocator<std::vector<unsigned int, std::allocator<unsigned int> > > >" = type { %"struct.std::_Vector_base<std::vector<unsigned int, std::allocator<unsigned int> >,std::allocator<std::vector<unsigned int, std::allocator<unsigned int> > > >" } -@_ZZNK4llvm8DenseMapIPNS_12MachineInstrEjNS_12DenseMapInfoIS2_EENS3_IjEEE15LookupBucketForERKS2_RPSt4pairIS2_jEE8__func__ = external constant [16 x i8] ; <[16 x i8]*> [#uses=1] -@"\01LC6" = external constant [56 x i8] ; <[56 x i8]*> [#uses=1] -@"\01LC7" = external constant [134 x i8] ; <[134 x i8]*> [#uses=1] -@"\01LC8" = external constant [72 x i8] ; <[72 x i8]*> [#uses=1] -@_ZZN4llvm13LiveIntervals24InsertMachineInstrInMapsEPNS_12MachineInstrEjE8__func__ = external constant [25 x i8] ; <[25 x i8]*> [#uses=1] -@"\01LC51" = external constant [42 x i8] ; <[42 x i8]*> [#uses=1] - -define void @_ZN4llvm13LiveIntervals24InsertMachineInstrInMapsEPNS_12MachineInstrEj(%"struct.llvm::LiveIntervals"* nocapture %this, %"struct.llvm::MachineInstr"* %MI, i32 %Index) nounwind ssp { -entry: - %0 = call i64 @_ZN4llvm8DenseMapIPNS_12MachineInstrEjNS_12DenseMapInfoIS2_EENS3_IjEEE4findERKS2_(%"struct.llvm::DenseMap<llvm::MachineInstr*,unsigned int,llvm::DenseMapInfo<llvm::MachineInstr*>,llvm::DenseMapInfo<unsigned int> >"* null, %"struct.llvm::MachineInstr"** null) nounwind ssp ; <i64> [#uses=1] - %1 = trunc i64 %0 to i32 ; <i32> [#uses=1] - %tmp11 = inttoptr i32 %1 to %"struct.std::pair<llvm::MachineInstr*,unsigned int>"* ; <%"struct.std::pair<llvm::MachineInstr*,unsigned int>"*> [#uses=1] - %2 = load %"struct.std::pair<llvm::MachineInstr*,unsigned int>"** null, align 4 ; <%"struct.std::pair<llvm::MachineInstr*,unsigned int>"*> [#uses=3] - %3 = getelementptr %"struct.llvm::LiveIntervals"* %this, i32 0, i32 12, i32 0 ; <i32*> [#uses=1] - %4 = load i32* %3, align 4 ; <i32> [#uses=2] - %5 = getelementptr %"struct.std::pair<llvm::MachineInstr*,unsigned int>"* %2, i32 %4 ; <%"struct.std::pair<llvm::MachineInstr*,unsigned int>"*> [#uses=1] - br label %bb1.i.i.i - -bb.i.i.i: ; preds = %bb2.i.i.i - %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=1] - br label %bb1.i.i.i - -bb1.i.i.i: ; preds = %bb.i.i.i, %entry - %indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb.i.i.i ] ; <i32> [#uses=2] - %tmp32 = shl i32 %indvar, 3 ; <i32> [#uses=1] - %ctg2.sum = add i32 0, %tmp32 ; <i32> [#uses=1] - %ctg237 = getelementptr i8* null, i32 %ctg2.sum ; <i8*> [#uses=1] - %.0.0.i = bitcast i8* %ctg237 to %"struct.std::pair<llvm::MachineInstr*,unsigned int>"* ; <%"struct.std::pair<llvm::MachineInstr*,unsigned int>"*> [#uses=2] - %6 = icmp eq %"struct.std::pair<llvm::MachineInstr*,unsigned int>"* %.0.0.i, %5 ; <i1> [#uses=1] - br i1 %6, label %_ZN4llvm8DenseMapIPNS_12MachineInstrEjNS_12DenseMapInfoIS2_EENS3_IjEEE3endEv.exit, label %bb2.i.i.i - -bb2.i.i.i: ; preds = %bb1.i.i.i - %7 = load %"struct.llvm::MachineInstr"** null, align 4 ; <%"struct.llvm::MachineInstr"*> [#uses=1] - %8 = icmp eq %"struct.llvm::MachineInstr"* %7, inttoptr (i32 -8 to %"struct.llvm::MachineInstr"*) ; <i1> [#uses=1] - %or.cond.i.i.i21 = or i1 false, %8 ; <i1> [#uses=1] - br i1 %or.cond.i.i.i21, label %bb.i.i.i, label %_ZN4llvm8DenseMapIPNS_12MachineInstrEjNS_12DenseMapInfoIS2_EENS3_IjEEE3endEv.exit - -_ZN4llvm8DenseMapIPNS_12MachineInstrEjNS_12DenseMapInfoIS2_EENS3_IjEEE3endEv.exit: ; preds = %bb2.i.i.i, %bb1.i.i.i - %9 = icmp eq %"struct.std::pair<llvm::MachineInstr*,unsigned int>"* %tmp11, %.0.0.i ; <i1> [#uses=1] - br i1 %9, label %bb7, label %bb6 - -bb6: ; preds = %_ZN4llvm8DenseMapIPNS_12MachineInstrEjNS_12DenseMapInfoIS2_EENS3_IjEEE3endEv.exit - call void @__assert_rtn(i8* getelementptr ([25 x i8]* @_ZZN4llvm13LiveIntervals24InsertMachineInstrInMapsEPNS_12MachineInstrEjE8__func__, i32 0, i32 0), i8* getelementptr ([72 x i8]* @"\01LC8", i32 0, i32 0), i32 251, i8* getelementptr ([42 x i8]* @"\01LC51", i32 0, i32 0)) noreturn nounwind - unreachable - -bb7: ; preds = %_ZN4llvm8DenseMapIPNS_12MachineInstrEjNS_12DenseMapInfoIS2_EENS3_IjEEE3endEv.exit - %10 = load %"struct.llvm::MachineInstr"** null, align 4 ; <%"struct.llvm::MachineInstr"*> [#uses=2] - %11 = icmp eq %"struct.llvm::MachineInstr"* %10, inttoptr (i32 -8 to %"struct.llvm::MachineInstr"*) ; <i1> [#uses=1] - %or.cond40.i.i.i = or i1 false, %11 ; <i1> [#uses=1] - br i1 %or.cond40.i.i.i, label %bb5.i.i.i, label %bb6.preheader.i.i.i - -bb6.preheader.i.i.i: ; preds = %bb7 - %12 = add i32 %4, -1 ; <i32> [#uses=1] - br label %bb6.i.i.i - -bb5.i.i.i: ; preds = %bb7 - call void @__assert_rtn(i8* getelementptr ([16 x i8]* @_ZZNK4llvm8DenseMapIPNS_12MachineInstrEjNS_12DenseMapInfoIS2_EENS3_IjEEE15LookupBucketForERKS2_RPSt4pairIS2_jEE8__func__, i32 0, i32 0), i8* getelementptr ([56 x i8]* @"\01LC6", i32 0, i32 0), i32 390, i8* getelementptr ([134 x i8]* @"\01LC7", i32 0, i32 0)) noreturn nounwind - unreachable - -bb6.i.i.i: ; preds = %bb17.i.i.i, %bb6.preheader.i.i.i - %FoundTombstone.1.i.i.i = phi %"struct.std::pair<llvm::MachineInstr*,unsigned int>"* [ %FoundTombstone.0.i.i.i, %bb17.i.i.i ], [ null, %bb6.preheader.i.i.i ] ; <%"struct.std::pair<llvm::MachineInstr*,unsigned int>"*> [#uses=2] - %ProbeAmt.0.i.i.i = phi i32 [ 0, %bb17.i.i.i ], [ 1, %bb6.preheader.i.i.i ] ; <i32> [#uses=1] - %BucketNo.0.i.i.i = phi i32 [ %20, %bb17.i.i.i ], [ 0, %bb6.preheader.i.i.i ] ; <i32> [#uses=2] - %13 = and i32 %BucketNo.0.i.i.i, %12 ; <i32> [#uses=2] - %14 = getelementptr %"struct.std::pair<llvm::MachineInstr*,unsigned int>"* %2, i32 %13 ; <%"struct.std::pair<llvm::MachineInstr*,unsigned int>"*> [#uses=2] - %15 = getelementptr %"struct.std::pair<llvm::MachineInstr*,unsigned int>"* %2, i32 %13, i32 0 ; <%"struct.llvm::MachineInstr"**> [#uses=1] - %16 = load %"struct.llvm::MachineInstr"** %15, align 4 ; <%"struct.llvm::MachineInstr"*> [#uses=2] - %17 = icmp eq %"struct.llvm::MachineInstr"* %16, %10 ; <i1> [#uses=1] - br i1 %17, label %_ZN4llvm8DenseMapIPNS_12MachineInstrEjNS_12DenseMapInfoIS2_EENS3_IjEEEixERKS2_.exit, label %bb17.i.i.i - -bb17.i.i.i: ; preds = %bb6.i.i.i - %18 = icmp eq %"struct.llvm::MachineInstr"* %16, inttoptr (i32 -8 to %"struct.llvm::MachineInstr"*) ; <i1> [#uses=1] - %19 = icmp eq %"struct.std::pair<llvm::MachineInstr*,unsigned int>"* %FoundTombstone.1.i.i.i, null ; <i1> [#uses=1] - %or.cond.i.i.i = and i1 %18, %19 ; <i1> [#uses=1] - %FoundTombstone.0.i.i.i = select i1 %or.cond.i.i.i, %"struct.std::pair<llvm::MachineInstr*,unsigned int>"* %14, %"struct.std::pair<llvm::MachineInstr*,unsigned int>"* %FoundTombstone.1.i.i.i ; <%"struct.std::pair<llvm::MachineInstr*,unsigned int>"*> [#uses=1] - %20 = add i32 %BucketNo.0.i.i.i, %ProbeAmt.0.i.i.i ; <i32> [#uses=1] - br label %bb6.i.i.i - -_ZN4llvm8DenseMapIPNS_12MachineInstrEjNS_12DenseMapInfoIS2_EENS3_IjEEEixERKS2_.exit: ; preds = %bb6.i.i.i - %21 = getelementptr %"struct.std::pair<llvm::MachineInstr*,unsigned int>"* %14, i32 0, i32 1 ; <i32*> [#uses=1] - store i32 %Index, i32* %21, align 4 - ret void -} - -declare void @__assert_rtn(i8*, i8*, i32, i8*) noreturn - -declare i64 @_ZN4llvm8DenseMapIPNS_12MachineInstrEjNS_12DenseMapInfoIS2_EENS3_IjEEE4findERKS2_(%"struct.llvm::DenseMap<llvm::MachineInstr*,unsigned int,llvm::DenseMapInfo<llvm::MachineInstr*>,llvm::DenseMapInfo<unsigned int> >"* nocapture, %"struct.llvm::MachineInstr"** nocapture) nounwind ssp diff --git a/test/CodeGen/X86/tls-1.ll b/test/CodeGen/X86/tls-1.ll new file mode 100644 index 0000000..5f6cbe0 --- /dev/null +++ b/test/CodeGen/X86/tls-1.ll @@ -0,0 +1,19 @@ +; RUN: llc < %s -mtriple x86_64-apple-darwin | FileCheck %s + +@a = thread_local global i32 0 ; <i32*> [#uses=0] +@b = thread_local global i32 0 ; <i32*> [#uses=0] + +; CHECK: .tbss _a$tlv$init, 4, 2 +; CHECK: .section __DATA,__thread_vars,thread_local_variables +; CHECK: .globl _a +; CHECK: _a: +; CHECK: .quad ___tlv_bootstrap +; CHECK: .quad 0 +; CHECK: .quad _a$tlv$init + +; CHECK: .tbss _b$tlv$init, 4, 2 +; CHECK: .globl _b +; CHECK: _b: +; CHECK: .quad ___tlv_bootstrap +; CHECK: .quad 0 +; CHECK: .quad _b$tlv$init diff --git a/test/CodeGen/X86/unknown-location.ll b/test/CodeGen/X86/unknown-location.ll new file mode 100644 index 0000000..fa98b78 --- /dev/null +++ b/test/CodeGen/X86/unknown-location.ll @@ -0,0 +1,34 @@ +; RUN: llc < %s -asm-verbose=false -march=x86-64 -use-unknown-locations | FileCheck %s + +; The divide instruction does not have a debug location. CodeGen should +; represent this in the debug information. This is checked by a check +; for a label between the code for the add and the code for the divide, +; which indicates that the add's location doesn't spill over unto the +; divide. + +; CHECK: leal (%rdi,%rsi), %eax +; CHECK-NEXT: Ltmp +; CHECK-NEXT: cltd +; CHECK-NEXT: idivl %r8d +; CHECK-NEXT: Ltmp +; CHECK-NEXT: addl %ecx, %eax +; CHECK-NEXT: ret +; CHECK-NEXT: Ltmp + +define i32 @foo(i32 %w, i32 %x, i32 %y, i32 %z) nounwind { +entry: + %a = add i32 %w, %x, !dbg !8 + %b = sdiv i32 %a, %y + %c = add i32 %b, %z, !dbg !8 + ret i32 %c, !dbg !8 +} + +!0 = metadata !{i32 524545, metadata !1, metadata !"x", metadata !2, i32 1, metadata !6} ; [ DW_TAG_arg_variable ] +!1 = metadata !{i32 524334, i32 0, metadata !2, metadata !"foo", metadata !"foo", metadata !"foo", metadata !2, i32 1, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false} ; [ DW_TAG_subprogram ] +!2 = metadata !{i32 524329, metadata !"test.c", metadata !"/dir", metadata !3} ; [ DW_TAG_file_type ] +!3 = metadata !{i32 524305, i32 0, i32 12, metadata !"test.c", metadata !".", metadata !"producer", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!4 = metadata !{i32 524309, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ] +!5 = metadata !{metadata !6} +!6 = metadata !{i32 524324, metadata !2, metadata !"int", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!7 = metadata !{i32 524299, metadata !1, i32 1, i32 30} ; [ DW_TAG_lexical_block ] +!8 = metadata !{i32 4, i32 3, metadata !7, null} |
