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-rw-r--r--test/CodeGen/ARM/2010-03-04-eabi-fp-spill.ll65
-rw-r--r--test/CodeGen/ARM/2010-03-04-stm-undef-addr.ll54
-rw-r--r--test/CodeGen/CellSPU/bss.ll5
-rw-r--r--test/CodeGen/Thumb2/thumb2-uxtb.ll20
-rw-r--r--test/CodeGen/X86/2008-08-05-SpillerBug.ll2
-rw-r--r--test/CodeGen/X86/2010-03-04-Mul8Bug.ll25
-rw-r--r--test/CodeGen/X86/2010-03-05-ConstantFoldCFG.ll42
-rw-r--r--test/CodeGen/X86/2010-03-05-EFLAGS-Redef.ll49
-rw-r--r--test/CodeGen/X86/bswap-inline-asm.ll67
-rw-r--r--test/CodeGen/X86/crash.ll20
-rw-r--r--test/CodeGen/X86/global-sections.ll3
-rw-r--r--test/CodeGen/X86/lsr-reuse-trunc.ll15
-rw-r--r--test/CodeGen/X86/sink-hoist.ll1
-rw-r--r--test/CodeGen/X86/tailcall2.ll21
-rw-r--r--test/CodeGen/X86/use-add-flags.ll12
15 files changed, 368 insertions, 33 deletions
diff --git a/test/CodeGen/ARM/2010-03-04-eabi-fp-spill.ll b/test/CodeGen/ARM/2010-03-04-eabi-fp-spill.ll
new file mode 100644
index 0000000..f7adf73
--- /dev/null
+++ b/test/CodeGen/ARM/2010-03-04-eabi-fp-spill.ll
@@ -0,0 +1,65 @@
+; RUN: llc < %s -mtriple=arm-unknown-linux-gnueabi
+
+define void @"java.lang.String::getChars"([84 x i8]* %method, i32 %base_pc, [788 x i8]* %thread) {
+ %1 = load i32* undef ; <i32> [#uses=1]
+ %2 = sub i32 %1, 48 ; <i32> [#uses=1]
+ br i1 undef, label %stack_overflow, label %no_overflow
+
+stack_overflow: ; preds = %0
+ unreachable
+
+no_overflow: ; preds = %0
+ %frame = inttoptr i32 %2 to [17 x i32]* ; <[17 x i32]*> [#uses=4]
+ %3 = load i32* undef ; <i32> [#uses=1]
+ %4 = load i32* null ; <i32> [#uses=1]
+ %5 = getelementptr inbounds [17 x i32]* %frame, i32 0, i32 13 ; <i32*> [#uses=1]
+ %6 = bitcast i32* %5 to [8 x i8]** ; <[8 x i8]**> [#uses=1]
+ %7 = load [8 x i8]** %6 ; <[8 x i8]*> [#uses=1]
+ %8 = getelementptr inbounds [17 x i32]* %frame, i32 0, i32 12 ; <i32*> [#uses=1]
+ %9 = load i32* %8 ; <i32> [#uses=1]
+ br i1 undef, label %bci_13, label %bci_4
+
+bci_13: ; preds = %no_overflow
+ br i1 undef, label %bci_30, label %bci_21
+
+bci_30: ; preds = %bci_13
+ br i1 undef, label %bci_46, label %bci_35
+
+bci_46: ; preds = %bci_30
+ %10 = sub i32 %4, %3 ; <i32> [#uses=1]
+ %11 = load [8 x i8]** null ; <[8 x i8]*> [#uses=1]
+ %callee = bitcast [8 x i8]* %11 to [84 x i8]* ; <[84 x i8]*> [#uses=1]
+ %12 = bitcast i8* undef to i32* ; <i32*> [#uses=1]
+ %base_pc7 = load i32* %12 ; <i32> [#uses=2]
+ %13 = add i32 %base_pc7, 0 ; <i32> [#uses=1]
+ %14 = inttoptr i32 %13 to void ([84 x i8]*, i32, [788 x i8]*)** ; <void ([84 x i8]*, i32, [788 x i8]*)**> [#uses=1]
+ %entry_point = load void ([84 x i8]*, i32, [788 x i8]*)** %14 ; <void ([84 x i8]*, i32, [788 x i8]*)*> [#uses=1]
+ %15 = getelementptr inbounds [17 x i32]* %frame, i32 0, i32 1 ; <i32*> [#uses=1]
+ %16 = ptrtoint i32* %15 to i32 ; <i32> [#uses=1]
+ %stack_pointer_addr9 = bitcast i8* undef to i32* ; <i32*> [#uses=1]
+ store i32 %16, i32* %stack_pointer_addr9
+ %17 = getelementptr inbounds [17 x i32]* %frame, i32 0, i32 2 ; <i32*> [#uses=1]
+ store i32 %9, i32* %17
+ store i32 %10, i32* undef
+ store [84 x i8]* %method, [84 x i8]** undef
+ %18 = add i32 %base_pc, 20 ; <i32> [#uses=1]
+ store i32 %18, i32* undef
+ store [8 x i8]* %7, [8 x i8]** undef
+ call void %entry_point([84 x i8]* %callee, i32 %base_pc7, [788 x i8]* %thread)
+ br i1 undef, label %no_exception, label %exception
+
+exception: ; preds = %bci_46
+ ret void
+
+no_exception: ; preds = %bci_46
+ ret void
+
+bci_35: ; preds = %bci_30
+ ret void
+
+bci_21: ; preds = %bci_13
+ ret void
+
+bci_4: ; preds = %no_overflow
+ ret void
+}
diff --git a/test/CodeGen/ARM/2010-03-04-stm-undef-addr.ll b/test/CodeGen/ARM/2010-03-04-stm-undef-addr.ll
new file mode 100644
index 0000000..b0b4cb3
--- /dev/null
+++ b/test/CodeGen/ARM/2010-03-04-stm-undef-addr.ll
@@ -0,0 +1,54 @@
+; RUN: llc < %s -march=arm
+
+define void @"java.lang.String::getChars"([84 x i8]* %method, i32 %base_pc, [788 x i8]* %thread) {
+ %1 = sub i32 undef, 48 ; <i32> [#uses=1]
+ br i1 undef, label %stack_overflow, label %no_overflow
+
+stack_overflow: ; preds = %0
+ unreachable
+
+no_overflow: ; preds = %0
+ %frame = inttoptr i32 %1 to [17 x i32]* ; <[17 x i32]*> [#uses=4]
+ %2 = load i32* null ; <i32> [#uses=2]
+ %3 = getelementptr inbounds [17 x i32]* %frame, i32 0, i32 14 ; <i32*> [#uses=1]
+ %4 = load i32* %3 ; <i32> [#uses=2]
+ %5 = load [8 x i8]** undef ; <[8 x i8]*> [#uses=2]
+ br i1 undef, label %bci_13, label %bci_4
+
+bci_13: ; preds = %no_overflow
+ br i1 undef, label %bci_30, label %bci_21
+
+bci_30: ; preds = %bci_13
+ %6 = icmp sle i32 %2, %4 ; <i1> [#uses=1]
+ br i1 %6, label %bci_46, label %bci_35
+
+bci_46: ; preds = %bci_30
+ store [84 x i8]* %method, [84 x i8]** undef
+ br i1 false, label %no_exception, label %exception
+
+exception: ; preds = %bci_46
+ ret void
+
+no_exception: ; preds = %bci_46
+ ret void
+
+bci_35: ; preds = %bci_30
+ %7 = getelementptr inbounds [17 x i32]* %frame, i32 0, i32 15 ; <i32*> [#uses=1]
+ store i32 %2, i32* %7
+ %8 = getelementptr inbounds [17 x i32]* %frame, i32 0, i32 14 ; <i32*> [#uses=1]
+ store i32 %4, i32* %8
+ %9 = getelementptr inbounds [17 x i32]* %frame, i32 0, i32 13 ; <i32*> [#uses=1]
+ %10 = bitcast i32* %9 to [8 x i8]** ; <[8 x i8]**> [#uses=1]
+ store [8 x i8]* %5, [8 x i8]** %10
+ call void inttoptr (i32 13839116 to void ([788 x i8]*, i32)*)([788 x i8]* %thread, i32 7)
+ ret void
+
+bci_21: ; preds = %bci_13
+ ret void
+
+bci_4: ; preds = %no_overflow
+ store [8 x i8]* %5, [8 x i8]** undef
+ store i32 undef, i32* undef
+ call void inttoptr (i32 13839116 to void ([788 x i8]*, i32)*)([788 x i8]* %thread, i32 7)
+ ret void
+}
diff --git a/test/CodeGen/CellSPU/bss.ll b/test/CodeGen/CellSPU/bss.ll
new file mode 100644
index 0000000..05a0f50
--- /dev/null
+++ b/test/CodeGen/CellSPU/bss.ll
@@ -0,0 +1,5 @@
+; RUN: llc < %s -march=cellspu > %t1.s
+; RUN: grep "\.section" %t1.s | grep "\.bss" | count 1
+
+@bssVar = global i32 zeroinitializer
+
diff --git a/test/CodeGen/Thumb2/thumb2-uxtb.ll b/test/CodeGen/Thumb2/thumb2-uxtb.ll
index 4e23f53..91598cd 100644
--- a/test/CodeGen/Thumb2/thumb2-uxtb.ll
+++ b/test/CodeGen/Thumb2/thumb2-uxtb.ll
@@ -2,14 +2,14 @@
define i32 @test1(i32 %x) {
; CHECK: test1
-; CHECK: uxtb16.w r0, r0
+; CHECK: uxtb16 r0, r0
%tmp1 = and i32 %x, 16711935 ; <i32> [#uses=1]
ret i32 %tmp1
}
define i32 @test2(i32 %x) {
; CHECK: test2
-; CHECK: uxtb16.w r0, r0, ror #8
+; CHECK: uxtb16 r0, r0, ror #8
%tmp1 = lshr i32 %x, 8 ; <i32> [#uses=1]
%tmp2 = and i32 %tmp1, 16711935 ; <i32> [#uses=1]
ret i32 %tmp2
@@ -17,7 +17,7 @@ define i32 @test2(i32 %x) {
define i32 @test3(i32 %x) {
; CHECK: test3
-; CHECK: uxtb16.w r0, r0, ror #8
+; CHECK: uxtb16 r0, r0, ror #8
%tmp1 = lshr i32 %x, 8 ; <i32> [#uses=1]
%tmp2 = and i32 %tmp1, 16711935 ; <i32> [#uses=1]
ret i32 %tmp2
@@ -25,7 +25,7 @@ define i32 @test3(i32 %x) {
define i32 @test4(i32 %x) {
; CHECK: test4
-; CHECK: uxtb16.w r0, r0, ror #8
+; CHECK: uxtb16 r0, r0, ror #8
%tmp1 = lshr i32 %x, 8 ; <i32> [#uses=1]
%tmp6 = and i32 %tmp1, 16711935 ; <i32> [#uses=1]
ret i32 %tmp6
@@ -33,7 +33,7 @@ define i32 @test4(i32 %x) {
define i32 @test5(i32 %x) {
; CHECK: test5
-; CHECK: uxtb16.w r0, r0, ror #8
+; CHECK: uxtb16 r0, r0, ror #8
%tmp1 = lshr i32 %x, 8 ; <i32> [#uses=1]
%tmp2 = and i32 %tmp1, 16711935 ; <i32> [#uses=1]
ret i32 %tmp2
@@ -41,7 +41,7 @@ define i32 @test5(i32 %x) {
define i32 @test6(i32 %x) {
; CHECK: test6
-; CHECK: uxtb16.w r0, r0, ror #16
+; CHECK: uxtb16 r0, r0, ror #16
%tmp1 = lshr i32 %x, 16 ; <i32> [#uses=1]
%tmp2 = and i32 %tmp1, 255 ; <i32> [#uses=1]
%tmp4 = shl i32 %x, 16 ; <i32> [#uses=1]
@@ -52,7 +52,7 @@ define i32 @test6(i32 %x) {
define i32 @test7(i32 %x) {
; CHECK: test7
-; CHECK: uxtb16.w r0, r0, ror #16
+; CHECK: uxtb16 r0, r0, ror #16
%tmp1 = lshr i32 %x, 16 ; <i32> [#uses=1]
%tmp2 = and i32 %tmp1, 255 ; <i32> [#uses=1]
%tmp4 = shl i32 %x, 16 ; <i32> [#uses=1]
@@ -63,7 +63,7 @@ define i32 @test7(i32 %x) {
define i32 @test8(i32 %x) {
; CHECK: test8
-; CHECK: uxtb16.w r0, r0, ror #24
+; CHECK: uxtb16 r0, r0, ror #24
%tmp1 = shl i32 %x, 8 ; <i32> [#uses=1]
%tmp2 = and i32 %tmp1, 16711680 ; <i32> [#uses=1]
%tmp5 = lshr i32 %x, 24 ; <i32> [#uses=1]
@@ -73,7 +73,7 @@ define i32 @test8(i32 %x) {
define i32 @test9(i32 %x) {
; CHECK: test9
-; CHECK: uxtb16.w r0, r0, ror #24
+; CHECK: uxtb16 r0, r0, ror #24
%tmp1 = lshr i32 %x, 24 ; <i32> [#uses=1]
%tmp4 = shl i32 %x, 8 ; <i32> [#uses=1]
%tmp5 = and i32 %tmp4, 16711680 ; <i32> [#uses=1]
@@ -86,7 +86,7 @@ define i32 @test10(i32 %p0) {
; CHECK: mov.w r1, #16253176
; CHECK: and.w r0, r1, r0, lsr #7
; CHECK: lsrs r1, r0, #5
-; CHECK: uxtb16.w r1, r1
+; CHECK: uxtb16 r1, r1
; CHECK: orr.w r0, r1, r0
%tmp1 = lshr i32 %p0, 7 ; <i32> [#uses=1]
diff --git a/test/CodeGen/X86/2008-08-05-SpillerBug.ll b/test/CodeGen/X86/2008-08-05-SpillerBug.ll
index 67e14ff..4c64934 100644
--- a/test/CodeGen/X86/2008-08-05-SpillerBug.ll
+++ b/test/CodeGen/X86/2008-08-05-SpillerBug.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=i386-apple-darwin -disable-fp-elim -stats |& grep asm-printer | grep 58
+; RUN: llc < %s -mtriple=i386-apple-darwin -disable-fp-elim -stats |& grep asm-printer | grep 55
; PR2568
@g_3 = external global i16 ; <i16*> [#uses=1]
diff --git a/test/CodeGen/X86/2010-03-04-Mul8Bug.ll b/test/CodeGen/X86/2010-03-04-Mul8Bug.ll
new file mode 100644
index 0000000..48e75e9
--- /dev/null
+++ b/test/CodeGen/X86/2010-03-04-Mul8Bug.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s
+; PR6489
+;
+; This test case produces a MUL8 instruction and then tries to read the result
+; from the AX register instead of AH/AL. That confuses live interval analysis.
+;
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-apple-darwin10.0.0"
+
+define void @func_56(i64 %p_57, i32*** %p_58) nounwind ssp {
+for.end:
+ %conv49 = trunc i32 undef to i8 ; <i8> [#uses=1]
+ %div.i = udiv i8 %conv49, 5 ; <i8> [#uses=1]
+ %conv51 = zext i8 %div.i to i32 ; <i32> [#uses=1]
+ %call55 = call i32 @qux(i32 undef, i32 -2) nounwind ; <i32> [#uses=1]
+ %rem.i = urem i32 %call55, -1 ; <i32> [#uses=1]
+ %cmp57 = icmp uge i32 %conv51, %rem.i ; <i1> [#uses=1]
+ %conv58 = zext i1 %cmp57 to i32 ; <i32> [#uses=1]
+ %call85 = call i32 @func_35(i32*** undef, i32 undef, i32 %conv58, i32 1247, i32 0) nounwind ; <i32> [#uses=0]
+ ret void
+}
+
+declare i32 @func_35(i32***, i32, i32, i32, i32)
+
+declare i32 @qux(i32, i32)
diff --git a/test/CodeGen/X86/2010-03-05-ConstantFoldCFG.ll b/test/CodeGen/X86/2010-03-05-ConstantFoldCFG.ll
new file mode 100644
index 0000000..5de1966
--- /dev/null
+++ b/test/CodeGen/X86/2010-03-05-ConstantFoldCFG.ll
@@ -0,0 +1,42 @@
+; RUN: llc < %s -verify-machineinstrs
+;
+; When BRCOND is constant-folded to BR, make sure that PHI nodes don't get
+; spurious operands when the CFG is trimmed.
+;
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-apple-darwin10.2"
+
+define fastcc void @_ZSt16__introsort_loopIPdl17less_than_functorEvT_S2_T0_T1_(double* %__first, double* %__last, i64 %__depth_limit) nounwind ssp {
+entry:
+ br i1 undef, label %bb1, label %bb2
+
+bb1: ; preds = %entry
+ ret void
+
+bb2: ; preds = %entry
+ br label %bb2.outer.i
+
+bb2.outer.i: ; preds = %bb9.i, %bb2
+ br i1 undef, label %bb1.i, label %bb5.preheader.i
+
+bb1.i: ; preds = %bb1.i, %bb2.outer.i
+ %indvar5.i = phi i64 [ %tmp, %bb1.i ], [ 0, %bb2.outer.i ] ; <i64> [#uses=1]
+ %tmp = add i64 %indvar5.i, 1 ; <i64> [#uses=2]
+ %scevgep.i = getelementptr double* undef, i64 %tmp ; <double*> [#uses=0]
+ br i1 undef, label %bb1.i, label %bb5.preheader.i
+
+bb5.preheader.i: ; preds = %bb1.i, %bb2.outer.i
+ br label %bb5.i
+
+bb5.i: ; preds = %bb5.i, %bb5.preheader.i
+ br i1 undef, label %bb5.i, label %bb7.i6
+
+bb7.i6: ; preds = %bb5.i
+ br i1 undef, label %bb9.i, label %_ZSt21__unguarded_partitionIPdd17less_than_functorET_S2_S2_T0_T1_.exit
+
+bb9.i: ; preds = %bb7.i6
+ br label %bb2.outer.i
+
+_ZSt21__unguarded_partitionIPdd17less_than_functorET_S2_S2_T0_T1_.exit: ; preds = %bb7.i6
+ unreachable
+}
diff --git a/test/CodeGen/X86/2010-03-05-EFLAGS-Redef.ll b/test/CodeGen/X86/2010-03-05-EFLAGS-Redef.ll
new file mode 100644
index 0000000..3cca10e
--- /dev/null
+++ b/test/CodeGen/X86/2010-03-05-EFLAGS-Redef.ll
@@ -0,0 +1,49 @@
+; RUN: llc < %s -verify-machineinstrs
+;
+; This test case is transformed into a single basic block by the machine
+; branch folding pass. That makes a complete mess of the %EFLAGS liveness, but
+; we don't care about liveness this late anyway.
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-apple-darwin10.2"
+
+define i32 @main(i32 %argc, i8** nocapture %argv) ssp {
+entry:
+ br i1 undef, label %bb, label %bb2
+
+bb: ; preds = %entry
+ br label %bb2
+
+bb2: ; preds = %bb, %entry
+ br i1 undef, label %bb3, label %bb5
+
+bb3: ; preds = %bb2
+ br label %bb5
+
+bb5: ; preds = %bb3, %bb2
+ br i1 undef, label %bb.nph239, label %bb8
+
+bb.nph239: ; preds = %bb5
+ unreachable
+
+bb8: ; preds = %bb5
+ br i1 undef, label %bb.nph237, label %bb47
+
+bb.nph237: ; preds = %bb8
+ unreachable
+
+bb47: ; preds = %bb8
+ br i1 undef, label %bb49, label %bb48
+
+bb48: ; preds = %bb47
+ unreachable
+
+bb49: ; preds = %bb47
+ br i1 undef, label %bb51, label %bb50
+
+bb50: ; preds = %bb49
+ ret i32 0
+
+bb51: ; preds = %bb49
+ ret i32 0
+}
diff --git a/test/CodeGen/X86/bswap-inline-asm.ll b/test/CodeGen/X86/bswap-inline-asm.ll
index 5bf58fa..2b70193 100644
--- a/test/CodeGen/X86/bswap-inline-asm.ll
+++ b/test/CodeGen/X86/bswap-inline-asm.ll
@@ -1,17 +1,80 @@
; RUN: llc < %s -march=x86-64 > %t
; RUN: not grep APP %t
-; RUN: grep bswapq %t | count 2
-; RUN: grep bswapl %t | count 1
+; RUN: FileCheck %s < %t
+; CHECK: foo:
+; CHECK: bswapq
define i64 @foo(i64 %x) nounwind {
%asmtmp = tail call i64 asm "bswap $0", "=r,0,~{dirflag},~{fpsr},~{flags}"(i64 %x) nounwind
ret i64 %asmtmp
}
+
+; CHECK: bar:
+; CHECK: bswapq
define i64 @bar(i64 %x) nounwind {
%asmtmp = tail call i64 asm "bswapq ${0:q}", "=r,0,~{dirflag},~{fpsr},~{flags}"(i64 %x) nounwind
ret i64 %asmtmp
}
+
+; CHECK: pen:
+; CHECK: bswapl
define i32 @pen(i32 %x) nounwind {
%asmtmp = tail call i32 asm "bswapl ${0:q}", "=r,0,~{dirflag},~{fpsr},~{flags}"(i32 %x) nounwind
ret i32 %asmtmp
}
+
+; CHECK: s16:
+; CHECK: rolw $8,
+define zeroext i16 @s16(i16 zeroext %x) nounwind {
+ %asmtmp = tail call i16 asm "rorw $$8, ${0:w}", "=r,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i16 %x) nounwind
+ ret i16 %asmtmp
+}
+
+; CHECK: t16:
+; CHECK: rolw $8,
+define zeroext i16 @t16(i16 zeroext %x) nounwind {
+ %asmtmp = tail call i16 asm "rorw $$8, ${0:w}", "=r,0,~{cc},~{dirflag},~{fpsr},~{flags}"(i16 %x) nounwind
+ ret i16 %asmtmp
+}
+
+; CHECK: u16:
+; CHECK: rolw $8,
+define zeroext i16 @u16(i16 zeroext %x) nounwind {
+ %asmtmp = tail call i16 asm "rolw $$8, ${0:w}", "=r,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i16 %x) nounwind
+ ret i16 %asmtmp
+}
+
+; CHECK: v16:
+; CHECK: rolw $8,
+define zeroext i16 @v16(i16 zeroext %x) nounwind {
+ %asmtmp = tail call i16 asm "rolw $$8, ${0:w}", "=r,0,~{cc},~{dirflag},~{fpsr},~{flags}"(i16 %x) nounwind
+ ret i16 %asmtmp
+}
+
+; CHECK: s32:
+; CHECK: bswapl
+define i32 @s32(i32 %x) nounwind {
+ %asmtmp = tail call i32 asm "bswap $0", "=r,0,~{dirflag},~{fpsr},~{flags}"(i32 %x) nounwind
+ ret i32 %asmtmp
+}
+
+; CHECK: t32:
+; CHECK: bswapl
+define i32 @t32(i32 %x) nounwind {
+ %asmtmp = tail call i32 asm "bswap $0", "=r,0,~{dirflag},~{flags},~{fpsr}"(i32 %x) nounwind
+ ret i32 %asmtmp
+}
+
+; CHECK: s64:
+; CHECK: bswapq
+define i64 @s64(i64 %x) nounwind {
+ %asmtmp = tail call i64 asm "bswap ${0:q}", "=r,0,~{dirflag},~{fpsr},~{flags}"(i64 %x) nounwind
+ ret i64 %asmtmp
+}
+
+; CHECK: t64:
+; CHECK: bswapq
+define i64 @t64(i64 %x) nounwind {
+ %asmtmp = tail call i64 asm "bswap ${0:q}", "=r,0,~{fpsr},~{dirflag},~{flags}"(i64 %x) nounwind
+ ret i64 %asmtmp
+}
diff --git a/test/CodeGen/X86/crash.ll b/test/CodeGen/X86/crash.ll
new file mode 100644
index 0000000..1e13046
--- /dev/null
+++ b/test/CodeGen/X86/crash.ll
@@ -0,0 +1,20 @@
+; RUN: llc -march=x86 %s -o -
+; RUN: llc -march=x86-64 %s -o -
+
+; PR6497
+
+; Chain and flag folding issues.
+define i32 @test1() nounwind ssp {
+entry:
+ %tmp5.i = volatile load i32* undef ; <i32> [#uses=1]
+ %conv.i = zext i32 %tmp5.i to i64 ; <i64> [#uses=1]
+ %tmp12.i = volatile load i32* undef ; <i32> [#uses=1]
+ %conv13.i = zext i32 %tmp12.i to i64 ; <i64> [#uses=1]
+ %shl.i = shl i64 %conv13.i, 32 ; <i64> [#uses=1]
+ %or.i = or i64 %shl.i, %conv.i ; <i64> [#uses=1]
+ %add16.i = add i64 %or.i, 256 ; <i64> [#uses=1]
+ %shr.i = lshr i64 %add16.i, 8 ; <i64> [#uses=1]
+ %conv19.i = trunc i64 %shr.i to i32 ; <i32> [#uses=1]
+ volatile store i32 %conv19.i, i32* undef
+ ret i32 undef
+}
diff --git a/test/CodeGen/X86/global-sections.ll b/test/CodeGen/X86/global-sections.ll
index 1a7b577..d79c56b 100644
--- a/test/CodeGen/X86/global-sections.ll
+++ b/test/CodeGen/X86/global-sections.ll
@@ -100,7 +100,7 @@
@G8 = constant [4 x i16] [ i16 1, i16 2, i16 3, i16 0 ]
-; DARWIN: .section __TEXT,__ustring
+; DARWIN: .section __TEXT,__const
; DARWIN: .globl _G8
; DARWIN: _G8:
@@ -110,7 +110,6 @@
@G9 = constant [4 x i32] [ i32 1, i32 2, i32 3, i32 0 ]
-; DARWIN: .section __TEXT,__const
; DARWIN: .globl _G9
; DARWIN: _G9:
diff --git a/test/CodeGen/X86/lsr-reuse-trunc.ll b/test/CodeGen/X86/lsr-reuse-trunc.ll
index a663a22..d1d7144 100644
--- a/test/CodeGen/X86/lsr-reuse-trunc.ll
+++ b/test/CodeGen/X86/lsr-reuse-trunc.ll
@@ -1,19 +1,10 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
+; RUN: llc < %s -march=x86-64 | FileCheck %s
; Full strength reduction wouldn't reduce register pressure, so LSR should
; stick with indexing here.
-; Also checks andps and andnps shares the same constantpool. Previously llvm
-; will codegen two andps, one using 0x80000000, the other 0x7fffffff.
-; rdar://7323335
-
-; CHECK: movaps LCPI1_0
-; CHECK: movaps LCPI1_1
-; CHECK-NOT: movaps LCPI1_2
-; CHECK: movaps (%rsi,%rax,4), %xmm2
-; CHECK: andps
-; CHECK: andnps
-; CHECK: movaps %xmm2, (%rdi,%rax,4)
+; CHECK: movaps (%rsi,%rax,4), %xmm3
+; CHECK: movaps %xmm3, (%rdi,%rax,4)
; CHECK: addq $4, %rax
; CHECK: cmpl %eax, (%rdx)
; CHECK-NEXT: jg
diff --git a/test/CodeGen/X86/sink-hoist.ll b/test/CodeGen/X86/sink-hoist.ll
index e1d0fe7..01d7373 100644
--- a/test/CodeGen/X86/sink-hoist.ll
+++ b/test/CodeGen/X86/sink-hoist.ll
@@ -63,6 +63,7 @@ entry:
; CHECK: vv:
; CHECK: LCPI4_0(%rip), %xmm0
; CHECK: LCPI4_1(%rip), %xmm1
+; CHECK: LCPI4_2(%rip), %xmm2
; CHECK: align
; CHECK-NOT: LCPI
; CHECK: ret
diff --git a/test/CodeGen/X86/tailcall2.ll b/test/CodeGen/X86/tailcall2.ll
index 80bab61..90315fd 100644
--- a/test/CodeGen/X86/tailcall2.ll
+++ b/test/CodeGen/X86/tailcall2.ll
@@ -195,3 +195,24 @@ bb2:
}
declare i32 @foo6(i32, i32, %struct.t* byval align 4)
+
+; rdar://r7717598
+%struct.ns = type { i32, i32 }
+%struct.cp = type { float, float }
+
+define %struct.ns* @t13(%struct.cp* %yy) nounwind ssp {
+; 32: t13:
+; 32-NOT: jmp
+; 32: call
+; 32: ret
+
+; 64: t13:
+; 64-NOT: jmp
+; 64: call
+; 64: ret
+entry:
+ %0 = tail call fastcc %struct.ns* @foo7(%struct.cp* byval align 4 %yy, i8 signext 0) nounwind
+ ret %struct.ns* %0
+}
+
+declare fastcc %struct.ns* @foo7(%struct.cp* byval align 4, i8 signext) nounwind ssp
diff --git a/test/CodeGen/X86/use-add-flags.ll b/test/CodeGen/X86/use-add-flags.ll
index 2dd2a4a..c2f0c23 100644
--- a/test/CodeGen/X86/use-add-flags.ll
+++ b/test/CodeGen/X86/use-add-flags.ll
@@ -5,13 +5,13 @@
; Use the flags on the add.
-; CHECK: add_zf:
+; CHECK: test1:
; CHECK: addl (%rdi), %esi
; CHECK-NEXT: movl %edx, %eax
; CHECK-NEXT: cmovnsl %ecx, %eax
; CHECK-NEXT: ret
-define i32 @add_zf(i32* %x, i32 %y, i32 %a, i32 %b) nounwind {
+define i32 @test1(i32* %x, i32 %y, i32 %a, i32 %b) nounwind {
%tmp2 = load i32* %x, align 4 ; <i32> [#uses=1]
%tmp4 = add i32 %tmp2, %y ; <i32> [#uses=1]
%tmp5 = icmp slt i32 %tmp4, 0 ; <i1> [#uses=1]
@@ -24,10 +24,10 @@ declare void @foo(i32)
; Don't use the flags result of the and here, since the and has no
; other use. A simple test is better.
-; CHECK: bar:
+; CHECK: test2:
; CHECK: testb $16, %dil
-define void @bar(i32 %x) nounwind {
+define void @test2(i32 %x) nounwind {
%y = and i32 %x, 16
%t = icmp eq i32 %y, 0
br i1 %t, label %true, label %false
@@ -40,11 +40,11 @@ false:
; Do use the flags result of the and here, since the and has another use.
-; CHECK: qux:
+; CHECK: test3:
; CHECK: andl $16, %edi
; CHECK-NEXT: jne
-define void @qux(i32 %x) nounwind {
+define void @test3(i32 %x) nounwind {
%y = and i32 %x, 16
%t = icmp eq i32 %y, 0
br i1 %t, label %true, label %false
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